OV - exec - Function PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone .omp

	Function: PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D<double>&, clover::Buffer2D<d ...	Module: exec	Source: PdV.cpp:69-83 [...]	Coverage (incl. loops): 6.47% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp: 69 - 83

--------------------------------------------------------------------------------

69: #pragma omp parallel for simd collapse(2)

70:     for (int j = (y_min + 1); j < (y_max + 2); j++) {

71:       for (int i = (x_min + 1); i < (x_max + 2); i++) {

72:         double left_flux = (xarea(i, j) * (xvel0(i, j) + xvel0(i + 0, j + 1) + xvel1(i, j) + xvel1(i + 0, j + 1))) * 0.25 * dt;

73:         double right_flux =

74:             (xarea(i + 1, j + 0) * (xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1) + xvel1(i + 1, j + 0) + xvel1(i + 1, j + 1))) * 0.25 * dt;

75:         double bottom_flux = (yarea(i, j) * (yvel0(i, j) + yvel0(i + 1, j + 0) + yvel1(i, j) + yvel1(i + 1, j + 0))) * 0.25 * dt;

76:         double top_flux =

77:             (yarea(i + 0, j + 1) * (yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1) + yvel1(i + 0, j + 1) + yvel1(i + 1, j + 1))) * 0.25 * dt;

78:         double total_flux = right_flux - left_flux + top_flux - bottom_flux;

79:         double volume_change_s = volume(i, j) / (volume(i, j) + total_flux);

80:         double recip_volume = 1.0 / volume(i, j);

81:         double energy_change = (pressure(i, j) / density0(i, j) + viscosity(i, j) / density0(i, j)) * total_flux * recip_volume;

82:         energy1(i, j) = energy0(i, j) - energy_change;

83:         density1(i, j) = density0(i, j) * volume_change_s;

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x245ee0 PUSH	%RBP

0x245ee1 MOV	%RSP,%RBP

0x245ee4 PUSH	%R15

0x245ee6 PUSH	%R14

0x245ee8 PUSH	%R13

0x245eea PUSH	%R12

0x245eec PUSH	%RBX

0x245eed AND	$-0x20,%RSP

0x245ef1 SUB	$0x1c0,%RSP

0x245ef8 MOV	(%RDX),%R12D

0x245efb MOV	(%RCX),%EBX

0x245efd INC	%R12D

0x245f00 ADD	$0x2,%EBX

0x245f03 SUB	%R12D,%EBX

0x245f06 JLE	246e6f

0x245f0c MOV	(%R9),%R15D

0x245f0f MOV	(%R8),%R14D

0x245f12 INC	%R14D

0x245f15 ADD	$0x2,%R15D

0x245f19 CMP	%R14D,%R15D

0x245f1c JLE	246e6f

0x245f22 SUB	%R14D,%R15D

0x245f25 MOV	(%RDI),%ESI

0x245f27 MOVQ	$0,0xe0(%RSP)

0x245f33 MOVQ	$0x1,0x118(%RSP)

0x245f3f MOVL	$0,0x4c(%RSP)

0x245f47 IMUL	%R15,%RBX

0x245f4b DEC	%RBX

0x245f4e MOV	%RBX,0x40(%RSP)

0x245f53 SUB	$0x8,%RSP

0x245f57 LEA	0x54(%RSP),%RCX

0x245f5c LEA	0x120(%RSP),%RAX

0x245f64 LEA	0x15755(%RIP),%RDI

0x245f6b LEA	0xe8(%RSP),%R8

0x245f73 LEA	0x48(%RSP),%R9

0x245f78 MOV	%ESI,0x50(%RSP)

0x245f7c MOV	$0x22,%EDX

0x245f81 PUSH	$0x1

0x245f83 PUSH	$0x1

0x245f85 PUSH	%RAX

0x245f86 CALL	259680 <@plt_start@+0x530>

0x245f8b ADD	$0x20,%RSP

0x245f8f MOV	0x40(%RSP),%RAX

0x245f94 MOV	0xe0(%RSP),%RCX

0x245f9c CMP	%RBX,%RAX

0x245f9f CMOVL	%RAX,%RBX

0x245fa3 MOV	%RBX,0x40(%RSP)

0x245fa8 CMP	%RBX,%RCX

0x245fab JG	246e5c

0x245fb1 MOV	0x10(%RBP),%RDI

0x245fb5 MOV	0x18(%RBP),%R9

0x245fb9 MOV	0x20(%RBP),%R10

0x245fbd MOV	0x30(%RBP),%RSI

0x245fc1 MOV	0x48(%RBP),%RAX

0x245fc5 MOV	0x40(%RBP),%RDX

0x245fc9 MOV	0x38(%RBP),%R8

0x245fcd MOV	%R12,0xb0(%RSP)

0x245fd5 MOV	%R14D,0xc(%RSP)

0x245fda MOV	%R15,0xa8(%RSP)

0x245fe2 MOV	%RBX,0x110(%RSP)

0x245fea MOV	(%RDI),%R11

0x245fed MOV	0x10(%RDI),%RDI

0x245ff1 MOV	%RDI,0xd8(%RSP)

0x245ff9 MOV	(%R9),%RDI

0x245ffc MOV	%R11,0xa0(%RSP)

0x246004 MOV	0x10(%R10),%R11

0x246008 MOV	0x10(%R9),%R9

0x24600c MOV	%RDI,0x98(%RSP)

0x246014 MOV	(%R10),%RDI

0x246017 MOV	0x10(%R8),%R10

0x24601b MOV	%RDI,0x90(%RSP)

0x246023 MOV	(%RSI),%RDI

0x246026 MOV	0x10(%RSI),%RSI

0x24602a MOV	%RDI,0x88(%RSP)

0x246032 MOV	%RSI,0x50(%RSP)

0x246037 MOV	(%R8),%RSI

0x24603a MOV	(%RDX),%RDI

0x24603d MOV	0x10(%RDX),%R8

0x246041 MOV	(%RAX),%RDX

0x246044 MOV	0x10(%RAX),%RAX

0x246048 MOV	%RAX,0xd0(%RSP)

0x246050 MOV	0x50(%RBP),%RAX

0x246054 MOV	%RDI,0x30(%RSP)

0x246059 MOV	%RSI,0x108(%RSP)

0x246061 MOV	%RDX,0x100(%RSP)

0x246069 MOV	(%RAX),%R13

0x24606c MOV	0x10(%RAX),%RAX

0x246070 MOV	%RAX,0xc8(%RSP)

0x246078 MOV	0x58(%RBP),%RAX

0x24607c MOV	%R13,0x80(%RSP)

0x246084 MOV	(%RAX),%R13

0x246087 MOV	0x10(%RAX),%RAX

0x24608b MOV	%RAX,0x10(%RSP)

0x246090 MOV	0x60(%RBP),%RAX

0x246094 MOV	%R13,0xf8(%RSP)

0x24609c MOV	(%RAX),%RDI

0x24609f MOV	0x10(%RAX),%RAX

0x2460a3 MOV	%RAX,0xc0(%RSP)

0x2460ab MOV	0x70(%RBP),%RAX

0x2460af MOV	%RDI,0x78(%RSP)

0x2460b4 MOV	(%RAX),%RDI

0x2460b7 MOV	0x10(%RAX),%RAX

0x2460bb MOV	%RAX,0x70(%RSP)

0x2460c0 MOV	0x68(%RBP),%RAX

0x2460c4 MOV	%RDI,0x68(%RSP)

0x2460c9 MOV	(%RAX),%RDI

0x2460cc MOV	0x10(%RAX),%RAX

0x2460d0 MOV	%RAX,0xb8(%RSP)

0x2460d8 MOV	0x78(%RBP),%RAX

0x2460dc MOV	%RDI,0x60(%RSP)

0x2460e1 MOV	(%RAX),%RDI

0x2460e4 MOV	0x10(%RAX),%RAX

0x2460e8 MOV	%RAX,0x38(%RSP)

0x2460ed MOV	%RBX,%RAX

0x2460f0 SUB	%RCX,%RAX

0x2460f3 MOV	%RDI,0x58(%RSP)

0x2460f8 INC	%RAX

0x2460fb CMP	$0x4,%RAX

0x2460ff JAE	246110

0x246101 MOV	0x50(%RSP),%RSI

0x246106 MOV	0x10(%RSP),%R13

0x24610b JMP	246bd4

0x246110 MOV	0xa0(%RSP),%RBX

0x246118 VPBROADCASTQ	%RSI,%YMM8

0x24611e MOV	0x30(%RSP),%RSI

0x246123 VPBROADCASTD	%R12D,%XMM2

0x246129 MOV	0x98(%RSP),%RDI

0x246131 VPBROADCASTQ	%RCX,%YMM0

0x246137 VPADDQ	-0x34e5f(%RIP),%YMM0,%YMM0

0x24613f VPBROADCASTQ	-0x34f79(%RIP),%YMM20

0x246149 VPBROADCASTQ	%R13,%YMM12

0x24614f MOV	0x10(%RSP),%R13

0x246154 MOV	%RAX,0xf0(%RSP)

0x24615c AND	$-0x4,%RAX

0x246160 VPBROADCASTQ	%R15,%YMM1

0x246166 VMOVDQA	%XMM2,0x130(%RSP)

0x24616f VPBROADCASTD	%R14D,%XMM2

0x246175 ADD	%RAX,%RCX

0x246178 VEXTRACTI32X4	$0x1,%YMM1,%XMM17

0x24617f MOV	%RAX,0xe8(%RSP)

0x246187 VMOVDQA	%XMM2,0x120(%RSP)

0x246190 MOV	%RCX,0x28(%RSP)

0x246195 VPBROADCASTQ	%RBX,%YMM2

0x24619b VPBROADCASTQ	%RSI,%YMM9

0x2461a1 MOV	0x78(%RSP),%RSI

0x2461a6 VPBROADCASTQ	%RDI,%YMM5

0x2461ac MOV	0x88(%RSP),%RDI

0x2461b4 MOV	0x90(%RSP),%RBX

0x2461bc VMOVDQA	%YMM2,0x180(%RSP)

0x2461c5 VPBROADCASTQ	%RDX,%YMM2

0x2461cb MOV	0x80(%RSP),%RDX

0x2461d3 VMOVDQA	%YMM2,0x160(%RSP)

0x2461dc VPBROADCASTQ	%RSI,%YMM13

0x2461e2 MOV	0x60(%RSP),%RSI

0x2461e7 VPBROADCASTQ	%RDI,%YMM7

0x2461ed MOV	0x70(%RSP),%RDI

0x2461f2 VPBROADCASTQ	%RBX,%YMM6

0x2461f8 VPBROADCASTQ	%RDX,%YMM2

0x2461fe MOV	0x68(%RSP),%RDX

0x246203 VMOVDQA	%YMM2,0x140(%RSP)

0x24620c VPCMPEQD	%XMM2,%XMM2,%XMM2

0x246210 VPBROADCASTQ	%RSI,%YMM15

0x246216 MOV	0x50(%RSP),%RSI

0x24621b VPBROADCASTQ	%RDX,%YMM14

0x246221 MOV	0x58(%RSP),%RDX

0x246226 VPBROADCASTQ	%RDX,%YMM16

0x24622c NOPL	(%RAX)

(263) 0x246230 VEXTRACTI32X4	$0x1,%YMM0,%XMM18

(263) 0x246237 MOV	%RAX,0x20(%RSP)

(263) 0x24623c VPEXTRQ	$0x1,%XMM17,%RBX

(263) 0x246243 VPEXTRQ	$0x1,%XMM18,%RAX

(263) 0x24624a CQTO

(263) 0x24624c IDIV	%RBX

(263) 0x24624f VMOVQ	%XMM18,%RDX

(263) 0x246255 VMOVQ	%XMM17,%RBX

(263) 0x24625b VMOVQ	%RAX,%XMM18

(263) 0x246261 MOV	%RDX,%RAX

(263) 0x246264 CQTO

(263) 0x246266 IDIV	%RBX

(263) 0x246269 VPEXTRQ	$0x1,%XMM1,%RBX

(263) 0x24626f VMOVQ	%RAX,%XMM19

(263) 0x246275 VPEXTRQ	$0x1,%XMM0,%RAX

(263) 0x24627b CQTO

(263) 0x24627d VPUNPCKLQDQ	%XMM18,%XMM19,%XMM18

(263) 0x246283 IDIV	%RBX

(263) 0x246286 VMOVQ	%XMM0,%RDX

(263) 0x24628b VMOVQ	%XMM1,%RBX

(263) 0x246290 VMOVQ	%RAX,%XMM19

(263) 0x246296 MOV	%RDX,%RAX

(263) 0x246299 CQTO

(263) 0x24629b IDIV	%RBX

(263) 0x24629e MOV	0xd8(%RSP),%R15

(263) 0x2462a6 VMOVQ	%RAX,%XMM21

(263) 0x2462ac VPUNPCKLQDQ	%XMM19,%XMM21,%XMM19

(263) 0x2462b2 VINSERTI32X4	$0x1,%XMM18,%YMM19,%YMM18

(263) 0x2462b9 VPMOVQD	%YMM18,%XMM19

(263) 0x2462bf VPADDD	0x130(%RSP),%XMM19,%XMM19

(263) 0x2462c7 VPMULLQ	%YMM1,%YMM18,%YMM18

(263) 0x2462cd VPSUBQ	%YMM18,%YMM0,%YMM18

(263) 0x2462d3 VPADDQ	%YMM20,%YMM0,%YMM0

(263) 0x2462d9 VPMOVQD	%YMM18,%XMM18

(263) 0x2462df VPADDD	0x120(%RSP),%XMM18,%XMM24

(263) 0x2462e7 VPMOVSXDQ	%XMM19,%YMM22

(263) 0x2462ed VPMULLQ	0x180(%RSP),%YMM22,%YMM26

(263) 0x2462f5 VPSUBD	%XMM2,%XMM19,%XMM19

(263) 0x2462fb VPMULLQ	%YMM22,%YMM5,%YMM30

(263) 0x246301 VPMOVSXDQ	%XMM24,%YMM21

(263) 0x246307 VPSUBD	%XMM2,%XMM24,%XMM24

(263) 0x24630d VPMOVSXDQ	%XMM24,%YMM24

(263) 0x246313 VPADDQ	%YMM21,%YMM30,%YMM23

(263) 0x246319 VPADDQ	%YMM24,%YMM30,%YMM11

(263) 0x24631f VPADDQ	%YMM21,%YMM26,%YMM18

(263) 0x246325 VPADDQ	%YMM24,%YMM26,%YMM26

(263) 0x24632b VMOVQ	%XMM18,%RAX

(263) 0x246331 VPEXTRQ	$0x1,%XMM18,%RDX

(263) 0x246338 VEXTRACTI32X4	$0x1,%YMM18,%XMM18

(263) 0x24633f VMOVQ	%XMM18,%RBX

(263) 0x246345 VPEXTRQ	$0x1,%XMM18,%R12

(263) 0x24634c VMOVSD	(%R15,%RAX,8),%XMM18

(263) 0x246353 VMOVQ	%XMM23,%RAX

(263) 0x246359 VMOVSD	(%R15,%RBX,8),%XMM25

(263) 0x246360 VPEXTRQ	$0x1,%XMM23,%RBX

(263) 0x246367 VEXTRACTI32X4	$0x1,%YMM23,%XMM23

(263) 0x24636e VMOVHPD	(%R15,%RDX,8),%XMM18,%XMM18

(263) 0x246375 VMOVQ	%XMM23,%RDX

(263) 0x24637b VPEXTRQ	$0x1,%XMM23,%R14

(263) 0x246382 VMOVSD	(%R9,%RAX,8),%XMM23

(263) 0x246389 VMOVHPD	(%R15,%R12,8),%XMM25,%XMM25

(263) 0x246390 VMOVHPD	(%R9,%RBX,8),%XMM23,%XMM28

(263) 0x246397 VPMOVSXDQ	%XMM19,%YMM23

(263) 0x24639d VMOVSD	(%R9,%RDX,8),%XMM27

(263) 0x2463a4 VMOVHPD	(%R9,%R14,8),%XMM27,%XMM27

(263) 0x2463ab VPMULLQ	%YMM23,%YMM5,%YMM31

(263) 0x2463b1 VPADDQ	%YMM21,%YMM31,%YMM19

(263) 0x2463b7 VMOVQ	%XMM19,%RAX

(263) 0x2463bd VPEXTRQ	$0x1,%XMM19,%RDX

(263) 0x2463c4 VEXTRACTI32X4	$0x1,%YMM19,%XMM19

(263) 0x2463cb VMOVQ	%XMM19,%RBX

(263) 0x2463d1 VPEXTRQ	$0x1,%XMM19,%R14

(263) 0x2463d8 VMOVSD	(%R9,%RAX,8),%XMM29

(263) 0x2463df VINSERTF32X4	$0x1,%XMM25,%YMM18,%YMM25

(263) 0x2463e6 VMOVSD	(%R9,%RBX,8),%XMM19

(263) 0x2463ed VMOVHPD	(%R9,%RDX,8),%XMM29,%XMM29

(263) 0x2463f4 VMOVHPD	(%R9,%R14,8),%XMM19,%XMM3

(263) 0x2463fb VPMULLQ	%YMM22,%YMM6,%YMM19

(263) 0x246401 VINSERTF32X4	$0x1,%XMM27,%YMM28,%YMM27

(263) 0x246408 VPADDQ	%YMM21,%YMM19,%YMM4

(263) 0x24640e VPADDQ	%YMM24,%YMM19,%YMM19

(263) 0x246414 VMOVQ	%XMM4,%RAX

(263) 0x246419 VPEXTRQ	$0x1,%XMM4,%RDX

(263) 0x24641f VEXTRACTI128	$0x1,%YMM4,%XMM4

(263) 0x246425 VMOVSD	(%R11,%RAX,8),%XMM18

(263) 0x24642c VMOVQ	%XMM4,%RBX

(263) 0x246431 VPEXTRQ	$0x1,%XMM4,%R14

(263) 0x246437 VMOVHPD	(%R11,%RDX,8),%XMM18,%XMM28

(263) 0x24643e VPMULLQ	%YMM23,%YMM6,%YMM18

(263) 0x246444 VMOVSD	(%R11,%RBX,8),%XMM4

(263) 0x24644a VMOVHPD	(%R11,%R14,8),%XMM4,%XMM4

(263) 0x246450 VINSERTF32X4	$0x1,%XMM3,%YMM29,%YMM29

(263) 0x246457 VPADDQ	%YMM21,%YMM18,%YMM10

(263) 0x24645d VPADDQ	%YMM24,%YMM18,%YMM18

(263) 0x246463 VMOVQ	%XMM10,%RAX

(263) 0x246468 VPEXTRQ	$0x1,%XMM10,%RDX

(263) 0x24646e VEXTRACTI128	$0x1,%YMM10,%XMM10

(263) 0x246474 VPEXTRQ	$0x1,%XMM18,0x18(%RSP)

(263) 0x24647d VADDPD	%YMM27,%YMM29,%YMM27

(263) 0x246483 VMOVQ	%XMM10,%R14

(263) 0x246488 VPEXTRQ	$0x1,%XMM10,%RBX

(263) 0x24648e VMOVSD	(%R11,%RAX,8),%XMM10

(263) 0x246494 VMOVQ	%XMM26,%RAX

(263) 0x24649a VMOVSD	(%R11,%R14,8),%XMM3

(263) 0x2464a0 VMOVHPD	(%R11,%RDX,8),%XMM10,%XMM10

(263) 0x2464a6 VPEXTRQ	$0x1,%XMM26,%RDX

(263) 0x2464ad VMOVHPD	(%R11,%RBX,8),%XMM3,%XMM3

(263) 0x2464b3 VINSERTF32X4	$0x1,%XMM4,%YMM28,%YMM28

(263) 0x2464ba VEXTRACTI32X4	$0x1,%YMM26,%XMM4

(263) 0x2464c1 VMOVQ	%XMM4,%RBX

(263) 0x2464c6 VPEXTRQ	$0x1,%XMM4,%R14

(263) 0x2464cc VMOVSD	(%R15,%RAX,8),%XMM4

(263) 0x2464d2 VMOVQ	%XMM11,%RAX

(263) 0x2464d7 VMOVSD	(%R15,%RBX,8),%XMM26

(263) 0x2464de VMOVHPD	(%R15,%RDX,8),%XMM4,%XMM4

(263) 0x2464e4 VPEXTRQ	$0x1,%XMM11,%RDX

(263) 0x2464ea VMOVHPD	(%R15,%R14,8),%XMM26,%XMM26

(263) 0x2464f1 VINSERTF32X4	$0x1,%XMM3,%YMM10,%YMM30

(263) 0x2464f8 VEXTRACTI128	$0x1,%YMM11,%XMM3

(263) 0x2464fe VPADDQ	%YMM24,%YMM31,%YMM11

(263) 0x246504 VMOVQ	%XMM3,%RBX

(263) 0x246509 VPEXTRQ	$0x1,%XMM3,%RCX

(263) 0x24650f VMOVSD	(%R9,%RAX,8),%XMM3

(263) 0x246515 VMOVQ	%XMM11,%RAX

(263) 0x24651a VMOVSD	(%R9,%RBX,8),%XMM10

(263) 0x246520 VMOVHPD	(%R9,%RDX,8),%XMM3,%XMM3

(263) 0x246526 VPEXTRQ	$0x1,%XMM11,%RDX

(263) 0x24652c VEXTRACTI128	$0x1,%YMM11,%XMM11

(263) 0x246532 VADDPD	%YMM30,%YMM28,%YMM28

(263) 0x246538 VPMULLQ	%YMM22,%YMM9,%YMM30

(263) 0x24653e VMOVHPD	(%R9,%RCX,8),%XMM10,%XMM10

(263) 0x246544 VMOVQ	%XMM11,%RBX

(263) 0x246549 VPEXTRQ	$0x1,%XMM11,%R14

(263) 0x24654f VMOVQ	%XMM18,%RCX

(263) 0x246555 VEXTRACTI32X4	$0x1,%YMM18,%XMM18

(263) 0x24655c VMOVSD	(%R9,%RBX,8),%XMM11

(263) 0x246562 VMOVQ	%XMM19,%RBX

(263) 0x246568 VINSERTF32X4	$0x1,%XMM26,%YMM4,%YMM26

(263) 0x24656f VMOVSD	(%R9,%RAX,8),%XMM4

(263) 0x246575 VMOVHPD	(%R9,%R14,8),%XMM11,%XMM11

(263) 0x24657b VPEXTRQ	$0x1,%XMM19,%RAX

(263) 0x246582 VEXTRACTI32X4	$0x1,%YMM19,%XMM19

(263) 0x246589 VPEXTRQ	$0x1,%XMM18,%R14

(263) 0x246590 VADDPD	%YMM28,%YMM27,%YMM27

(263) 0x246596 VMOVHPD	(%R9,%RDX,8),%XMM4,%XMM4

(263) 0x24659c VMOVQ	%XMM19,%RDX

(263) 0x2465a2 VPEXTRQ	$0x1,%XMM19,%R12

(263) 0x2465a9 VMOVSD	(%R11,%RDX,8),%XMM19

(263) 0x2465b0 VMOVQ	%XMM18,%RDX

(263) 0x2465b6 VMOVSD	(%R11,%RBX,8),%XMM18

(263) 0x2465bd VMOVHPD	(%R11,%RAX,8),%XMM18,%XMM18

(263) 0x2465c4 VMOVHPD	(%R11,%R12,8),%XMM19,%XMM19

(263) 0x2465cb VINSERTF128	$0x1,%XMM10,%YMM3,%YMM3

(263) 0x2465d1 VPMULLQ	%YMM22,%YMM7,%YMM10

(263) 0x2465d7 VPADDQ	%YMM21,%YMM10,%YMM10

(263) 0x2465dd VINSERTF128	$0x1,%XMM11,%YMM4,%YMM4

(263) 0x2465e3 VMOVQ	%XMM10,%RAX

(263) 0x2465e8 VPEXTRQ	$0x1,%XMM10,%RBX

(263) 0x2465ee VEXTRACTI128	$0x1,%YMM10,%XMM10

(263) 0x2465f4 VMOVQ	%XMM10,%R12

(263) 0x2465f9 VMOVSD	(%RSI,%RAX,8),%XMM11

(263) 0x2465fe VPEXTRQ	$0x1,%XMM10,%R15

(263) 0x246604 VINSERTF32X4	$0x1,%XMM19,%YMM18,%YMM18

(263) 0x24660b VADDPD	%YMM3,%YMM4,%YMM3

(263) 0x24660f VPADDQ	%YMM21,%YMM30,%YMM4

(263) 0x246615 VMOVSD	(%RSI,%R12,8),%XMM10

(263) 0x24661b VMOVHPD	(%RSI,%RBX,8),%XMM11,%XMM11

(263) 0x246620 VMOVHPD	(%RSI,%R15,8),%XMM10,%XMM10

(263) 0x246626 VINSERTF128	$0x1,%XMM10,%YMM11,%YMM10

(263) 0x24662c VPMULLQ	%YMM22,%YMM8,%YMM11

(263) 0x246632 VPADDQ	%YMM21,%YMM11,%YMM19

(263) 0x246638 VPADDQ	%YMM24,%YMM11,%YMM11

(263) 0x24663e VMOVQ	%XMM19,%RAX

(263) 0x246644 VPEXTRQ	$0x1,%XMM19,%RBX

(263) 0x24664b VEXTRACTI32X4	$0x1,%YMM19,%XMM19

(263) 0x246652 VMOVQ	%XMM19,%R15

(263) 0x246658 VMOVSD	(%R10,%RAX,8),%XMM29

(263) 0x24665f VPEXTRQ	$0x1,%XMM19,%R12

(263) 0x246666 VMOVQ	%XMM11,%RAX

(263) 0x24666b VMOVSD	(%R10,%R15,8),%XMM19

(263) 0x246672 VMOVHPD	(%R10,%RBX,8),%XMM29,%XMM29

(263) 0x246679 VPEXTRQ	$0x1,%XMM11,%RBX

(263) 0x24667f VEXTRACTI128	$0x1,%YMM11,%XMM11

(263) 0x246685 VMOVHPD	(%R10,%R12,8),%XMM19,%XMM19

(263) 0x24668c VMOVQ	%XMM11,%R15

(263) 0x246691 VPEXTRQ	$0x1,%XMM11,%R12

(263) 0x246697 VMOVSD	(%R10,%R15,8),%XMM11

(263) 0x24669d VMOVHPD	(%R10,%R12,8),%XMM11,%XMM11

(263) 0x2466a3 VINSERTF32X4	$0x1,%XMM19,%YMM29,%YMM19

(263) 0x2466aa VMOVSD	(%R10,%RAX,8),%XMM29

(263) 0x2466b1 VMOVQ	%XMM4,%RAX

(263) 0x2466b6 VMOVHPD	(%R10,%RBX,8),%XMM29,%XMM29

(263) 0x2466bd VPEXTRQ	$0x1,%XMM4,%RBX

(263) 0x2466c3 VEXTRACTI128	$0x1,%YMM4,%XMM4

(263) 0x2466c9 VMOVQ	%XMM4,%R15

(263) 0x2466ce VMOVSD	(%R8,%R15,8),%XMM28

(263) 0x2466d5 VPEXTRQ	$0x1,%XMM4,%R15

(263) 0x2466db VMOVSD	(%R8,%RAX,8),%XMM4

(263) 0x2466e1 VMOVHPD	(%R8,%R15,8),%XMM28,%XMM28

(263) 0x2466e8 VMOVHPD	(%R8,%RBX,8),%XMM4,%XMM4

(263) 0x2466ee VINSERTF32X4	$0x1,%XMM11,%YMM29,%YMM11

(263) 0x2466f5 VINSERTF32X4	$0x1,%XMM28,%YMM4,%YMM4

(263) 0x2466fc VADDPD	%YMM4,%YMM19,%YMM4

(263) 0x246702 VPADDQ	%YMM24,%YMM30,%YMM19

(263) 0x246708 VEXTRACTI32X4	$0x1,%YMM19,%XMM28

(263) 0x24670f VMOVQ	%XMM28,%RAX

(263) 0x246715 VPEXTRQ	$0x1,%XMM28,%RBX

(263) 0x24671c VMOVSD	(%R8,%RAX,8),%XMM28

(263) 0x246723 VPEXTRQ	$0x1,%XMM19,%RAX

(263) 0x24672a VMOVHPD	(%R8,%RBX,8),%XMM28,%XMM28

(263) 0x246731 VMOVQ	%XMM19,%RBX

(263) 0x246737 VMOVSD	(%R8,%RBX,8),%XMM19

(263) 0x24673e VMOVHPD	(%R8,%RAX,8),%XMM19,%XMM19

(263) 0x246745 MOV	0x18(%RSP),%RAX

(263) 0x24674a VINSERTF32X4	$0x1,%XMM28,%YMM19,%YMM19

(263) 0x246751 VADDPD	%YMM19,%YMM11,%YMM11

(263) 0x246757 VMULPD	%YMM25,%YMM27,%YMM19

(263) 0x24675d VADDPD	%YMM4,%YMM11,%YMM25

(263) 0x246763 VMOVSD	(%R11,%RDX,8),%XMM4

(263) 0x246769 VMOVHPD	(%R11,%R14,8),%XMM4,%XMM4

(263) 0x24676f VFNMSUB213PD	%YMM19,%YMM10,%YMM25

(263) 0x246775 VMOVSD	(%R11,%RCX,8),%XMM10

(263) 0x24677b MOV	0x28(%RBP),%RCX

(263) 0x24677f VMOVHPD	(%R11,%RAX,8),%XMM10,%XMM10

(263) 0x246785 VINSERTF128	$0x1,%XMM4,%YMM10,%YMM4

(263) 0x24678b VPMULLQ	%YMM23,%YMM7,%YMM10

(263) 0x246791 VADDPD	%YMM4,%YMM18,%YMM4

(263) 0x246797 VPADDQ	%YMM21,%YMM10,%YMM10

(263) 0x24679d VMOVQ	%XMM10,%RAX

(263) 0x2467a2 VPEXTRQ	$0x1,%XMM10,%RDX

(263) 0x2467a8 VADDPD	%YMM4,%YMM3,%YMM3

(263) 0x2467ac VEXTRACTI128	$0x1,%YMM10,%XMM4

(263) 0x2467b2 VPMULLQ	%YMM23,%YMM8,%YMM10

(263) 0x2467b8 VMOVQ	%XMM4,%R14

(263) 0x2467bd VPEXTRQ	$0x1,%XMM4,%RBX

(263) 0x2467c3 VMOVSD	(%RSI,%RAX,8),%XMM4

(263) 0x2467c8 VMOVHPD	(%RSI,%RDX,8),%XMM4,%XMM4

(263) 0x2467cd VFMADD231PD	%YMM3,%YMM26,%YMM25

(263) 0x2467d3 VMOVSD	(%RSI,%R14,8),%XMM3

(263) 0x2467d9 VPADDQ	%YMM21,%YMM10,%YMM11

(263) 0x2467df VPADDQ	%YMM24,%YMM10,%YMM10

(263) 0x2467e5 VMOVHPD	(%RSI,%RBX,8),%XMM3,%XMM3

(263) 0x2467ea VMOVQ	%XMM11,%RAX

(263) 0x2467ef VPEXTRQ	$0x1,%XMM11,%RDX

(263) 0x2467f5 VEXTRACTI128	$0x1,%YMM11,%XMM11

(263) 0x2467fb VMOVQ	%XMM11,%RBX

(263) 0x246800 VPEXTRQ	$0x1,%XMM11,%R14

(263) 0x246806 VINSERTF32X4	$0x1,%XMM3,%YMM4,%YMM26

(263) 0x24680d VMOVSD	(%R10,%RAX,8),%XMM4

(263) 0x246813 VMOVSD	(%R10,%RBX,8),%XMM3

(263) 0x246819 VMOVQ	%XMM10,%RAX

(263) 0x24681e VMOVHPD	(%R10,%RDX,8),%XMM4,%XMM4

(263) 0x246824 VMOVHPD	(%R10,%R14,8),%XMM3,%XMM3

(263) 0x24682a VPEXTRQ	$0x1,%XMM10,%RDX

(263) 0x246830 VEXTRACTI128	$0x1,%YMM10,%XMM10

(263) 0x246836 VMOVSD	(%R10,%RAX,8),%XMM18

(263) 0x24683d VMOVQ	%XMM10,%RBX

(263) 0x246842 VPEXTRQ	$0x1,%XMM10,%R14

(263) 0x246848 VPMULLQ	%YMM23,%YMM9,%YMM10

(263) 0x24684e VMOVHPD	(%R10,%RDX,8),%XMM18,%XMM18

(263) 0x246855 VPADDQ	%YMM21,%YMM10,%YMM11

(263) 0x24685b VPADDQ	%YMM24,%YMM10,%YMM10

(263) 0x246861 VMOVQ	%XMM10,%RAX

(263) 0x246866 VPEXTRQ	$0x1,%XMM10,%RDX

(263) 0x24686c VEXTRACTI128	$0x1,%YMM10,%XMM10

(263) 0x246872 VINSERTF128	$0x1,%XMM3,%YMM4,%YMM3

(263) 0x246878 VEXTRACTI128	$0x1,%YMM11,%XMM4

(263) 0x24687e VMOVQ	%XMM4,%R15

(263) 0x246883 VPEXTRQ	$0x1,%XMM4,%R12

(263) 0x246889 VMOVSD	(%R8,%R15,8),%XMM4

(263) 0x24688f VMOVQ	%XMM11,%R15

(263) 0x246894 VMOVHPD	(%R8,%R12,8),%XMM4,%XMM4

(263) 0x24689a VPEXTRQ	$0x1,%XMM11,%R12

(263) 0x2468a0 VMOVSD	(%R8,%R15,8),%XMM11

(263) 0x2468a6 MOV	0xd0(%RSP),%R15

(263) 0x2468ae VMOVHPD	(%R8,%R12,8),%XMM11,%XMM11

(263) 0x2468b4 VINSERTF128	$0x1,%XMM4,%YMM11,%YMM4

(263) 0x2468ba VMOVSD	(%R10,%RBX,8),%XMM11

(263) 0x2468c0 VMOVQ	%XMM10,%RBX

(263) 0x2468c5 VMOVHPD	(%R10,%R14,8),%XMM11,%XMM11

(263) 0x2468cb VPEXTRQ	$0x1,%XMM10,%R14

(263) 0x2468d1 VMOVSD	(%R8,%RAX,8),%XMM10

(263) 0x2468d7 VADDPD	%YMM4,%YMM3,%YMM3

(263) 0x2468db VMOVSD	(%R8,%RBX,8),%XMM4

(263) 0x2468e1 VMOVHPD	(%R8,%RDX,8),%XMM10,%XMM10

(263) 0x2468e7 VMOVHPD	(%R8,%R14,8),%XMM4,%XMM4

(263) 0x2468ed VINSERTF32X4	$0x1,%XMM11,%YMM18,%YMM11

(263) 0x2468f4 VPMULLQ	%YMM22,%YMM13,%YMM18

(263) 0x2468fa VINSERTF128	$0x1,%XMM4,%YMM10,%YMM4

(263) 0x246900 VPMULLQ	0x160(%RSP),%YMM22,%YMM10

(263) 0x246908 VPADDQ	%YMM21,%YMM18,%YMM18

(263) 0x24690e VADDPD	%YMM4,%YMM11,%YMM4

(263) 0x246912 VADDPD	%YMM3,%YMM4,%YMM3

(263) 0x246916 VFMADD213PD	%YMM25,%YMM26,%YMM3

(263) 0x24691c VPADDQ	%YMM21,%YMM10,%YMM10

(263) 0x246922 VMOVQ	%XMM10,%RAX

(263) 0x246927 VPEXTRQ	$0x1,%XMM10,%RDX

(263) 0x24692d VEXTRACTI128	$0x1,%YMM10,%XMM10

(263) 0x246933 VMOVQ	%XMM10,%RBX

(263) 0x246938 VMOVSD	(%R15,%RAX,8),%XMM11

(263) 0x24693e VPEXTRQ	$0x1,%XMM10,%R14

(263) 0x246944 VMOVSD	(%R15,%RBX,8),%XMM10

(263) 0x24694a VMOVHPD	(%R15,%RDX,8),%XMM11,%XMM11

(263) 0x246950 VMOVHPD	(%R15,%R14,8),%XMM10,%XMM10

(263) 0x246956 MOV	0xc8(%RSP),%R15

(263) 0x24695e VINSERTF32X4	$0x1,%XMM10,%YMM11,%YMM23

(263) 0x246965 VPMULLQ	0x140(%RSP),%YMM22,%YMM10

(263) 0x24696d VPADDQ	%YMM21,%YMM10,%YMM10

(263) 0x246973 VMOVQ	%XMM10,%RAX

(263) 0x246978 VPEXTRQ	$0x1,%XMM10,%RDX

(263) 0x24697e VEXTRACTI128	$0x1,%YMM10,%XMM10

(263) 0x246984 VMOVQ	%XMM10,%RBX

(263) 0x246989 VPEXTRQ	$0x1,%XMM10,%R14

(263) 0x24698f VMOVSD	(%R15,%RAX,8),%XMM10

(263) 0x246995 VMOVSD	(%R15,%RBX,8),%XMM4

(263) 0x24699b VMOVHPD	(%R15,%RDX,8),%XMM10,%XMM10

(263) 0x2469a1 VMOVHPD	(%R15,%R14,8),%XMM4,%XMM4

(263) 0x2469a7 VINSERTF128	$0x1,%XMM4,%YMM10,%YMM4

(263) 0x2469ad VPMULLQ	%YMM22,%YMM12,%YMM10

(263) 0x2469b3 VPADDQ	%YMM21,%YMM10,%YMM10

(263) 0x2469b9 VMOVQ	%XMM10,%RAX

(263) 0x2469be VPEXTRQ	$0x1,%XMM10,%RDX

(263) 0x2469c4 VEXTRACTI128	$0x1,%YMM10,%XMM10

(263) 0x2469ca VMOVQ	%XMM10,%RBX

(263) 0x2469cf VMOVSD	(%R13,%RAX,8),%XMM11

(263) 0x2469d6 VPEXTRQ	$0x1,%XMM10,%R12

(263) 0x2469dc MOV	%RAX,0x18(%RSP)

(263) 0x2469e1 MOV	%RDI,%RAX

(263) 0x2469e4 MOV	0xc0(%RSP),%RDI

(263) 0x2469ec VMOVSD	(%R13,%RBX,8),%XMM10

(263) 0x2469f3 VMOVHPD	(%R13,%RDX,8),%XMM11,%XMM11

(263) 0x2469fa VMOVHPD	(%R13,%R12,8),%XMM10,%XMM10

(263) 0x246a01 VINSERTF128	$0x1,%XMM10,%YMM11,%YMM10

(263) 0x246a07 VEXTRACTI32X4	$0x1,%YMM18,%XMM11

(263) 0x246a0e VMOVQ	%XMM11,%R14

(263) 0x246a13 VPEXTRQ	$0x1,%XMM11,%R15

(263) 0x246a19 VMOVSD	(%RDI,%R14,8),%XMM11

(263) 0x246a1f VMOVQ	%XMM18,%R14

(263) 0x246a25 VMULPD	%YMM23,%YMM10,%YMM10

(263) 0x246a2b VMOVHPD	(%RDI,%R15,8),%XMM11,%XMM11

(263) 0x246a31 VPEXTRQ	$0x1,%XMM18,%R15

(263) 0x246a38 VMOVSD	-0x358b2(%RIP),%XMM18

(263) 0x246a42 VMULSD	(%RCX),%XMM18,%XMM18

(263) 0x246a48 MOV	0x38(%RSP),%RCX

(263) 0x246a4d VBROADCASTSD	%XMM18,%YMM18

(263) 0x246a53 VMULPD	%YMM3,%YMM18,%YMM3

(263) 0x246a59 VMOVSD	(%RDI,%R14,8),%XMM18

(263) 0x246a60 VMOVHPD	(%RDI,%R15,8),%XMM18,%XMM18

(263) 0x246a67 MOV	%RAX,%RDI

(263) 0x246a6a VINSERTF32X4	$0x1,%XMM11,%YMM18,%YMM11

(263) 0x246a71 VADDPD	%YMM4,%YMM11,%YMM4

(263) 0x246a75 VMULPD	%YMM3,%YMM4,%YMM4

(263) 0x246a79 VADDPD	%YMM23,%YMM3,%YMM3

(263) 0x246a7f VDIVPD	%YMM10,%YMM4,%YMM4

(263) 0x246a84 VPMULLQ	%YMM22,%YMM14,%YMM10

(263) 0x246a8a VPADDQ	%YMM21,%YMM10,%YMM10

(263) 0x246a90 VEXTRACTI128	$0x1,%YMM10,%XMM11

(263) 0x246a96 VMOVQ	%XMM11,%R15

(263) 0x246a9b VPEXTRQ	$0x1,%XMM11,%R14

(263) 0x246aa1 VMOVSD	(%RAX,%R15,8),%XMM11

(263) 0x246aa7 VMOVQ	%XMM10,%R15

(263) 0x246aac VMOVHPD	(%RAX,%R14,8),%XMM11,%XMM11

(263) 0x246ab2 VPEXTRQ	$0x1,%XMM10,%R14

(263) 0x246ab8 VMOVSD	(%RAX,%R15,8),%XMM10

(263) 0x246abe VMOVHPD	(%RAX,%R14,8),%XMM10,%XMM10

(263) 0x246ac4 MOV	0xb8(%RSP),%RAX

(263) 0x246acc VINSERTF128	$0x1,%XMM11,%YMM10,%YMM10

(263) 0x246ad2 VSUBPD	%YMM4,%YMM10,%YMM4

(263) 0x246ad6 VPMULLQ	%YMM22,%YMM15,%YMM10

(263) 0x246adc VPADDQ	%YMM21,%YMM10,%YMM10

(263) 0x246ae2 VMOVQ	%XMM10,%R14

(263) 0x246ae7 VMOVLPD	%XMM4,(%RAX,%R14,8)

(263) 0x246aed VPEXTRQ	$0x1,%XMM10,%R14

(263) 0x246af3 VEXTRACTI128	$0x1,%YMM10,%XMM10

(263) 0x246af9 VMOVHPD	%XMM4,(%RAX,%R14,8)

(263) 0x246aff VEXTRACTF128	$0x1,%YMM4,%XMM4

(263) 0x246b05 VMOVQ	%XMM10,%R14

(263) 0x246b0a VMOVLPD	%XMM4,(%RAX,%R14,8)

(263) 0x246b10 VPEXTRQ	$0x1,%XMM10,%R14

(263) 0x246b16 VMOVHPD	%XMM4,(%RAX,%R14,8)

(263) 0x246b1c MOV	0x18(%RSP),%RAX

(263) 0x246b21 VMOVSD	(%R13,%RBX,8),%XMM4

(263) 0x246b28 VMOVHPD	(%R13,%R12,8),%XMM4,%XMM4

(263) 0x246b2f VMOVSD	(%R13,%RAX,8),%XMM10

(263) 0x246b36 VMOVHPD	(%R13,%RDX,8),%XMM10,%XMM10

(263) 0x246b3d VINSERTF128	$0x1,%XMM4,%YMM10,%YMM4

(263) 0x246b43 VMULPD	%YMM23,%YMM4,%YMM4

(263) 0x246b49 VDIVPD	%YMM3,%YMM4,%YMM3

(263) 0x246b4d VPMULLQ	%YMM22,%YMM16,%YMM4

(263) 0x246b53 VPADDQ	%YMM21,%YMM4,%YMM4

(263) 0x246b59 VMOVQ	%XMM4,%RDX

(263) 0x246b5e VPEXTRQ	$0x1,%XMM4,%RAX

(263) 0x246b64 VEXTRACTI128	$0x1,%YMM4,%XMM4

(263) 0x246b6a VMOVQ	%XMM4,%RBX

(263) 0x246b6f VPEXTRQ	$0x1,%XMM4,%R14

(263) 0x246b75 VMOVLPD	%XMM3,(%RCX,%RDX,8)

(263) 0x246b7a MOV	0x38(%RSP),%RCX

(263) 0x246b7f VMOVHPD	%XMM3,(%RCX,%RAX,8)

(263) 0x246b84 MOV	0x20(%RSP),%RAX

(263) 0x246b89 VEXTRACTF128	$0x1,%YMM3,%XMM3

(263) 0x246b8f VMOVLPD	%XMM3,(%RCX,%RBX,8)

(263) 0x246b94 VMOVHPD	%XMM3,(%RCX,%R14,8)

(263) 0x246b9a ADD	$-0x4,%RAX

(263) 0x246b9e JNE	246230

0x246ba4 MOV	0xe8(%RSP),%RAX

0x246bac MOV	0xb0(%RSP),%R12

0x246bb4 MOV	0xc(%RSP),%R14D

0x246bb9 MOV	0xa8(%RSP),%R15

0x246bc1 MOV	0x28(%RSP),%RCX

0x246bc6 CMP	%RAX,0xf0(%RSP)

0x246bce JE	246e5c

0x246bd4 VMOVSD	-0x35a4c(%RIP),%XMM0

0x246bdc NOPL	(%RAX)

(264) 0x246be0 MOV	%RCX,%RAX

(264) 0x246be3 CQTO

(264) 0x246be5 MOV	%RCX,0x28(%RSP)

(264) 0x246bea IDIV	%R15

(264) 0x246bed MOV	0x98(%RSP),%RDI

(264) 0x246bf5 ADD	%R14D,%EDX

(264) 0x246bf8 MOVSXD	%EDX,%RDX

(264) 0x246bfb MOV	%RDI,%R14

(264) 0x246bfe LEA	(%R12,%RAX,1),%EBX

(264) 0x246c02 LEA	0x1(%R12,%RAX,1),%EAX

(264) 0x246c07 MOV	%RDI,%R12

(264) 0x246c0a MOV	0x90(%RSP),%RDI

(264) 0x246c12 MOVSXD	%EBX,%RBX

(264) 0x246c15 CLTQ

(264) 0x246c17 IMUL	%RBX,%R14

(264) 0x246c1b IMUL	%RAX,%R12

(264) 0x246c1f LEA	(%R14,%RDX,1),%R15

(264) 0x246c23 LEA	(%R12,%RDX,1),%RCX

(264) 0x246c27 VMOVSD	(%R9,%RCX,8),%XMM1

(264) 0x246c2d MOV	%RDI,%RCX

(264) 0x246c30 IMUL	%RBX,%RCX

(264) 0x246c34 VADDSD	(%R9,%R15,8),%XMM1,%XMM1

(264) 0x246c3a LEA	(%RCX,%RDX,1),%R15

(264) 0x246c3e LEA	0x1(%RCX,%RDX,1),%RCX

(264) 0x246c43 VADDSD	(%R11,%R15,8),%XMM1,%XMM1

(264) 0x246c49 MOV	%RDI,%R15

(264) 0x246c4c IMUL	%RAX,%R15

(264) 0x246c50 LEA	(%R15,%RDX,1),%RDI

(264) 0x246c54 VADDSD	(%R11,%RDI,8),%XMM1,%XMM1

(264) 0x246c5a LEA	0x1(%R12,%RDX,1),%RDI

(264) 0x246c5f MOV	0xb0(%RSP),%R12

(264) 0x246c67 VMOVSD	(%R9,%RDI,8),%XMM2

(264) 0x246c6d LEA	0x1(%R14,%RDX,1),%RDI

(264) 0x246c72 MOV	0x108(%RSP),%R14

(264) 0x246c7a VADDSD	(%R9,%RDI,8),%XMM2,%XMM2

(264) 0x246c80 VADDSD	(%R11,%RCX,8),%XMM2,%XMM2

(264) 0x246c86 LEA	0x1(%R15,%RDX,1),%RCX

(264) 0x246c8b MOV	0xa8(%RSP),%R15

(264) 0x246c93 VADDSD	(%R11,%RCX,8),%XMM2,%XMM2

(264) 0x246c99 MOV	%R14,%RCX

(264) 0x246c9c IMUL	%RBX,%RCX

(264) 0x246ca0 LEA	0x1(%RCX,%RDX,1),%RDI

(264) 0x246ca5 ADD	%RDX,%RCX

(264) 0x246ca8 VMOVSD	(%R10,%RDI,8),%XMM3

(264) 0x246cae VADDSD	(%R10,%RCX,8),%XMM3,%XMM3

(264) 0x246cb4 MOV	0x30(%RSP),%RCX

(264) 0x246cb9 IMUL	%RBX,%RCX

(264) 0x246cbd LEA	(%RCX,%RDX,1),%RDI

(264) 0x246cc1 LEA	0x1(%RCX,%RDX,1),%RCX

(264) 0x246cc6 VADDSD	(%R8,%RDI,8),%XMM3,%XMM3

(264) 0x246ccc VADDSD	(%R8,%RCX,8),%XMM3,%XMM3

(264) 0x246cd2 MOV	%R14,%RCX

(264) 0x246cd5 IMUL	%RAX,%RCX

(264) 0x246cd9 MOV	0x88(%RSP),%R14

(264) 0x246ce1 LEA	0x1(%RCX,%RDX,1),%RDI

(264) 0x246ce6 ADD	%RDX,%RCX

(264) 0x246ce9 VMOVSD	(%R10,%RDI,8),%XMM4

(264) 0x246cef MOV	%R14,%RDI

(264) 0x246cf2 IMUL	%RAX,%RDI

(264) 0x246cf6 IMUL	0x30(%RSP),%RAX

(264) 0x246cfc VADDSD	(%R10,%RCX,8),%XMM4,%XMM4

(264) 0x246d02 ADD	%RDX,%RDI

(264) 0x246d05 LEA	(%RAX,%RDX,1),%RCX

(264) 0x246d09 LEA	0x1(%RAX,%RDX,1),%RAX

(264) 0x246d0e VADDSD	(%R8,%RCX,8),%XMM4,%XMM4

(264) 0x246d14 MOV	0xa0(%RSP),%RCX

(264) 0x246d1c VADDSD	(%R8,%RAX,8),%XMM4,%XMM4

(264) 0x246d22 IMUL	%RBX,%RCX

(264) 0x246d26 LEA	(%RCX,%RDX,1),%RAX

(264) 0x246d2a LEA	0x1(%RCX,%RDX,1),%RCX

(264) 0x246d2f MOV	%RCX,0x20(%RSP)

(264) 0x246d34 MOV	0xd8(%RSP),%RCX

(264) 0x246d3c VMULSD	(%RCX,%RAX,8),%XMM1,%XMM1

(264) 0x246d41 MOV	%R14,%RAX

(264) 0x246d44 IMUL	%RBX,%RAX

(264) 0x246d48 MOV	0xc(%RSP),%R14D

(264) 0x246d4d ADD	%RDX,%RAX

(264) 0x246d50 VFNMSUB231SD	(%RSI,%RAX,8),%XMM3,%XMM1

(264) 0x246d56 MOV	0x20(%RSP),%RAX

(264) 0x246d5b VFMADD231SD	(%RCX,%RAX,8),%XMM2,%XMM1

(264) 0x246d61 MOV	0x28(%RBP),%RAX

(264) 0x246d65 MOV	0xd0(%RSP),%RCX

(264) 0x246d6d VFMADD231SD	(%RSI,%RDI,8),%XMM4,%XMM1

(264) 0x246d73 MOV	0xc0(%RSP),%RDI

(264) 0x246d7b VMULSD	(%RAX),%XMM0,%XMM2

(264) 0x246d7f MOV	0x100(%RSP),%RAX

(264) 0x246d87 IMUL	%RBX,%RAX

(264) 0x246d8b ADD	%RDX,%RAX

(264) 0x246d8e VMOVSD	(%RCX,%RAX,8),%XMM5

(264) 0x246d93 MOV	0x78(%RSP),%RCX

(264) 0x246d98 MOV	0x80(%RSP),%RAX

(264) 0x246da0 VMULSD	%XMM1,%XMM2,%XMM1

(264) 0x246da4 IMUL	%RBX,%RCX

(264) 0x246da8 IMUL	%RBX,%RAX

(264) 0x246dac ADD	%RDX,%RCX

(264) 0x246daf ADD	%RDX,%RAX

(264) 0x246db2 VMOVSD	(%RDI,%RCX,8),%XMM3

(264) 0x246db7 MOV	0xf8(%RSP),%RCX

(264) 0x246dbf MOV	0xc8(%RSP),%RDI

(264) 0x246dc7 IMUL	%RBX,%RCX

(264) 0x246dcb VADDSD	(%RDI,%RAX,8),%XMM3,%XMM3

(264) 0x246dd0 MOV	0x68(%RSP),%RAX

(264) 0x246dd5 MOV	0x70(%RSP),%RDI

(264) 0x246dda ADD	%RDX,%RCX

(264) 0x246ddd VMULSD	(%R13,%RCX,8),%XMM5,%XMM4

(264) 0x246de4 MOV	%RSI,%R13

(264) 0x246de7 MOV	0xb8(%RSP),%RSI

(264) 0x246def IMUL	%RBX,%RAX

(264) 0x246df3 ADD	%RDX,%RAX

(264) 0x246df6 VMULSD	%XMM1,%XMM3,%XMM3

(264) 0x246dfa VADDSD	%XMM5,%XMM1,%XMM1

(264) 0x246dfe VDIVSD	%XMM4,%XMM3,%XMM3

(264) 0x246e02 VMOVSD	(%RDI,%RAX,8),%XMM4

(264) 0x246e07 MOV	0x60(%RSP),%RAX

(264) 0x246e0c IMUL	%RBX,%RAX

(264) 0x246e10 IMUL	0x58(%RSP),%RBX

(264) 0x246e16 ADD	%RDX,%RAX

(264) 0x246e19 ADD	%RDX,%RBX

(264) 0x246e1c MOV	0x38(%RSP),%RDX

(264) 0x246e21 VSUBSD	%XMM3,%XMM4,%XMM3

(264) 0x246e25 VMOVSD	%XMM3,(%RSI,%RAX,8)

(264) 0x246e2a MOV	%R13,%RSI

(264) 0x246e2d MOV	0x10(%RSP),%R13

(264) 0x246e32 MOV	0x28(%RSP),%RAX

(264) 0x246e37 VMULSD	(%R13,%RCX,8),%XMM5,%XMM3

(264) 0x246e3e MOV	0x110(%RSP),%RCX

(264) 0x246e46 VDIVSD	%XMM1,%XMM3,%XMM1

(264) 0x246e4a VMOVSD	%XMM1,(%RDX,%RBX,8)

(264) 0x246e4f CMP	%RCX,%RAX

(264) 0x246e52 LEA	0x1(%RAX),%RCX

(264) 0x246e56 JL	246be0

0x246e5c MOV	0x48(%RSP),%ESI

0x246e60 LEA	0x14871(%RIP),%RDI

0x246e67 VZEROUPPER

0x246e6a CALL	259690 <@plt_start@+0x540>

0x246e6f LEA	-0x28(%RBP),%RSP

0x246e73 POP	%RBX

0x246e74 POP	%R12

0x246e76 POP	%R13

0x246e78 POP	%R14

0x246e7a POP	%R15

0x246e7c POP	%RBP

0x246e7d RET

0x246e7e XCHG	%AX,%AX

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run aocc_8

Source file and lines	PdV.cpp:69-83
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:69-83
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 28.25 to 9.50 cycles (2.97x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 13% of vector register length is used (average across all SSE/AVX instructions).

Details

9% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

5% of SSE/AVX loads are used in vector version.
12% of SSE/AVX stores are used in vector version.
12% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
11% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 28.25 to 25.75 cycles (1.10x speedup).

Workaround

Read less array elements
Write less array elements

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:69

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVL: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:70
VPBROADCASTD: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:70
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:70
VPBROADCASTQ: 15 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:70
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:70
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:70
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:70
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:70
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:70
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:70
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:70
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:70
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:70
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:70
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:70
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:70
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:70
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:70

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 564 bytes. The binary function is storing 396 bytes.

General properties

nb instructions	189
nb uops	206
loop length	944
used x86 registers	16
used mmx registers	0
used xmm registers	3
used ymm registers	14
used zmm registers	0
nb stack references	54

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	25.75 cycles
front end	25.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	6.67	6.67	6.67	6.67	6.67	6.67	28.25	28.25	28.25	28.25	1.00	9.50	9.50	1.00	2.50	2.50
cycles	6.67	6.67	6.67	6.67	6.67	6.67	28.25	28.25	28.25	28.25	1.00	9.50	9.50	1.00	2.50	2.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	25.75
Dispatch	28.25
Overall L1	28.25

Vectorization ratios

INT

all	10%
load	5%
store	12%
mul	0%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	9%
load	5%
store	12%
mul	0%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Vector efficiency ratios

INT

all	13%
load	12%
store	15%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	13%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	13%
load	12%
store	15%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 28.25 cycles. At this rate:

7% of peak load performance is reached (19.96 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
10% of peak store performance is reached (14.02 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 245ee0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND $-0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB $0x1c0,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RDX),%R12D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
MOV (%RCX),%EBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
INC %R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD $0x2,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SUB %R12D,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 246e6f <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined.2+0xf8f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV (%R9),%R15D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
MOV (%R8),%R14D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
INC %R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD $0x2,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CMP %R14D,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 246e6f <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined.2+0xf8f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
SUB %R14D,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOVQ $0,0xe0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOVQ $0x1,0x118(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOVL $0,0x4c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
IMUL %R15,%RBX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
DEC %RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RBX,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x54(%RSP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x120(%RSP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x15755(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0xe8(%RSP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x48(%RSP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %ESI,0x50(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 259680 <@plt_start@+0x530>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x40(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xe0(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CMP %RBX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMOVL %RAX,%RBX	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
MOV %RBX,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
CMP %RBX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JG 246e5c <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined.2+0xf7c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x10(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x18(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x20(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x30(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x48(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x40(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x38(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R12,0xb0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R14D,0xc(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV %R15,0xa8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RBX,0x110(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RDI),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%RDI),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,0xd8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%R9),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R11,0xa0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x10(%R10),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%R9),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,0x98(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%R10),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%R8),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,0x90(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RSI),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RSI),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,0x88(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RSI,0x50(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%R8),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RDX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RDX),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RAX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RAX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,0xd0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x50(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RSI,0x108(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDX,0x100(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RAX),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%RAX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,0xc8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x58(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R13,0x80(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RAX),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%RAX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x60(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R13,0xf8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RAX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RAX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,0xc0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x70(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,0x78(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RAX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RAX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,0x70(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x68(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,0x68(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RAX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RAX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,0xb8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x78(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,0x60(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RAX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RAX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RBX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RCX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDI,0x58(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x4,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 246110 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined.2+0x230>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x50(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RSP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
JMP 246bd4 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined.2+0xcf4>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV 0xa0(%RSP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
VPBROADCASTQ %RSI,%YMM8	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
MOV 0x30(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VPBROADCASTD %R12D,%XMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (6.3%)
MOV 0x98(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VPBROADCASTQ %RCX,%YMM0	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
VPADDQ -0x34e5f(%RIP),%YMM0,%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (50.0%)
VPBROADCASTQ -0x34f79(%RIP),%YMM20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VPBROADCASTQ %R13,%YMM12	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
MOV 0x10(%RSP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV %RAX,0xf0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
AND $-0x4,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VPBROADCASTQ %R15,%YMM1	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
VMOVDQA %XMM2,0x130(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VPBROADCASTD %R14D,%XMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (6.3%)
ADD %RAX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VEXTRACTI32X4 $0x1,%YMM1,%XMM17	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
MOV %RAX,0xe8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVDQA %XMM2,0x120(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
MOV %RCX,0x28(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VPBROADCASTQ %RBX,%YMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
VPBROADCASTQ %RSI,%YMM9	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
MOV 0x78(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VPBROADCASTQ %RDI,%YMM5	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
MOV 0x88(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x90(%RSP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
VMOVDQA %YMM2,0x180(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPBROADCASTQ %RDX,%YMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
MOV 0x80(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVDQA %YMM2,0x160(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPBROADCASTQ %RSI,%YMM13	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
MOV 0x60(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VPBROADCASTQ %RDI,%YMM7	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
MOV 0x70(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VPBROADCASTQ %RBX,%YMM6	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
VPBROADCASTQ %RDX,%YMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
MOV 0x68(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVDQA %YMM2,0x140(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPCMPEQD %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VPBROADCASTQ %RSI,%YMM15	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
MOV 0x50(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VPBROADCASTQ %RDX,%YMM14	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
MOV 0x58(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VPBROADCASTQ %RDX,%YMM16	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV 0xe8(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xb0(%RSP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0xc(%RSP),%R14D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
MOV 0xa8(%RSP),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x28(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CMP %RAX,0xf0(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
JE 246e5c <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined.2+0xf7c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVSD -0x35a4c(%RIP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV 0x48(%RSP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA 0x14871(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 259690 <@plt_start@+0x540>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run aocc_8

Source file and lines	PdV.cpp:69-83
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:69-83
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 28.25 to 9.50 cycles (2.97x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 13% of vector register length is used (average across all SSE/AVX instructions).

Details

9% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

5% of SSE/AVX loads are used in vector version.
12% of SSE/AVX stores are used in vector version.
12% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
11% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 28.25 to 25.75 cycles (1.10x speedup).

Workaround

Read less array elements
Write less array elements

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:69

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVL: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:70
VPBROADCASTD: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:70
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:70
VPBROADCASTQ: 15 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:70
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:70
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:70
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:70
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:70
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:70
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:70
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:70
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:70
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:70
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:70
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:70
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:70
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:70
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:70

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 564 bytes. The binary function is storing 396 bytes.

General properties

nb instructions	189
nb uops	206
loop length	944
used x86 registers	16
used mmx registers	0
used xmm registers	3
used ymm registers	14
used zmm registers	0
nb stack references	54

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	25.75 cycles
front end	25.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	6.67	6.67	6.67	6.67	6.67	6.67	28.25	28.25	28.25	28.25	1.00	9.50	9.50	1.00	2.50	2.50
cycles	6.67	6.67	6.67	6.67	6.67	6.67	28.25	28.25	28.25	28.25	1.00	9.50	9.50	1.00	2.50	2.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	25.75
Dispatch	28.25
Overall L1	28.25

Vectorization ratios

INT

all	10%
load	5%
store	12%
mul	0%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	9%
load	5%
store	12%
mul	0%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Vector efficiency ratios

INT

all	13%
load	12%
store	15%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	13%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	13%
load	12%
store	15%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 28.25 cycles. At this rate:

7% of peak load performance is reached (19.96 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
10% of peak store performance is reached (14.02 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 245ee0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND $-0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB $0x1c0,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RDX),%R12D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
MOV (%RCX),%EBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
INC %R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD $0x2,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SUB %R12D,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 246e6f <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined.2+0xf8f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV (%R9),%R15D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
MOV (%R8),%R14D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
INC %R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD $0x2,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CMP %R14D,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 246e6f <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined.2+0xf8f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
SUB %R14D,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOVQ $0,0xe0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOVQ $0x1,0x118(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOVL $0,0x4c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
IMUL %R15,%RBX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
DEC %RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RBX,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x54(%RSP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x120(%RSP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x15755(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0xe8(%RSP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x48(%RSP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %ESI,0x50(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 259680 <@plt_start@+0x530>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x40(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xe0(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CMP %RBX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMOVL %RAX,%RBX	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
MOV %RBX,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
CMP %RBX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JG 246e5c <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined.2+0xf7c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x10(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x18(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x20(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x30(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x48(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x40(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x38(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R12,0xb0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R14D,0xc(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV %R15,0xa8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RBX,0x110(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RDI),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%RDI),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,0xd8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%R9),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R11,0xa0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x10(%R10),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%R9),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,0x98(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%R10),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%R8),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,0x90(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RSI),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RSI),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,0x88(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RSI,0x50(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%R8),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RDX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RDX),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RAX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RAX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,0xd0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x50(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RSI,0x108(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDX,0x100(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RAX),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%RAX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,0xc8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x58(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R13,0x80(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RAX),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%RAX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x60(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R13,0xf8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RAX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RAX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,0xc0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x70(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,0x78(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RAX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RAX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,0x70(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x68(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,0x68(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RAX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RAX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,0xb8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x78(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,0x60(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RAX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RAX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RBX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RCX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDI,0x58(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x4,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 246110 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined.2+0x230>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x50(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RSP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
JMP 246bd4 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined.2+0xcf4>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV 0xa0(%RSP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
VPBROADCASTQ %RSI,%YMM8	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
MOV 0x30(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VPBROADCASTD %R12D,%XMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (6.3%)
MOV 0x98(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VPBROADCASTQ %RCX,%YMM0	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
VPADDQ -0x34e5f(%RIP),%YMM0,%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (50.0%)
VPBROADCASTQ -0x34f79(%RIP),%YMM20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VPBROADCASTQ %R13,%YMM12	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
MOV 0x10(%RSP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV %RAX,0xf0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
AND $-0x4,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VPBROADCASTQ %R15,%YMM1	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
VMOVDQA %XMM2,0x130(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VPBROADCASTD %R14D,%XMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (6.3%)
ADD %RAX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VEXTRACTI32X4 $0x1,%YMM1,%XMM17	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
MOV %RAX,0xe8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVDQA %XMM2,0x120(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
MOV %RCX,0x28(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VPBROADCASTQ %RBX,%YMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
VPBROADCASTQ %RSI,%YMM9	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
MOV 0x78(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VPBROADCASTQ %RDI,%YMM5	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
MOV 0x88(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x90(%RSP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
VMOVDQA %YMM2,0x180(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPBROADCASTQ %RDX,%YMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
MOV 0x80(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVDQA %YMM2,0x160(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPBROADCASTQ %RSI,%YMM13	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
MOV 0x60(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VPBROADCASTQ %RDI,%YMM7	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
MOV 0x70(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VPBROADCASTQ %RBX,%YMM6	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
VPBROADCASTQ %RDX,%YMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
MOV 0x68(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVDQA %YMM2,0x140(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPCMPEQD %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VPBROADCASTQ %RSI,%YMM15	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
MOV 0x50(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VPBROADCASTQ %RDX,%YMM14	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
MOV 0x58(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VPBROADCASTQ %RDX,%YMM16	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV 0xe8(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xb0(%RSP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0xc(%RSP),%R14D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
MOV 0xa8(%RSP),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x28(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CMP %RAX,0xf0(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
JE 246e5c <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined.2+0xf7c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVSD -0x35a4c(%RIP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV 0x48(%RSP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA 0x14871(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 259690 <@plt_start@+0x540>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	6.47	2.42
○Loop 263 - PdV.cpp:70-83 - exec	6.47	2.41
○Loop 264 - PdV.cpp:70-83 - exec	0.00	0.00

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