OV - exec - Function PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone .omp

	Function: PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D<double>&, clover::Buffer2D<d ...	Module: exec	Source: PdV.cpp:48-63 [...]	Coverage (incl. loops): 5.49% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp: 48 - 63

--------------------------------------------------------------------------------

48: #pragma omp parallel for simd collapse(2)

49:     for (int j = (y_min + 1); j < (y_max + 2); j++) {

50:       for (int i = (x_min + 1); i < (x_max + 2); i++) {

51:         double left_flux = (xarea(i, j) * (xvel0(i, j) + xvel0(i + 0, j + 1) + xvel0(i, j) + xvel0(i + 0, j + 1))) * 0.25 * dt * 0.5;

52:         double right_flux =

53:             (xarea(i + 1, j + 0) * (xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1) + xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1))) * 0.25 * dt *

54:             0.5;

55:         double bottom_flux = (yarea(i, j) * (yvel0(i, j) + yvel0(i + 1, j + 0) + yvel0(i, j) + yvel0(i + 1, j + 0))) * 0.25 * dt * 0.5;

56:         double top_flux = (yarea(i + 0, j + 1) * (yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1) + yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1))) *

57:                           0.25 * dt * 0.5;

58:         double total_flux = right_flux - left_flux + top_flux - bottom_flux;

59:         double volume_change_s = volume(i, j) / (volume(i, j) + total_flux);

60:         double recip_volume = 1.0 / volume(i, j);

61:         double energy_change = (pressure(i, j) / density0(i, j) + viscosity(i, j) / density0(i, j)) * total_flux * recip_volume;

62:         energy1(i, j) = energy0(i, j) - energy_change;

63:         density1(i, j) = density0(i, j) * volume_change_s;

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x2452a0 PUSH	%RBP

0x2452a1 MOV	%RSP,%RBP

0x2452a4 PUSH	%R15

0x2452a6 PUSH	%R14

0x2452a8 PUSH	%R13

0x2452aa PUSH	%R12

0x2452ac PUSH	%RBX

0x2452ad AND	$-0x20,%RSP

0x2452b1 SUB	$0x1e0,%RSP

0x2452b8 MOV	(%RDX),%R13D

0x2452bb MOV	(%RCX),%R15D

0x2452be INC	%R13D

0x2452c1 ADD	$0x2,%R15D

0x2452c5 SUB	%R13D,%R15D

0x2452c8 JLE	245ecd

0x2452ce MOV	(%R9),%EBX

0x2452d1 MOV	(%R8),%R14D

0x2452d4 INC	%R14D

0x2452d7 ADD	$0x2,%EBX

0x2452da CMP	%R14D,%EBX

0x2452dd JLE	245ecd

0x2452e3 SUB	%R14D,%EBX

0x2452e6 MOV	(%RDI),%ESI

0x2452e8 MOVQ	$0,0xb0(%RSP)

0x2452f4 MOVQ	$0x1,0xd8(%RSP)

0x245300 MOVL	$0,0x1c(%RSP)

0x245308 IMUL	%RBX,%R15

0x24530c DEC	%R15

0x24530f MOV	%R15,0x10(%RSP)

0x245314 SUB	$0x8,%RSP

0x245318 LEA	0x24(%RSP),%RCX

0x24531d LEA	0xe0(%RSP),%RAX

0x245325 LEA	0x1634c(%RIP),%RDI

0x24532c LEA	0xb8(%RSP),%R8

0x245334 LEA	0x18(%RSP),%R9

0x245339 MOV	%ESI,0x20(%RSP)

0x24533d MOV	$0x22,%EDX

0x245342 PUSH	$0x1

0x245344 PUSH	$0x1

0x245346 PUSH	%RAX

0x245347 CALL	259680 <@plt_start@+0x530>

0x24534c ADD	$0x20,%RSP

0x245350 MOV	0x10(%RSP),%RAX

0x245355 MOV	0xb0(%RSP),%RCX

0x24535d CMP	%R15,%RAX

0x245360 CMOVL	%RAX,%R15

0x245364 MOV	%R15,0x10(%RSP)

0x245369 CMP	%R15,%RCX

0x24536c JG	245eba

0x245372 MOV	0x10(%RBP),%R8

0x245376 MOV	0x18(%RBP),%R10

0x24537a MOV	0x28(%RBP),%R9

0x24537e MOV	0x38(%RBP),%RSI

0x245382 MOV	0x40(%RBP),%RDX

0x245386 MOV	0x30(%RBP),%R12

0x24538a MOV	%RBX,0x40(%RSP)

0x24538f MOV	0x48(%RBP),%RAX

0x245393 MOV	%R13,0x88(%RSP)

0x24539b MOV	%R14D,0x4(%RSP)

0x2453a0 MOV	(%R8),%RDI

0x2453a3 MOV	0x10(%R9),%RBX

0x2453a7 MOV	0x10(%R8),%R8

0x2453ab MOV	%RDI,0x80(%RSP)

0x2453b3 MOV	(%R10),%RDI

0x2453b6 MOV	0x10(%R10),%R10

0x2453ba MOV	%RDI,0x78(%RSP)

0x2453bf MOV	(%R9),%RDI

0x2453c2 MOV	(%R12),%R9

0x2453c6 MOV	%RDI,0x70(%RSP)

0x2453cb MOV	%RCX,%RDI

0x2453ce MOV	%RDI,%RCX

0x2453d1 MOV	(%RSI),%RDI

0x2453d4 MOV	%R9,0x68(%RSP)

0x2453d9 MOV	0x10(%R12),%R9

0x2453de MOV	0x10(%RSI),%RSI

0x2453e2 MOV	0x10(%RAX),%R12

0x2453e6 MOV	%RDI,0x60(%RSP)

0x2453eb MOV	(%RDX),%RDI

0x2453ee MOV	%RSI,0x30(%RSP)

0x2453f3 MOV	0x10(%RDX),%RDX

0x2453f7 MOV	%RDI,0x58(%RSP)

0x2453fc MOV	(%RAX),%RDI

0x2453ff MOV	0x50(%RBP),%RAX

0x245403 MOV	%RDX,0xa8(%RSP)

0x24540b MOV	(%RAX),%RSI

0x24540e MOV	%RDI,0x50(%RSP)

0x245413 MOV	%RSI,0x48(%RSP)

0x245418 MOV	0x10(%RAX),%RSI

0x24541c MOV	0x60(%RBP),%RAX

0x245420 MOV	(%RAX),%R11

0x245423 MOV	%RSI,0x98(%RSP)

0x24542b MOV	%R11,0x38(%RSP)

0x245430 MOV	0x10(%RAX),%R11

0x245434 MOV	0x58(%RBP),%RAX

0x245438 MOV	(%RAX),%RDI

0x24543b MOV	0x10(%RAX),%RDX

0x24543f MOV	0x68(%RBP),%RAX

0x245443 MOV	%R11,0xd0(%RSP)

0x24544b MOV	%RDI,0x28(%RSP)

0x245450 MOV	(%RAX),%RDI

0x245453 MOV	0x10(%RAX),%RAX

0x245457 MOV	%RDX,0x90(%RSP)

0x24545f MOV	%RDI,0x20(%RSP)

0x245464 MOV	%R15,%RDI

0x245467 SUB	%RCX,%RDI

0x24546a MOV	%RAX,0xa0(%RSP)

0x245472 INC	%RDI

0x245475 CMP	$0x4,%RDI

0x245479 JB	245cda

0x24547f MOV	0x80(%RSP),%RDX

0x245487 VPBROADCASTD	%R13D,%XMM2

0x24548d MOV	0x78(%RSP),%RSI

0x245492 MOV	0x40(%RSP),%RAX

0x245497 VPBROADCASTQ	%RCX,%YMM0

0x24549d VPADDQ	-0x341c5(%RIP),%YMM0,%YMM0

0x2454a5 VPBROADCASTQ	-0x342df(%RIP),%YMM18

0x2454af MOV	%RDI,0xc0(%RSP)

0x2454b7 AND	$-0x4,%RDI

0x2454bb MOV	%R15,0xc8(%RSP)

0x2454c3 VMOVDQA	%XMM2,0xf0(%RSP)

0x2454cc VPBROADCASTD	%R14D,%XMM2

0x2454d2 ADD	%RDI,%RCX

0x2454d5 MOV	%RDI,0xb8(%RSP)

0x2454dd VMOVDQA	%XMM2,0xe0(%RSP)

0x2454e6 VPBROADCASTQ	%RDX,%YMM2

0x2454ec MOV	0x70(%RSP),%RDX

0x2454f1 VPBROADCASTQ	%RSI,%YMM5

0x2454f7 MOV	0x68(%RSP),%RSI

0x2454fc VPBROADCASTQ	%RAX,%YMM1

0x245502 MOV	%RDI,%RAX

0x245505 MOV	0x30(%RSP),%RDI

0x24550a VMOVDQA	%YMM2,0x1a0(%RSP)

0x245513 VEXTRACTI128	$0x1,%YMM1,%XMM15

0x245519 VPBROADCASTQ	%RDX,%YMM6

0x24551f MOV	0x60(%RSP),%RDX

0x245524 VPBROADCASTQ	%RSI,%YMM7

0x24552a MOV	0x58(%RSP),%RSI

0x24552f VPBROADCASTQ	%RDX,%YMM2

0x245535 MOV	0x50(%RSP),%RDX

0x24553a VMOVDQA	%YMM2,0x180(%RSP)

0x245543 VPBROADCASTQ	%RSI,%YMM2

0x245549 MOV	0x48(%RSP),%RSI

0x24554e VMOVDQA	%YMM2,0x160(%RSP)

0x245557 VPBROADCASTQ	%RDX,%YMM2

0x24555d MOV	0x38(%RSP),%RDX

0x245562 VMOVDQA	%YMM2,0x140(%RSP)

0x24556b VPBROADCASTQ	%RSI,%YMM2

0x245571 MOV	0x28(%RSP),%RSI

0x245576 VMOVDQA	%YMM2,0x120(%RSP)

0x24557f VPBROADCASTQ	%RDX,%YMM2

0x245585 MOV	0x20(%RSP),%RDX

0x24558a VMOVDQA	%YMM2,0x100(%RSP)

0x245593 VPBROADCASTQ	%RSI,%YMM13

0x245599 VPCMPEQD	%XMM2,%XMM2,%XMM2

0x24559d VPBROADCASTQ	%RDX,%YMM14

0x2455a3 NOPW	%CS:(%RAX,%RAX,1)

(262) 0x2455b0 VEXTRACTI32X4	$0x1,%YMM0,%XMM17

(262) 0x2455b7 MOV	%RAX,0x8(%RSP)

(262) 0x2455bc VPEXTRQ	$0x1,%XMM15,%RSI

(262) 0x2455c2 VMOVQ	%XMM1,%R13

(262) 0x2455c7 VPEXTRQ	$0x1,%XMM17,%RAX

(262) 0x2455ce CQTO

(262) 0x2455d0 IDIV	%RSI

(262) 0x2455d3 VMOVQ	%XMM17,%RDX

(262) 0x2455d9 VMOVQ	%XMM15,%RSI

(262) 0x2455de VMOVQ	%RAX,%XMM17

(262) 0x2455e4 MOV	%RDX,%RAX

(262) 0x2455e7 CQTO

(262) 0x2455e9 IDIV	%RSI

(262) 0x2455ec VPEXTRQ	$0x1,%XMM1,%RSI

(262) 0x2455f2 VMOVQ	%RAX,%XMM19

(262) 0x2455f8 VPEXTRQ	$0x1,%XMM0,%RAX

(262) 0x2455fe CQTO

(262) 0x245600 VPUNPCKLQDQ	%XMM17,%XMM19,%XMM17

(262) 0x245606 IDIV	%RSI

(262) 0x245609 MOV	%RAX,%RSI

(262) 0x24560c VMOVQ	%XMM0,%RAX

(262) 0x245611 VMOVQ	%RSI,%XMM19

(262) 0x245617 CQTO

(262) 0x245619 IDIV	%R13

(262) 0x24561c MOV	0xa8(%RSP),%R15

(262) 0x245624 VMOVQ	%RAX,%XMM20

(262) 0x24562a VPUNPCKLQDQ	%XMM19,%XMM20,%XMM19

(262) 0x245630 VINSERTI32X4	$0x1,%XMM17,%YMM19,%YMM17

(262) 0x245637 VPMOVQD	%YMM17,%XMM19

(262) 0x24563d VPADDD	0xf0(%RSP),%XMM19,%XMM21

(262) 0x245645 VPMULLQ	%YMM1,%YMM17,%YMM17

(262) 0x24564b VPSUBQ	%YMM17,%YMM0,%YMM17

(262) 0x245651 VPADDQ	%YMM18,%YMM0,%YMM0

(262) 0x245657 VPMOVQD	%YMM17,%XMM17

(262) 0x24565d VPADDD	0xe0(%RSP),%XMM17,%XMM17

(262) 0x245665 VPMOVSXDQ	%XMM21,%YMM20

(262) 0x24566b VPMULLQ	0x1a0(%RSP),%YMM20,%YMM26

(262) 0x245673 VPSUBD	%XMM2,%XMM21,%XMM21

(262) 0x245679 VPMOVSXDQ	%XMM21,%YMM21

(262) 0x24567f VPMULLQ	%YMM20,%YMM5,%YMM27

(262) 0x245685 VPMULLQ	%YMM20,%YMM6,%YMM9

(262) 0x24568b VPMULLQ	%YMM21,%YMM5,%YMM16

(262) 0x245691 VPMOVSXDQ	%XMM17,%YMM19

(262) 0x245697 VPSUBD	%XMM2,%XMM17,%XMM17

(262) 0x24569d VPADDQ	%YMM19,%YMM27,%YMM25

(262) 0x2456a3 VPADDQ	%YMM19,%YMM9,%YMM9

(262) 0x2456a9 VPADDQ	%YMM19,%YMM26,%YMM22

(262) 0x2456af VMOVQ	%XMM22,%RDX

(262) 0x2456b5 VPEXTRQ	$0x1,%XMM22,%RSI

(262) 0x2456bc VEXTRACTI32X4	$0x1,%YMM22,%XMM22

(262) 0x2456c3 VMOVQ	%XMM22,%R13

(262) 0x2456c9 VPEXTRQ	$0x1,%XMM22,%RAX

(262) 0x2456d0 VMOVSD	(%R8,%RDX,8),%XMM23

(262) 0x2456d7 VMOVSD	(%R8,%R13,8),%XMM22

(262) 0x2456de VMOVHPD	(%R8,%RSI,8),%XMM23,%XMM24

(262) 0x2456e5 VEXTRACTI32X4	$0x1,%YMM25,%XMM23

(262) 0x2456ec VMOVQ	%XMM25,%R13

(262) 0x2456f2 VPEXTRQ	$0x1,%XMM25,%RSI

(262) 0x2456f9 VPADDQ	%YMM19,%YMM16,%YMM25

(262) 0x2456ff VMOVHPD	(%R8,%RAX,8),%XMM22,%XMM31

(262) 0x245706 VPMOVSXDQ	%XMM17,%YMM22

(262) 0x24570c VMOVQ	%XMM23,%R14

(262) 0x245712 VPEXTRQ	$0x1,%XMM23,%RDX

(262) 0x245719 VMOVSD	(%R10,%R13,8),%XMM23

(262) 0x245720 VMOVSD	(%R10,%R14,8),%XMM28

(262) 0x245727 VMOVHPD	(%R10,%RSI,8),%XMM23,%XMM23

(262) 0x24572e VMOVQ	%XMM25,%RSI

(262) 0x245734 VPEXTRQ	$0x1,%XMM25,%R14

(262) 0x24573b VEXTRACTI32X4	$0x1,%YMM25,%XMM25

(262) 0x245742 VPADDQ	%YMM22,%YMM26,%YMM17

(262) 0x245748 VMOVHPD	(%R10,%RDX,8),%XMM28,%XMM30

(262) 0x24574f VMOVQ	%XMM25,%R13

(262) 0x245755 VPADDQ	%YMM22,%YMM27,%YMM27

(262) 0x24575b VPADDQ	%YMM22,%YMM16,%YMM16

(262) 0x245761 VMOVQ	%XMM17,%RDX

(262) 0x245767 VMOVSD	(%R10,%R13,8),%XMM29

(262) 0x24576e VPEXTRQ	$0x1,%XMM25,%R13

(262) 0x245775 VMOVSD	(%R10,%RSI,8),%XMM25

(262) 0x24577c VPEXTRQ	$0x1,%XMM17,%RSI

(262) 0x245783 VEXTRACTI32X4	$0x1,%YMM17,%XMM17

(262) 0x24578a VEXTRACTI32X4	$0x1,%YMM27,%XMM3

(262) 0x245791 VMOVSD	(%R8,%RDX,8),%XMM26

(262) 0x245798 VMOVHPD	(%R10,%R14,8),%XMM25,%XMM25

(262) 0x24579f VMOVQ	%XMM17,%R14

(262) 0x2457a5 VPEXTRQ	$0x1,%XMM17,%RAX

(262) 0x2457ac VPEXTRQ	$0x1,%XMM27,%RDX

(262) 0x2457b3 VMOVHPD	(%R10,%R13,8),%XMM29,%XMM29

(262) 0x2457ba VMOVHPD	(%R8,%RSI,8),%XMM26,%XMM26

(262) 0x2457c1 VMOVQ	%XMM27,%RSI

(262) 0x2457c7 VMOVSD	(%R8,%R14,8),%XMM17

(262) 0x2457ce VMOVQ	%XMM3,%R14

(262) 0x2457d3 VMOVSD	(%R10,%RSI,8),%XMM27

(262) 0x2457da VMOVQ	%XMM16,%RSI

(262) 0x2457e0 VMOVSD	(%R10,%R14,8),%XMM4

(262) 0x2457e6 VPEXTRQ	$0x1,%XMM16,%R14

(262) 0x2457ed VEXTRACTI32X4	$0x1,%YMM16,%XMM16

(262) 0x2457f4 VMOVHPD	(%R8,%RAX,8),%XMM17,%XMM11

(262) 0x2457fb VMOVHPD	(%R10,%RDX,8),%XMM27,%XMM28

(262) 0x245802 VMOVSD	(%R10,%RSI,8),%XMM27

(262) 0x245809 VMOVQ	%XMM9,%RDX

(262) 0x24580e VPEXTRQ	$0x1,%XMM9,%RSI

(262) 0x245814 VEXTRACTI128	$0x1,%YMM9,%XMM9

(262) 0x24581a VMOVQ	%XMM16,%R13

(262) 0x245820 VMOVHPD	(%R10,%R14,8),%XMM27,%XMM27

(262) 0x245827 VMOVQ	%XMM9,%R14

(262) 0x24582c VMOVSD	(%R10,%R13,8),%XMM8

(262) 0x245832 VPEXTRQ	$0x1,%XMM3,%R13

(262) 0x245838 VINSERTF32X4	$0x1,%XMM31,%YMM24,%YMM24

(262) 0x24583f VMOVSD	(%RBX,%R14,8),%XMM3

(262) 0x245845 VPEXTRQ	$0x1,%XMM9,%R14

(262) 0x24584b VMOVSD	(%RBX,%RDX,8),%XMM9

(262) 0x245850 VMOVHPD	(%R10,%R13,8),%XMM4,%XMM4

(262) 0x245856 VMOVHPD	(%RBX,%R14,8),%XMM3,%XMM3

(262) 0x24585c VPEXTRQ	$0x1,%XMM16,%R14

(262) 0x245863 VPMULLQ	%YMM20,%YMM7,%YMM16

(262) 0x245869 VMOVHPD	(%RBX,%RSI,8),%XMM9,%XMM9

(262) 0x24586e VINSERTF32X4	$0x1,%XMM30,%YMM23,%YMM30

(262) 0x245875 VINSERTF32X4	$0x1,%XMM29,%YMM25,%YMM29

(262) 0x24587c VPADDQ	%YMM19,%YMM16,%YMM10

(262) 0x245882 VMOVQ	%XMM10,%RDX

(262) 0x245887 VPEXTRQ	$0x1,%XMM10,%RAX

(262) 0x24588d VEXTRACTI128	$0x1,%YMM10,%XMM10

(262) 0x245893 VMOVSD	(%R9,%RDX,8),%XMM17

(262) 0x24589a VMOVQ	%XMM10,%R13

(262) 0x24589f VPEXTRQ	$0x1,%XMM10,%RSI

(262) 0x2458a5 VMOVHPD	(%R9,%RAX,8),%XMM17,%XMM12

(262) 0x2458ac VMOVHPD	(%R10,%R14,8),%XMM8,%XMM17

(262) 0x2458b3 VPADDQ	%YMM22,%YMM16,%YMM8

(262) 0x2458b9 VPMULLQ	%YMM21,%YMM6,%YMM16

(262) 0x2458bf VMOVSD	(%R9,%R13,8),%XMM10

(262) 0x2458c5 VMOVQ	%XMM8,%RAX

(262) 0x2458ca VPEXTRQ	$0x1,%XMM8,%RDX

(262) 0x2458d0 VEXTRACTI128	$0x1,%YMM8,%XMM8

(262) 0x2458d6 VMOVHPD	(%R9,%RSI,8),%XMM10,%XMM10

(262) 0x2458dc VINSERTF32X4	$0x1,%XMM4,%YMM28,%YMM4

(262) 0x2458e3 VMOVQ	%XMM8,%R14

(262) 0x2458e8 VPEXTRQ	$0x1,%XMM8,%RSI

(262) 0x2458ee VINSERTF32X4	$0x1,%XMM3,%YMM9,%YMM25

(262) 0x2458f5 VPMULLQ	%YMM21,%YMM7,%YMM9

(262) 0x2458fb VPADDQ	%YMM19,%YMM16,%YMM16

(262) 0x245901 VMOVSD	(%R9,%R14,8),%XMM8

(262) 0x245907 VEXTRACTI32X4	$0x1,%YMM16,%XMM23

(262) 0x24590e VMOVQ	%XMM16,%R14

(262) 0x245914 VMOVHPD	(%R9,%RSI,8),%XMM8,%XMM8

(262) 0x24591a VMOVQ	%XMM23,%R13

(262) 0x245920 VMOVSD	(%RBX,%R14,8),%XMM3

(262) 0x245926 VMOVSD	(%RBX,%R13,8),%XMM31

(262) 0x24592d VPEXTRQ	$0x1,%XMM23,%R13

(262) 0x245934 VMOVHPD	(%RBX,%R13,8),%XMM31,%XMM23

(262) 0x24593b VPEXTRQ	$0x1,%XMM16,%R13

(262) 0x245942 VPADDQ	%YMM19,%YMM9,%YMM16

(262) 0x245948 VPADDQ	%YMM22,%YMM9,%YMM9

(262) 0x24594e VINSERTF32X4	$0x1,%XMM11,%YMM26,%YMM22

(262) 0x245955 VADDPD	%YMM30,%YMM29,%YMM11

(262) 0x24595b VMOVHPD	(%RBX,%R13,8),%XMM3,%XMM3

(262) 0x245961 VEXTRACTI32X4	$0x1,%YMM16,%XMM21

(262) 0x245968 VINSERTF32X4	$0x1,%XMM17,%YMM27,%YMM17

(262) 0x24596f VMOVQ	%XMM21,%R14

(262) 0x245975 VINSERTF128	$0x1,%XMM10,%YMM12,%YMM10

(262) 0x24597b VPEXTRQ	$0x1,%XMM21,%R13

(262) 0x245982 VPMULLQ	0x180(%RSP),%YMM20,%YMM21

(262) 0x24598a VMOVSD	(%R9,%R14,8),%XMM12

(262) 0x245990 VMOVQ	%XMM16,%R14

(262) 0x245996 VMULPD	%YMM24,%YMM11,%YMM11

(262) 0x24599c VADDPD	%YMM4,%YMM17,%YMM4

(262) 0x2459a2 VINSERTF32X4	$0x1,%XMM23,%YMM3,%YMM23

(262) 0x2459a9 VMOVHPD	(%R9,%R13,8),%XMM12,%XMM3

(262) 0x2459af VPEXTRQ	$0x1,%XMM16,%R13

(262) 0x2459b6 VMOVSD	(%R9,%R14,8),%XMM12

(262) 0x2459bc VMOVHPD	(%R9,%R13,8),%XMM12,%XMM12

(262) 0x2459c2 VPADDQ	%YMM19,%YMM21,%YMM21

(262) 0x2459c8 VINSERTF128	$0x1,%XMM3,%YMM12,%YMM3

(262) 0x2459ce VMOVSD	(%R9,%RAX,8),%XMM12

(262) 0x2459d4 VMOVQ	%XMM9,%RAX

(262) 0x2459d9 VMOVHPD	(%R9,%RDX,8),%XMM12,%XMM12

(262) 0x2459df VPEXTRQ	$0x1,%XMM9,%RDX

(262) 0x2459e5 VEXTRACTI128	$0x1,%YMM9,%XMM9

(262) 0x2459eb VMOVSD	(%R9,%RAX,8),%XMM16

(262) 0x2459f2 VMOVQ	%XMM21,%RAX

(262) 0x2459f8 VMOVQ	%XMM9,%R14

(262) 0x2459fd VPEXTRQ	$0x1,%XMM9,%RSI

(262) 0x245a03 VMOVHPD	(%R9,%RDX,8),%XMM16,%XMM16

(262) 0x245a0a VPEXTRQ	$0x1,%XMM21,%RDX

(262) 0x245a11 VEXTRACTI32X4	$0x1,%YMM21,%XMM21

(262) 0x245a18 VMOVSD	(%R9,%R14,8),%XMM9

(262) 0x245a1e VPEXTRQ	$0x1,%XMM21,%R14

(262) 0x245a25 VMOVHPD	(%R9,%RSI,8),%XMM9,%XMM9

(262) 0x245a2b VMOVQ	%XMM21,%RSI

(262) 0x245a31 VMOVSD	(%RDI,%RSI,8),%XMM21

(262) 0x245a38 VINSERTF128	$0x1,%XMM8,%YMM12,%YMM8

(262) 0x245a3e VMOVHPD	(%RDI,%R14,8),%XMM21,%XMM12

(262) 0x245a45 VMOVSD	(%RDI,%RAX,8),%XMM21

(262) 0x245a4c VMOVHPD	(%RDI,%RDX,8),%XMM21,%XMM21

(262) 0x245a53 VADDPD	%YMM10,%YMM8,%YMM8

(262) 0x245a58 VINSERTF32X4	$0x1,%XMM9,%YMM16,%YMM9

(262) 0x245a5f VFNMSUB213PD	%YMM11,%YMM25,%YMM8

(262) 0x245a65 VPMULLQ	0x120(%RSP),%YMM20,%YMM11

(262) 0x245a6d VADDPD	%YMM3,%YMM9,%YMM3

(262) 0x245a71 VPMULLQ	0x140(%RSP),%YMM20,%YMM9

(262) 0x245a79 VINSERTF32X4	$0x1,%XMM12,%YMM21,%YMM21

(262) 0x245a80 VPMULLQ	0x160(%RSP),%YMM20,%YMM12

(262) 0x245a88 VFMADD231PD	%YMM4,%YMM22,%YMM8

(262) 0x245a8e VFMADD213PD	%YMM8,%YMM23,%YMM3

(262) 0x245a94 VPADDQ	%YMM19,%YMM11,%YMM11

(262) 0x245a9a VPADDQ	%YMM19,%YMM9,%YMM9

(262) 0x245aa0 VEXTRACTI32X4	$0x1,%YMM11,%XMM16

(262) 0x245aa7 VPADDQ	%YMM19,%YMM12,%YMM12

(262) 0x245aad VMOVQ	%XMM12,%RAX

(262) 0x245ab2 VPEXTRQ	$0x1,%XMM12,%RDX

(262) 0x245ab8 VEXTRACTI128	$0x1,%YMM12,%XMM12

(262) 0x245abe VMOVQ	%XMM12,%RSI

(262) 0x245ac3 VMOVSD	(%R15,%RAX,8),%XMM10

(262) 0x245ac9 VPEXTRQ	$0x1,%XMM12,%R14

(262) 0x245acf MOV	0x20(%RBP),%RAX

(262) 0x245ad3 VMOVSD	(%R15,%RSI,8),%XMM12

(262) 0x245ad9 VMOVHPD	(%R15,%RDX,8),%XMM10,%XMM10

(262) 0x245adf VPEXTRQ	$0x1,%XMM9,%RDX

(262) 0x245ae5 VMOVHPD	(%R15,%R14,8),%XMM12,%XMM12

(262) 0x245aeb MOV	0x98(%RSP),%R15

(262) 0x245af3 VMOVQ	%XMM16,%R14

(262) 0x245af9 VMOVSD	(%R15,%R14,8),%XMM4

(262) 0x245aff VPEXTRQ	$0x1,%XMM16,%R14

(262) 0x245b06 VMOVHPD	(%R15,%R14,8),%XMM4,%XMM4

(262) 0x245b0c VMOVQ	%XMM11,%R14

(262) 0x245b11 VMOVSD	(%R15,%R14,8),%XMM8

(262) 0x245b17 VPEXTRQ	$0x1,%XMM11,%R14

(262) 0x245b1d VMOVHPD	(%R15,%R14,8),%XMM8,%XMM8

(262) 0x245b23 VINSERTF128	$0x1,%XMM12,%YMM10,%YMM10

(262) 0x245b29 VMOVSD	-0x349a1(%RIP),%XMM12

(262) 0x245b31 MOV	0x90(%RSP),%R15

(262) 0x245b39 VMULSD	(%RAX),%XMM12,%XMM12

(262) 0x245b3d VMOVQ	%XMM9,%RAX

(262) 0x245b42 VEXTRACTI128	$0x1,%YMM9,%XMM9

(262) 0x245b48 VMOVQ	%XMM9,%RSI

(262) 0x245b4d VMOVSD	(%R12,%RAX,8),%XMM16

(262) 0x245b54 VPEXTRQ	$0x1,%XMM9,%R13

(262) 0x245b5a VMOVSD	(%R12,%RSI,8),%XMM9

(262) 0x245b60 VMOVHPD	(%R12,%RDX,8),%XMM16,%XMM16

(262) 0x245b67 VMOVHPD	(%R12,%R13,8),%XMM9,%XMM9

(262) 0x245b6d VINSERTF128	$0x1,%XMM4,%YMM8,%YMM4

(262) 0x245b73 VPMULLQ	0x100(%RSP),%YMM20,%YMM8

(262) 0x245b7b VADDPD	%YMM4,%YMM10,%YMM4

(262) 0x245b7f VBROADCASTSD	%XMM12,%YMM12

(262) 0x245b84 VINSERTF32X4	$0x1,%XMM9,%YMM16,%YMM9

(262) 0x245b8b VMULPD	%YMM3,%YMM12,%YMM3

(262) 0x245b8f VMULPD	%YMM21,%YMM9,%YMM9

(262) 0x245b95 VMULPD	%YMM3,%YMM4,%YMM4

(262) 0x245b99 VADDPD	%YMM21,%YMM3,%YMM3

(262) 0x245b9f VPADDQ	%YMM19,%YMM8,%YMM8

(262) 0x245ba5 VEXTRACTI128	$0x1,%YMM8,%XMM10

(262) 0x245bab VDIVPD	%YMM9,%YMM4,%YMM4

(262) 0x245bb0 VMOVQ	%XMM10,%R14

(262) 0x245bb5 VMOVSD	(%R11,%R14,8),%XMM11

(262) 0x245bbb VPEXTRQ	$0x1,%XMM10,%R14

(262) 0x245bc1 VMOVHPD	(%R11,%R14,8),%XMM11,%XMM10

(262) 0x245bc7 VMOVQ	%XMM8,%R14

(262) 0x245bcc VMOVSD	(%R11,%R14,8),%XMM11

(262) 0x245bd2 VPEXTRQ	$0x1,%XMM8,%R14

(262) 0x245bd8 VMOVHPD	(%R11,%R14,8),%XMM11,%XMM8

(262) 0x245bde VINSERTF128	$0x1,%XMM10,%YMM8,%YMM8

(262) 0x245be4 VSUBPD	%YMM4,%YMM8,%YMM4

(262) 0x245be8 VPMULLQ	%YMM20,%YMM13,%YMM8

(262) 0x245bee VPADDQ	%YMM19,%YMM8,%YMM8

(262) 0x245bf4 VMOVQ	%XMM8,%R14

(262) 0x245bf9 VMOVLPD	%XMM4,(%R15,%R14,8)

(262) 0x245bff VPEXTRQ	$0x1,%XMM8,%R14

(262) 0x245c05 VEXTRACTI128	$0x1,%YMM8,%XMM8

(262) 0x245c0b VMOVHPD	%XMM4,(%R15,%R14,8)

(262) 0x245c11 VEXTRACTF128	$0x1,%YMM4,%XMM4

(262) 0x245c17 VMOVQ	%XMM8,%R14

(262) 0x245c1c VMOVLPD	%XMM4,(%R15,%R14,8)

(262) 0x245c22 VPEXTRQ	$0x1,%XMM8,%R14

(262) 0x245c28 VMOVHPD	%XMM4,(%R15,%R14,8)

(262) 0x245c2e VMOVSD	(%R12,%RSI,8),%XMM4

(262) 0x245c34 VMOVSD	(%R12,%RAX,8),%XMM8

(262) 0x245c3a VMOVHPD	(%R12,%RDX,8),%XMM8,%XMM8

(262) 0x245c40 VMOVHPD	(%R12,%R13,8),%XMM4,%XMM4

(262) 0x245c46 MOV	0xa0(%RSP),%RDX

(262) 0x245c4e VINSERTF128	$0x1,%XMM4,%YMM8,%YMM4

(262) 0x245c54 VMULPD	%YMM21,%YMM4,%YMM4

(262) 0x245c5a VDIVPD	%YMM3,%YMM4,%YMM3

(262) 0x245c5e VPMULLQ	%YMM20,%YMM14,%YMM4

(262) 0x245c64 VPADDQ	%YMM19,%YMM4,%YMM4

(262) 0x245c6a VMOVQ	%XMM4,%RAX

(262) 0x245c6f VMOVLPD	%XMM3,(%RDX,%RAX,8)

(262) 0x245c74 VPEXTRQ	$0x1,%XMM4,%RAX

(262) 0x245c7a VEXTRACTI128	$0x1,%YMM4,%XMM4

(262) 0x245c80 VMOVHPD	%XMM3,(%RDX,%RAX,8)

(262) 0x245c85 VEXTRACTF128	$0x1,%YMM3,%XMM3

(262) 0x245c8b VMOVQ	%XMM4,%RAX

(262) 0x245c90 VMOVLPD	%XMM3,(%RDX,%RAX,8)

(262) 0x245c95 VPEXTRQ	$0x1,%XMM4,%RAX

(262) 0x245c9b VMOVHPD	%XMM3,(%RDX,%RAX,8)

(262) 0x245ca0 MOV	0x8(%RSP),%RAX

(262) 0x245ca5 ADD	$-0x4,%RAX

(262) 0x245ca9 JNE	2455b0

0x245caf MOV	0xb8(%RSP),%RAX

0x245cb7 MOV	0x88(%RSP),%R13

0x245cbf MOV	0x4(%RSP),%R14D

0x245cc4 MOV	0xc8(%RSP),%R15

0x245ccc CMP	%RAX,0xc0(%RSP)

0x245cd4 JE	245eba

0x245cda VMOVSD	-0x34b52(%RIP),%XMM0

0x245ce2 NOPW	%CS:(%RAX,%RAX,1)

(261) 0x245cf0 MOV	%RCX,%RAX

(261) 0x245cf3 MOV	%RCX,0x8(%RSP)

(261) 0x245cf8 CQTO

(261) 0x245cfa IDIVQ	0x40(%RSP)

(261) 0x245cff MOV	0x78(%RSP),%R11

(261) 0x245d04 MOV	0x68(%RSP),%RCX

(261) 0x245d09 MOV	0x70(%RSP),%RDI

(261) 0x245d0e ADD	%R14D,%EDX

(261) 0x245d11 MOV	%R11,%R14

(261) 0x245d14 MOVSXD	%EDX,%RDX

(261) 0x245d17 LEA	(%R13,%RAX,1),%ESI

(261) 0x245d1c LEA	0x1(%R13,%RAX,1),%EAX

(261) 0x245d21 MOVSXD	%ESI,%RSI

(261) 0x245d24 CLTQ

(261) 0x245d26 IMUL	%RSI,%R14

(261) 0x245d2a IMUL	%RAX,%R11

(261) 0x245d2e LEA	(%R11,%RDX,1),%R13

(261) 0x245d32 LEA	0x1(%R11,%RDX,1),%R11

(261) 0x245d37 VMOVSD	(%R10,%R13,8),%XMM1

(261) 0x245d3d LEA	(%R14,%RDX,1),%R13

(261) 0x245d41 LEA	0x1(%R14,%RDX,1),%R14

(261) 0x245d46 VMOVSD	(%R10,%R11,8),%XMM2

(261) 0x245d4c MOV	%RCX,%R11

(261) 0x245d4f IMUL	%RSI,%R11

(261) 0x245d53 VADDSD	(%R10,%R13,8),%XMM1,%XMM1

(261) 0x245d59 MOV	0x80(%RSP),%R13

(261) 0x245d61 VADDSD	(%R10,%R14,8),%XMM2,%XMM2

(261) 0x245d67 LEA	0x1(%R11,%RDX,1),%R14

(261) 0x245d6c ADD	%RDX,%R11

(261) 0x245d6f VMOVSD	(%R9,%R14,8),%XMM3

(261) 0x245d75 IMUL	%RSI,%R13

(261) 0x245d79 VADDSD	(%R9,%R11,8),%XMM3,%XMM3

(261) 0x245d7f MOV	%RDI,%R11

(261) 0x245d82 IMUL	%RAX,%R11

(261) 0x245d86 IMUL	%RCX,%RAX

(261) 0x245d8a MOV	0x30(%RSP),%RCX

(261) 0x245d8f LEA	0x1(%RAX,%RDX,1),%R14

(261) 0x245d94 ADD	%RDX,%RAX

(261) 0x245d97 ADD	%RDX,%R11

(261) 0x245d9a VMOVSD	(%R9,%R14,8),%XMM4

(261) 0x245da0 LEA	0x1(%R13,%RDX,1),%R14

(261) 0x245da5 ADD	%RDX,%R13

(261) 0x245da8 VADDSD	(%R9,%RAX,8),%XMM4,%XMM4

(261) 0x245dae MOV	%RDI,%RAX

(261) 0x245db1 IMUL	%RSI,%RAX

(261) 0x245db5 VMULSD	(%R8,%R13,8),%XMM1,%XMM1

(261) 0x245dbb MOV	0x98(%RSP),%RDI

(261) 0x245dc3 MOV	0x88(%RSP),%R13

(261) 0x245dcb ADD	%RDX,%RAX

(261) 0x245dce VFNMSUB231SD	(%RBX,%RAX,8),%XMM3,%XMM1

(261) 0x245dd4 MOV	0x20(%RBP),%RAX

(261) 0x245dd8 VFMADD231SD	(%R8,%R14,8),%XMM2,%XMM1

(261) 0x245dde MOV	0x4(%RSP),%R14D

(261) 0x245de3 VMULSD	(%RAX),%XMM0,%XMM2

(261) 0x245de7 MOV	0x60(%RSP),%RAX

(261) 0x245dec VFMADD231SD	(%RBX,%R11,8),%XMM4,%XMM1

(261) 0x245df2 MOV	0x48(%RSP),%R11

(261) 0x245df7 IMUL	%RSI,%RAX

(261) 0x245dfb IMUL	%RSI,%R11

(261) 0x245dff ADD	%RDX,%RAX

(261) 0x245e02 VMOVSD	(%RCX,%RAX,8),%XMM5

(261) 0x245e07 MOV	0x58(%RSP),%RAX

(261) 0x245e0c MOV	0xd0(%RSP),%RCX

(261) 0x245e14 ADD	%RDX,%R11

(261) 0x245e17 VMOVSD	(%RDI,%R11,8),%XMM3

(261) 0x245e1d MOV	0x50(%RSP),%R11

(261) 0x245e22 MOV	%R15,%RDI

(261) 0x245e25 MOV	0xa8(%RSP),%R15

(261) 0x245e2d IMUL	%RSI,%RAX

(261) 0x245e31 VMULSD	%XMM1,%XMM2,%XMM1

(261) 0x245e35 IMUL	%RSI,%R11

(261) 0x245e39 ADD	%RDX,%RAX

(261) 0x245e3c VADDSD	(%R15,%RAX,8),%XMM3,%XMM3

(261) 0x245e42 MOV	0x38(%RSP),%RAX

(261) 0x245e47 MOV	%RDI,%R15

(261) 0x245e4a MOV	0x90(%RSP),%RDI

(261) 0x245e52 ADD	%RDX,%R11

(261) 0x245e55 VMULSD	(%R12,%R11,8),%XMM5,%XMM4

(261) 0x245e5b IMUL	%RSI,%RAX

(261) 0x245e5f ADD	%RDX,%RAX

(261) 0x245e62 VMULSD	%XMM1,%XMM3,%XMM3

(261) 0x245e66 VADDSD	%XMM5,%XMM1,%XMM1

(261) 0x245e6a VDIVSD	%XMM4,%XMM3,%XMM3

(261) 0x245e6e VMOVSD	(%RCX,%RAX,8),%XMM4

(261) 0x245e73 MOV	0x28(%RSP),%RAX

(261) 0x245e78 IMUL	%RSI,%RAX

(261) 0x245e7c IMUL	0x20(%RSP),%RSI

(261) 0x245e82 ADD	%RDX,%RAX

(261) 0x245e85 ADD	%RDX,%RSI

(261) 0x245e88 MOV	0xa0(%RSP),%RDX

(261) 0x245e90 VSUBSD	%XMM3,%XMM4,%XMM3

(261) 0x245e94 VMOVSD	%XMM3,(%RDI,%RAX,8)

(261) 0x245e99 MOV	0x8(%RSP),%RAX

(261) 0x245e9e VMULSD	(%R12,%R11,8),%XMM5,%XMM3

(261) 0x245ea4 LEA	0x1(%RAX),%RCX

(261) 0x245ea8 VDIVSD	%XMM1,%XMM3,%XMM1

(261) 0x245eac VMOVSD	%XMM1,(%RDX,%RSI,8)

(261) 0x245eb1 CMP	%R15,%RAX

(261) 0x245eb4 JL	245cf0

0x245eba MOV	0x18(%RSP),%ESI

0x245ebe LEA	0x157cb(%RIP),%RDI

0x245ec5 VZEROUPPER

0x245ec8 CALL	259690 <@plt_start@+0x540>

0x245ecd LEA	-0x28(%RBP),%RSP

0x245ed1 POP	%RBX

0x245ed2 POP	%R12

0x245ed4 POP	%R13

0x245ed6 POP	%R14

0x245ed8 POP	%R15

0x245eda POP	%RBP

0x245edb RET

0x245edc NOPL	(%RAX)

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run aocc_8

Source file and lines	PdV.cpp:48-63
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:48-63
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 25.25 to 8.50 cycles (2.97x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 15% of vector register length is used (average across all SSE/AVX instructions).

Details

14% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

7% of SSE/AVX loads are used in vector version.
21% of SSE/AVX stores are used in vector version.
12% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
12% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 25.25 to 24.00 cycles (1.05x speedup).

Workaround

Read less array elements
Write less array elements

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:48
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:48

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVL: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:49
VPBROADCASTD: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:49
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:49
VPBROADCASTQ: 13 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:49
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:49
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:49
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:49
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:49
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:49
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:49
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:49
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:49
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:49
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:49
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:49
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:49

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 492 bytes. The binary function is storing 444 bytes.

General properties

nb instructions	177
nb uops	192
loop length	887
used x86 registers	16
used mmx registers	0
used xmm registers	3
used ymm registers	9
used zmm registers	0
nb stack references	49

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	24.00 cycles
front end	24.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	6.50	6.50	6.50	6.50	6.50	6.50	25.25	25.25	25.25	25.25	1.00	8.50	8.50	1.00	4.00	4.00
cycles	6.50	6.50	6.50	6.50	6.50	6.50	25.25	25.25	25.25	25.25	1.00	8.50	8.50	1.00	4.00	4.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	24.00
Dispatch	25.25
Overall L1	25.25

Vectorization ratios

INT

all	15%
load	8%
store	21%
mul	0%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	14%
load	7%
store	21%
mul	0%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Vector efficiency ratios

INT

all	15%
load	13%
store	18%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	13%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	15%
load	12%
store	18%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.25 cycles. At this rate:

7% of peak load performance is reached (19.49 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
13% of peak store performance is reached (17.58 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 2452a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND $-0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB $0x1e0,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RDX),%R13D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
MOV (%RCX),%R15D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
INC %R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD $0x2,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SUB %R13D,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 245ecd <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined+0xc2d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV (%R9),%EBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
MOV (%R8),%R14D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
INC %R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD $0x2,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CMP %R14D,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 245ecd <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined+0xc2d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
SUB %R14D,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOVQ $0,0xb0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOVQ $0x1,0xd8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOVL $0,0x1c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
IMUL %RBX,%R15	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
DEC %R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R15,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x24(%RSP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0xe0(%RSP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x1634c(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0xb8(%RSP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x18(%RSP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %ESI,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 259680 <@plt_start@+0x530>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x10(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xb0(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CMP %R15,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMOVL %RAX,%R15	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
MOV %R15,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
CMP %R15,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JG 245eba <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined+0xc1a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x10(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x18(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x28(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x38(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x40(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x30(%RBP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RBX,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x48(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R13,0x88(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R14D,0x4(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV (%R8),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%R9),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%R8),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,0x80(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%R10),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%R10),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,0x78(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%R9),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%R12),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,0x70(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RCX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%RSI),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R9,0x68(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x10(%R12),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RSI),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RAX),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,0x60(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RDX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RSI,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x10(%RDX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,0x58(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RAX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x50(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDX,0xa8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RAX),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,0x50(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RSI,0x48(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x10(%RAX),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x60(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RAX),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV %RSI,0x98(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R11,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x10(%RAX),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x58(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RAX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RAX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x68(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R11,0xd0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDI,0x28(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RAX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RAX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDX,0x90(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDI,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R15,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RCX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,0xa0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
INC %RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x4,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JB 245cda <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined+0xa3a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x80(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VPBROADCASTD %R13D,%XMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (6.3%)
MOV 0x78(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x40(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VPBROADCASTQ %RCX,%YMM0	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
VPADDQ -0x341c5(%RIP),%YMM0,%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (50.0%)
VPBROADCASTQ -0x342df(%RIP),%YMM18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
MOV %RDI,0xc0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
AND $-0x4,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R15,0xc8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVDQA %XMM2,0xf0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VPBROADCASTD %R14D,%XMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (6.3%)
ADD %RDI,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDI,0xb8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVDQA %XMM2,0xe0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VPBROADCASTQ %RDX,%YMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
MOV 0x70(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VPBROADCASTQ %RSI,%YMM5	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
MOV 0x68(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VPBROADCASTQ %RAX,%YMM1	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
MOV %RDI,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x30(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVDQA %YMM2,0x1a0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VEXTRACTI128 $0x1,%YMM1,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VPBROADCASTQ %RDX,%YMM6	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
MOV 0x60(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VPBROADCASTQ %RSI,%YMM7	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
MOV 0x58(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VPBROADCASTQ %RDX,%YMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
MOV 0x50(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVDQA %YMM2,0x180(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPBROADCASTQ %RSI,%YMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
MOV 0x48(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVDQA %YMM2,0x160(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPBROADCASTQ %RDX,%YMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
MOV 0x38(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVDQA %YMM2,0x140(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPBROADCASTQ %RSI,%YMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
MOV 0x28(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVDQA %YMM2,0x120(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPBROADCASTQ %RDX,%YMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
MOV 0x20(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVDQA %YMM2,0x100(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPBROADCASTQ %RSI,%YMM13	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
VPCMPEQD %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VPBROADCASTQ %RDX,%YMM14	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV 0xb8(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x88(%RSP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x4(%RSP),%R14D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
MOV 0xc8(%RSP),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
CMP %RAX,0xc0(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
JE 245eba <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined+0xc1a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVSD -0x34b52(%RIP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV 0x18(%RSP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA 0x157cb(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 259690 <@plt_start@+0x540>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run aocc_8

Source file and lines	PdV.cpp:48-63
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:48-63
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 25.25 to 8.50 cycles (2.97x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 15% of vector register length is used (average across all SSE/AVX instructions).

Details

14% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

7% of SSE/AVX loads are used in vector version.
21% of SSE/AVX stores are used in vector version.
12% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
12% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 25.25 to 24.00 cycles (1.05x speedup).

Workaround

Read less array elements
Write less array elements

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:48
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:48

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVL: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:49
VPBROADCASTD: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:49
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:49
VPBROADCASTQ: 13 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:49
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:49
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:49
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:49
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:49
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:49
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:49
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:49
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:49
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:49
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:49
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:49
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:49

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 492 bytes. The binary function is storing 444 bytes.

General properties

nb instructions	177
nb uops	192
loop length	887
used x86 registers	16
used mmx registers	0
used xmm registers	3
used ymm registers	9
used zmm registers	0
nb stack references	49

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	24.00 cycles
front end	24.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	6.50	6.50	6.50	6.50	6.50	6.50	25.25	25.25	25.25	25.25	1.00	8.50	8.50	1.00	4.00	4.00
cycles	6.50	6.50	6.50	6.50	6.50	6.50	25.25	25.25	25.25	25.25	1.00	8.50	8.50	1.00	4.00	4.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	24.00
Dispatch	25.25
Overall L1	25.25

Vectorization ratios

INT

all	15%
load	8%
store	21%
mul	0%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	14%
load	7%
store	21%
mul	0%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Vector efficiency ratios

INT

all	15%
load	13%
store	18%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	13%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	15%
load	12%
store	18%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.25 cycles. At this rate:

7% of peak load performance is reached (19.49 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
13% of peak store performance is reached (17.58 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 2452a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND $-0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB $0x1e0,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RDX),%R13D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
MOV (%RCX),%R15D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
INC %R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD $0x2,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SUB %R13D,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 245ecd <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined+0xc2d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV (%R9),%EBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
MOV (%R8),%R14D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
INC %R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD $0x2,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CMP %R14D,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 245ecd <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined+0xc2d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
SUB %R14D,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOVQ $0,0xb0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOVQ $0x1,0xd8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOVL $0,0x1c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
IMUL %RBX,%R15	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
DEC %R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R15,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x24(%RSP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0xe0(%RSP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x1634c(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0xb8(%RSP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x18(%RSP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %ESI,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 259680 <@plt_start@+0x530>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x10(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xb0(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CMP %R15,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMOVL %RAX,%R15	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
MOV %R15,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
CMP %R15,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JG 245eba <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined+0xc1a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x10(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x18(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x28(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x38(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x40(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x30(%RBP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RBX,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x48(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R13,0x88(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R14D,0x4(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV (%R8),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%R9),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%R8),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,0x80(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%R10),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%R10),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,0x78(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%R9),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%R12),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,0x70(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RCX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%RSI),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R9,0x68(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x10(%R12),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RSI),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RAX),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,0x60(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RDX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RSI,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x10(%RDX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,0x58(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RAX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x50(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDX,0xa8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RAX),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,0x50(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RSI,0x48(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x10(%RAX),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x60(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RAX),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV %RSI,0x98(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R11,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x10(%RAX),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x58(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RAX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RAX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x68(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R11,0xd0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDI,0x28(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RAX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RAX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDX,0x90(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDI,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R15,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RCX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,0xa0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
INC %RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x4,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JB 245cda <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined+0xa3a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x80(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VPBROADCASTD %R13D,%XMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (6.3%)
MOV 0x78(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x40(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VPBROADCASTQ %RCX,%YMM0	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
VPADDQ -0x341c5(%RIP),%YMM0,%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (50.0%)
VPBROADCASTQ -0x342df(%RIP),%YMM18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
MOV %RDI,0xc0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
AND $-0x4,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R15,0xc8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVDQA %XMM2,0xf0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VPBROADCASTD %R14D,%XMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (6.3%)
ADD %RDI,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDI,0xb8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVDQA %XMM2,0xe0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VPBROADCASTQ %RDX,%YMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
MOV 0x70(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VPBROADCASTQ %RSI,%YMM5	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
MOV 0x68(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VPBROADCASTQ %RAX,%YMM1	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
MOV %RDI,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x30(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVDQA %YMM2,0x1a0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VEXTRACTI128 $0x1,%YMM1,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VPBROADCASTQ %RDX,%YMM6	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
MOV 0x60(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VPBROADCASTQ %RSI,%YMM7	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
MOV 0x58(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VPBROADCASTQ %RDX,%YMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
MOV 0x50(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVDQA %YMM2,0x180(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPBROADCASTQ %RSI,%YMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
MOV 0x48(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVDQA %YMM2,0x160(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPBROADCASTQ %RDX,%YMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
MOV 0x38(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVDQA %YMM2,0x140(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPBROADCASTQ %RSI,%YMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
MOV 0x28(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVDQA %YMM2,0x120(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPBROADCASTQ %RDX,%YMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
MOV 0x20(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVDQA %YMM2,0x100(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPBROADCASTQ %RSI,%YMM13	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
VPCMPEQD %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VPBROADCASTQ %RDX,%YMM14	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV 0xb8(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x88(%RSP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x4(%RSP),%R14D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
MOV 0xc8(%RSP),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
CMP %RAX,0xc0(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
JE 245eba <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined+0xc1a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVSD -0x34b52(%RIP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV 0x18(%RSP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA 0x157cb(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 259690 <@plt_start@+0x540>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	5.49	2.05
○Loop 262 - PdV.cpp:49-63 - exec	5.49	2.05
○Loop 261 - PdV.cpp:49-63 - exec	0.00	0.00

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512-bits vectorization

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Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

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Back-end

Cycles summary

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Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code