OV - exec - Function generate_chunk(int, global_variables&) [clone .omp

	Function: generate_chunk(int, global_variables&) [clone .omp_outlined]	Module: exec	Source: generate_chunk.cpp:74-80 [...]	Coverage (incl. loops): 0.04% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp: 74 - 80

--------------------------------------------------------------------------------

74: #pragma omp parallel for simd collapse(2)

75:   for (int j = (0); j < (yrange); j++) {

76:     for (int i = (0); i < (xrange); i++) {

77:       field.energy0(i, j) = state_energy[0];

78:       field.density0(i, j) = state_density[0];

79:       field.xvel0(i, j) = state_xvel[0];

80:       field.yvel0(i, j) = state_yvel[0];

0x23ef20 PUSH	%RBP

0x23ef21 MOV	%RSP,%RBP

0x23ef24 PUSH	%R15

0x23ef26 PUSH	%R14

0x23ef28 PUSH	%R13

0x23ef2a PUSH	%R12

0x23ef2c PUSH	%RBX

0x23ef2d SUB	$0x78,%RSP

0x23ef31 MOV	(%RDX),%R12D

0x23ef34 TEST	%R12D,%R12D

0x23ef37 JLE	23f307

0x23ef3d MOV	(%RCX),%EAX

0x23ef3f TEST	%EAX,%EAX

0x23ef41 JLE	23f307

0x23ef47 MOVSXD	%EAX,%R13

0x23ef4a MOV	(%RDI),%ESI

0x23ef4c MOV	%R9,%RBX

0x23ef4f MOV	%R8,%R15

0x23ef52 MOVQ	$0,-0x50(%RBP)

0x23ef5a MOVQ	$0x1,-0x98(%RBP)

0x23ef65 MOVL	$0,-0x38(%RBP)

0x23ef6c IMUL	%R13,%R12

0x23ef70 DEC	%R12

0x23ef73 MOV	%R12,-0x30(%RBP)

0x23ef77 SUB	$0x8,%RSP

0x23ef7b LEA	-0x38(%RBP),%RCX

0x23ef7f LEA	-0x98(%RBP),%RAX

0x23ef86 LEA	0x1c25b(%RIP),%RDI

0x23ef8d LEA	-0x50(%RBP),%R8

0x23ef91 LEA	-0x30(%RBP),%R9

0x23ef95 MOV	%ESI,-0x34(%RBP)

0x23ef98 MOV	$0x22,%EDX

0x23ef9d PUSH	$0x1

0x23ef9f PUSH	$0x1

0x23efa1 PUSH	%RAX

0x23efa2 CALL	259680 <@plt_start@+0x530>

0x23efa7 ADD	$0x20,%RSP

0x23efab MOV	-0x30(%RBP),%RAX

0x23efaf MOV	-0x50(%RBP),%RCX

0x23efb3 CMP	%R12,%RAX

0x23efb6 CMOVL	%RAX,%R12

0x23efba MOV	%R12,-0x30(%RBP)

0x23efbe CMP	%R12,%RCX

0x23efc1 JG	23f2f5

0x23efc7 MOV	0x8(%RBX),%RAX

0x23efcb MOV	0x10(%RBP),%R8

0x23efcf MOV	0x20(%RBP),%RSI

0x23efd3 MOV	0x18(%RBP),%RDX

0x23efd7 MOV	0x40(%R15),%RDI

0x23efdb MOV	0x30(%R15),%R9

0x23efdf MOV	(%R15),%R10

0x23efe2 MOV	0x10(%R15),%R11

0x23efe6 MOV	0xb8(%R15),%RBX

0x23efed MOV	0xa8(%R15),%R14

0x23eff4 MOV	%RAX,-0x48(%RBP)

0x23eff8 MOV	0x8(%R8),%RAX

0x23effc MOV	0x8(%RDX),%RDX

0x23f000 MOV	0xe8(%R15),%R8

0x23f007 MOV	0xd8(%R15),%R15

0x23f00e MOV	0x8(%RSI),%RSI

0x23f012 MOV	%RAX,-0x40(%RBP)

0x23f016 MOV	%R12,%RAX

0x23f019 SUB	%RCX,%RAX

0x23f01c MOV	%R15,-0x90(%RBP)

0x23f023 MOV	%RDX,-0x88(%RBP)

0x23f02a INC	%RAX

0x23f02d CMP	$0x4,%RAX

0x23f031 JAE	23f03b

0x23f033 MOV	%RSI,%R15

0x23f036 JMP	23f280

0x23f03b VPBROADCASTQ	%RCX,%YMM0

0x23f041 VPADDQ	-0x2dd69(%RIP),%YMM0,%YMM0

0x23f049 VPBROADCASTQ	-0x2de82(%RIP),%YMM7

0x23f052 MOV	%R9,-0x78(%RBP)

0x23f056 VPBROADCASTQ	%R9,%YMM2

0x23f05c MOV	-0x40(%RBP),%R9

0x23f060 MOV	%RAX,-0x60(%RBP)

0x23f064 AND	$-0x4,%RAX

0x23f068 VPBROADCASTQ	%R13,%YMM1

0x23f06e VPBROADCASTQ	%R15,%YMM5

0x23f074 VPBROADCASTQ	%R10,%YMM3

0x23f07a VPBROADCASTQ	%R14,%YMM4

0x23f080 MOV	%R10,-0x70(%RBP)

0x23f084 MOV	%R14,-0x68(%RBP)

0x23f088 MOV	%R13,-0x80(%RBP)

0x23f08c MOV	%RDX,%R10

0x23f08f MOV	%RSI,%R15

0x23f092 ADD	%RAX,%RCX

0x23f095 VEXTRACTI128	$0x1,%YMM1,%XMM6

0x23f09b MOV	%RAX,%R14

0x23f09e MOV	%RAX,-0x58(%RBP)

0x23f0a2 NOPW	%CS:(%RAX,%RAX,1)

(214) 0x23f0b0 VEXTRACTI128	$0x1,%YMM0,%XMM8

(214) 0x23f0b6 VPEXTRQ	$0x1,%XMM6,%R13

(214) 0x23f0bc VPEXTRQ	$0x1,%XMM8,%RAX

(214) 0x23f0c2 CQTO

(214) 0x23f0c4 IDIV	%R13

(214) 0x23f0c7 VMOVQ	%XMM6,%R13

(214) 0x23f0cc VMOVQ	%RAX,%XMM9

(214) 0x23f0d1 VMOVQ	%XMM8,%RAX

(214) 0x23f0d6 CQTO

(214) 0x23f0d8 IDIV	%R13

(214) 0x23f0db VPEXTRQ	$0x1,%XMM1,%R13

(214) 0x23f0e1 VMOVQ	%RAX,%XMM8

(214) 0x23f0e6 VPEXTRQ	$0x1,%XMM0,%RAX

(214) 0x23f0ec CQTO

(214) 0x23f0ee VPUNPCKLQDQ	%XMM9,%XMM8,%XMM8

(214) 0x23f0f3 IDIV	%R13

(214) 0x23f0f6 VMOVQ	%XMM1,%R13

(214) 0x23f0fb VMOVQ	%RAX,%XMM9

(214) 0x23f100 VMOVQ	%XMM0,%RAX

(214) 0x23f105 CQTO

(214) 0x23f107 IDIV	%R13

(214) 0x23f10a MOV	-0x48(%RBP),%RDX

(214) 0x23f10e ADD	$-0x4,%R14

(214) 0x23f112 VMOVQ	%RAX,%XMM10

(214) 0x23f117 VPUNPCKLQDQ	%XMM9,%XMM10,%XMM9

(214) 0x23f11c VMOVSD	(%RDX),%XMM10

(214) 0x23f120 VINSERTI128	$0x1,%XMM8,%YMM9,%YMM8

(214) 0x23f126 VPMULLQ	%YMM1,%YMM8,%YMM9

(214) 0x23f12c VPSLLQ	$0x20,%YMM8,%YMM8

(214) 0x23f132 VPSRAQ	$0x20,%YMM8,%YMM8

(214) 0x23f139 VPMULLQ	%YMM2,%YMM8,%YMM11

(214) 0x23f13f VPSUBQ	%YMM9,%YMM0,%YMM9

(214) 0x23f144 VPADDQ	%YMM7,%YMM0,%YMM0

(214) 0x23f148 VPSLLQ	$0x20,%YMM9,%YMM9

(214) 0x23f14e VPSRAQ	$0x20,%YMM9,%YMM9

(214) 0x23f155 VPADDQ	%YMM11,%YMM9,%YMM11

(214) 0x23f15a VMOVQ	%XMM11,%RAX

(214) 0x23f15f VPEXTRQ	$0x1,%XMM11,%RDX

(214) 0x23f165 VEXTRACTI128	$0x1,%YMM11,%XMM11

(214) 0x23f16b VMOVQ	%XMM11,%R13

(214) 0x23f170 VPEXTRQ	$0x1,%XMM11,%RSI

(214) 0x23f176 VMOVSD	%XMM10,(%RDI,%RAX,8)

(214) 0x23f17b VMOVSD	%XMM10,(%RDI,%RDX,8)

(214) 0x23f180 VPMULLQ	%YMM3,%YMM8,%YMM11

(214) 0x23f186 VMOVSD	%XMM10,(%RDI,%R13,8)

(214) 0x23f18c VMOVSD	%XMM10,(%RDI,%RSI,8)

(214) 0x23f191 VMOVSD	(%R9),%XMM10

(214) 0x23f196 VPADDQ	%YMM11,%YMM9,%YMM11

(214) 0x23f19b VMOVQ	%XMM11,%RAX

(214) 0x23f1a0 VPEXTRQ	$0x1,%XMM11,%RDX

(214) 0x23f1a6 VEXTRACTI128	$0x1,%YMM11,%XMM11

(214) 0x23f1ac VMOVQ	%XMM11,%RSI

(214) 0x23f1b1 VPEXTRQ	$0x1,%XMM11,%R13

(214) 0x23f1b7 VPMULLQ	%YMM4,%YMM8,%YMM11

(214) 0x23f1bd VPMULLQ	%YMM5,%YMM8,%YMM8

(214) 0x23f1c3 VPADDQ	%YMM11,%YMM9,%YMM11

(214) 0x23f1c8 VPADDQ	%YMM8,%YMM9,%YMM8

(214) 0x23f1cd VMOVSD	%XMM10,(%R11,%RAX,8)

(214) 0x23f1d3 VMOVSD	%XMM10,(%R11,%RDX,8)

(214) 0x23f1d9 VMOVSD	%XMM10,(%R11,%RSI,8)

(214) 0x23f1df VMOVSD	%XMM10,(%R11,%R13,8)

(214) 0x23f1e5 VMOVQ	%XMM11,%RAX

(214) 0x23f1ea VPEXTRQ	$0x1,%XMM11,%RDX

(214) 0x23f1f0 VEXTRACTI128	$0x1,%YMM11,%XMM11

(214) 0x23f1f6 VMOVSD	(%R10),%XMM10

(214) 0x23f1fb VMOVQ	%XMM11,%RSI

(214) 0x23f200 VPEXTRQ	$0x1,%XMM11,%R13

(214) 0x23f206 VMOVSD	%XMM10,(%RBX,%RAX,8)

(214) 0x23f20b VMOVSD	%XMM10,(%RBX,%RDX,8)

(214) 0x23f210 VMOVSD	%XMM10,(%RBX,%RSI,8)

(214) 0x23f215 VMOVSD	%XMM10,(%RBX,%R13,8)

(214) 0x23f21b VMOVQ	%XMM8,%RAX

(214) 0x23f220 VPEXTRQ	$0x1,%XMM8,%RDX

(214) 0x23f226 VEXTRACTI128	$0x1,%YMM8,%XMM8

(214) 0x23f22c VMOVSD	(%R15),%XMM10

(214) 0x23f231 VMOVQ	%XMM8,%RSI

(214) 0x23f236 VPEXTRQ	$0x1,%XMM8,%R13

(214) 0x23f23c VMOVSD	%XMM10,(%R8,%RAX,8)

(214) 0x23f242 VMOVSD	%XMM10,(%R8,%RDX,8)

(214) 0x23f248 VMOVSD	%XMM10,(%R8,%RSI,8)

(214) 0x23f24e VMOVSD	%XMM10,(%R8,%R13,8)

(214) 0x23f254 JNE	23f0b0

0x23f25a MOV	-0x58(%RBP),%RAX

0x23f25e MOV	-0x80(%RBP),%R13

0x23f262 MOV	-0x78(%RBP),%R9

0x23f266 MOV	-0x70(%RBP),%R10

0x23f26a MOV	-0x68(%RBP),%R14

0x23f26e CMP	%RAX,-0x60(%RBP)

0x23f272 JE	23f2f5

0x23f278 NOPL	(%RAX,%RAX,1)

(215) 0x23f280 MOV	%RCX,%RAX

(215) 0x23f283 CQTO

(215) 0x23f285 IDIV	%R13

(215) 0x23f288 MOV	-0x48(%RBP),%RSI

(215) 0x23f28c MOVSXD	%EDX,%RDX

(215) 0x23f28f VMOVSD	(%RSI),%XMM0

(215) 0x23f293 CLTQ

(215) 0x23f295 MOV	%RAX,%RSI

(215) 0x23f298 IMUL	%R9,%RSI

(215) 0x23f29c ADD	%RDX,%RSI

(215) 0x23f29f VMOVSD	%XMM0,(%RDI,%RSI,8)

(215) 0x23f2a4 MOV	-0x40(%RBP),%RSI

(215) 0x23f2a8 VMOVSD	(%RSI),%XMM0

(215) 0x23f2ac MOV	%RAX,%RSI

(215) 0x23f2af IMUL	%R10,%RSI

(215) 0x23f2b3 ADD	%RDX,%RSI

(215) 0x23f2b6 VMOVSD	%XMM0,(%R11,%RSI,8)

(215) 0x23f2bc MOV	-0x88(%RBP),%RSI

(215) 0x23f2c3 VMOVSD	(%RSI),%XMM0

(215) 0x23f2c7 MOV	%RAX,%RSI

(215) 0x23f2ca IMUL	%R14,%RSI

(215) 0x23f2ce IMUL	-0x90(%RBP),%RAX

(215) 0x23f2d6 ADD	%RDX,%RSI

(215) 0x23f2d9 ADD	%RDX,%RAX

(215) 0x23f2dc VMOVSD	%XMM0,(%RBX,%RSI,8)

(215) 0x23f2e1 VMOVQ	(%R15),%XMM0

(215) 0x23f2e6 VMOVQ	%XMM0,(%R8,%RAX,8)

(215) 0x23f2ec CMP	%R12,%RCX

(215) 0x23f2ef LEA	0x1(%RCX),%RCX

(215) 0x23f2f3 JL	23f280

0x23f2f5 MOV	-0x34(%RBP),%ESI

0x23f2f8 LEA	0x1bf01(%RIP),%RDI

0x23f2ff VZEROUPPER

0x23f302 CALL	259690 <@plt_start@+0x540>

0x23f307 ADD	$0x78,%RSP

0x23f30b POP	%RBX

0x23f30c POP	%R12

0x23f30e POP	%R13

0x23f310 POP	%R14

0x23f312 POP	%R15

0x23f314 POP	%RBP

0x23f315 RET

0x23f316 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run aocc_8

Source file and lines	generate_chunk.cpp:74-80
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp:74-80

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 14.88 to 4.00 cycles (3.72x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions).

Details

6% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

7% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
50% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
10% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp:74
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp:74

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVL: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp:75
VPBROADCASTQ: 6 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp:75
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp:75
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp:75
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp:75
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp:75
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp:75

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 248 bytes. The binary function is storing 120 bytes.

General properties

nb instructions	113
nb uops	119
loop length	481
used x86 registers	16
used mmx registers	0
used xmm registers	1
used ymm registers	7
used zmm registers	0
nb stack references	18

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	14.88 cycles
front end	14.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.83	5.83	5.83	5.83	5.83	5.83	12.00	12.00	12.00	12.00	0.50	4.00	4.00	0.50	0.00	0.00
cycles	5.83	5.83	5.83	5.83	5.83	5.83	12.00	12.00	12.00	12.00	0.50	4.00	4.00	0.50	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	14.88
Dispatch	12.00
Overall L1	14.88

Vectorization ratios

all	6%
load	7%
store	0%
mul	0%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Vector efficiency ratios

all	12%
load	14%
store	10%
mul	12%
add-sub	31%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 14.88 cycles. At this rate:

6% of peak load performance is reached (16.67 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (8.07 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 14.88 to 12.00 cycles (1.24x speedup).

ASM code

In the binary file, the address of the function is: 23ef20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x78,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RDX),%R12D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
TEST %R12D,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 23f307 <_Z14generate_chunkiR16global_variables.omp_outlined+0x3e7>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV (%RCX),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
TEST %EAX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 23f307 <_Z14generate_chunkiR16global_variables.omp_outlined+0x3e7>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOVSXD %EAX,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %R9,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R8,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVQ $0,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOVQ $0x1,-0x98(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOVL $0,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
IMUL %R13,%R12	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
DEC %R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R12,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x38(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x98(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x1c25b(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x50(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x30(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %ESI,-0x34(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 259680 <@plt_start@+0x530>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x30(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x50(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
CMP %R12,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMOVL %RAX,%R12	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
MOV %R12,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
CMP %R12,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JG 23f2f5 <_Z14generate_chunkiR16global_variables.omp_outlined+0x3d5>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x8(%RBX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x10(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x20(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x18(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x40(%R15),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x30(%R15),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV (%R15),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%R15),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV 0xb8(%R15),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0xa8(%R15),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV %RAX,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x8(%R8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x8(%RDX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0xe8(%R15),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0xd8(%R15),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x8(%RSI),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RAX,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R12,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RCX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R15,-0x90(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDX,-0x88(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x4,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 23f03b <_Z14generate_chunkiR16global_variables.omp_outlined+0x11b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RSI,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 23f280 <_Z14generate_chunkiR16global_variables.omp_outlined+0x360>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
VPBROADCASTQ %RCX,%YMM0	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPADDQ -0x2dd69(%RIP),%YMM0,%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	1	0.50	vect (50.0%)
VPBROADCASTQ -0x2de82(%RIP),%YMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	1	0.50	scal (12.5%)
MOV %R9,-0x78(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
VPBROADCASTQ %R9,%YMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
MOV -0x40(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV %RAX,-0x60(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
AND $-0x4,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VPBROADCASTQ %R13,%YMM1	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPBROADCASTQ %R15,%YMM5	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPBROADCASTQ %R10,%YMM3	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPBROADCASTQ %R14,%YMM4	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
MOV %R10,-0x70(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R14,-0x68(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R13,-0x80(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDX,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RSI,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %RAX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VEXTRACTI128 $0x1,%YMM1,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	3	0.50	vect (25.0%)
MOV %RAX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RAX,-0x58(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0x58(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x80(%RBP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV -0x78(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV -0x70(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV -0x68(%RBP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
CMP %RAX,-0x60(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JE 23f2f5 <_Z14generate_chunkiR16global_variables.omp_outlined+0x3d5>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0x34(%RBP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
LEA 0x1bf01(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 259690 <@plt_start@+0x540>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
ADD $0x78,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run aocc_8

Source file and lines	generate_chunk.cpp:74-80
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp:74-80

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 14.88 to 4.00 cycles (3.72x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions).

Details

6% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

7% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
50% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
10% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp:74
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp:74

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVL: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp:75
VPBROADCASTQ: 6 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp:75
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp:75
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp:75
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp:75
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp:75
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp:75

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 248 bytes. The binary function is storing 120 bytes.

General properties

nb instructions	113
nb uops	119
loop length	481
used x86 registers	16
used mmx registers	0
used xmm registers	1
used ymm registers	7
used zmm registers	0
nb stack references	18

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	14.88 cycles
front end	14.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.83	5.83	5.83	5.83	5.83	5.83	12.00	12.00	12.00	12.00	0.50	4.00	4.00	0.50	0.00	0.00
cycles	5.83	5.83	5.83	5.83	5.83	5.83	12.00	12.00	12.00	12.00	0.50	4.00	4.00	0.50	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	14.88
Dispatch	12.00
Overall L1	14.88

Vectorization ratios

all	6%
load	7%
store	0%
mul	0%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Vector efficiency ratios

all	12%
load	14%
store	10%
mul	12%
add-sub	31%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 14.88 cycles. At this rate:

6% of peak load performance is reached (16.67 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (8.07 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 23ef20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x78,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RDX),%R12D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
TEST %R12D,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 23f307 <_Z14generate_chunkiR16global_variables.omp_outlined+0x3e7>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV (%RCX),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
TEST %EAX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 23f307 <_Z14generate_chunkiR16global_variables.omp_outlined+0x3e7>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOVSXD %EAX,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %R9,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R8,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVQ $0,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOVQ $0x1,-0x98(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOVL $0,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
IMUL %R13,%R12	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
DEC %R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R12,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x38(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x98(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x1c25b(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x50(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x30(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %ESI,-0x34(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 259680 <@plt_start@+0x530>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x30(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x50(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
CMP %R12,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMOVL %RAX,%R12	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
MOV %R12,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
CMP %R12,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JG 23f2f5 <_Z14generate_chunkiR16global_variables.omp_outlined+0x3d5>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x8(%RBX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x10(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x20(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x18(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x40(%R15),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x30(%R15),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV (%R15),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%R15),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV 0xb8(%R15),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0xa8(%R15),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV %RAX,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x8(%R8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x8(%RDX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0xe8(%R15),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0xd8(%R15),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x8(%RSI),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RAX,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R12,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RCX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R15,-0x90(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDX,-0x88(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x4,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 23f03b <_Z14generate_chunkiR16global_variables.omp_outlined+0x11b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RSI,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 23f280 <_Z14generate_chunkiR16global_variables.omp_outlined+0x360>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
VPBROADCASTQ %RCX,%YMM0	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPADDQ -0x2dd69(%RIP),%YMM0,%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	1	0.50	vect (50.0%)
VPBROADCASTQ -0x2de82(%RIP),%YMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	1	0.50	scal (12.5%)
MOV %R9,-0x78(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
VPBROADCASTQ %R9,%YMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
MOV -0x40(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV %RAX,-0x60(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
AND $-0x4,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VPBROADCASTQ %R13,%YMM1	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPBROADCASTQ %R15,%YMM5	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPBROADCASTQ %R10,%YMM3	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPBROADCASTQ %R14,%YMM4	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
MOV %R10,-0x70(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R14,-0x68(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R13,-0x80(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDX,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RSI,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %RAX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VEXTRACTI128 $0x1,%YMM1,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	3	0.50	vect (25.0%)
MOV %RAX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RAX,-0x58(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0x58(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x80(%RBP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV -0x78(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV -0x70(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV -0x68(%RBP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
CMP %RAX,-0x60(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JE 23f2f5 <_Z14generate_chunkiR16global_variables.omp_outlined+0x3d5>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0x34(%RBP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
LEA 0x1bf01(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 259690 <@plt_start@+0x540>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
ADD $0x78,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼generate_chunk(int, global_variables&) [clone .omp_outlined]–	0.04	0.02
○Loop 214 - generate_chunk.cpp:75-80 - exec	0.04	0.02
○Loop 215 - generate_chunk.cpp:75-80 - exec	0.00	0.00

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512-bits vectorization

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512-bits vectorization

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Complex instructions

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Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

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Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code