OV - exec - Function flux_calc_kernel(int, int, int, int, double, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone .omp

	Function: flux_calc_kernel(int, int, int, int, double, clover::Buffer2D<double>&, clover::Buffer2D<d ...	Module: exec	Source: flux_calc.cpp:36-40 [...]	Coverage (incl. loops): 4.25% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/flux_calc.cpp: 36 - 40

--------------------------------------------------------------------------------

36: #pragma omp parallel for simd collapse(2)

37:   for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) {

38:     for (int i = (x_min + 1); i < (x_max + 1 + 2); i++) {

39:       vol_flux_x(i, j) = 0.25 * dt * xarea(i, j) * (xvel0(i, j) + xvel0(i + 0, j + 1) + xvel1(i, j) + xvel1(i + 0, j + 1));

40:       vol_flux_y(i, j) = 0.25 * dt * yarea(i, j) * (yvel0(i, j) + yvel0(i + 1, j + 0) + yvel1(i, j) + yvel1(i + 1, j + 0));

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x23e130 PUSH	%RBP

0x23e131 MOV	%RSP,%RBP

0x23e134 PUSH	%R15

0x23e136 PUSH	%R14

0x23e138 PUSH	%R13

0x23e13a PUSH	%R12

0x23e13c PUSH	%RBX

0x23e13d SUB	$0xb8,%RSP

0x23e144 MOV	(%RDX),%EAX

0x23e146 MOV	(%RCX),%R15D

0x23e149 INC	%EAX

0x23e14b ADD	$0x3,%R15D

0x23e14f SUB	%EAX,%R15D

0x23e152 JLE	23e9eb

0x23e158 MOV	(%R9),%EDX

0x23e15b MOV	(%R8),%ECX

0x23e15e INC	%ECX

0x23e160 ADD	$0x3,%EDX

0x23e163 CMP	%ECX,%EDX

0x23e165 JLE	23e9eb

0x23e16b SUB	%ECX,%EDX

0x23e16d MOV	(%RDI),%ESI

0x23e16f MOVQ	$0,-0x98(%RBP)

0x23e17a MOVQ	$0x1,-0xd8(%RBP)

0x23e185 MOVL	$0,-0x50(%RBP)

0x23e18c IMUL	%RDX,%R15

0x23e190 DEC	%R15

0x23e193 MOV	%R15,-0x48(%RBP)

0x23e197 SUB	$0x8,%RSP

0x23e19b MOV	%ECX,%R14D

0x23e19e LEA	-0x50(%RBP),%RCX

0x23e1a2 MOV	%RAX,%RBX

0x23e1a5 MOV	%RDX,%R12

0x23e1a8 LEA	-0xd8(%RBP),%RAX

0x23e1af LEA	0x1cfea(%RIP),%RDI

0x23e1b6 LEA	-0x98(%RBP),%R8

0x23e1bd LEA	-0x48(%RBP),%R9

0x23e1c1 MOV	%ESI,-0x4c(%RBP)

0x23e1c4 MOV	$0x22,%EDX

0x23e1c9 PUSH	$0x1

0x23e1cb PUSH	$0x1

0x23e1cd PUSH	%RAX

0x23e1ce CALL	259680 <@plt_start@+0x530>

0x23e1d3 ADD	$0x20,%RSP

0x23e1d7 MOV	-0x48(%RBP),%RAX

0x23e1db MOV	-0x98(%RBP),%RCX

0x23e1e2 CMP	%R15,%RAX

0x23e1e5 CMOVL	%RAX,%R15

0x23e1e9 MOV	%R15,-0x48(%RBP)

0x23e1ed CMP	%R15,%RCX

0x23e1f0 JG	23e9d9

0x23e1f6 MOV	0x20(%RBP),%R9

0x23e1fa MOV	0x10(%RBP),%R10

0x23e1fe MOV	0x50(%RBP),%RAX

0x23e202 MOV	0x48(%RBP),%RDX

0x23e206 MOV	%R12,-0x80(%RBP)

0x23e20a MOV	0x40(%RBP),%RSI

0x23e20e MOV	0x30(%RBP),%RDI

0x23e212 MOV	0x28(%RBP),%R8

0x23e216 MOV	%R14D,-0x2c(%RBP)

0x23e21a MOV	%RBX,-0x38(%RBP)

0x23e21e MOV	(%R9),%R11

0x23e221 MOV	0x10(%R9),%R9

0x23e225 MOV	0x10(%RDX),%R12

0x23e229 MOV	0x10(%RAX),%R13

0x23e22d MOV	(%R8),%RBX

0x23e230 MOV	(%RDI),%R14

0x23e233 MOV	%R9,-0x70(%RBP)

0x23e237 MOV	0x10(%R10),%R9

0x23e23b MOV	%R11,-0x78(%RBP)

0x23e23f MOV	0x10(%R8),%R11

0x23e243 MOV	0x10(%RDI),%R8

0x23e247 MOV	(%R10),%RDI

0x23e24a MOV	(%RSI),%R10

0x23e24d MOV	0x10(%RSI),%RSI

0x23e251 MOV	%R9,-0x58(%RBP)

0x23e255 MOV	(%RDX),%R9

0x23e258 MOV	(%RAX),%RDX

0x23e25b MOV	0x38(%RBP),%RAX

0x23e25f MOV	%RDI,-0xd0(%RBP)

0x23e266 MOV	%R10,-0xc8(%RBP)

0x23e26d MOV	%RSI,-0x88(%RBP)

0x23e274 MOV	%R9,-0x68(%RBP)

0x23e278 MOV	(%RAX),%R9

0x23e27b MOV	0x10(%RAX),%RAX

0x23e27f MOV	%RDX,-0xc0(%RBP)

0x23e286 MOV	%R9,-0x60(%RBP)

0x23e28a MOV	%R15,%R9

0x23e28d SUB	%RCX,%R9

0x23e290 MOV	%RAX,-0x90(%RBP)

0x23e297 INC	%R9

0x23e29a CMP	$0x4,%R9

0x23e29e JAE	23e2b1

0x23e2a0 MOV	-0x38(%RBP),%R9

0x23e2a4 MOV	-0x2c(%RBP),%R10D

0x23e2a8 MOV	0x18(%RBP),%RDI

0x23e2ac JMP	23e896

0x23e2b1 MOV	-0x80(%RBP),%RAX

0x23e2b5 MOV	-0x2c(%RBP),%ESI

0x23e2b8 VPBROADCASTQ	%RCX,%YMM0

0x23e2be VPADDQ	-0x2cfe6(%RIP),%YMM0,%YMM0

0x23e2c6 VMOVSD	-0x2d13e(%RIP),%XMM13

0x23e2ce VPBROADCASTQ	-0x2d107(%RIP),%YMM15

0x23e2d7 VPBROADCASTQ	%RDX,%YMM10

0x23e2dd MOV	-0x60(%RBP),%RDX

0x23e2e1 VPBROADCASTQ	%RDI,%YMM7

0x23e2e7 VPBROADCASTQ	%R10,%YMM8

0x23e2ed MOV	%RBX,-0xb8(%RBP)

0x23e2f4 VPBROADCASTQ	%RBX,%YMM5

0x23e2fa MOV	-0x70(%RBP),%R10

0x23e2fe MOV	-0x58(%RBP),%RBX

0x23e302 MOV	0x18(%RBP),%RDI

0x23e306 MOV	%R9,-0xa8(%RBP)

0x23e30d AND	$-0x4,%R9

0x23e311 VPBROADCASTQ	%R14,%YMM6

0x23e317 VPCMPEQD	%XMM14,%XMM14,%XMM14

0x23e31c MOV	%R14,-0xb0(%RBP)

0x23e323 ADD	%R9,%RCX

0x23e326 MOV	%R9,-0xa0(%RBP)

0x23e32d VPBROADCASTQ	%RAX,%YMM1

0x23e333 MOV	-0x38(%RBP),%RAX

0x23e337 VPBROADCASTD	%ESI,%XMM3

0x23e33d MOV	-0x68(%RBP),%RSI

0x23e341 VPBROADCASTQ	%RDX,%YMM11

0x23e347 VEXTRACTI128	$0x1,%YMM1,%XMM12

0x23e34d VPBROADCASTD	%EAX,%XMM2

0x23e353 MOV	-0x78(%RBP),%RAX

0x23e357 VPBROADCASTQ	%RSI,%YMM9

0x23e35d VPBROADCASTQ	%RAX,%YMM4

0x23e363 NOPW	%CS:(%RAX,%RAX,1)

(209) 0x23e370 VEXTRACTI32X4	$0x1,%YMM0,%XMM16

(209) 0x23e377 VPEXTRQ	$0x1,%XMM12,%RSI

(209) 0x23e37d MOV	%R9,-0x40(%RBP)

(209) 0x23e381 MOV	%RDI,%R14

(209) 0x23e384 VMOVQ	%XMM12,%RDI

(209) 0x23e389 VPEXTRQ	$0x1,%XMM1,%R9

(209) 0x23e38f VPEXTRQ	$0x1,%XMM16,%RAX

(209) 0x23e396 CQTO

(209) 0x23e398 IDIV	%RSI

(209) 0x23e39b MOV	%RAX,%RSI

(209) 0x23e39e VMOVQ	%XMM16,%RAX

(209) 0x23e3a4 VMOVQ	%RSI,%XMM16

(209) 0x23e3aa VMOVQ	%XMM1,%RSI

(209) 0x23e3af CQTO

(209) 0x23e3b1 IDIV	%RDI

(209) 0x23e3b4 MOV	%RAX,%RDI

(209) 0x23e3b7 VPEXTRQ	$0x1,%XMM0,%RAX

(209) 0x23e3bd VMOVQ	%RDI,%XMM17

(209) 0x23e3c3 MOV	%R14,%RDI

(209) 0x23e3c6 CQTO

(209) 0x23e3c8 VPUNPCKLQDQ	%XMM16,%XMM17,%XMM16

(209) 0x23e3ce IDIV	%R9

(209) 0x23e3d1 VMOVQ	%RAX,%XMM18

(209) 0x23e3d7 VMOVQ	%XMM0,%RAX

(209) 0x23e3dc CQTO

(209) 0x23e3de IDIV	%RSI

(209) 0x23e3e1 VMULSD	(%R14),%XMM13,%XMM20

(209) 0x23e3e7 MOV	-0x88(%RBP),%RSI

(209) 0x23e3ee MOV	-0x40(%RBP),%R9

(209) 0x23e3f2 ADD	$-0x4,%R9

(209) 0x23e3f6 VBROADCASTSD	%XMM20,%YMM20

(209) 0x23e3fc VMOVQ	%RAX,%XMM19

(209) 0x23e402 VPUNPCKLQDQ	%XMM18,%XMM19,%XMM17

(209) 0x23e408 VINSERTI32X4	$0x1,%XMM16,%YMM17,%YMM16

(209) 0x23e40f VPMOVQD	%YMM16,%XMM17

(209) 0x23e415 VPMULLQ	%YMM1,%YMM16,%YMM16

(209) 0x23e41b VPSUBQ	%YMM16,%YMM0,%YMM16

(209) 0x23e421 VPADDQ	%YMM0,%YMM15,%YMM0

(209) 0x23e425 VPMOVQD	%YMM16,%XMM16

(209) 0x23e42b VPADDD	%XMM17,%XMM2,%XMM19

(209) 0x23e431 VPMOVSXDQ	%XMM19,%YMM17

(209) 0x23e437 VPSUBD	%XMM14,%XMM19,%XMM19

(209) 0x23e43d VPMOVSXDQ	%XMM19,%YMM19

(209) 0x23e443 VPMULLQ	%YMM17,%YMM4,%YMM21

(209) 0x23e449 VPADDD	%XMM16,%XMM3,%XMM18

(209) 0x23e44f VPMOVSXDQ	%XMM18,%YMM16

(209) 0x23e455 VPSUBD	%XMM14,%XMM18,%XMM18

(209) 0x23e45b VPMOVSXDQ	%XMM18,%YMM18

(209) 0x23e461 VPADDQ	%YMM16,%YMM21,%YMM21

(209) 0x23e467 VEXTRACTI32X4	$0x1,%YMM21,%XMM22

(209) 0x23e46e VMOVQ	%XMM21,%RAX

(209) 0x23e474 VMOVQ	%XMM22,%RDX

(209) 0x23e47a VMOVSD	(%R10,%RDX,8),%XMM23

(209) 0x23e481 VPEXTRQ	$0x1,%XMM21,%RDX

(209) 0x23e488 VMOVSD	(%R10,%RAX,8),%XMM21

(209) 0x23e48f VPEXTRQ	$0x1,%XMM22,%RAX

(209) 0x23e496 VPMULLQ	%YMM17,%YMM5,%YMM22

(209) 0x23e49c VMOVHPD	(%R10,%RDX,8),%XMM21,%XMM21

(209) 0x23e4a3 VMOVHPD	(%R10,%RAX,8),%XMM23,%XMM23

(209) 0x23e4aa VPADDQ	%YMM16,%YMM22,%YMM22

(209) 0x23e4b0 VEXTRACTI32X4	$0x1,%YMM22,%XMM24

(209) 0x23e4b7 VMOVQ	%XMM24,%RDX

(209) 0x23e4bd VMOVSD	(%R11,%RDX,8),%XMM25

(209) 0x23e4c4 VMOVQ	%XMM22,%RDX

(209) 0x23e4ca VMOVSD	(%R11,%RDX,8),%XMM26

(209) 0x23e4d1 VPEXTRQ	$0x1,%XMM22,%RDX

(209) 0x23e4d8 VMOVHPD	(%R11,%RDX,8),%XMM26,%XMM22

(209) 0x23e4df VPEXTRQ	$0x1,%XMM24,%RDX

(209) 0x23e4e6 VPMULLQ	%YMM19,%YMM5,%YMM24

(209) 0x23e4ec VPMULLQ	%YMM19,%YMM6,%YMM19

(209) 0x23e4f2 VMOVHPD	(%R11,%RDX,8),%XMM25,%XMM25

(209) 0x23e4f9 VINSERTF32X4	$0x1,%XMM23,%YMM21,%YMM21

(209) 0x23e500 VPADDQ	%YMM16,%YMM24,%YMM24

(209) 0x23e506 VPADDQ	%YMM16,%YMM19,%YMM19

(209) 0x23e50c VMULPD	%YMM21,%YMM20,%YMM20

(209) 0x23e512 VEXTRACTI32X4	$0x1,%YMM24,%XMM26

(209) 0x23e519 VMOVQ	%XMM26,%RAX

(209) 0x23e51f VPEXTRQ	$0x1,%XMM26,%RDX

(209) 0x23e526 VMOVSD	(%R11,%RAX,8),%XMM27

(209) 0x23e52d VMOVQ	%XMM24,%RAX

(209) 0x23e533 VMOVHPD	(%R11,%RDX,8),%XMM27,%XMM26

(209) 0x23e53a VPEXTRQ	$0x1,%XMM24,%RDX

(209) 0x23e541 VPMULLQ	%YMM17,%YMM6,%YMM24

(209) 0x23e547 VMOVSD	(%R11,%RAX,8),%XMM23

(209) 0x23e54e VMOVHPD	(%R11,%RDX,8),%XMM23,%XMM23

(209) 0x23e555 VINSERTF32X4	$0x1,%XMM25,%YMM22,%YMM22

(209) 0x23e55c VPADDQ	%YMM16,%YMM24,%YMM24

(209) 0x23e562 VEXTRACTI32X4	$0x1,%YMM24,%XMM25

(209) 0x23e569 VMOVQ	%XMM24,%RAX

(209) 0x23e56f VMOVQ	%XMM25,%RDX

(209) 0x23e575 VMOVSD	(%R8,%RDX,8),%XMM27

(209) 0x23e57c VPEXTRQ	$0x1,%XMM25,%RDX

(209) 0x23e583 VMOVHPD	(%R8,%RDX,8),%XMM27,%XMM25

(209) 0x23e58a VPEXTRQ	$0x1,%XMM24,%RDX

(209) 0x23e591 VMOVSD	(%R8,%RAX,8),%XMM24

(209) 0x23e598 VPEXTRQ	$0x1,%XMM19,%RAX

(209) 0x23e59f VMOVHPD	(%R8,%RDX,8),%XMM24,%XMM24

(209) 0x23e5a6 VINSERTF32X4	$0x1,%XMM26,%YMM23,%YMM23

(209) 0x23e5ad VADDPD	%YMM22,%YMM23,%YMM22

(209) 0x23e5b3 VINSERTF32X4	$0x1,%XMM25,%YMM24,%YMM24

(209) 0x23e5ba VEXTRACTI32X4	$0x1,%YMM19,%XMM25

(209) 0x23e5c1 VMOVQ	%XMM25,%RDX

(209) 0x23e5c7 VMOVSD	(%R8,%RDX,8),%XMM21

(209) 0x23e5ce VPEXTRQ	$0x1,%XMM25,%RDX

(209) 0x23e5d5 VMOVHPD	(%R8,%RDX,8),%XMM21,%XMM21

(209) 0x23e5dc VMOVQ	%XMM19,%RDX

(209) 0x23e5e2 VMOVSD	(%R8,%RDX,8),%XMM19

(209) 0x23e5e9 VMOVHPD	(%R8,%RAX,8),%XMM19,%XMM19

(209) 0x23e5f0 VINSERTF32X4	$0x1,%XMM21,%YMM19,%YMM19

(209) 0x23e5f7 VPMULLQ	%YMM17,%YMM7,%YMM21

(209) 0x23e5fd VADDPD	%YMM19,%YMM24,%YMM19

(209) 0x23e603 VPADDQ	%YMM16,%YMM21,%YMM21

(209) 0x23e609 VMOVQ	%XMM21,%RAX

(209) 0x23e60f VPEXTRQ	$0x1,%XMM21,%RDX

(209) 0x23e616 VADDPD	%YMM19,%YMM22,%YMM19

(209) 0x23e61c VMULPD	%YMM19,%YMM20,%YMM19

(209) 0x23e622 VEXTRACTI32X4	$0x1,%YMM21,%XMM20

(209) 0x23e629 VMOVLPD	%XMM19,(%RBX,%RAX,8)

(209) 0x23e630 VMOVHPD	%XMM19,(%RBX,%RDX,8)

(209) 0x23e637 VMOVQ	%XMM20,%RAX

(209) 0x23e63d VPEXTRQ	$0x1,%XMM20,%RDX

(209) 0x23e644 VPMULLQ	%YMM17,%YMM8,%YMM20

(209) 0x23e64a VEXTRACTF32X4	$0x1,%YMM19,%XMM19

(209) 0x23e651 VMOVLPD	%XMM19,(%RBX,%RAX,8)

(209) 0x23e658 VMOVHPD	%XMM19,(%RBX,%RDX,8)

(209) 0x23e65f VPADDQ	%YMM16,%YMM20,%YMM20

(209) 0x23e665 VEXTRACTI32X4	$0x1,%YMM20,%XMM19

(209) 0x23e66c VMOVQ	%XMM20,%RAX

(209) 0x23e672 VMOVQ	%XMM19,%RDX

(209) 0x23e678 VMOVSD	(%RSI,%RDX,8),%XMM21

(209) 0x23e67f VPEXTRQ	$0x1,%XMM19,%RDX

(209) 0x23e686 VMOVHPD	(%RSI,%RDX,8),%XMM21,%XMM19

(209) 0x23e68d VPMULLQ	%YMM17,%YMM9,%YMM21

(209) 0x23e693 VPEXTRQ	$0x1,%XMM20,%RDX

(209) 0x23e69a VMOVSD	(%RSI,%RAX,8),%XMM20

(209) 0x23e6a1 VMOVHPD	(%RSI,%RDX,8),%XMM20,%XMM20

(209) 0x23e6a8 VPADDQ	%YMM16,%YMM21,%YMM22

(209) 0x23e6ae VPADDQ	%YMM18,%YMM21,%YMM21

(209) 0x23e6b4 VEXTRACTI32X4	$0x1,%YMM22,%XMM23

(209) 0x23e6bb VMOVQ	%XMM22,%RAX

(209) 0x23e6c1 VMOVQ	%XMM23,%RDX

(209) 0x23e6c7 VMOVSD	(%R12,%RDX,8),%XMM24

(209) 0x23e6ce VPEXTRQ	$0x1,%XMM23,%RDX

(209) 0x23e6d5 VMOVHPD	(%R12,%RDX,8),%XMM24,%XMM23

(209) 0x23e6dc VEXTRACTI32X4	$0x1,%YMM21,%XMM24

(209) 0x23e6e3 VPEXTRQ	$0x1,%XMM22,%RDX

(209) 0x23e6ea VMOVSD	(%R12,%RAX,8),%XMM22

(209) 0x23e6f1 VMOVQ	%XMM24,%RAX

(209) 0x23e6f7 VMOVHPD	(%R12,%RDX,8),%XMM22,%XMM22

(209) 0x23e6fe VPEXTRQ	$0x1,%XMM24,%RDX

(209) 0x23e705 VMOVSD	(%R12,%RAX,8),%XMM24

(209) 0x23e70c VMOVQ	%XMM21,%RAX

(209) 0x23e712 VINSERTF32X4	$0x1,%XMM19,%YMM20,%YMM19

(209) 0x23e719 VMOVSD	(%R12,%RAX,8),%XMM25

(209) 0x23e720 VPEXTRQ	$0x1,%XMM21,%RAX

(209) 0x23e727 VMOVHPD	(%R12,%RDX,8),%XMM24,%XMM24

(209) 0x23e72e MOV	-0x90(%RBP),%RDX

(209) 0x23e735 VMOVHPD	(%R12,%RAX,8),%XMM25,%XMM21

(209) 0x23e73c VPMULLQ	%YMM17,%YMM10,%YMM25

(209) 0x23e742 VPMULLQ	%YMM17,%YMM11,%YMM17

(209) 0x23e748 VPADDQ	%YMM16,%YMM25,%YMM26

(209) 0x23e74e VPADDQ	%YMM18,%YMM25,%YMM18

(209) 0x23e754 VPADDQ	%YMM16,%YMM17,%YMM16

(209) 0x23e75a VEXTRACTI32X4	$0x1,%YMM26,%XMM27

(209) 0x23e761 VMOVQ	%XMM27,%RAX

(209) 0x23e767 VINSERTF32X4	$0x1,%XMM23,%YMM22,%YMM22

(209) 0x23e76e VMOVSD	(%R13,%RAX,8),%XMM20

(209) 0x23e776 VPEXTRQ	$0x1,%XMM27,%RAX

(209) 0x23e77d VMOVHPD	(%R13,%RAX,8),%XMM20,%XMM20

(209) 0x23e785 VMOVQ	%XMM26,%RAX

(209) 0x23e78b VMOVSD	(%R13,%RAX,8),%XMM23

(209) 0x23e793 VPEXTRQ	$0x1,%XMM26,%RAX

(209) 0x23e79a VINSERTF32X4	$0x1,%XMM24,%YMM21,%YMM21

(209) 0x23e7a1 VMULSD	(%R14),%XMM13,%XMM26

(209) 0x23e7a7 VMOVHPD	(%R13,%RAX,8),%XMM23,%XMM23

(209) 0x23e7af VINSERTF32X4	$0x1,%XMM20,%YMM23,%YMM20

(209) 0x23e7b6 VEXTRACTI32X4	$0x1,%YMM18,%XMM23

(209) 0x23e7bd VMOVQ	%XMM23,%RAX

(209) 0x23e7c3 VBROADCASTSD	%XMM26,%YMM25

(209) 0x23e7c9 VMOVSD	(%R13,%RAX,8),%XMM24

(209) 0x23e7d1 VPEXTRQ	$0x1,%XMM23,%RAX

(209) 0x23e7d8 VADDPD	%YMM20,%YMM22,%YMM20

(209) 0x23e7de VMOVHPD	(%R13,%RAX,8),%XMM24,%XMM23

(209) 0x23e7e6 VMOVQ	%XMM18,%RAX

(209) 0x23e7ec VMULPD	%YMM19,%YMM25,%YMM19

(209) 0x23e7f2 VMOVSD	(%R13,%RAX,8),%XMM24

(209) 0x23e7fa VPEXTRQ	$0x1,%XMM18,%RAX

(209) 0x23e801 VMOVHPD	(%R13,%RAX,8),%XMM24,%XMM18

(209) 0x23e809 VMOVQ	%XMM16,%RAX

(209) 0x23e80f VINSERTF32X4	$0x1,%XMM23,%YMM18,%YMM18

(209) 0x23e816 VADDPD	%YMM18,%YMM21,%YMM18

(209) 0x23e81c VADDPD	%YMM20,%YMM18,%YMM18

(209) 0x23e822 VMULPD	%YMM18,%YMM19,%YMM18

(209) 0x23e828 VMOVLPD	%XMM18,(%RDX,%RAX,8)

(209) 0x23e82f VPEXTRQ	$0x1,%XMM16,%RAX

(209) 0x23e836 VEXTRACTI32X4	$0x1,%YMM16,%XMM16

(209) 0x23e83d VEXTRACTF32X4	$0x1,%YMM18,%XMM17

(209) 0x23e844 VMOVHPD	%XMM18,(%RDX,%RAX,8)

(209) 0x23e84b VMOVQ	%XMM16,%RAX

(209) 0x23e851 VMOVLPD	%XMM17,(%RDX,%RAX,8)

(209) 0x23e858 VPEXTRQ	$0x1,%XMM16,%RAX

(209) 0x23e85f VMOVHPD	%XMM17,(%RDX,%RAX,8)

(209) 0x23e866 JNE	23e370

0x23e86c MOV	-0xa0(%RBP),%RAX

0x23e873 MOV	-0x38(%RBP),%R9

0x23e877 MOV	-0x2c(%RBP),%R10D

0x23e87b MOV	-0xb8(%RBP),%RBX

0x23e882 MOV	-0xb0(%RBP),%R14

0x23e889 CMP	%RAX,-0xa8(%RBP)

0x23e890 JE	23e9d9

0x23e896 VMOVSD	-0x2d70e(%RIP),%XMM0

0x23e89e XCHG	%AX,%AX

(210) 0x23e8a0 MOV	%RCX,%RAX

(210) 0x23e8a3 CQTO

(210) 0x23e8a5 IDIVQ	-0x80(%RBP)

(210) 0x23e8a9 VMULSD	(%RDI),%XMM0,%XMM1

(210) 0x23e8ad MOV	-0x78(%RBP),%RDI

(210) 0x23e8b1 ADD	%R10D,%EDX

(210) 0x23e8b4 MOV	%R15,%R10

(210) 0x23e8b7 MOV	%R14,%R15

(210) 0x23e8ba MOV	%RBX,%R14

(210) 0x23e8bd MOV	-0x70(%RBP),%RBX

(210) 0x23e8c1 MOVSXD	%EDX,%RDX

(210) 0x23e8c4 LEA	(%R9,%RAX,1),%ESI

(210) 0x23e8c8 LEA	0x1(%R9,%RAX,1),%EAX

(210) 0x23e8cd MOVSXD	%ESI,%RSI

(210) 0x23e8d0 IMUL	%RSI,%RDI

(210) 0x23e8d4 CLTQ

(210) 0x23e8d6 ADD	%RDX,%RDI

(210) 0x23e8d9 VMULSD	(%RBX,%RDI,8),%XMM1,%XMM1

(210) 0x23e8de MOV	%R14,%RBX

(210) 0x23e8e1 MOV	%RBX,%R9

(210) 0x23e8e4 IMUL	%RAX,%R9

(210) 0x23e8e8 MOV	%RBX,%RDI

(210) 0x23e8eb IMUL	%RSI,%RDI

(210) 0x23e8ef MOV	%R15,%R14

(210) 0x23e8f2 IMUL	%R14,%RAX

(210) 0x23e8f6 MOV	%R10,%R15

(210) 0x23e8f9 MOV	-0x2c(%RBP),%R10D

(210) 0x23e8fd ADD	%RDX,%R9

(210) 0x23e900 ADD	%RDX,%RDI

(210) 0x23e903 ADD	%RDX,%RAX

(210) 0x23e906 VMOVSD	(%R11,%R9,8),%XMM2

(210) 0x23e90c VADDSD	(%R11,%RDI,8),%XMM2,%XMM2

(210) 0x23e912 MOV	%R14,%RDI

(210) 0x23e915 IMUL	%RSI,%RDI

(210) 0x23e919 ADD	%RDX,%RDI

(210) 0x23e91c VADDSD	(%R8,%RDI,8),%XMM2,%XMM2

(210) 0x23e922 MOV	-0x58(%RBP),%RDI

(210) 0x23e926 VADDSD	(%R8,%RAX,8),%XMM2,%XMM2

(210) 0x23e92c MOV	-0xd0(%RBP),%RAX

(210) 0x23e933 IMUL	%RSI,%RAX

(210) 0x23e937 ADD	%RDX,%RAX

(210) 0x23e93a VMULSD	%XMM2,%XMM1,%XMM1

(210) 0x23e93e VMOVSD	%XMM1,(%RDI,%RAX,8)

(210) 0x23e943 MOV	-0x68(%RBP),%RDI

(210) 0x23e947 MOV	0x18(%RBP),%RAX

(210) 0x23e94b IMUL	%RSI,%RDI

(210) 0x23e94f VMULSD	(%RAX),%XMM0,%XMM1

(210) 0x23e953 MOV	-0xc8(%RBP),%RAX

(210) 0x23e95a LEA	0x1(%RDI,%RDX,1),%R9

(210) 0x23e95f ADD	%RDX,%RDI

(210) 0x23e962 MOV	%R9,-0x40(%RBP)

(210) 0x23e966 MOV	-0x88(%RBP),%R9

(210) 0x23e96d IMUL	%RSI,%RAX

(210) 0x23e971 ADD	%RDX,%RAX

(210) 0x23e974 VMULSD	(%R9,%RAX,8),%XMM1,%XMM1

(210) 0x23e97a MOV	-0x40(%RBP),%RAX

(210) 0x23e97e MOV	-0x38(%RBP),%R9

(210) 0x23e982 VMOVSD	(%R12,%RAX,8),%XMM2

(210) 0x23e988 MOV	-0xc0(%RBP),%RAX

(210) 0x23e98f VADDSD	(%R12,%RDI,8),%XMM2,%XMM2

(210) 0x23e995 IMUL	%RSI,%RAX

(210) 0x23e999 IMUL	-0x60(%RBP),%RSI

(210) 0x23e99e LEA	(%RAX,%RDX,1),%RDI

(210) 0x23e9a2 LEA	0x1(%RAX,%RDX,1),%RAX

(210) 0x23e9a7 VADDSD	(%R13,%RDI,8),%XMM2,%XMM2

(210) 0x23e9ae MOV	0x18(%RBP),%RDI

(210) 0x23e9b2 VADDSD	(%R13,%RAX,8),%XMM2,%XMM2

(210) 0x23e9b9 ADD	%RDX,%RSI

(210) 0x23e9bc MOV	-0x90(%RBP),%RDX

(210) 0x23e9c3 VMULSD	%XMM2,%XMM1,%XMM1

(210) 0x23e9c7 VMOVSD	%XMM1,(%RDX,%RSI,8)

(210) 0x23e9cc CMP	%R15,%RCX

(210) 0x23e9cf LEA	0x1(%RCX),%RCX

(210) 0x23e9d3 JL	23e8a0

0x23e9d9 MOV	-0x4c(%RBP),%ESI

0x23e9dc LEA	0x1c7d5(%RIP),%RDI

0x23e9e3 VZEROUPPER

0x23e9e6 CALL	259690 <@plt_start@+0x540>

0x23e9eb ADD	$0xb8,%RSP

0x23e9f2 POP	%RBX

0x23e9f3 POP	%R12

0x23e9f5 POP	%R13

0x23e9f7 POP	%R14

0x23e9f9 POP	%R15

0x23e9fb POP	%RBP

0x23e9fc RET

0x23e9fd NOPL	(%RAX)

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run aocc_8

Source file and lines	flux_calc.cpp:36-40
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/flux_calc.cpp:36-40
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 20.50 to 7.00 cycles (2.93x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions).

Details

6% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

6% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
25% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
12% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/flux_calc.cpp:36
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/flux_calc.cpp:36

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVL: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/flux_calc.cpp:37
VPBROADCASTD: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/flux_calc.cpp:37
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/flux_calc.cpp:37
VPBROADCASTQ: 10 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/flux_calc.cpp:37
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/flux_calc.cpp:37
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/flux_calc.cpp:37
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/flux_calc.cpp:37
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/flux_calc.cpp:37
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/flux_calc.cpp:37
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/flux_calc.cpp:37
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/flux_calc.cpp:37
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/flux_calc.cpp:37
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/flux_calc.cpp:37

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 420 bytes. The binary function is storing 172 bytes.

General properties

nb instructions	152
nb uops	164
loop length	667
used x86 registers	16
used mmx registers	0
used xmm registers	6
used ymm registers	11
used zmm registers	0
nb stack references	31

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	20.50 cycles
front end	20.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	6.50	6.50	6.50	6.50	6.50	6.50	19.75	19.75	19.75	19.75	1.00	7.00	7.00	1.00	0.00	0.00
cycles	6.50	6.50	6.50	6.50	6.50	6.50	19.75	19.75	19.75	19.75	1.00	7.00	7.00	1.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	20.50
Dispatch	19.75
Overall L1	20.50

Vectorization ratios

INT

all	6%
load	7%
store	0%
mul	0%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	6%
load	6%
store	0%
mul	0%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Vector efficiency ratios

INT

all	12%
load	14%
store	11%
mul	12%
add-sub	18%
fma	NA (no fma vectorizable/vectorized instructions)
other	13%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	14%
store	11%
mul	12%
add-sub	18%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.50 cycles. At this rate:

8% of peak load performance is reached (20.49 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (8.39 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 23e130

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0xb8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RDX),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV (%RCX),%R15D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
INC %EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x3,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SUB %EAX,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 23e9eb <_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_.omp_outlined+0x8bb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV (%R9),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV (%R8),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
INC %ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x3,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %ECX,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 23e9eb <_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_.omp_outlined+0x8bb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
SUB %ECX,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVQ $0,-0x98(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOVQ $0x1,-0xd8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOVL $0,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
IMUL %RDX,%R15	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
DEC %R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R15,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %ECX,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
LEA -0x50(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RDX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
LEA -0xd8(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x1cfea(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x98(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x48(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %ESI,-0x4c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 259680 <@plt_start@+0x530>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x48(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x98(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
CMP %R15,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMOVL %RAX,%R15	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
MOV %R15,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
CMP %R15,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JG 23e9d9 <_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_.omp_outlined+0x8a9>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x20(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x10(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x50(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x48(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %R12,-0x80(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x40(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x30(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x28(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %R14D,-0x2c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOV %RBX,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV (%R9),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%R9),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x10(%RDX),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%RAX),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV (%R8),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV (%RDI),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV %R9,-0x70(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x10(%R10),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %R11,-0x78(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x10(%R8),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%RDI),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV (%R10),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV (%RSI),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x10(%RSI),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %R9,-0x58(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RDX),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV (%RAX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x38(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RDI,-0xd0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R10,-0xc8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %RSI,-0x88(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R9,-0x68(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RAX),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x10(%RAX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RDX,-0xc0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R9,-0x60(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R15,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RCX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,-0x90(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
INC %R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x4,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 23e2b1 <_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_.omp_outlined+0x181>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x38(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x2c(%RBP),%R10D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x18(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
JMP 23e896 <_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_.omp_outlined+0x766>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
MOV -0x80(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x2c(%RBP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VPBROADCASTQ %RCX,%YMM0	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPADDQ -0x2cfe6(%RIP),%YMM0,%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	1	0.50	vect (50.0%)
VMOVSD -0x2d13e(%RIP),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VPBROADCASTQ -0x2d107(%RIP),%YMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	1	0.50	scal (12.5%)
VPBROADCASTQ %RDX,%YMM10	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
MOV -0x60(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VPBROADCASTQ %RDI,%YMM7	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPBROADCASTQ %R10,%YMM8	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
MOV %RBX,-0xb8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
VPBROADCASTQ %RBX,%YMM5	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
MOV -0x70(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x58(%RBP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x18(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %R9,-0xa8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
AND $-0x4,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VPBROADCASTQ %R14,%YMM6	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPCMPEQD %XMM14,%XMM14,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (25.0%)
MOV %R14,-0xb0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
ADD %R9,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R9,-0xa0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
VPBROADCASTQ %RAX,%YMM1	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
MOV -0x38(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VPBROADCASTD %ESI,%XMM3	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (6.3%)
MOV -0x68(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VPBROADCASTQ %RDX,%YMM11	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VEXTRACTI128 $0x1,%YMM1,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	3	0.50	vect (25.0%)
VPBROADCASTD %EAX,%XMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (6.3%)
MOV -0x78(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VPBROADCASTQ %RSI,%YMM9	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPBROADCASTQ %RAX,%YMM4	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0xa0(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x38(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x2c(%RBP),%R10D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0xb8(%RBP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV -0xb0(%RBP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
CMP %RAX,-0xa8(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JE 23e9d9 <_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_.omp_outlined+0x8a9>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVSD -0x2d70e(%RIP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0x4c(%RBP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
LEA 0x1c7d5(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 259690 <@plt_start@+0x540>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
ADD $0xb8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run aocc_8

Source file and lines	flux_calc.cpp:36-40
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/flux_calc.cpp:36-40
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 20.50 to 7.00 cycles (2.93x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions).

Details

6% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

6% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
25% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
12% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/flux_calc.cpp:36
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/flux_calc.cpp:36

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVL: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/flux_calc.cpp:37
VPBROADCASTD: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/flux_calc.cpp:37
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/flux_calc.cpp:37
VPBROADCASTQ: 10 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/flux_calc.cpp:37
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/flux_calc.cpp:37
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/flux_calc.cpp:37
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/flux_calc.cpp:37
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/flux_calc.cpp:37
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/flux_calc.cpp:37
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/flux_calc.cpp:37
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/flux_calc.cpp:37
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/flux_calc.cpp:37
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/flux_calc.cpp:37

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 420 bytes. The binary function is storing 172 bytes.

General properties

nb instructions	152
nb uops	164
loop length	667
used x86 registers	16
used mmx registers	0
used xmm registers	6
used ymm registers	11
used zmm registers	0
nb stack references	31

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	20.50 cycles
front end	20.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	6.50	6.50	6.50	6.50	6.50	6.50	19.75	19.75	19.75	19.75	1.00	7.00	7.00	1.00	0.00	0.00
cycles	6.50	6.50	6.50	6.50	6.50	6.50	19.75	19.75	19.75	19.75	1.00	7.00	7.00	1.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	20.50
Dispatch	19.75
Overall L1	20.50

Vectorization ratios

INT

all	6%
load	7%
store	0%
mul	0%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	6%
load	6%
store	0%
mul	0%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Vector efficiency ratios

INT

all	12%
load	14%
store	11%
mul	12%
add-sub	18%
fma	NA (no fma vectorizable/vectorized instructions)
other	13%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	14%
store	11%
mul	12%
add-sub	18%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.50 cycles. At this rate:

8% of peak load performance is reached (20.49 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (8.39 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 23e130

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0xb8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RDX),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV (%RCX),%R15D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
INC %EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x3,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SUB %EAX,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 23e9eb <_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_.omp_outlined+0x8bb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV (%R9),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV (%R8),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
INC %ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x3,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %ECX,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 23e9eb <_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_.omp_outlined+0x8bb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
SUB %ECX,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVQ $0,-0x98(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOVQ $0x1,-0xd8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOVL $0,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
IMUL %RDX,%R15	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
DEC %R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R15,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %ECX,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
LEA -0x50(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RDX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
LEA -0xd8(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x1cfea(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x98(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x48(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %ESI,-0x4c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 259680 <@plt_start@+0x530>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x48(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x98(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
CMP %R15,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMOVL %RAX,%R15	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
MOV %R15,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
CMP %R15,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JG 23e9d9 <_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_.omp_outlined+0x8a9>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x20(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x10(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x50(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x48(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %R12,-0x80(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x40(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x30(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x28(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %R14D,-0x2c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOV %RBX,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV (%R9),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%R9),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x10(%RDX),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%RAX),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV (%R8),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV (%RDI),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV %R9,-0x70(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x10(%R10),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %R11,-0x78(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x10(%R8),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%RDI),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV (%R10),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV (%RSI),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x10(%RSI),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %R9,-0x58(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RDX),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV (%RAX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x38(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RDI,-0xd0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R10,-0xc8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %RSI,-0x88(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R9,-0x68(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RAX),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x10(%RAX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RDX,-0xc0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R9,-0x60(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R15,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RCX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,-0x90(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
INC %R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x4,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 23e2b1 <_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_.omp_outlined+0x181>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x38(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x2c(%RBP),%R10D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x18(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
JMP 23e896 <_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_.omp_outlined+0x766>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
MOV -0x80(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x2c(%RBP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VPBROADCASTQ %RCX,%YMM0	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPADDQ -0x2cfe6(%RIP),%YMM0,%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	1	0.50	vect (50.0%)
VMOVSD -0x2d13e(%RIP),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VPBROADCASTQ -0x2d107(%RIP),%YMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	1	0.50	scal (12.5%)
VPBROADCASTQ %RDX,%YMM10	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
MOV -0x60(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VPBROADCASTQ %RDI,%YMM7	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPBROADCASTQ %R10,%YMM8	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
MOV %RBX,-0xb8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
VPBROADCASTQ %RBX,%YMM5	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
MOV -0x70(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x58(%RBP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x18(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %R9,-0xa8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
AND $-0x4,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VPBROADCASTQ %R14,%YMM6	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPCMPEQD %XMM14,%XMM14,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (25.0%)
MOV %R14,-0xb0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
ADD %R9,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R9,-0xa0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
VPBROADCASTQ %RAX,%YMM1	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
MOV -0x38(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VPBROADCASTD %ESI,%XMM3	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (6.3%)
MOV -0x68(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VPBROADCASTQ %RDX,%YMM11	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VEXTRACTI128 $0x1,%YMM1,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	3	0.50	vect (25.0%)
VPBROADCASTD %EAX,%XMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (6.3%)
MOV -0x78(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VPBROADCASTQ %RSI,%YMM9	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPBROADCASTQ %RAX,%YMM4	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0xa0(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x38(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x2c(%RBP),%R10D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0xb8(%RBP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV -0xb0(%RBP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
CMP %RAX,-0xa8(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JE 23e9d9 <_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_.omp_outlined+0x8a9>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVSD -0x2d70e(%RIP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0x4c(%RBP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
LEA 0x1c7d5(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 259690 <@plt_start@+0x540>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
ADD $0xb8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼flux_calc_kernel(int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	4.25	1.59
○Loop 209 - flux_calc.cpp:37-40 - exec	4.25	1.59
○Loop 210 - flux_calc.cpp:37-40 - exec	0.00	0.01

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512-bits vectorization

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ASM code

Code clean check

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Vectorization

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Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code