OV - exec - Function calc_dt_kernel(int, int, int, int, double, double, double, double, double, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, double&, int&, double&, double&, int&, int&, int&) [clone .omp

	Function: calc_dt_kernel(int, int, int, int, double, double, double, double, double, clover::Buffer2 ...	Module: exec	Source: calc_dt.cpp:49-75 [...]	Coverage (incl. loops): 3.22% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 46 - 69

--------------------------------------------------------------------------------

46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp: 49 - 75

--------------------------------------------------------------------------------

49: #pragma omp parallel for simd collapse(2) reduction(min : dt_min_val0)

50:   for (int j = (y_min + 1); j < (y_max + 2); j++) {

51:     for (int i = (x_min + 1); i < (x_max + 2); i++) {

52:       double dsx = celldx[i];

53:       double dsy = celldy[j];

54:       double cc = soundspeed(i, j) * soundspeed(i, j);

55:       cc = cc + 2.0 * viscosity_a(i, j) / density0(i, j);

56:       cc = std::fmax(std::sqrt(cc), g_small);

57:       double dtct = dtc_safe * std::fmin(dsx, dsy) / cc;

58:       double div = 0.0;

59:       double dv1 = (xvel0(i, j) + xvel0(i + 0, j + 1)) * xarea(i, j);

60:       double dv2 = (xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1)) * xarea(i + 1, j + 0);

61:       div = div + dv2 - dv1;

62:       double dtut = dtu_safe * 2.0 * volume(i, j) / std::fmax(std::fmax(std::fabs(dv1), std::fabs(dv2)), g_small * volume(i, j));

63:       dv1 = (yvel0(i, j) + yvel0(i + 1, j + 0)) * yarea(i, j);

64:       dv2 = (yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1)) * yarea(i + 0, j + 1);

65:       div = div + dv2 - dv1;

66:       double dtvt = dtv_safe * 2.0 * volume(i, j) / std::fmax(std::fmax(std::fabs(dv1), std::fabs(dv2)), g_small * volume(i, j));

67:       div = div / (2.0 * volume(i, j));

68:       double dtdivt;

69:       if (div < -g_small) {

70:         dtdivt = dtdiv_safe * (-1.0 / div);

71:       } else {

72:         dtdivt = g_big;

73:       }

74:       double mins = std::fmin(dtct, std::fmin(dtut, std::fmin(dtvt, std::fmin(dtdivt, g_big))));

75:       dt_min_val0 = std::fmin(mins, dt_min_val0);

0x23a930 PUSH	%RBP

0x23a931 MOV	%RSP,%RBP

0x23a934 PUSH	%R15

0x23a936 PUSH	%R14

0x23a938 PUSH	%R13

0x23a93a PUSH	%R12

0x23a93c PUSH	%RBX

0x23a93d AND	$-0x20,%RSP

0x23a941 SUB	$0x500,%RSP

0x23a948 MOV	(%RDX),%R14D

0x23a94b MOV	(%RCX),%EBX

0x23a94d INC	%R14D

0x23a950 ADD	$0x2,%EBX

0x23a953 SUB	%R14D,%EBX

0x23a956 JLE	23bfd5

0x23a95c MOV	(%R9),%R12D

0x23a95f MOV	(%R8),%R15D

0x23a962 INC	%R15D

0x23a965 ADD	$0x2,%R12D

0x23a969 CMP	%R15D,%R12D

0x23a96c JLE	23bfd5

0x23a972 SUB	%R15D,%R12D

0x23a975 MOV	(%RDI),%ESI

0x23a977 MOV	$0x7fefffffffffffff,%RAX

0x23a981 MOVQ	$0,0xa8(%RSP)

0x23a98d MOVQ	$0x1,0x138(%RSP)

0x23a999 MOVL	$0,0x64(%RSP)

0x23a9a1 IMUL	%R12,%RBX

0x23a9a5 MOV	%RAX,0x18(%RSP)

0x23a9aa DEC	%RBX

0x23a9ad MOV	%RBX,0x58(%RSP)

0x23a9b2 SUB	$0x8,%RSP

0x23a9b6 LEA	0x20723(%RIP),%RDI

0x23a9bd LEA	0x140(%RSP),%RAX

0x23a9c5 LEA	0x6c(%RSP),%RCX

0x23a9ca LEA	0xb0(%RSP),%R8

0x23a9d2 LEA	0x60(%RSP),%R9

0x23a9d7 MOV	%ESI,0x68(%RSP)

0x23a9db MOV	$0x22,%EDX

0x23a9e0 PUSH	$0x1

0x23a9e2 PUSH	$0x1

0x23a9e4 PUSH	%RAX

0x23a9e5 CALL	259680 <@plt_start@+0x530>

0x23a9ea ADD	$0x20,%RSP

0x23a9ee MOV	0x58(%RSP),%RAX

0x23a9f3 MOV	0xa8(%RSP),%RDI

0x23a9fb CMP	%RBX,%RAX

0x23a9fe CMOVL	%RAX,%RBX

0x23aa02 MOV	%RBX,0x58(%RSP)

0x23aa07 CMP	%RBX,%RDI

0x23aa0a JLE	23aa19

0x23aa0c VMOVSD	-0x29904(%RIP),%XMM0

0x23aa14 JMP	23bcdf

0x23aa19 MOV	%R14,0x20(%RSP)

0x23aa1e MOV	0x18(%RBP),%R14

0x23aa22 MOV	0x20(%RBP),%R11

0x23aa26 MOV	%R12,0x78(%RSP)

0x23aa2b MOV	0x30(%RBP),%R12

0x23aa2f MOV	0x28(%RBP),%R10

0x23aa33 MOV	%R15D,0x14(%RSP)

0x23aa38 MOV	0x10(%RBP),%R15

0x23aa3c MOV	%RDI,0x28(%RSP)

0x23aa41 MOV	0x78(%RBP),%RDI

0x23aa45 MOV	0x70(%RBP),%R9

0x23aa49 MOV	0x50(%RBP),%R13

0x23aa4d MOV	0x58(%RBP),%RCX

0x23aa51 MOV	0x48(%RBP),%RSI

0x23aa55 MOV	0x40(%RBP),%R8

0x23aa59 MOV	0x38(%RBP),%RAX

0x23aa5d MOV	(%R11),%RDX

0x23aa60 MOV	0x8(%R14),%R14

0x23aa64 MOV	0x10(%R11),%R11

0x23aa68 VMOVSD	(%RDI),%XMM0

0x23aa6c MOV	0x8(%R15),%R15

0x23aa70 VMOVSD	(%R13),%XMM16

0x23aa77 VMOVSD	(%R9),%XMM17

0x23aa7d MOV	(%R8),%R9

0x23aa80 MOV	0x10(%RCX),%RDI

0x23aa84 MOV	0x10(%RSI),%R13

0x23aa88 VMOVSD	(%RAX),%XMM15

0x23aa8c MOV	0x28(%RSP),%RAX

0x23aa91 VXORPD	-0x29923(%RIP){1to2},%XMM0,%XMM18

0x23aa9b MOV	%R14,0xa0(%RSP)

0x23aaa3 MOV	%R11,0x98(%RSP)

0x23aaab MOV	(%R10),%R11

0x23aaae MOV	0x10(%R10),%R10

0x23aab2 MOV	0x10(%R12),%R14

0x23aab7 MOV	%R15,0x50(%RSP)

0x23aabc MOV	%RDI,0x88(%RSP)

0x23aac4 MOV	%R9,0x70(%RSP)

0x23aac9 MOV	%RDX,0xf0(%RSP)

0x23aad1 MOV	%R10,0x80(%RSP)

0x23aad9 MOV	(%R12),%R10

0x23aadd MOV	%R14,0x90(%RSP)

0x23aae5 MOV	0x10(%R8),%R12

0x23aae9 MOV	(%RSI),%R8

0x23aaec MOV	(%RCX),%RSI

0x23aaef MOV	0x60(%RBP),%RCX

0x23aaf3 MOV	0x68(%RBP),%R14

0x23aaf7 MOV	%R11,0xe8(%RSP)

0x23aaff MOV	(%RCX),%RDI

0x23ab02 MOV	0x10(%RCX),%R15

0x23ab06 MOV	(%R14),%RCX

0x23ab09 MOV	%R10,0xe0(%RSP)

0x23ab11 MOV	%R8,0xd8(%RSP)

0x23ab19 MOV	%RSI,0xd0(%RSP)

0x23ab21 MOV	%RCX,0x68(%RSP)

0x23ab26 MOV	0x10(%R14),%RCX

0x23ab2a MOV	%RBX,%R14

0x23ab2d SUB	%RAX,%R14

0x23ab30 MOV	%RDI,0xc8(%RSP)

0x23ab38 INC	%R14

0x23ab3b CMP	$0x8,%R14

0x23ab3f JAE	23ab56

0x23ab41 VMOVSD	-0x29a39(%RIP),%XMM0

0x23ab49 MOV	%RBX,%R14

0x23ab4c MOV	0x20(%RSP),%RBX

0x23ab51 JMP	23bd83

0x23ab56 MOV	%R14,0xb8(%RSP)

0x23ab5e AND	$-0x8,%R14

0x23ab62 VPBROADCASTQ	%RAX,%YMM0

0x23ab68 MOV	%RBX,0xc0(%RSP)

0x23ab70 MOV	0x14(%RSP),%EBX

0x23ab74 VPADDQ	-0x2989c(%RIP),%YMM0,%YMM4

0x23ab7c VBROADCASTSD	-0x29a75(%RIP),%YMM1

0x23ab85 VBROADCASTSD	-0x29a37(%RIP),%YMM24

0x23ab8f VMOVAPD	%XMM15,0x230(%RSP)

0x23ab98 VMOVAPD	%XMM16,0x220(%RSP)

0x23aba0 VMOVAPD	%XMM17,0x210(%RSP)

0x23aba8 VMOVAPD	%XMM18,0x200(%RSP)

0x23abb0 ADD	%R14,%RAX

0x23abb3 MOV	%R14,0xb0(%RSP)

0x23abbb MOV	%RAX,0x28(%RSP)

0x23abc0 MOV	0x78(%RSP),%RAX

0x23abc5 VPBROADCASTQ	%RAX,%YMM27

0x23abcb MOV	0x20(%RSP),%RAX

0x23abd0 VPBROADCASTD	%EAX,%XMM0

0x23abd6 MOV	0x68(%RSP),%RAX

0x23abdb VMOVDQA	%XMM0,0x250(%RSP)

0x23abe4 VPBROADCASTD	%EBX,%XMM0

0x23abea VMOVDQA	%XMM0,0x240(%RSP)

0x23abf3 VPBROADCASTQ	%RDX,%YMM0

0x23abf9 VMOVDQA	%YMM0,0x460(%RSP)

0x23ac02 VPBROADCASTQ	%R11,%YMM0

0x23ac08 VMOVDQA	%YMM0,0x440(%RSP)

0x23ac11 VPBROADCASTQ	%R10,%YMM0

0x23ac17 VMOVDQA	%YMM0,0x420(%RSP)

0x23ac20 VBROADCASTSD	%XMM15,%YMM0

0x23ac25 VMOVAPD	%YMM0,0x400(%RSP)

0x23ac2e VPBROADCASTQ	%R9,%YMM0

0x23ac34 VMOVDQA	%YMM0,0x3e0(%RSP)

0x23ac3d VPBROADCASTQ	%R8,%YMM0

0x23ac43 VMOVDQA	%YMM0,0x3c0(%RSP)

0x23ac4c VPBROADCASTQ	%RSI,%YMM0

0x23ac52 VMOVDQA	%YMM0,0x3a0(%RSP)

0x23ac5b VBROADCASTSD	%XMM16,%YMM0

0x23ac61 VMOVAPD	%YMM0,0x380(%RSP)

0x23ac6a VPBROADCASTQ	%RDI,%YMM0

0x23ac70 VMOVDQA	%YMM0,0x360(%RSP)

0x23ac79 VPBROADCASTQ	%RAX,%YMM0

0x23ac7f MOV	%R14,%RAX

0x23ac82 MOV	0x50(%RSP),%R14

0x23ac87 VMOVDQA	%YMM0,0x340(%RSP)

0x23ac90 VBROADCASTSD	%XMM17,%YMM0

0x23ac96 VMOVAPD	%YMM0,0x320(%RSP)

0x23ac9f VBROADCASTSD	%XMM18,%YMM0

0x23aca5 VMOVAPD	%YMM0,0x300(%RSP)

0x23acae VBROADCASTSD	-0x29aff(%RIP),%YMM0

0x23acb7 VMOVAPS	%YMM0,0x2e0(%RSP)

0x23acc0 VBROADCASTSD	-0x29af9(%RIP),%YMM0

0x23acc9 VMOVAPS	%YMM0,0x2c0(%RSP)

0x23acd2 VBROADCASTSD	-0x29ba3(%RIP),%YMM0

0x23acdb VMOVAPS	%YMM0,0x2a0(%RSP)

0x23ace4 VBROADCASTSD	-0x29b6d(%RIP),%YMM0

0x23aced VMOVAPS	%YMM0,0x280(%RSP)

0x23acf6 VBROADCASTSD	-0x29c17(%RIP),%YMM0

0x23acff VMOVAPS	%YMM0,0x260(%RSP)

0x23ad08 VMOVAPD	%YMM1,%YMM0

0x23ad0c NOPL	(%RAX)

(188) 0x23ad10 VMOVAPD	%YMM0,0x4c0(%RSP)

(188) 0x23ad19 VEXTRACTI128	$0x1,%YMM4,%XMM0

(188) 0x23ad1f VEXTRACTI32X4	$0x1,%YMM27,%XMM2

(188) 0x23ad26 MOV	%RAX,0x128(%RSP)

(188) 0x23ad2e VMOVAPD	%YMM1,0x4a0(%RSP)

(188) 0x23ad37 VPADDQ	0x2c0(%RSP),%YMM4,%YMM1

(188) 0x23ad40 VMOVQ	%XMM27,%R11

(188) 0x23ad46 VPEXTRQ	$0x1,%XMM0,%RAX

(188) 0x23ad4c VPEXTRQ	$0x1,%XMM2,%R8

(188) 0x23ad52 VMOVQ	%XMM2,%R9

(188) 0x23ad57 CQTO

(188) 0x23ad59 IDIV	%R8

(188) 0x23ad5c VEXTRACTI128	$0x1,%YMM1,%XMM3

(188) 0x23ad62 MOV	%RAX,%RSI

(188) 0x23ad65 VMOVQ	%XMM0,%RAX

(188) 0x23ad6a VMOVQ	%RSI,%XMM0

(188) 0x23ad6f VPEXTRQ	$0x1,%XMM27,%RSI

(188) 0x23ad76 CQTO

(188) 0x23ad78 IDIV	%R9

(188) 0x23ad7b MOV	%RAX,%RDI

(188) 0x23ad7e VPEXTRQ	$0x1,%XMM4,%RAX

(188) 0x23ad84 VMOVQ	%RDI,%XMM2

(188) 0x23ad89 VMOVQ	%XMM27,%RDI

(188) 0x23ad8f CQTO

(188) 0x23ad91 VPUNPCKLQDQ	%XMM0,%XMM2,%XMM0

(188) 0x23ad95 IDIV	%RSI

(188) 0x23ad98 MOV	%RAX,%RSI

(188) 0x23ad9b VMOVQ	%XMM4,%RAX

(188) 0x23ada0 VMOVQ	%RSI,%XMM2

(188) 0x23ada5 CQTO

(188) 0x23ada7 IDIV	%R11

(188) 0x23adaa VPEXTRQ	$0x1,%XMM3,%RDX

(188) 0x23adb0 VMOVQ	%RAX,%XMM6

(188) 0x23adb5 MOV	%RDX,%RAX

(188) 0x23adb8 CQTO

(188) 0x23adba IDIV	%R8

(188) 0x23adbd VPUNPCKLQDQ	%XMM2,%XMM6,%XMM2

(188) 0x23adc1 VINSERTI128	$0x1,%XMM0,%YMM2,%YMM2

(188) 0x23adc7 MOV	%RAX,%RSI

(188) 0x23adca VMOVQ	%XMM3,%RAX

(188) 0x23adcf VMOVQ	%RSI,%XMM0

(188) 0x23add4 VPEXTRQ	$0x1,%XMM27,%RSI

(188) 0x23addb CQTO

(188) 0x23addd IDIV	%R9

(188) 0x23ade0 VPEXTRQ	$0x1,%XMM1,%RDX

(188) 0x23ade6 VMOVQ	%RAX,%XMM3

(188) 0x23adeb MOV	%RDX,%RAX

(188) 0x23adee CQTO

(188) 0x23adf0 IDIV	%RSI

(188) 0x23adf3 VPUNPCKLQDQ	%XMM0,%XMM3,%XMM0

(188) 0x23adf7 MOV	%RAX,%RSI

(188) 0x23adfa VMOVQ	%XMM1,%RAX

(188) 0x23adff VMOVQ	%RSI,%XMM3

(188) 0x23ae04 CQTO

(188) 0x23ae06 IDIV	%RDI

(188) 0x23ae09 VMOVDQA	0x240(%RSP),%XMM9

(188) 0x23ae12 VMOVDQA	0x250(%RSP),%XMM8

(188) 0x23ae1b VMOVDQA	0x440(%RSP),%YMM10

(188) 0x23ae24 VMOVDQA	0x420(%RSP),%YMM12

(188) 0x23ae2d VMOVDQA64	0x3e0(%RSP),%YMM16

(188) 0x23ae35 VMOVQ	%RAX,%XMM6

(188) 0x23ae3a VPUNPCKLQDQ	%XMM3,%XMM6,%XMM3

(188) 0x23ae3e VINSERTI128	$0x1,%XMM0,%YMM3,%YMM3

(188) 0x23ae44 VPMOVQD	%YMM2,%XMM0

(188) 0x23ae4a VPMULLQ	%YMM27,%YMM2,%YMM2

(188) 0x23ae50 VPMOVQD	%YMM3,%XMM7

(188) 0x23ae56 VPMULLQ	%YMM27,%YMM3,%YMM3

(188) 0x23ae5c VPSUBQ	%YMM2,%YMM4,%YMM2

(188) 0x23ae60 VPADDQ	0x260(%RSP),%YMM4,%YMM4

(188) 0x23ae69 VPMOVQD	%YMM2,%XMM2

(188) 0x23ae6f VPADDD	%XMM0,%XMM8,%XMM0

(188) 0x23ae73 VPMOVSXDQ	%XMM0,%YMM22

(188) 0x23ae79 VMOVQ	%XMM22,%R9

(188) 0x23ae7f VPMULLQ	%YMM22,%YMM16,%YMM25

(188) 0x23ae85 VPADDD	%XMM2,%XMM9,%XMM6

(188) 0x23ae89 VPSUBQ	%YMM3,%YMM1,%YMM2

(188) 0x23ae8d VPADDD	%XMM7,%XMM8,%XMM1

(188) 0x23ae91 VPMOVSXDQ	%XMM6,%YMM29

(188) 0x23ae97 VPMOVQD	%YMM2,%XMM2

(188) 0x23ae9d VPMOVSXDQ	%XMM1,%YMM23

(188) 0x23aea3 VEXTRACTI32X4	$0x1,%YMM29,%XMM3

(188) 0x23aeaa VMOVQ	%XMM29,%RAX

(188) 0x23aeb0 VPEXTRQ	$0x1,%XMM29,%RDX

(188) 0x23aeb7 VPEXTRQ	$0x1,%XMM23,%R11

(188) 0x23aebe VPMULLQ	%YMM23,%YMM16,%YMM28

(188) 0x23aec4 VMOVQ	%XMM3,%RSI

(188) 0x23aec9 VMOVSD	(%R14,%RAX,8),%XMM7

(188) 0x23aecf VPEXTRQ	$0x1,%XMM3,%RDI

(188) 0x23aed5 MOV	0xa0(%RSP),%RAX

(188) 0x23aedd VMOVSD	(%R14,%RSI,8),%XMM3

(188) 0x23aee3 VMOVHPD	(%R14,%RDX,8),%XMM7,%XMM7

(188) 0x23aee9 VPADDD	%XMM2,%XMM9,%XMM31

(188) 0x23aeef VEXTRACTI32X4	$0x1,%YMM22,%XMM2

(188) 0x23aef6 VPEXTRQ	$0x1,%XMM22,%RSI

(188) 0x23aefd VMOVQ	%XMM23,%RDX

(188) 0x23af03 VMOVHPD	(%R14,%RDI,8),%XMM3,%XMM3

(188) 0x23af09 VMOVQ	%XMM2,%RDI

(188) 0x23af0e VPEXTRQ	$0x1,%XMM2,%R8

(188) 0x23af14 VEXTRACTI32X4	$0x1,%YMM23,%XMM2

(188) 0x23af1b VPMOVSXDQ	%XMM31,%YMM30

(188) 0x23af21 MOV	0x50(%RSP),%R14

(188) 0x23af26 VPEXTRQ	$0x1,%XMM2,%R10

(188) 0x23af2c VMOVQ	%XMM2,%RBX

(188) 0x23af31 VMOVQ	%XMM30,0x160(%RSP)

(188) 0x23af39 VEXTRACTI32X4	$0x1,%YMM30,%XMM9

(188) 0x23af40 VPEXTRQ	$0x1,%XMM30,0x1e0(%RSP)

(188) 0x23af49 VMOVSD	(%RAX,%RDI,8),%XMM2

(188) 0x23af4e VPEXTRQ	$0x1,%XMM9,0x1c0(%RSP)

(188) 0x23af59 VMOVHPD	(%RAX,%R8,8),%XMM2,%XMM2

(188) 0x23af5f VINSERTF128	$0x1,%XMM3,%YMM7,%YMM3

(188) 0x23af65 VMOVSD	(%RAX,%R9,8),%XMM7

(188) 0x23af6b VMOVHPD	(%RAX,%RSI,8),%XMM7,%XMM7

(188) 0x23af70 MOV	0x160(%RSP),%RSI

(188) 0x23af78 VINSERTF128	$0x1,%XMM2,%YMM7,%YMM2

(188) 0x23af7e VMINPD	%YMM2,%YMM3,%YMM2

(188) 0x23af82 VMOVDQA	0x460(%RSP),%YMM3

(188) 0x23af8b VMOVAPD	%YMM2,0x480(%RSP)

(188) 0x23af94 VMOVSD	(%RAX,%RBX,8),%XMM2

(188) 0x23af99 MOV	0x90(%RSP),%RBX

(188) 0x23afa1 VMOVHPS	(%RAX,%R10,8),%XMM2,%XMM21

(188) 0x23afa8 VMOVSD	(%RAX,%RDX,8),%XMM2

(188) 0x23afad VMOVQ	%XMM9,%RDX

(188) 0x23afb2 VMOVSD	(%R14,%RSI,8),%XMM9

(188) 0x23afb8 VMOVHPS	(%RAX,%R11,8),%XMM2,%XMM8

(188) 0x23afbe MOV	0x98(%RSP),%R11

(188) 0x23afc6 VPMULLQ	%YMM22,%YMM3,%YMM2

(188) 0x23afcc VPMULLQ	%YMM23,%YMM3,%YMM3

(188) 0x23afd2 VPADDQ	%YMM29,%YMM2,%YMM2

(188) 0x23afd8 VPADDQ	%YMM30,%YMM3,%YMM3

(188) 0x23afde VMOVQ	%XMM2,%RAX

(188) 0x23afe3 VPEXTRQ	$0x1,%XMM2,%RDI

(188) 0x23afe9 VEXTRACTI128	$0x1,%YMM2,%XMM2

(188) 0x23afef VEXTRACTI128	$0x1,%YMM3,%XMM11

(188) 0x23aff5 VPEXTRQ	$0x1,%XMM3,0x140(%RSP)

(188) 0x23b000 VMOVQ	%XMM2,%RSI

(188) 0x23b005 VMOVSD	(%R11,%RAX,8),%XMM7

(188) 0x23b00b VPEXTRQ	$0x1,%XMM2,%R8

(188) 0x23b011 MOV	0x80(%RSP),%RAX

(188) 0x23b019 VMOVQ	%XMM11,0x38(%RSP)

(188) 0x23b01f VPEXTRQ	$0x1,%XMM11,0x160(%RSP)

(188) 0x23b02a VMOVSD	(%R11,%RSI,8),%XMM2

(188) 0x23b030 VMOVHPD	(%R11,%RDI,8),%XMM7,%XMM7

(188) 0x23b036 VMOVQ	%XMM3,%RSI

(188) 0x23b03b VMOVSD	(%R14,%RDX,8),%XMM3

(188) 0x23b041 VMOVHPD	(%R11,%R8,8),%XMM2,%XMM2

(188) 0x23b047 VINSERTF128	$0x1,%XMM2,%YMM7,%YMM7

(188) 0x23b04d VPMULLQ	%YMM22,%YMM10,%YMM2

(188) 0x23b053 VPMULLQ	%YMM23,%YMM10,%YMM10

(188) 0x23b059 VPADDQ	%YMM29,%YMM2,%YMM2

(188) 0x23b05f VPADDQ	%YMM30,%YMM10,%YMM10

(188) 0x23b065 VPEXTRQ	$0x1,%XMM2,%R10

(188) 0x23b06b VMOVQ	%XMM2,%RDI

(188) 0x23b070 VEXTRACTI128	$0x1,%YMM2,%XMM2

(188) 0x23b076 VMOVQ	%XMM10,%RDX

(188) 0x23b07b VPEXTRQ	$0x1,%XMM10,0x180(%RSP)

(188) 0x23b086 VEXTRACTI128	$0x1,%YMM10,%XMM10

(188) 0x23b08c VMOVQ	%XMM2,%R8

(188) 0x23b091 VPEXTRQ	$0x1,%XMM2,%R9

(188) 0x23b097 VMOVQ	%XMM10,0x8(%RSP)

(188) 0x23b09d VPEXTRQ	$0x1,%XMM10,0x40(%RSP)

(188) 0x23b0a5 VMOVSD	(%RAX,%R8,8),%XMM2

(188) 0x23b0ab MOV	0x1e0(%RSP),%R8

(188) 0x23b0b3 VMOVHPD	(%RAX,%R9,8),%XMM2,%XMM2

(188) 0x23b0b9 VMOVHPD	(%R14,%R8,8),%XMM9,%XMM26

(188) 0x23b0c0 VMOVSD	(%RAX,%RDI,8),%XMM9

(188) 0x23b0c5 VMOVHPD	(%RAX,%R10,8),%XMM9,%XMM9

(188) 0x23b0cb VINSERTF128	$0x1,%XMM2,%YMM9,%YMM2

(188) 0x23b0d1 VADDPD	%YMM2,%YMM2,%YMM9

(188) 0x23b0d5 VPMULLQ	%YMM22,%YMM12,%YMM2

(188) 0x23b0db VPMULLQ	%YMM23,%YMM12,%YMM12

(188) 0x23b0e1 VPADDQ	%YMM29,%YMM2,%YMM2

(188) 0x23b0e7 VPADDQ	%YMM30,%YMM12,%YMM12

(188) 0x23b0ed VEXTRACTI128	$0x1,%YMM2,%XMM11

(188) 0x23b0f3 VMOVQ	%XMM2,%RDI

(188) 0x23b0f8 VPEXTRQ	$0x1,%XMM2,%R8

(188) 0x23b0fe VMOVSD	(%R11,%RSI,8),%XMM2

(188) 0x23b104 VMOVQ	%XMM12,%RSI

(188) 0x23b109 VPEXTRQ	$0x1,%XMM12,0x1a0(%RSP)

(188) 0x23b114 VMOVQ	%XMM11,%R9

(188) 0x23b119 VPEXTRQ	$0x1,%XMM11,%R10

(188) 0x23b11f VEXTRACTI128	$0x1,%YMM12,%XMM11

(188) 0x23b125 VMOVSD	(%RBX,%RDI,8),%XMM13

(188) 0x23b12a VMOVSD	(%RBX,%R9,8),%XMM12

(188) 0x23b130 VMOVHPD	(%RBX,%R8,8),%XMM13,%XMM10

(188) 0x23b136 VMOVQ	%XMM11,%RDI

(188) 0x23b13b VPEXTRQ	$0x1,%XMM11,0x120(%RSP)

(188) 0x23b146 VMOVHPD	(%RBX,%R10,8),%XMM12,%XMM12

(188) 0x23b14c VINSERTF128	$0x1,%XMM12,%YMM10,%YMM10

(188) 0x23b152 VDIVPD	%YMM10,%YMM9,%YMM5

(188) 0x23b157 VMOVSD	(%RAX,%RDX,8),%XMM10

(188) 0x23b15c VPADDQ	%YMM30,%YMM28,%YMM9

(188) 0x23b162 VEXTRACTI128	$0x1,%YMM9,%XMM13

(188) 0x23b168 VPEXTRQ	$0x1,%XMM9,0x48(%RSP)

(188) 0x23b170 VMOVQ	%XMM13,0x30(%RSP)

(188) 0x23b176 VPEXTRQ	$0x1,%XMM13,0xf8(%RSP)

(188) 0x23b181 VFMADD231PD	%YMM7,%YMM7,%YMM5

(188) 0x23b186 VPADDQ	%YMM29,%YMM25,%YMM7

(188) 0x23b18c VEXTRACTI128	$0x1,%YMM7,%XMM12

(188) 0x23b192 VMOVQ	%XMM7,%RDX

(188) 0x23b197 VMOVQ	%XMM12,%R8

(188) 0x23b19c VPEXTRQ	$0x1,%XMM12,%R9

(188) 0x23b1a2 VMOVSD	(%R12,%R8,8),%XMM12

(188) 0x23b1a8 VPEXTRQ	$0x1,%XMM7,%R8

(188) 0x23b1ae VMOVSD	(%RBX,%RSI,8),%XMM7

(188) 0x23b1b3 MOV	0x1c0(%RSP),%RSI

(188) 0x23b1bb VMOVHPD	(%R12,%R9,8),%XMM12,%XMM11

(188) 0x23b1c1 VMOVSD	(%R12,%RDX,8),%XMM12

(188) 0x23b1c7 VMOVQ	%XMM9,%RDX

(188) 0x23b1cc MOV	0x180(%RSP),%R9

(188) 0x23b1d4 VMOVAPD	%YMM5,0x1e0(%RSP)

(188) 0x23b1dd VPCMPEQD	%XMM5,%XMM5,%XMM5

(188) 0x23b1e1 VMOVHPD	(%R12,%R8,8),%XMM12,%XMM9

(188) 0x23b1e7 VMOVSD	(%R12,%RDX,8),%XMM15

(188) 0x23b1ed MOV	0x38(%RSP),%RDX

(188) 0x23b1f2 VPSUBD	%XMM5,%XMM0,%XMM0

(188) 0x23b1f6 VPSUBD	%XMM5,%XMM6,%XMM6

(188) 0x23b1fa VPMOVSXDQ	%XMM6,%YMM6

(188) 0x23b1ff VMOVHPD	(%R14,%RSI,8),%XMM3,%XMM14

(188) 0x23b205 VPSUBD	%XMM5,%XMM1,%XMM3

(188) 0x23b209 VPMOVSXDQ	%XMM0,%YMM1

(188) 0x23b20e VMOVHPS	(%RAX,%R9,8),%XMM10,%XMM10

(188) 0x23b214 VPMOVSXDQ	%XMM3,%YMM19

(188) 0x23b21a VMOVSD	(%R11,%RDX,8),%XMM0

(188) 0x23b220 MOV	0x8(%RSP),%RDX

(188) 0x23b225 VPMULLQ	%YMM19,%YMM16,%YMM3

(188) 0x23b22b VINSERTF128	$0x1,%XMM11,%YMM9,%YMM11

(188) 0x23b231 VPMULLQ	%YMM1,%YMM16,%YMM9

(188) 0x23b237 VPADDQ	%YMM30,%YMM3,%YMM18

(188) 0x23b23d VMOVSD	(%RAX,%RDX,8),%XMM16

(188) 0x23b244 VMOVQ	%XMM18,%R10

(188) 0x23b24a VPEXTRQ	$0x1,%XMM18,0x8(%RSP)

(188) 0x23b253 VPADDQ	%YMM29,%YMM9,%YMM12

(188) 0x23b259 VMOVQ	%XMM12,%RDX

(188) 0x23b25e VPEXTRQ	$0x1,%XMM12,%R8

(188) 0x23b264 VEXTRACTI128	$0x1,%YMM12,%XMM12

(188) 0x23b26a VMOVAPS	%YMM10,0x180(%RSP)

(188) 0x23b273 VMOVQ	%XMM12,%RSI

(188) 0x23b278 VMOVSD	(%R12,%RDX,8),%XMM13

(188) 0x23b27e VPEXTRQ	$0x1,%XMM12,%R9

(188) 0x23b284 VEXTRACTI32X4	$0x1,%YMM18,%XMM12

(188) 0x23b28b MOV	0x40(%RSP),%RDX

(188) 0x23b290 VMOVSD	(%R12,%RSI,8),%XMM10

(188) 0x23b296 VMOVHPD	(%R12,%R8,8),%XMM13,%XMM13

(188) 0x23b29c VMOVQ	%XMM12,%RSI

(188) 0x23b2a1 VPEXTRQ	$0x1,%XMM12,0x100(%RSP)

(188) 0x23b2ac VMOVHPD	(%R12,%R9,8),%XMM10,%XMM10

(188) 0x23b2b2 VINSERTF128	$0x1,%XMM10,%YMM13,%YMM10

(188) 0x23b2b8 VADDPD	%YMM11,%YMM10,%YMM18

(188) 0x23b2be VMOVDQA	0x3c0(%RSP),%YMM10

(188) 0x23b2c7 VMOVHPD	(%RAX,%RDX,8),%XMM16,%XMM11

(188) 0x23b2ce MOV	0x140(%RSP),%RAX

(188) 0x23b2d6 VPMULLQ	%YMM22,%YMM10,%YMM13

(188) 0x23b2dc VPMULLQ	%YMM23,%YMM10,%YMM12

(188) 0x23b2e2 VMOVHPS	(%R11,%RAX,8),%XMM2,%XMM10

(188) 0x23b2e8 MOV	0x1a0(%RSP),%RAX

(188) 0x23b2f0 VPADDQ	%YMM29,%YMM13,%YMM16

(188) 0x23b2f6 VEXTRACTI32X4	$0x1,%YMM16,%XMM2

(188) 0x23b2fd VPEXTRQ	$0x1,%XMM16,%R8

(188) 0x23b304 VMOVQ	%XMM16,%R9

(188) 0x23b30a VPADDQ	%YMM30,%YMM12,%YMM16

(188) 0x23b310 VMOVQ	%XMM2,%RDX

(188) 0x23b315 VMOVQ	%XMM16,0x140(%RSP)

(188) 0x23b31d VMOVHPD	(%RBX,%RAX,8),%XMM7,%XMM7

(188) 0x23b322 MOV	0x30(%RSP),%RAX

(188) 0x23b327 VMOVSD	(%R13,%RDX,8),%XMM17

(188) 0x23b32f VPEXTRQ	$0x1,%XMM2,%RDX

(188) 0x23b335 VMOVSD	(%RBX,%RDI,8),%XMM2

(188) 0x23b33a VPEXTRQ	$0x1,%XMM16,%RDI

(188) 0x23b341 VEXTRACTI32X4	$0x1,%YMM16,%XMM16

(188) 0x23b348 VMOVHPD	(%R13,%RDX,8),%XMM17,%XMM17

(188) 0x23b350 VMOVQ	%XMM16,%RDX

(188) 0x23b356 VPEXTRQ	$0x1,%XMM16,0x108(%RSP)

(188) 0x23b35f VMOVSD	(%R13,%R9,8),%XMM16

(188) 0x23b367 VMOVHPD	(%R13,%R8,8),%XMM16,%XMM16

(188) 0x23b36f VINSERTF32X4	$0x1,%XMM17,%YMM16,%YMM16

(188) 0x23b376 VMOVSD	(%R12,%R10,8),%XMM17

(188) 0x23b37d MOV	0x88(%RSP),%R10

(188) 0x23b385 VMULPD	%YMM18,%YMM16,%YMM20

(188) 0x23b38b VMOVSD	(%R12,%RAX,8),%XMM16

(188) 0x23b392 MOV	0x48(%RSP),%RAX

(188) 0x23b397 VPSUBD	%XMM5,%XMM31,%XMM18

(188) 0x23b39d VINSERTF32X4	$0x1,%XMM21,%YMM8,%YMM5

(188) 0x23b3a4 VPMOVSXDQ	%XMM18,%YMM31

(188) 0x23b3aa VPADDQ	%YMM6,%YMM25,%YMM18

(188) 0x23b3b0 VMOVQ	%XMM18,%R8

(188) 0x23b3b6 VPEXTRQ	$0x1,%XMM18,%R9

(188) 0x23b3bd VMOVAPS	%YMM5,0x1a0(%RSP)

(188) 0x23b3c6 VPADDQ	%YMM31,%YMM28,%YMM28

(188) 0x23b3cc VPADDQ	%YMM31,%YMM3,%YMM3

(188) 0x23b3d2 VPADDQ	%YMM31,%YMM12,%YMM12

(188) 0x23b3d8 VMOVAPD	%YMM20,0x1c0(%RSP)

(188) 0x23b3e0 VPEXTRQ	$0x1,%XMM28,0x40(%RSP)

(188) 0x23b3e9 VPEXTRQ	$0x1,%XMM3,0x30(%RSP)

(188) 0x23b3f1 VMOVHPD	(%R12,%RAX,8),%XMM15,%XMM25

(188) 0x23b3f8 VEXTRACTI32X4	$0x1,%YMM18,%XMM15

(188) 0x23b3ff VEXTRACTI32X4	$0x1,%YMM28,%XMM18

(188) 0x23b406 VMOVQ	%XMM15,%RAX

(188) 0x23b40b VMOVQ	%XMM18,0x38(%RSP)

(188) 0x23b413 VPEXTRQ	$0x1,%XMM18,0x48(%RSP)

(188) 0x23b41c VMOVSD	(%R12,%R8,8),%XMM18

(188) 0x23b423 VMOVSD	(%R12,%RAX,8),%XMM8

(188) 0x23b429 VPEXTRQ	$0x1,%XMM15,%RAX

(188) 0x23b42f VMOVHPD	(%R12,%R9,8),%XMM18,%XMM18

(188) 0x23b436 VMOVSD	(%R12,%RSI,8),%XMM15

(188) 0x23b43c MOV	0x8(%RSP),%RSI

(188) 0x23b441 VMOVQ	%XMM3,0x8(%RSP)

(188) 0x23b447 VEXTRACTI128	$0x1,%YMM3,%XMM3

(188) 0x23b44d VMOVHPD	(%R12,%RAX,8),%XMM8,%XMM8

(188) 0x23b453 VMOVQ	%XMM28,%RAX

(188) 0x23b459 VMOVQ	%XMM3,0x118(%RSP)

(188) 0x23b462 VPEXTRQ	$0x1,%XMM3,0x110(%RSP)

(188) 0x23b46d VINSERTF32X4	$0x1,%XMM8,%YMM18,%YMM18

(188) 0x23b474 VPADDQ	%YMM6,%YMM9,%YMM8

(188) 0x23b478 VMOVHPD	(%R12,%RSI,8),%XMM17,%XMM9

(188) 0x23b47f VEXTRACTI32X4	$0x1,%YMM8,%XMM28

(188) 0x23b486 VMOVQ	%XMM28,%RSI

(188) 0x23b48c VPEXTRQ	$0x1,%XMM28,%R8

(188) 0x23b493 VMOVSD	(%R13,%RDX,8),%XMM28

(188) 0x23b49b MOV	0x160(%RSP),%RDX

(188) 0x23b4a3 VMOVSD	(%R12,%RSI,8),%XMM17

(188) 0x23b4aa VMOVQ	%XMM8,%RSI

(188) 0x23b4af VMOVHPD	(%R12,%R8,8),%XMM17,%XMM17

(188) 0x23b4b6 VPEXTRQ	$0x1,%XMM8,%R8

(188) 0x23b4bc VMOVSD	(%R12,%RSI,8),%XMM8

(188) 0x23b4c2 VPEXTRQ	$0x1,%XMM12,%RSI

(188) 0x23b4c8 VMOVHPD	(%R12,%R8,8),%XMM8,%XMM8

(188) 0x23b4ce VMOVHPS	(%R11,%RDX,8),%XMM0,%XMM21

(188) 0x23b4d5 MOV	0x140(%RSP),%RDX

(188) 0x23b4dd VMOVSD	(%R12,%RAX,8),%XMM0

(188) 0x23b4e3 MOV	0xf8(%RSP),%RAX

(188) 0x23b4eb MOV	0x48(%RSP),%R11

(188) 0x23b4f0 VMOVSD	(%R13,%RDX,8),%XMM3

(188) 0x23b4f7 MOV	0x120(%RSP),%RDX

(188) 0x23b4ff VINSERTF32X4	$0x1,%XMM17,%YMM8,%YMM17

(188) 0x23b506 VMOVHPD	(%R13,%RDI,8),%XMM3,%XMM8

(188) 0x23b50d VPADDQ	%YMM6,%YMM13,%YMM3

(188) 0x23b511 VMOVHPD	(%R12,%RAX,8),%XMM16,%XMM13

(188) 0x23b518 VMOVQ	%XMM3,%RDI

(188) 0x23b51d VPEXTRQ	$0x1,%XMM3,%R8

(188) 0x23b523 VEXTRACTI128	$0x1,%YMM3,%XMM3

(188) 0x23b529 VPEXTRQ	$0x1,%XMM3,%RAX

(188) 0x23b52f VADDPD	%YMM18,%YMM17,%YMM17

(188) 0x23b535 VMOVDQA64	0x3a0(%RSP),%YMM18

(188) 0x23b53d VINSERTF32X4	$0x1,%XMM21,%YMM10,%YMM5

(188) 0x23b544 VMOVHPD	(%RBX,%RDX,8),%XMM2,%XMM2

(188) 0x23b549 MOV	0x100(%RSP),%RDX

(188) 0x23b551 VMOVQ	%XMM12,%RBX

(188) 0x23b556 VEXTRACTI128	$0x1,%YMM12,%XMM12

(188) 0x23b55c VMOVAPS	%YMM5,0x140(%RSP)

(188) 0x23b565 VMOVAPD	0x180(%RSP),%YMM5

(188) 0x23b56e VINSERTF32X4	$0x1,%XMM13,%YMM25,%YMM25

(188) 0x23b575 VANDPD	%YMM24,%YMM20,%YMM13

(188) 0x23b57b VMOVDQA64	0x360(%RSP),%YMM20

(188) 0x23b583 VMOVHPD	(%R12,%RDX,8),%XMM15,%XMM15

(188) 0x23b589 VMOVQ	%XMM3,%RDX

(188) 0x23b58e VMOVSD	(%R13,%RDX,8),%XMM3

(188) 0x23b595 VPEXTRQ	$0x1,%XMM12,%RDX

(188) 0x23b59b VMOVHPD	(%R13,%RAX,8),%XMM3,%XMM16

(188) 0x23b5a3 VMOVQ	%XMM12,%RAX

(188) 0x23b5a8 VMOVSD	(%R13,%RDI,8),%XMM12

(188) 0x23b5af VINSERTF32X4	$0x1,%XMM14,%YMM26,%YMM3

(188) 0x23b5b6 VMOVHPD	(%R13,%R8,8),%XMM12,%XMM12

(188) 0x23b5bd VINSERTF32X4	$0x1,%XMM16,%YMM12,%YMM14

(188) 0x23b5c4 VPMULLQ	%YMM22,%YMM18,%YMM12

(188) 0x23b5ca VPADDQ	%YMM29,%YMM12,%YMM12

(188) 0x23b5d0 VEXTRACTI32X4	$0x1,%YMM12,%XMM16

(188) 0x23b5d7 VMOVQ	%XMM16,%RDI

(188) 0x23b5dd VPEXTRQ	$0x1,%XMM16,%R8

(188) 0x23b5e4 VMOVSD	(%R10,%RDI,8),%XMM16

(188) 0x23b5eb VMOVQ	%XMM12,%RDI

(188) 0x23b5f0 VMOVHPD	(%R10,%R8,8),%XMM16,%XMM16

(188) 0x23b5f7 MOV	0x108(%RSP),%R8

(188) 0x23b5ff VMOVSD	(%R10,%RDI,8),%XMM10

(188) 0x23b605 VPEXTRQ	$0x1,%XMM12,%RDI

(188) 0x23b60b VPMULLQ	%YMM23,%YMM18,%YMM12

(188) 0x23b611 VMOVHPD	(%R10,%RDI,8),%XMM10,%XMM10

(188) 0x23b617 VPADDQ	%YMM30,%YMM12,%YMM12

(188) 0x23b61d VPEXTRQ	$0x1,%XMM12,%R9

(188) 0x23b623 VMOVHPD	(%R13,%R8,8),%XMM28,%XMM18

(188) 0x23b62b VINSERTF32X4	$0x1,%XMM11,%YMM5,%YMM28

(188) 0x23b632 VMOVAPD	0x2e0(%RSP),%YMM5

(188) 0x23b63b VMOVQ	%XMM12,%R8

(188) 0x23b640 VMULPD	%YMM14,%YMM17,%YMM11

(188) 0x23b646 VEXTRACTI128	$0x1,%YMM12,%XMM12

(188) 0x23b64c VMOVSD	(%R10,%R8,8),%XMM26

(188) 0x23b653 VMOVQ	%XMM12,%RDI

(188) 0x23b658 VMOVHPD	(%R10,%R9,8),%XMM26,%XMM14

(188) 0x23b65f VMOVAPD	0x380(%RSP),%YMM26

(188) 0x23b667 VMOVSD	(%R10,%RDI,8),%XMM21

(188) 0x23b66e VPEXTRQ	$0x1,%XMM12,%RDI

(188) 0x23b674 VINSERTF128	$0x1,%XMM2,%YMM7,%YMM12

(188) 0x23b67a VANDPD	%YMM24,%YMM11,%YMM17

(188) 0x23b680 VINSERTF32X4	$0x1,%XMM16,%YMM10,%YMM2

(188) 0x23b687 VADDPD	%YMM2,%YMM2,%YMM7

(188) 0x23b68b VMULPD	%YMM5,%YMM2,%YMM10

(188) 0x23b68f VINSERTF32X4	$0x1,%XMM18,%YMM8,%YMM8

(188) 0x23b696 VMULPD	%YMM26,%YMM7,%YMM16

(188) 0x23b69c VMAXPD	%YMM10,%YMM13,%YMM2

(188) 0x23b6a1 VINSERTF128	$0x1,%XMM15,%YMM9,%YMM13

(188) 0x23b6a7 VMINPD	0x1a0(%RSP),%YMM3,%YMM15

(188) 0x23b6b0 VMAXPD	%YMM17,%YMM2,%YMM2

(188) 0x23b6b6 VMOVHPD	(%R10,%RDI,8),%XMM21,%XMM17

(188) 0x23b6bd VPMULLQ	%YMM23,%YMM20,%YMM21

(188) 0x23b6c3 MOV	0x40(%RSP),%R10

(188) 0x23b6c8 VADDPD	%YMM25,%YMM13,%YMM13

(188) 0x23b6ce VPMULLQ	%YMM19,%YMM20,%YMM25

(188) 0x23b6d4 VDIVPD	%YMM2,%YMM16,%YMM2

(188) 0x23b6da VMULPD	%YMM13,%YMM8,%YMM8

(188) 0x23b6df VPADDQ	%YMM31,%YMM25,%YMM13

(188) 0x23b6e5 VINSERTF32X4	$0x1,%XMM17,%YMM14,%YMM14

(188) 0x23b6ec VMOVAPD	%YMM2,0x160(%RSP)

(188) 0x23b6f5 VPMULLQ	%YMM22,%YMM20,%YMM2

(188) 0x23b6fb VPADDQ	%YMM29,%YMM2,%YMM9

(188) 0x23b701 VPADDQ	%YMM6,%YMM2,%YMM2

(188) 0x23b705 VEXTRACTI32X4	$0x1,%YMM9,%XMM16

(188) 0x23b70c VMOVQ	%XMM9,%RDI

(188) 0x23b711 VMOVQ	%XMM16,%R9

(188) 0x23b717 VPEXTRQ	$0x1,%XMM16,%R8

(188) 0x23b71e VMOVSD	(%R15,%R9,8),%XMM16

(188) 0x23b725 VMOVHPD	(%R15,%R8,8),%XMM16,%XMM16

(188) 0x23b72c VPEXTRQ	$0x1,%XMM9,%R8

(188) 0x23b732 VMOVSD	(%R15,%RDI,8),%XMM9

(188) 0x23b738 VMOVHPD	(%R15,%R8,8),%XMM9,%XMM9

(188) 0x23b73e VINSERTF32X4	$0x1,%XMM16,%YMM9,%YMM16

(188) 0x23b745 VPADDQ	%YMM30,%YMM21,%YMM9

(188) 0x23b74b VMOVQ	%XMM9,%RDI

(188) 0x23b750 VPEXTRQ	$0x1,%XMM9,%R8

(188) 0x23b756 VEXTRACTI128	$0x1,%YMM9,%XMM9

(188) 0x23b75c VMOVQ	%XMM9,%R9

(188) 0x23b761 VMOVSD	(%R15,%R9,8),%XMM17

(188) 0x23b768 VPEXTRQ	$0x1,%XMM9,%R9

(188) 0x23b76e VMOVSD	(%R15,%RDI,8),%XMM9

(188) 0x23b774 VMOVQ	%XMM2,%RDI

(188) 0x23b779 VMOVHPD	(%R15,%R8,8),%XMM9,%XMM9

(188) 0x23b77f VMOVHPD	(%R15,%R9,8),%XMM17,%XMM17

(188) 0x23b786 MOV	0x38(%RSP),%R8

(188) 0x23b78b VMOVSD	(%R12,%R8,8),%XMM18

(188) 0x23b792 VPEXTRQ	$0x1,%XMM2,%R8

(188) 0x23b798 VEXTRACTI128	$0x1,%YMM2,%XMM2

(188) 0x23b79e VPEXTRQ	$0x1,%XMM2,%R9

(188) 0x23b7a4 VMOVHPD	(%R12,%R11,8),%XMM18,%XMM18

(188) 0x23b7ab VINSERTF32X4	$0x1,%XMM17,%YMM9,%YMM9

(188) 0x23b7b2 VPADDQ	%YMM31,%YMM21,%YMM17

(188) 0x23b7b8 VMOVHPD	(%R12,%R10,8),%XMM0,%XMM21

(188) 0x23b7bf VMOVQ	%XMM2,%R10

(188) 0x23b7c4 VMOVDQA	0x340(%RSP),%YMM0

(188) 0x23b7cd VMOVSD	(%R15,%R10,8),%XMM2

(188) 0x23b7d3 VEXTRACTI32X4	$0x1,%YMM17,%XMM3

(188) 0x23b7da VPEXTRQ	$0x1,%XMM17,%R10

(188) 0x23b7e1 VMOVHPD	(%R15,%R9,8),%XMM2,%XMM2

(188) 0x23b7e7 VMOVQ	%XMM17,%R9

(188) 0x23b7ed VMOVSD	(%R15,%RDI,8),%XMM17

(188) 0x23b7f4 VPEXTRQ	$0x1,%XMM3,%RDI

(188) 0x23b7fa VMOVQ	%XMM3,%R11

(188) 0x23b7ff VMOVHPD	(%R15,%R8,8),%XMM17,%XMM3

(188) 0x23b806 MOV	0x118(%RSP),%R8

(188) 0x23b80e VINSERTF32X4	$0x1,%XMM18,%YMM21,%YMM17

(188) 0x23b815 VPMULLQ	%YMM22,%YMM0,%YMM21

(188) 0x23b81b VPMULLQ	%YMM23,%YMM0,%YMM22

(188) 0x23b821 VADDPD	%YMM28,%YMM28,%YMM23

(188) 0x23b827 VPMULLQ	%YMM1,%YMM20,%YMM28

(188) 0x23b82d VPMULLQ	%YMM1,%YMM0,%YMM1

(188) 0x23b833 VPMULLQ	%YMM19,%YMM0,%YMM0

(188) 0x23b839 VINSERTF128	$0x1,%XMM2,%YMM3,%YMM2

(188) 0x23b83f VMOVSD	(%R12,%R8,8),%XMM3

(188) 0x23b845 MOV	0x110(%RSP),%R8

(188) 0x23b84d VPADDQ	%YMM29,%YMM21,%YMM21

(188) 0x23b853 VPADDQ	%YMM30,%YMM22,%YMM22

(188) 0x23b859 VPADDQ	%YMM6,%YMM28,%YMM6

(188) 0x23b85f VDIVPD	%YMM12,%YMM23,%YMM12

(188) 0x23b865 VPADDQ	%YMM29,%YMM1,%YMM1

(188) 0x23b86b VPADDQ	%YMM30,%YMM0,%YMM0

(188) 0x23b871 VADDPD	%YMM16,%YMM2,%YMM16

(188) 0x23b877 VMOVSD	(%R13,%RAX,8),%XMM2

(188) 0x23b87e VMOVQ	%XMM21,%RAX

(188) 0x23b884 VMOVHPD	(%R13,%RDX,8),%XMM2,%XMM2

(188) 0x23b88b VPEXTRQ	$0x1,%XMM21,%RDX

(188) 0x23b892 VMOVHPD	(%R12,%R8,8),%XMM3,%XMM3

(188) 0x23b898 MOV	0x8(%RSP),%R8

(188) 0x23b89d VMOVSD	(%R12,%R8,8),%XMM18

(188) 0x23b8a4 MOV	0x30(%RSP),%R8

(188) 0x23b8a9 VMOVHPD	(%R12,%R8,8),%XMM18,%XMM18

(188) 0x23b8b0 VINSERTF32X4	$0x1,%XMM3,%YMM18,%YMM18

(188) 0x23b8b7 VMOVSD	(%R13,%RBX,8),%XMM3

(188) 0x23b8be VMOVHPD	(%R13,%RSI,8),%XMM3,%XMM3

(188) 0x23b8c5 VADDPD	%YMM17,%YMM18,%YMM17

(188) 0x23b8cb VPADDQ	%YMM29,%YMM28,%YMM18

(188) 0x23b8d1 VINSERTF128	$0x1,%XMM2,%YMM3,%YMM2

(188) 0x23b8d7 VEXTRACTI32X4	$0x1,%YMM21,%XMM3

(188) 0x23b8de VMOVSD	(%R15,%R11,8),%XMM21

(188) 0x23b8e5 VPEXTRQ	$0x1,%XMM3,%RSI

(188) 0x23b8eb VMOVQ	%XMM3,%R8

(188) 0x23b8f0 VMOVSD	(%R15,%R9,8),%XMM3

(188) 0x23b8f6 VMOVHPD	(%R15,%RDI,8),%XMM21,%XMM21

(188) 0x23b8fd VMOVQ	%XMM22,%RDI

(188) 0x23b903 VPEXTRQ	$0x1,%XMM22,%R9

(188) 0x23b90a VEXTRACTI32X4	$0x1,%YMM22,%XMM22

(188) 0x23b911 VMOVHPD	(%R15,%R10,8),%XMM3,%XMM3

(188) 0x23b917 VMOVQ	%XMM22,%R10

(188) 0x23b91d VPEXTRQ	$0x1,%XMM22,%R11

(188) 0x23b924 VMOVSD	(%RCX,%RAX,8),%XMM22

(188) 0x23b92b VMOVQ	%XMM18,%RAX

(188) 0x23b931 VMULPD	%YMM2,%YMM17,%YMM2

(188) 0x23b937 VMOVAPD	0x400(%RSP),%YMM17

(188) 0x23b93f VMOVHPD	(%RCX,%RDX,8),%XMM22,%XMM22

(188) 0x23b946 VPEXTRQ	$0x1,%XMM18,%RDX

(188) 0x23b94d VEXTRACTI32X4	$0x1,%YMM18,%XMM18

(188) 0x23b954 VINSERTF32X4	$0x1,%XMM21,%YMM3,%YMM21

(188) 0x23b95b VMOVSD	(%RCX,%R8,8),%XMM3

(188) 0x23b961 VMOVHPD	(%RCX,%RSI,8),%XMM3,%XMM3

(188) 0x23b966 VMOVQ	%XMM18,%RSI

(188) 0x23b96c VADDPD	%YMM9,%YMM21,%YMM9

(188) 0x23b972 VMOVSD	(%R15,%RAX,8),%XMM21

(188) 0x23b979 VMOVQ	%XMM6,%RAX

(188) 0x23b97e VMOVHPD	(%R15,%RDX,8),%XMM21,%XMM21

(188) 0x23b985 VPEXTRQ	$0x1,%XMM6,%RDX

(188) 0x23b98b VEXTRACTI128	$0x1,%YMM6,%XMM6

(188) 0x23b991 VINSERTF32X4	$0x1,%XMM3,%YMM22,%YMM3

(188) 0x23b998 VMOVSD	(%RCX,%RDI,8),%XMM22

(188) 0x23b99f VPEXTRQ	$0x1,%XMM18,%RDI

(188) 0x23b9a6 VPADDQ	%YMM30,%YMM25,%YMM18

(188) 0x23b9ac VMOVHPD	(%RCX,%R9,8),%XMM22,%XMM22

(188) 0x23b9b3 VMOVQ	%XMM18,%R8

(188) 0x23b9b9 VPEXTRQ	$0x1,%XMM18,%R9

(188) 0x23b9c0 VEXTRACTI32X4	$0x1,%YMM18,%XMM18

(188) 0x23b9c7 VMULPD	%YMM16,%YMM3,%YMM3

(188) 0x23b9cd VMOVSD	(%RCX,%R10,8),%XMM16

(188) 0x23b9d4 VMOVQ	%XMM18,%R10

(188) 0x23b9da VMOVSD	(%R15,%R8,8),%XMM23

(188) 0x23b9e1 VMOVQ	%XMM13,%R8

(188) 0x23b9e6 VMOVHPD	(%RCX,%R11,8),%XMM16,%XMM16

(188) 0x23b9ed VPEXTRQ	$0x1,%XMM18,%R11

(188) 0x23b9f4 VMOVSD	(%R15,%RSI,8),%XMM18

(188) 0x23b9fb VMOVHPD	(%R15,%R9,8),%XMM23,%XMM23

(188) 0x23ba02 VMOVQ	%XMM6,%RSI

(188) 0x23ba07 VPEXTRQ	$0x1,%XMM13,%R9

(188) 0x23ba0d VMOVHPD	(%R15,%RDI,8),%XMM18,%XMM18

(188) 0x23ba14 VPEXTRQ	$0x1,%XMM6,%RDI

(188) 0x23ba1a VEXTRACTI128	$0x1,%YMM13,%XMM6

(188) 0x23ba20 VMOVSD	(%R15,%RAX,8),%XMM13

(188) 0x23ba26 VMOVQ	%XMM1,%RAX

(188) 0x23ba2b VMOVHPD	(%R15,%RDX,8),%XMM13,%XMM13

(188) 0x23ba31 VPEXTRQ	$0x1,%XMM1,%RDX

(188) 0x23ba37 VEXTRACTI128	$0x1,%YMM1,%XMM1

(188) 0x23ba3d VINSERTF32X4	$0x1,%XMM16,%YMM22,%YMM16

(188) 0x23ba44 VINSERTF32X4	$0x1,%XMM18,%YMM21,%YMM18

(188) 0x23ba4b VMOVSD	(%R15,%R10,8),%XMM21

(188) 0x23ba52 VMOVQ	%XMM6,%R10

(188) 0x23ba57 VMOVHPD	(%R15,%R11,8),%XMM21,%XMM21

(188) 0x23ba5e VPEXTRQ	$0x1,%XMM6,%R11

(188) 0x23ba64 VMOVSD	(%R15,%RSI,8),%XMM6

(188) 0x23ba6a VMOVQ	%XMM1,%RSI

(188) 0x23ba6f VMULPD	%YMM9,%YMM16,%YMM9

(188) 0x23ba75 VMOVSD	(%R15,%R8,8),%XMM16

(188) 0x23ba7c VMOVQ	%XMM0,%R8

(188) 0x23ba81 VMOVHPD	(%R15,%RDI,8),%XMM6,%XMM6

(188) 0x23ba87 VPEXTRQ	$0x1,%XMM1,%RDI

(188) 0x23ba8d VSQRTPD	0x1e0(%RSP),%YMM1

(188) 0x23ba96 VMOVHPD	(%R15,%R9,8),%XMM16,%XMM16

(188) 0x23ba9d VPEXTRQ	$0x1,%XMM0,%R9

(188) 0x23baa3 VEXTRACTI128	$0x1,%YMM0,%XMM0

(188) 0x23baa9 VINSERTF32X4	$0x1,%XMM21,%YMM23,%YMM21

(188) 0x23bab0 VINSERTF128	$0x1,%XMM6,%YMM13,%YMM6

(188) 0x23bab6 VMOVSD	(%R15,%R10,8),%XMM13

(188) 0x23babc VMOVQ	%XMM0,%R10

(188) 0x23bac1 VMOVHPD	(%R15,%R11,8),%XMM13,%XMM13

(188) 0x23bac7 VADDPD	%YMM18,%YMM6,%YMM6

(188) 0x23bacd VADDPD	%YMM14,%YMM14,%YMM18

(188) 0x23bad3 VINSERTF32X4	$0x1,%XMM13,%YMM16,%YMM13

(188) 0x23bada VMULPD	0x480(%RSP),%YMM17,%YMM16

(188) 0x23bae2 VADDPD	%YMM21,%YMM13,%YMM13

(188) 0x23bae8 VMAXPD	%YMM5,%YMM1,%YMM1

(188) 0x23baec VDIVPD	%YMM1,%YMM16,%YMM1

(188) 0x23baf2 VMOVSD	(%RCX,%RSI,8),%XMM16

(188) 0x23baf9 VPEXTRQ	$0x1,%XMM0,%RSI

(188) 0x23baff VMOVSD	(%RCX,%RAX,8),%XMM0

(188) 0x23bb04 MOV	0x128(%RSP),%RAX

(188) 0x23bb0c VMOVHPD	(%RCX,%RDI,8),%XMM16,%XMM16

(188) 0x23bb13 VMOVHPD	(%RCX,%RDX,8),%XMM0,%XMM0

(188) 0x23bb18 ADD	$-0x8,%RAX

(188) 0x23bb1c VINSERTF32X4	$0x1,%XMM16,%YMM0,%YMM0

(188) 0x23bb23 VMOVSD	(%RCX,%R10,8),%XMM16

(188) 0x23bb2a VMOVHPD	(%RCX,%RSI,8),%XMM16,%XMM16

(188) 0x23bb31 VMULPD	%YMM0,%YMM6,%YMM0

(188) 0x23bb35 VMOVSD	(%RCX,%R8,8),%XMM6

(188) 0x23bb3b VMOVHPD	(%RCX,%R9,8),%XMM6,%XMM6

(188) 0x23bb41 VINSERTF32X4	$0x1,%XMM16,%YMM6,%YMM6

(188) 0x23bb48 VMULPD	%YMM6,%YMM13,%YMM6

(188) 0x23bb4c VADDPD	0x1c0(%RSP),%YMM3,%YMM13

(188) 0x23bb55 VANDPD	%YMM24,%YMM3,%YMM3

(188) 0x23bb5b VANDPD	%YMM24,%YMM6,%YMM16

(188) 0x23bb61 VSUBPD	%YMM13,%YMM11,%YMM11

(188) 0x23bb66 VMOVAPD	0x140(%RSP),%YMM13

(188) 0x23bb6f VADDPD	%YMM0,%YMM11,%YMM11

(188) 0x23bb73 VANDPD	%YMM24,%YMM0,%YMM0

(188) 0x23bb79 VMAXPD	%YMM0,%YMM3,%YMM0

(188) 0x23bb7d VMULPD	%YMM5,%YMM14,%YMM3

(188) 0x23bb81 VMAXPD	%YMM0,%YMM10,%YMM0

(188) 0x23bb85 VMULPD	%YMM26,%YMM18,%YMM10

(188) 0x23bb8b VFMADD231PD	%YMM13,%YMM13,%YMM12

(188) 0x23bb90 VANDPD	%YMM24,%YMM8,%YMM13

(188) 0x23bb96 VADDPD	%YMM9,%YMM8,%YMM8

(188) 0x23bb9b VANDPD	%YMM24,%YMM9,%YMM9

(188) 0x23bba1 VMAXPD	%YMM16,%YMM9,%YMM9

(188) 0x23bba7 VMOVAPD	0x320(%RSP),%YMM16

(188) 0x23bbaf VMAXPD	%YMM3,%YMM13,%YMM13

(188) 0x23bbb3 VSUBPD	%YMM8,%YMM2,%YMM8

(188) 0x23bbb8 VANDPD	%YMM24,%YMM2,%YMM2

(188) 0x23bbbe VMAXPD	%YMM3,%YMM9,%YMM3

(188) 0x23bbc2 VMAXPD	%YMM2,%YMM13,%YMM2

(188) 0x23bbc6 VADDPD	%YMM6,%YMM8,%YMM6

(188) 0x23bbca VDIVPD	%YMM2,%YMM10,%YMM2

(188) 0x23bbce VMULPD	%YMM16,%YMM7,%YMM10

(188) 0x23bbd4 VDIVPD	%YMM7,%YMM11,%YMM7

(188) 0x23bbd8 VDIVPD	%YMM18,%YMM6,%YMM6

(188) 0x23bbde VMULPD	%YMM16,%YMM18,%YMM9

(188) 0x23bbe4 VMOVAPD	0x280(%RSP),%YMM11

(188) 0x23bbed VDIVPD	%YMM0,%YMM10,%YMM0

(188) 0x23bbf1 VMOVAPD	0x2a0(%RSP),%YMM10

(188) 0x23bbfa VDIVPD	%YMM3,%YMM9,%YMM3

(188) 0x23bbfe VMOVAPD	0x300(%RSP),%YMM9

(188) 0x23bc07 VMOVAPD	%YMM11,%YMM8

(188) 0x23bc0c VCMPPD	$0x1,%YMM10,%YMM7,%K1

(188) 0x23bc13 VDIVPD	%YMM7,%YMM9,%YMM8{%K1}

(188) 0x23bc19 VCMPPD	$0x1,%YMM10,%YMM6,%K1

(188) 0x23bc20 VMOVAPD	%YMM11,%YMM7

(188) 0x23bc24 VMINPD	%YMM0,%YMM11,%YMM0

(188) 0x23bc28 VMINPD	0x160(%RSP),%YMM0,%YMM0

(188) 0x23bc31 VDIVPD	%YMM6,%YMM9,%YMM7{%K1}

(188) 0x23bc37 VSQRTPD	%YMM12,%YMM6

(188) 0x23bc3c VMULPD	%YMM17,%YMM15,%YMM9

(188) 0x23bc42 VMINPD	%YMM0,%YMM8,%YMM0

(188) 0x23bc46 VMINPD	0x4a0(%RSP),%YMM0,%YMM0

(188) 0x23bc4f VMINPD	%YMM0,%YMM1,%YMM1

(188) 0x23bc53 VMINPD	%YMM3,%YMM11,%YMM0

(188) 0x23bc57 VMAXPD	%YMM5,%YMM6,%YMM6

(188) 0x23bc5b VMINPD	%YMM0,%YMM2,%YMM0

(188) 0x23bc5f VDIVPD	%YMM6,%YMM9,%YMM6

(188) 0x23bc63 VMINPD	%YMM7,%YMM0,%YMM0

(188) 0x23bc67 VMINPD	0x4c0(%RSP),%YMM0,%YMM0

(188) 0x23bc70 VMINPD	%YMM0,%YMM6,%YMM0

(188) 0x23bc74 JNE	23ad10

0x23bc7a VMINPD	%YMM0,%YMM1,%YMM0

0x23bc7e MOV	0xb0(%RSP),%RAX

0x23bc86 VMOVAPD	0x230(%RSP),%XMM15

0x23bc8f VMOVAPD	0x220(%RSP),%XMM16

0x23bc97 VMOVAPD	0x210(%RSP),%XMM17

0x23bc9f VMOVAPD	0x200(%RSP),%XMM18

0x23bca7 MOV	0x20(%RSP),%RBX

0x23bcac MOV	0xc0(%RSP),%R14

0x23bcb4 MOV	0x70(%RSP),%R9

0x23bcb9 VEXTRACTF128	$0x1,%YMM0,%XMM1

0x23bcbf VMINPD	%XMM1,%XMM0,%XMM0

0x23bcc3 VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

0x23bcc8 VMINSD	%XMM1,%XMM0,%XMM0

0x23bccc CMP	%RAX,0xb8(%RSP)

0x23bcd4 MOV	0x28(%RSP),%RAX

0x23bcd9 JNE	23bd83

0x23bcdf MOV	0x60(%RSP),%R14D

0x23bce4 MOV	0x80(%RBP),%RBX

0x23bceb LEA	0x1f406(%RIP),%RDI

0x23bcf2 VMOVSD	%XMM0,0x18(%RSP)

0x23bcf8 MOV	%R14D,%ESI

0x23bcfb VZEROUPPER

0x23bcfe CALL	259690 <@plt_start@+0x540>

0x23bd03 LEA	0x18(%RSP),%RAX

0x23bd08 MOV	%RAX,0x130(%RSP)

0x23bd10 SUB	$0x8,%RSP

0x23bd14 LEA	0x2329d(%RIP),%RAX

0x23bd1b LEA	0x1f3ee(%RIP),%RDI

0x23bd22 LEA	-0x1419(%RIP),%R9

0x23bd29 LEA	0x138(%RSP),%R8

0x23bd31 MOV	$0x8,%ECX

0x23bd36 MOV	%R14D,%ESI

0x23bd39 MOV	$0x1,%EDX

0x23bd3e PUSH	%RAX

0x23bd3f CALL	2596b0 <@plt_start@+0x560>

0x23bd44 ADD	$0x10,%RSP

0x23bd48 CMP	$0x2,%EAX

0x23bd4b JE	23bfb6

0x23bd51 CMP	$0x1,%EAX

0x23bd54 JNE	23bfd5

0x23bd5a VMOVSD	(%RBX),%XMM0

0x23bd5e LEA	0x23253(%RIP),%RDX

0x23bd65 LEA	0x1f3a4(%RIP),%RDI

0x23bd6c MOV	%R14D,%ESI

0x23bd6f VMINSD	0x18(%RSP),%XMM0,%XMM0

0x23bd75 VMOVSD	%XMM0,(%RBX)

0x23bd79 CALL	2596c0 <@plt_start@+0x570>

0x23bd7e JMP	23bfd5

0x23bd83 VMOVSD	-0x2abd3(%RIP),%XMM1

0x23bd8b VMOVDDUP	-0x2ac3b(%RIP),%XMM2

0x23bd93 VMOVSD	-0x2ac1b(%RIP),%XMM3

0x23bd9b VMOVSD	-0x2ac6b(%RIP),%XMM4

0x23bda3 JMP	23be96

0x23bda8 NOPL	(%RAX,%RAX,1)

(190) 0x23bdb0 MOV	0x50(%RSP),%RAX

(190) 0x23bdb5 MOV	0x98(%RSP),%RDI

(190) 0x23bdbd VMULSD	%XMM1,%XMM7,%XMM7

(190) 0x23bdc1 VANDPD	%XMM2,%XMM5,%XMM5

(190) 0x23bdc5 VANDPD	%XMM2,%XMM8,%XMM8

(190) 0x23bdc9 VANDPD	%XMM2,%XMM6,%XMM6

(190) 0x23bdcd VANDPD	%XMM2,%XMM9,%XMM9

(190) 0x23bdd1 MOV	0x70(%RSP),%R9

(190) 0x23bdd6 VMAXSD	%XMM7,%XMM5,%XMM5

(190) 0x23bdda VMAXSD	%XMM7,%XMM8,%XMM7

(190) 0x23bdde VMOVSD	(%RAX,%RSI,8),%XMM12

(190) 0x23bde3 MOV	0xf0(%RSP),%RAX

(190) 0x23bdeb VMAXSD	%XMM6,%XMM5,%XMM5

(190) 0x23bdef VMULSD	%XMM17,%XMM10,%XMM6

(190) 0x23bdf5 VMAXSD	%XMM7,%XMM9,%XMM7

(190) 0x23bdf9 VDIVSD	%XMM7,%XMM6,%XMM6

(190) 0x23bdfd VMINSD	%XMM3,%XMM11,%XMM7

(190) 0x23be01 IMUL	%RDX,%RAX

(190) 0x23be05 ADD	%RSI,%RAX

(190) 0x23be08 VMOVSD	(%RDI,%RAX,8),%XMM13

(190) 0x23be0d MOV	0xe8(%RSP),%RAX

(190) 0x23be15 MOV	0x80(%RSP),%RDI

(190) 0x23be1d IMUL	%RDX,%RAX

(190) 0x23be21 VMINSD	%XMM7,%XMM6,%XMM6

(190) 0x23be25 ADD	%RSI,%RAX

(190) 0x23be28 VMOVSD	(%RDI,%RAX,8),%XMM14

(190) 0x23be2d MOV	0xe0(%RSP),%RAX

(190) 0x23be35 MOV	0x90(%RSP),%RDI

(190) 0x23be3d IMUL	%RDX,%RAX

(190) 0x23be41 ADD	%RSI,%RAX

(190) 0x23be44 VADDSD	%XMM14,%XMM14,%XMM14

(190) 0x23be49 VDIVSD	(%RDI,%RAX,8),%XMM14,%XMM14

(190) 0x23be4e MOV	0xa0(%RSP),%RAX

(190) 0x23be56 VMINSD	(%RAX,%RDX,8),%XMM12,%XMM12

(190) 0x23be5b LEA	0x1(%R11),%RAX

(190) 0x23be5f VMULSD	%XMM15,%XMM12,%XMM12

(190) 0x23be64 VFMADD231SD	%XMM13,%XMM13,%XMM14

(190) 0x23be69 VSQRTSD	%XMM14,%XMM14,%XMM13

(190) 0x23be6e VMULSD	%XMM16,%XMM10,%XMM14

(190) 0x23be74 VDIVSD	%XMM5,%XMM14,%XMM5

(190) 0x23be78 VMINSD	%XMM6,%XMM5,%XMM5

(190) 0x23be7c VMINSD	%XMM0,%XMM5,%XMM0

(190) 0x23be80 VMAXSD	%XMM1,%XMM13,%XMM13

(190) 0x23be84 VDIVSD	%XMM13,%XMM12,%XMM12

(190) 0x23be89 VMINSD	%XMM0,%XMM12,%XMM0

(190) 0x23be8d CMP	%R14,%R11

(190) 0x23be90 JGE	23bcdf

(190) 0x23be96 MOV	%RAX,%R11

(190) 0x23be99 CQTO

(190) 0x23be9b IDIVQ	0x78(%RSP)

(190) 0x23bea0 ADD	0x14(%RSP),%EDX

(190) 0x23bea4 MOVSXD	%EDX,%RSI

(190) 0x23bea7 LEA	(%RBX,%RAX,1),%EDI

(190) 0x23beaa LEA	0x1(%RBX,%RAX,1),%EAX

(190) 0x23beae MOVSXD	%EDI,%RDX

(190) 0x23beb1 MOV	%R9,%RDI

(190) 0x23beb4 CLTQ

(190) 0x23beb6 IMUL	%RDX,%RDI

(190) 0x23beba IMUL	%RAX,%R9

(190) 0x23bebe LEA	(%RDI,%RSI,1),%R8

(190) 0x23bec2 LEA	0x1(%RDI,%RSI,1),%RDI

(190) 0x23bec7 LEA	(%R9,%RSI,1),%R10

(190) 0x23becb LEA	0x1(%R9,%RSI,1),%R9

(190) 0x23bed0 VMOVSD	(%R12,%R10,8),%XMM5

(190) 0x23bed6 VADDSD	(%R12,%R8,8),%XMM5,%XMM5

(190) 0x23bedc MOV	0xd8(%RSP),%R8

(190) 0x23bee4 VMOVSD	(%R12,%R9,8),%XMM6

(190) 0x23beea MOV	0xc8(%RSP),%R9

(190) 0x23bef2 VADDSD	(%R12,%RDI,8),%XMM6,%XMM6

(190) 0x23bef8 IMUL	%RDX,%R8

(190) 0x23befc LEA	0x1(%R8,%RSI,1),%RDI

(190) 0x23bf01 LEA	(%R8,%RSI,1),%R10

(190) 0x23bf05 MOV	0x88(%RSP),%R8

(190) 0x23bf0d VMULSD	(%R13,%R10,8),%XMM5,%XMM5

(190) 0x23bf14 MOV	0x68(%RSP),%R10

(190) 0x23bf19 VMULSD	(%R13,%RDI,8),%XMM6,%XMM6

(190) 0x23bf20 MOV	0xd0(%RSP),%RDI

(190) 0x23bf28 IMUL	%RDX,%RDI

(190) 0x23bf2c ADD	%RSI,%RDI

(190) 0x23bf2f VMOVSD	(%R8,%RDI,8),%XMM7

(190) 0x23bf35 MOV	%R9,%RDI

(190) 0x23bf38 IMUL	%RDX,%RDI

(190) 0x23bf3c LEA	0x1(%RDI,%RSI,1),%R8

(190) 0x23bf41 ADD	%RSI,%RDI

(190) 0x23bf44 VMOVSD	(%R15,%R8,8),%XMM8

(190) 0x23bf4a VADDSD	(%R15,%RDI,8),%XMM8,%XMM8

(190) 0x23bf50 MOV	%R10,%RDI

(190) 0x23bf53 IMUL	%RDX,%RDI

(190) 0x23bf57 VADDSD	%XMM7,%XMM7,%XMM10

(190) 0x23bf5b ADD	%RSI,%RDI

(190) 0x23bf5e VMULSD	(%RCX,%RDI,8),%XMM8,%XMM8

(190) 0x23bf63 MOV	%R9,%RDI

(190) 0x23bf66 IMUL	%RAX,%RDI

(190) 0x23bf6a IMUL	%R10,%RAX

(190) 0x23bf6e LEA	0x1(%RDI,%RSI,1),%R8

(190) 0x23bf73 ADD	%RSI,%RDI

(190) 0x23bf76 ADD	%RSI,%RAX

(190) 0x23bf79 VMOVSD	(%R15,%R8,8),%XMM9

(190) 0x23bf7f VADDSD	(%R15,%RDI,8),%XMM9,%XMM9

(190) 0x23bf85 VMULSD	(%RCX,%RAX,8),%XMM9,%XMM9

(190) 0x23bf8a VADDSD	%XMM5,%XMM8,%XMM11

(190) 0x23bf8e VSUBSD	%XMM11,%XMM6,%XMM11

(190) 0x23bf93 VADDSD	%XMM9,%XMM11,%XMM11

(190) 0x23bf98 VDIVSD	%XMM10,%XMM11,%XMM12

(190) 0x23bf9d VMOVAPD	%XMM3,%XMM11

(190) 0x23bfa1 VUCOMISD	%XMM4,%XMM12

(190) 0x23bfa5 JAE	23bdb0

(190) 0x23bfab VDIVSD	%XMM12,%XMM18,%XMM11

(190) 0x23bfb1 JMP	23bdb0

0x23bfb6 MOV	(%RBX),%RAX

0x23bfb9 VMOVSD	0x18(%RSP),%XMM0

0x23bfbf NOP

(189) 0x23bfc0 VMOVQ	%RAX,%XMM1

(189) 0x23bfc5 VMINSD	%XMM0,%XMM1,%XMM1

(189) 0x23bfc9 VMOVQ	%XMM1,%RCX

(189) 0x23bfce LOCK CMPXCHG	%RCX,(%RBX)

(189) 0x23bfd3 JNE	23bfc0

0x23bfd5 LEA	-0x28(%RBP),%RSP

0x23bfd9 POP	%RBX

0x23bfda POP	%R12

0x23bfdc POP	%R13

0x23bfde POP	%R14

0x23bfe0 POP	%R15

0x23bfe2 POP	%RBP

0x23bfe3 RET

0x23bfe4 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run aocc_8

Source file and lines	calc_dt.cpp:49-75
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:49-75

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 35.00 to 12.75 cycles (2.75x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 20% of vector register length is used (average across all SSE/AVX instructions).

Details

31% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

22% of SSE/AVX loads are used in vector version.
41% of SSE/AVX stores are used in vector version.
18% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 35.00 to 32.25 cycles (1.09x speedup).

Workaround

Read less array elements
Write less array elements

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 4 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:49
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:49
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:49
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:49

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVL: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:50
VPBROADCASTD: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:50
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:50
VPBROADCASTQ: 10 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:50
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:50
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:50
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:50
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:50
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:50
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:50
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:50
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:50
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:50

Vector unaligned load/store instructions

Detected 1 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:50

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time). 1 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 676 bytes (84 double precision FP elements). The binary function is storing 884 bytes (110 double precision FP elements).

General properties

nb instructions	245
nb uops	258
loop length	1339
used x86 registers	16
used mmx registers	0
used xmm registers	9
used ymm registers	5
used zmm registers	0
nb stack references	69

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	32.25 cycles
front end	32.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	10.17	10.17	10.17	10.17	10.17	10.17	35.00	35.00	35.00	35.00	4.00	8.50	8.50	4.00	12.50	12.50
cycles	10.17	10.17	10.17	10.17	10.17	10.17	35.00	35.00	35.00	35.00	4.00	8.50	8.50	4.00	12.50	12.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	32.25
Dispatch	35.00
Overall L1	35.00

Vectorization ratios

INT

all	20%
load	50%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	5%

all	46%
load	20%
store	86%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	31%

INT+FP

all	31%
load	22%
store	41%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

Vector efficiency ratios

INT

all	17%
load	31%
store	19%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	23%
load	15%
store	38%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	19%

INT+FP

all	20%
load	16%
store	24%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 35.00 cycles. At this rate:

7% of peak load performance is reached (19.31 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
19% of peak store performance is reached (25.26 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 23a930

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND $-0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB $0x500,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RDX),%R14D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RCX),%EBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
INC %R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x2,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %R14D,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JLE 23bfd5 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x16a5>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV (%R9),%R12D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%R8),%R15D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
INC %R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x2,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R15D,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 23bfd5 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x16a5>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
SUB %R15D,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV $0x7fefffffffffffff,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVQ $0,0xa8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOVQ $0x1,0x138(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOVL $0,0x64(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
IMUL %R12,%RBX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
MOV %RAX,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
DEC %RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RBX,0x58(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x20723(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x140(%RSP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x6c(%RSP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0xb0(%RSP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x60(%RSP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %ESI,0x68(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 259680 <@plt_start@+0x530>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x58(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xa8(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CMP %RBX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMOVL %RAX,%RBX	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %RBX,0x58(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
CMP %RBX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JLE 23aa19 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0xe9>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVSD -0x29904(%RIP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
JMP 23bcdf <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x13af>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV %R14,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x18(%RBP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x20(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R12,0x78(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x30(%RBP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x28(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R15D,0x14(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV 0x10(%RBP),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,0x28(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x78(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x70(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x50(%RBP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x58(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x48(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x40(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x38(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%R11),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x8(%R14),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%R11),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD (%RDI),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x8(%R15),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD (%R13),%XMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD (%R9),%XMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV (%R8),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RCX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RSI),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD (%RAX),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x28(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VXORPD -0x29923(%RIP){1to2},%XMM0,%XMM18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (25.0%)
MOV %R14,0xa0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R11,0x98(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%R10),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%R10),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%R12),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R15,0x50(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDI,0x88(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R9,0x70(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDX,0xf0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R10,0x80(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%R12),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R14,0x90(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x10(%R8),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RSI),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RCX),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x60(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x68(%RBP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R11,0xe8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RCX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RCX),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%R14),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R10,0xe0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R8,0xd8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RSI,0xd0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RCX,0x68(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x10(%R14),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RBX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RAX,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDI,0xc8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
INC %R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x8,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 23ab56 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x226>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVSD -0x29a39(%RIP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV %RBX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x20(%RSP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JMP 23bd83 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x1453>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV %R14,0xb8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
AND $-0x8,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VPBROADCASTQ %RAX,%YMM0	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
MOV %RBX,0xc0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x14(%RSP),%EBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VPADDQ -0x2989c(%RIP),%YMM0,%YMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (50.0%)
VBROADCASTSD -0x29a75(%RIP),%YMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VBROADCASTSD -0x29a37(%RIP),%YMM24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVAPD %XMM15,0x230(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVAPD %XMM16,0x220(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVAPD %XMM17,0x210(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVAPD %XMM18,0x200(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
ADD %R14,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R14,0xb0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RAX,0x28(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x78(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VPBROADCASTQ %RAX,%YMM27	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
MOV 0x20(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VPBROADCASTD %EAX,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (6.3%)
MOV 0x68(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVDQA %XMM0,0x250(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VPBROADCASTD %EBX,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (6.3%)
VMOVDQA %XMM0,0x240(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VPBROADCASTQ %RDX,%YMM0	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
VMOVDQA %YMM0,0x460(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPBROADCASTQ %R11,%YMM0	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
VMOVDQA %YMM0,0x440(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPBROADCASTQ %R10,%YMM0	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
VMOVDQA %YMM0,0x420(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VBROADCASTSD %XMM15,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VMOVAPD %YMM0,0x400(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPBROADCASTQ %R9,%YMM0	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
VMOVDQA %YMM0,0x3e0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPBROADCASTQ %R8,%YMM0	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
VMOVDQA %YMM0,0x3c0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPBROADCASTQ %RSI,%YMM0	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
VMOVDQA %YMM0,0x3a0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VBROADCASTSD %XMM16,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VMOVAPD %YMM0,0x380(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPBROADCASTQ %RDI,%YMM0	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
VMOVDQA %YMM0,0x360(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPBROADCASTQ %RAX,%YMM0	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
MOV %R14,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x50(%RSP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVDQA %YMM0,0x340(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VBROADCASTSD %XMM17,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VMOVAPD %YMM0,0x320(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VBROADCASTSD %XMM18,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VMOVAPD %YMM0,0x300(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VBROADCASTSD -0x29aff(%RIP),%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVAPS %YMM0,0x2e0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VBROADCASTSD -0x29af9(%RIP),%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVAPS %YMM0,0x2c0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VBROADCASTSD -0x29ba3(%RIP),%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVAPS %YMM0,0x2a0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VBROADCASTSD -0x29b6d(%RIP),%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVAPS %YMM0,0x280(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VBROADCASTSD -0x29c17(%RIP),%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVAPS %YMM0,0x260(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VMOVAPD %YMM1,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VMINPD %YMM0,%YMM1,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
MOV 0xb0(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVAPD 0x230(%RSP),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVAPD 0x220(%RSP),%XMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVAPD 0x210(%RSP),%XMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVAPD 0x200(%RSP),%XMM18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MOV 0x20(%RSP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xc0(%RSP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x70(%RSP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VEXTRACTF128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMINPD %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VMINSD %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
CMP %RAX,0xb8(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOV 0x28(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JNE 23bd83 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x1453>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x60(%RSP),%R14D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x80(%RBP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA 0x1f406(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVSD %XMM0,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 259690 <@plt_start@+0x540>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
LEA 0x18(%RSP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RAX,0x130(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x2329d(%RIP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x1f3ee(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x1419(%RIP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x138(%RSP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x8,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x1,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 2596b0 <@plt_start@+0x560>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
ADD $0x10,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x2,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 23bfb6 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x1686>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x1,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 23bfd5 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x16a5>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVSD (%RBX),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
LEA 0x23253(%RIP),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x1f3a4(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMINSD 0x18(%RSP),%XMM0,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM0,(%RBX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
CALL 2596c0 <@plt_start@+0x570>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
JMP 23bfd5 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x16a5>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VMOVSD -0x2abd3(%RIP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVDDUP -0x2ac3b(%RIP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVSD -0x2ac1b(%RIP),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD -0x2ac6b(%RIP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
JMP 23be96 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x1566>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV (%RBX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD 0x18(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run aocc_8

Source file and lines	calc_dt.cpp:49-75
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:49-75

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 20% of vector register length is used (average across all SSE/AVX instructions).

Details

31% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

22% of SSE/AVX loads are used in vector version.
41% of SSE/AVX stores are used in vector version.
18% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 35.00 to 32.25 cycles (1.09x speedup).

Workaround

Read less array elements
Write less array elements

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

unknown: 4 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:49
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:49
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:49
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:49

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVL: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:50
VPBROADCASTD: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:50
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:50
VPBROADCASTQ: 10 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:50
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:50
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:50
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:50
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:50
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:50
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:50
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:50
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:50
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:50

Vector unaligned load/store instructions

Detected 1 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:50

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

nb instructions	245
nb uops	258
loop length	1339
used x86 registers	16
used mmx registers	0
used xmm registers	9
used ymm registers	5
used zmm registers	0
nb stack references	69

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	32.25 cycles
front end	32.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	10.17	10.17	10.17	10.17	10.17	10.17	35.00	35.00	35.00	35.00	4.00	8.50	8.50	4.00	12.50	12.50
cycles	10.17	10.17	10.17	10.17	10.17	10.17	35.00	35.00	35.00	35.00	4.00	8.50	8.50	4.00	12.50	12.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	32.25
Dispatch	35.00
Overall L1	35.00

Vectorization ratios

INT

all	20%
load	50%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	5%

all	46%
load	20%
store	86%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	31%

INT+FP

all	31%
load	22%
store	41%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

Vector efficiency ratios

INT

all	17%
load	31%
store	19%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	23%
load	15%
store	38%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	19%

INT+FP

all	20%
load	16%
store	24%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 35.00 cycles. At this rate:

7% of peak load performance is reached (19.31 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
19% of peak store performance is reached (25.26 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 23a930

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND $-0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB $0x500,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RDX),%R14D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RCX),%EBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
INC %R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x2,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %R14D,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JLE 23bfd5 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x16a5>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV (%R9),%R12D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%R8),%R15D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
INC %R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x2,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R15D,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 23bfd5 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x16a5>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
SUB %R15D,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV $0x7fefffffffffffff,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVQ $0,0xa8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOVQ $0x1,0x138(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOVL $0,0x64(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
IMUL %R12,%RBX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
MOV %RAX,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
DEC %RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RBX,0x58(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x20723(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x140(%RSP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x6c(%RSP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0xb0(%RSP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x60(%RSP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %ESI,0x68(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 259680 <@plt_start@+0x530>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x58(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xa8(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CMP %RBX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMOVL %RAX,%RBX	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %RBX,0x58(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
CMP %RBX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JLE 23aa19 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0xe9>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVSD -0x29904(%RIP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
JMP 23bcdf <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x13af>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV %R14,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x18(%RBP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x20(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R12,0x78(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x30(%RBP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x28(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R15D,0x14(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV 0x10(%RBP),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,0x28(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x78(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x70(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x50(%RBP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x58(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x48(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x40(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x38(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%R11),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x8(%R14),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%R11),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD (%RDI),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x8(%R15),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD (%R13),%XMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD (%R9),%XMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV (%R8),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RCX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RSI),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD (%RAX),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x28(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VXORPD -0x29923(%RIP){1to2},%XMM0,%XMM18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (25.0%)
MOV %R14,0xa0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R11,0x98(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%R10),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%R10),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%R12),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R15,0x50(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDI,0x88(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R9,0x70(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDX,0xf0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R10,0x80(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%R12),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R14,0x90(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x10(%R8),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RSI),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RCX),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x60(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x68(%RBP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R11,0xe8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RCX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RCX),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%R14),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R10,0xe0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R8,0xd8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RSI,0xd0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RCX,0x68(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x10(%R14),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RBX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RAX,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDI,0xc8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
INC %R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x8,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 23ab56 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x226>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVSD -0x29a39(%RIP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV %RBX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x20(%RSP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JMP 23bd83 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x1453>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV %R14,0xb8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
AND $-0x8,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VPBROADCASTQ %RAX,%YMM0	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
MOV %RBX,0xc0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x14(%RSP),%EBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VPADDQ -0x2989c(%RIP),%YMM0,%YMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (50.0%)
VBROADCASTSD -0x29a75(%RIP),%YMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VBROADCASTSD -0x29a37(%RIP),%YMM24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVAPD %XMM15,0x230(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVAPD %XMM16,0x220(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVAPD %XMM17,0x210(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVAPD %XMM18,0x200(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
ADD %R14,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R14,0xb0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RAX,0x28(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x78(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VPBROADCASTQ %RAX,%YMM27	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
MOV 0x20(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VPBROADCASTD %EAX,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (6.3%)
MOV 0x68(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVDQA %XMM0,0x250(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VPBROADCASTD %EBX,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (6.3%)
VMOVDQA %XMM0,0x240(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VPBROADCASTQ %RDX,%YMM0	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
VMOVDQA %YMM0,0x460(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPBROADCASTQ %R11,%YMM0	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
VMOVDQA %YMM0,0x440(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPBROADCASTQ %R10,%YMM0	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
VMOVDQA %YMM0,0x420(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VBROADCASTSD %XMM15,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VMOVAPD %YMM0,0x400(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPBROADCASTQ %R9,%YMM0	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
VMOVDQA %YMM0,0x3e0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPBROADCASTQ %R8,%YMM0	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
VMOVDQA %YMM0,0x3c0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPBROADCASTQ %RSI,%YMM0	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
VMOVDQA %YMM0,0x3a0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VBROADCASTSD %XMM16,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VMOVAPD %YMM0,0x380(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPBROADCASTQ %RDI,%YMM0	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
VMOVDQA %YMM0,0x360(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPBROADCASTQ %RAX,%YMM0	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
MOV %R14,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x50(%RSP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVDQA %YMM0,0x340(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VBROADCASTSD %XMM17,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VMOVAPD %YMM0,0x320(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VBROADCASTSD %XMM18,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VMOVAPD %YMM0,0x300(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VBROADCASTSD -0x29aff(%RIP),%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVAPS %YMM0,0x2e0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VBROADCASTSD -0x29af9(%RIP),%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVAPS %YMM0,0x2c0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VBROADCASTSD -0x29ba3(%RIP),%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVAPS %YMM0,0x2a0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VBROADCASTSD -0x29b6d(%RIP),%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVAPS %YMM0,0x280(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VBROADCASTSD -0x29c17(%RIP),%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVAPS %YMM0,0x260(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VMOVAPD %YMM1,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VMINPD %YMM0,%YMM1,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
MOV 0xb0(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVAPD 0x230(%RSP),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVAPD 0x220(%RSP),%XMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVAPD 0x210(%RSP),%XMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVAPD 0x200(%RSP),%XMM18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MOV 0x20(%RSP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xc0(%RSP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x70(%RSP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VEXTRACTF128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMINPD %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VMINSD %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
CMP %RAX,0xb8(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOV 0x28(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JNE 23bd83 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x1453>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x60(%RSP),%R14D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x80(%RBP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA 0x1f406(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVSD %XMM0,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 259690 <@plt_start@+0x540>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
LEA 0x18(%RSP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RAX,0x130(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x2329d(%RIP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x1f3ee(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x1419(%RIP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x138(%RSP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x8,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x1,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 2596b0 <@plt_start@+0x560>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
ADD $0x10,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x2,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 23bfb6 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x1686>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x1,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 23bfd5 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x16a5>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVSD (%RBX),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
LEA 0x23253(%RIP),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x1f3a4(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMINSD 0x18(%RSP),%XMM0,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM0,(%RBX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
CALL 2596c0 <@plt_start@+0x570>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
JMP 23bfd5 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x16a5>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VMOVSD -0x2abd3(%RIP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVDDUP -0x2ac3b(%RIP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVSD -0x2ac1b(%RIP),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD -0x2ac6b(%RIP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
JMP 23be96 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x1566>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV (%RBX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD 0x18(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼calc_dt_kernel(int, int, int, int, double, double, double, double, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D–	3.22	1.20
○Loop 188 - calc_dt.cpp:50-75 - exec	3.22	1.20
○Loop 189 - calc_dt.cpp:49-49 - exec	0.00	0.00
○Loop 190 - calc_dt.cpp:49-75 - exec	0.00	0.00

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ASM code

Code clean check

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Vectorization

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Execution units bottlenecks

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512-bits vectorization

Workaround

CALL instructions

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Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code