OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone .omp

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: advec_mom.cpp:180-211 [...]	Coverage (incl. loops): 4.37% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 180 - 211

--------------------------------------------------------------------------------

180: #pragma omp parallel for simd collapse(2)

181:     for (int j = (y_min - 1 + 1); j < (y_max + 1 + 2); j++) {

182:       for (int i = (x_min + 1); i < (x_max + 1 + 2); i++)

183:         ({

184:           int upwind, donor, downwind, dif;

185:           double sigma, width, limiter, vdiffuw, vdiffdw, auw, adw, wind, advec_vel_s;

186:           if (node_flux(i, j) < 0.0) {

187:             upwind = j + 2;

188:             donor = j + 1;

189:             downwind = j;

190:             dif = donor;

191:           } else {

192:             upwind = j - 1;

193:             donor = j;

194:             downwind = j + 1;

195:             dif = upwind;

196:           }

197:           sigma = std::fabs(node_flux(i, j)) / (node_mass_pre(i, donor));

198:           width = celldy[j];

199:           vdiffuw = vel1(i, donor) - vel1(i, upwind);

200:           vdiffdw = vel1(i, downwind) - vel1(i, donor);

201:           limiter = 0.0;

202:           if (vdiffuw * vdiffdw > 0.0) {

203:             auw = std::fabs(vdiffuw);

204:             adw = std::fabs(vdiffdw);

205:             wind = 1.0;

206:             if (vdiffdw <= 0.0) wind = -1.0;

207:             limiter =

208:                 wind * std::fmin(std::fmin(width * ((2.0 - sigma) * adw / width + (1.0 + sigma) * auw / celldy[dif]) / 6.0, auw), adw);

209:           }

210:           advec_vel_s = vel1(i, donor) + (1.0 - sigma) * limiter;

211:           mom_flux(i, j) = advec_vel_s * node_flux(i, j);

0x2376e0 PUSH	%RBP

0x2376e1 MOV	%RSP,%RBP

0x2376e4 PUSH	%R15

0x2376e6 PUSH	%R14

0x2376e8 PUSH	%R13

0x2376ea PUSH	%R12

0x2376ec PUSH	%RBX

0x2376ed SUB	$0x68,%RSP

0x2376f1 MOV	(%RCX),%R15D

0x2376f4 MOV	(%RDX),%EAX

0x2376f6 ADD	$0x3,%R15D

0x2376fa MOV	%RAX,-0x50(%RBP)

0x2376fe SUB	%EAX,%R15D

0x237701 JLE	237c33

0x237707 MOV	(%R9),%R12D

0x23770a MOV	(%R8),%R13D

0x23770d INC	%R13D

0x237710 ADD	$0x3,%R12D

0x237714 CMP	%R13D,%R12D

0x237717 JLE	237c33

0x23771d SUB	%R13D,%R12D

0x237720 MOV	(%RDI),%ESI

0x237722 MOVQ	$0,-0x58(%RBP)

0x23772a MOVQ	$0x1,-0x88(%RBP)

0x237735 MOVL	$0,-0x40(%RBP)

0x23773c IMUL	%R12,%R15

0x237740 DEC	%R15

0x237743 MOV	%R15,-0x38(%RBP)

0x237747 SUB	$0x8,%RSP

0x23774b LEA	-0x40(%RBP),%RCX

0x23774f LEA	-0x88(%RBP),%RAX

0x237756 LEA	0x236b3(%RIP),%RDI

0x23775d LEA	-0x58(%RBP),%R8

0x237761 LEA	-0x38(%RBP),%R9

0x237765 MOV	%ESI,-0x3c(%RBP)

0x237768 MOV	$0x22,%EDX

0x23776d PUSH	$0x1

0x23776f PUSH	$0x1

0x237771 PUSH	%RAX

0x237772 CALL	259680 <@plt_start@+0x530>

0x237777 ADD	$0x20,%RSP

0x23777b MOV	-0x38(%RBP),%RAX

0x23777f MOV	-0x58(%RBP),%RCX

0x237783 CMP	%R15,%RAX

0x237786 CMOVL	%RAX,%R15

0x23778a MOV	%R15,-0x38(%RBP)

0x23778e CMP	%R15,%RCX

0x237791 JG	237c21

0x237797 MOV	0x20(%RBP),%RSI

0x23779b MOV	0x28(%RBP),%RDX

0x23779f MOV	0x18(%RBP),%R8

0x2377a3 MOV	0x10(%RBP),%RDI

0x2377a7 MOV	0x30(%RBP),%RAX

0x2377ab MOV	0x8(%RSI),%RSI

0x2377af MOV	(%RDI),%RBX

0x2377b2 MOV	(%R8),%R14

0x2377b5 MOV	0x10(%R8),%R9

0x2377b9 MOV	0x10(%RDI),%RDI

0x2377bd MOV	(%RDX),%R10

0x2377c0 MOV	0x10(%RDX),%R11

0x2377c4 MOV	(%RAX),%RDX

0x2377c7 MOV	%R15,%R8

0x2377ca SUB	%RCX,%R8

0x2377cd INC	%R8

0x2377d0 MOV	%RSI,-0x48(%RBP)

0x2377d4 MOV	0x10(%RAX),%RSI

0x2377d8 MOV	%RBX,-0x80(%RBP)

0x2377dc MOV	%R14,-0x78(%RBP)

0x2377e0 MOV	%RDX,-0x70(%RBP)

0x2377e4 CMP	$0x4,%R8

0x2377e8 JB	237c42

0x2377ee VBROADCASTSD	-0x266a7(%RIP),%YMM13

0x2377f7 VPBROADCASTQ	%RCX,%YMM0

0x2377fd VPADDQ	-0x26525(%RIP),%YMM0,%YMM0

0x237805 VBROADCASTSD	-0x266b6(%RIP),%YMM11

0x23780e VBROADCASTSD	-0x266b7(%RIP),%YMM12

0x237817 VPBROADCASTQ	-0x26650(%RIP),%YMM14

0x237820 MOV	-0x50(%RBP),%RAX

0x237824 MOV	%R8,-0x30(%RBP)

0x237828 AND	$-0x4,%R8

0x23782c VPBROADCASTQ	%R12,%YMM1

0x237832 VPBROADCASTD	%R13D,%XMM26

0x237838 VPBROADCASTQ	%RBX,%YMM27

0x23783e VPBROADCASTQ	%R14,%YMM5

0x237844 VPBROADCASTQ	%R10,%YMM6

0x23784a VPBROADCASTQ	%RDX,%YMM7

0x237850 VXORPD	%XMM9,%XMM9,%XMM9

0x237855 VPCMPEQD	%XMM10,%XMM10,%XMM10

0x23785a ADD	%R8,%RCX

0x23785d VEXTRACTI128	$0x1,%YMM1,%XMM8

0x237863 MOV	%R8,-0x60(%RBP)

0x237867 VPBROADCASTD	%EAX,%XMM17

0x23786d JMP	2378d5

0x23786f NOP

(168) 0x237870 VSUBPD	%YMM19,%YMM13,%YMM4

(168) 0x237876 VMOVAPD	%YMM24,%YMM3{%K1}{z}

(168) 0x23787c ADD	$-0x4,%R8

(168) 0x237880 VPADDQ	%YMM0,%YMM14,%YMM0

(168) 0x237884 VFMADD213PD	%YMM21,%YMM3,%YMM4

(168) 0x23788a VPMULLQ	%YMM16,%YMM7,%YMM3

(168) 0x237890 VPADDQ	%YMM3,%YMM15,%YMM3

(168) 0x237894 VMULPD	%YMM2,%YMM4,%YMM2

(168) 0x237898 VMOVQ	%XMM3,%RDX

(168) 0x23789d VPEXTRQ	$0x1,%XMM3,%RAX

(168) 0x2378a3 VEXTRACTI128	$0x1,%YMM3,%XMM3

(168) 0x2378a9 VMOVQ	%XMM3,%RBX

(168) 0x2378ae VPEXTRQ	$0x1,%XMM3,%R14

(168) 0x2378b4 VMOVLPD	%XMM2,(%RSI,%RDX,8)

(168) 0x2378b9 VMOVHPD	%XMM2,(%RSI,%RAX,8)

(168) 0x2378be VEXTRACTF128	$0x1,%YMM2,%XMM2

(168) 0x2378c4 VMOVLPD	%XMM2,(%RSI,%RBX,8)

(168) 0x2378c9 VMOVHPD	%XMM2,(%RSI,%R14,8)

(168) 0x2378cf JE	237c17

(168) 0x2378d5 VEXTRACTI128	$0x1,%YMM0,%XMM2

(168) 0x2378db VPEXTRQ	$0x1,%XMM8,%RBX

(168) 0x2378e1 VPEXTRQ	$0x1,%XMM2,%RAX

(168) 0x2378e7 CQTO

(168) 0x2378e9 IDIV	%RBX

(168) 0x2378ec VMOVQ	%XMM8,%RBX

(168) 0x2378f1 VMOVQ	%RAX,%XMM15

(168) 0x2378f6 VMOVQ	%XMM2,%RAX

(168) 0x2378fb CQTO

(168) 0x2378fd IDIV	%RBX

(168) 0x237900 VPEXTRQ	$0x1,%XMM1,%RBX

(168) 0x237906 VMOVQ	%RAX,%XMM2

(168) 0x23790b VPEXTRQ	$0x1,%XMM0,%RAX

(168) 0x237911 CQTO

(168) 0x237913 VPUNPCKLQDQ	%XMM15,%XMM2,%XMM2

(168) 0x237918 IDIV	%RBX

(168) 0x23791b VMOVQ	%XMM1,%RBX

(168) 0x237920 VMOVQ	%RAX,%XMM15

(168) 0x237925 VMOVQ	%XMM0,%RAX

(168) 0x23792a CQTO

(168) 0x23792c IDIV	%RBX

(168) 0x23792f VMOVQ	%RAX,%XMM16

(168) 0x237935 VPUNPCKLQDQ	%XMM15,%XMM16,%XMM15

(168) 0x23793b VINSERTI128	$0x1,%XMM2,%YMM15,%YMM2

(168) 0x237941 VPMOVQD	%YMM2,%XMM15

(168) 0x237947 VPMULLQ	%YMM1,%YMM2,%YMM2

(168) 0x23794d VPSUBQ	%YMM2,%YMM0,%YMM2

(168) 0x237951 VPMOVQD	%YMM2,%XMM2

(168) 0x237957 VPADDD	%XMM15,%XMM17,%XMM19

(168) 0x23795d VPMOVSXDQ	%XMM19,%YMM16

(168) 0x237963 VPSUBD	%XMM10,%XMM19,%XMM20

(168) 0x237969 VPMOVSXDQ	%XMM20,%YMM23

(168) 0x23796f VPADDD	%XMM2,%XMM26,%XMM2

(168) 0x237975 VPMOVSXDQ	%XMM2,%YMM15

(168) 0x23797a VPMULLQ	%YMM16,%YMM27,%YMM2

(168) 0x237980 VPADDQ	%YMM2,%YMM15,%YMM2

(168) 0x237984 VMOVQ	%XMM2,%RAX

(168) 0x237989 VPEXTRQ	$0x1,%XMM2,%RDX

(168) 0x23798f VEXTRACTI128	$0x1,%YMM2,%XMM2

(168) 0x237995 VMOVQ	%XMM2,%RBX

(168) 0x23799a VMOVSD	(%RDI,%RAX,8),%XMM18

(168) 0x2379a1 VPEXTRQ	$0x1,%XMM2,%R14

(168) 0x2379a7 VMOVSD	(%RDI,%RBX,8),%XMM2

(168) 0x2379ac VMOVHPD	(%RDI,%RDX,8),%XMM18,%XMM18

(168) 0x2379b3 VMOVHPD	(%RDI,%R14,8),%XMM2,%XMM2

(168) 0x2379b9 VINSERTF32X4	$0x1,%XMM2,%YMM18,%YMM2

(168) 0x2379c0 VPADDD	%XMM10,%XMM19,%XMM18

(168) 0x2379c6 VMOVDQA64	%XMM18,%XMM22

(168) 0x2379cc VCMPPD	$0x1,%YMM9,%YMM2,%K1

(168) 0x2379d3 VPBLENDMQ	%YMM23,%YMM16,%YMM21{%K1}

(168) 0x2379d9 VPADDD	-0x34ddf(%RIP){1to4},%XMM19,%XMM22{%K1}

(168) 0x2379e3 VANDPD	%YMM11,%YMM2,%YMM19

(168) 0x2379e9 VMOVDQA64	%YMM16,%YMM23{%K1}

(168) 0x2379ef VPMULLQ	%YMM6,%YMM23,%YMM23

(168) 0x2379f5 VPMULLQ	%YMM5,%YMM21,%YMM24

(168) 0x2379fb VPMULLQ	%YMM6,%YMM21,%YMM21

(168) 0x237a01 VPADDQ	%YMM15,%YMM23,%YMM23

(168) 0x237a07 VPADDQ	%YMM15,%YMM24,%YMM24

(168) 0x237a0d VPADDQ	%YMM15,%YMM21,%YMM21

(168) 0x237a13 VMOVQ	%XMM24,%RAX

(168) 0x237a19 VPEXTRQ	$0x1,%XMM24,%RDX

(168) 0x237a20 VEXTRACTI32X4	$0x1,%YMM24,%XMM24

(168) 0x237a27 VMOVQ	%XMM24,%RBX

(168) 0x237a2d VMOVSD	(%R9,%RAX,8),%XMM25

(168) 0x237a34 VPEXTRQ	$0x1,%XMM24,%R14

(168) 0x237a3b VMOVQ	%XMM21,%RAX

(168) 0x237a41 VMOVSD	(%R9,%RBX,8),%XMM24

(168) 0x237a48 VMOVHPD	(%R9,%RDX,8),%XMM25,%XMM25

(168) 0x237a4f VPEXTRQ	$0x1,%XMM21,%RDX

(168) 0x237a56 VEXTRACTI32X4	$0x1,%YMM21,%XMM21

(168) 0x237a5d VMOVHPD	(%R9,%R14,8),%XMM24,%XMM24

(168) 0x237a64 VMOVQ	%XMM21,%RBX

(168) 0x237a6a VPEXTRQ	$0x1,%XMM21,%R14

(168) 0x237a71 VPMOVSXDQ	%XMM22,%YMM22

(168) 0x237a77 VMOVSD	(%R11,%RBX,8),%XMM21

(168) 0x237a7e VMOVHPD	(%R11,%R14,8),%XMM21,%XMM21

(168) 0x237a85 VPMULLQ	%YMM22,%YMM6,%YMM22

(168) 0x237a8b VPADDQ	%YMM15,%YMM22,%YMM22

(168) 0x237a91 VINSERTF32X4	$0x1,%XMM24,%YMM25,%YMM24

(168) 0x237a98 VDIVPD	%YMM24,%YMM19,%YMM19

(168) 0x237a9e VMOVSD	(%R11,%RAX,8),%XMM24

(168) 0x237aa5 VMOVQ	%XMM22,%RAX

(168) 0x237aab VMOVHPD	(%R11,%RDX,8),%XMM24,%XMM24

(168) 0x237ab2 VPEXTRQ	$0x1,%XMM22,%RDX

(168) 0x237ab9 VEXTRACTI32X4	$0x1,%YMM22,%XMM22

(168) 0x237ac0 VMOVQ	%XMM22,%RBX

(168) 0x237ac6 VPEXTRQ	$0x1,%XMM22,%R14

(168) 0x237acd VMOVSD	(%R11,%RBX,8),%XMM22

(168) 0x237ad4 VMOVHPD	(%R11,%R14,8),%XMM22,%XMM22

(168) 0x237adb VINSERTF32X4	$0x1,%XMM21,%YMM24,%YMM21

(168) 0x237ae2 VMOVSD	(%R11,%RAX,8),%XMM24

(168) 0x237ae9 VMOVQ	%XMM23,%RAX

(168) 0x237aef VMOVHPD	(%R11,%RDX,8),%XMM24,%XMM24

(168) 0x237af6 VPEXTRQ	$0x1,%XMM23,%RDX

(168) 0x237afd VEXTRACTI32X4	$0x1,%YMM23,%XMM23

(168) 0x237b04 VMOVQ	%XMM23,%RBX

(168) 0x237b0a VPEXTRQ	$0x1,%XMM23,%R14

(168) 0x237b11 VMOVSD	(%R11,%RBX,8),%XMM23

(168) 0x237b18 VMOVHPD	(%R11,%R14,8),%XMM23,%XMM23

(168) 0x237b1f VINSERTF32X4	$0x1,%XMM22,%YMM24,%YMM22

(168) 0x237b26 VMOVSD	(%R11,%RAX,8),%XMM24

(168) 0x237b2d VMOVHPD	(%R11,%RDX,8),%XMM24,%XMM24

(168) 0x237b34 VSUBPD	%YMM22,%YMM21,%YMM22

(168) 0x237b3a VINSERTF32X4	$0x1,%XMM23,%YMM24,%YMM23

(168) 0x237b41 VSUBPD	%YMM21,%YMM23,%YMM23

(168) 0x237b47 VMULPD	%YMM22,%YMM23,%YMM3

(168) 0x237b4d VCMPPD	$0x1,%YMM3,%YMM9,%K0

(168) 0x237b54 VCMPPD	$0x1,%YMM3,%YMM9,%YMM3

(168) 0x237b59 VANDPD	%YMM3,%YMM12,%YMM3

(168) 0x237b5d KORTESTB	%K0,%K0

(168) 0x237b61 VPCMPEQQ	%YMM12,%YMM3,%K1

(168) 0x237b67 JE	237870

(168) 0x237b6d VCMPPD	$0x1,%YMM9,%YMM2,%YMM3

(168) 0x237b73 MOV	-0x48(%RBP),%RAX

(168) 0x237b77 VXORPD	%XMM4,%XMM4,%XMM4

(168) 0x237b7b KMOVQ	%K1,%K3

(168) 0x237b80 VANDPD	%YMM3,%YMM12,%YMM3

(168) 0x237b84 VPCMPEQQ	%YMM12,%YMM3,%K2

(168) 0x237b8a VXORPD	%XMM3,%XMM3,%XMM3

(168) 0x237b8e VMOVDQA32	%XMM20,%XMM18{%K2}

(168) 0x237b94 KMOVQ	%K1,%K2

(168) 0x237b99 VANDPD	%YMM11,%YMM22,%YMM20

(168) 0x237b9f VANDPD	%YMM11,%YMM23,%YMM22

(168) 0x237ba5 VGATHERQPD	(%RAX,%YMM16,8),%YMM3{%K2}

(168) 0x237bac VCMPPD	$0x1,%YMM23,%YMM9,%K2

(168) 0x237bb3 VBROADCASTSD	-0x26ab5(%RIP),%YMM23

(168) 0x237bbd VGATHERDPD	(%RAX,%XMM18,8),%YMM4{%K3}

(168) 0x237bc4 VSUBPD	%YMM19,%YMM23,%YMM23

(168) 0x237bca VMULPD	%YMM23,%YMM22,%YMM23

(168) 0x237bd0 VMINPD	%YMM22,%YMM20,%YMM22

(168) 0x237bd6 VFMADD213PD	%YMM20,%YMM19,%YMM20

(168) 0x237bdc VDIVPD	%YMM3,%YMM23,%YMM23

(168) 0x237be2 VMULPD	-0x26a04(%RIP){1to4},%YMM3,%YMM3

(168) 0x237bec VDIVPD	%YMM4,%YMM20,%YMM4

(168) 0x237bf2 VADDPD	%YMM23,%YMM4,%YMM4

(168) 0x237bf8 VMULPD	%YMM4,%YMM3,%YMM3

(168) 0x237bfc VMINPD	%YMM22,%YMM3,%YMM3

(168) 0x237c02 VXORPD	-0x26a94(%RIP){1to4},%YMM3,%YMM24

(168) 0x237c0c VMOVAPD	%YMM3,%YMM24{%K2}

(168) 0x237c12 JMP	237870

0x237c17 MOV	-0x60(%RBP),%RAX

0x237c1b CMP	%RAX,-0x30(%RBP)

0x237c1f JNE	237c42

0x237c21 MOV	-0x3c(%RBP),%ESI

0x237c24 LEA	0x231fd(%RIP),%RDI

0x237c2b VZEROUPPER

0x237c2e CALL	259690 <@plt_start@+0x540>

0x237c33 ADD	$0x68,%RSP

0x237c37 POP	%RBX

0x237c38 POP	%R12

0x237c3a POP	%R13

0x237c3c POP	%R14

0x237c3e POP	%R15

0x237c40 POP	%RBP

0x237c41 RET

0x237c42 VMOVDDUP	-0x26af2(%RIP),%XMM1

0x237c4a VMOVDDUP	-0x26afa(%RIP),%XMM2

0x237c52 VMOVSD	-0x26b52(%RIP),%XMM3

0x237c5a VMOVSD	-0x26a7a(%RIP),%XMM4

0x237c62 VMOVDDUP	-0x26af2(%RIP),%XMM5

0x237c6a VMOVSD	-0x26b22(%RIP),%XMM6

0x237c72 VPXOR	%XMM0,%XMM0,%XMM0

0x237c76 MOV	%R13D,-0x30(%RBP)

0x237c7a MOV	%R12,-0x68(%RBP)

0x237c7e JMP	237cb4

(167) 0x237c80 VSUBSD	%XMM8,%XMM6,%XMM8

(167) 0x237c85 IMUL	-0x70(%RBP),%R14

(167) 0x237c8a MOV	-0x30(%RBP),%R13D

(167) 0x237c8e MOV	-0x68(%RBP),%R12

(167) 0x237c92 LEA	0x1(%RCX),%RAX

(167) 0x237c96 VFMADD213SD	%XMM9,%XMM11,%XMM8

(167) 0x237c9b VMULSD	%XMM7,%XMM8,%XMM7

(167) 0x237c9f ADD	%RDX,%R14

(167) 0x237ca2 VMOVSD	%XMM7,(%RSI,%R14,8)

(167) 0x237ca8 CMP	%R15,%RCX

(167) 0x237cab MOV	%RAX,%RCX

(167) 0x237cae JGE	237c21

(167) 0x237cb4 MOV	%RCX,%RAX

(167) 0x237cb7 CQTO

(167) 0x237cb9 IDIV	%R12

(167) 0x237cbc MOV	-0x50(%RBP),%R12

(167) 0x237cc0 MOV	-0x80(%RBP),%R8

(167) 0x237cc4 ADD	%R13D,%EDX

(167) 0x237cc7 MOVSXD	%EDX,%RDX

(167) 0x237cca MOV	%RAX,%RBX

(167) 0x237ccd ADD	%R12D,%EAX

(167) 0x237cd0 LEA	0x1(%R12,%RBX,1),%EBX

(167) 0x237cd5 MOVSXD	%EAX,%R14

(167) 0x237cd8 IMUL	%R14,%R8

(167) 0x237cdc MOVSXD	%EBX,%R12

(167) 0x237cdf ADD	%RDX,%R8

(167) 0x237ce2 VMOVSD	(%RDI,%R8,8),%XMM7

(167) 0x237ce8 VUCOMISD	%XMM7,%XMM0

(167) 0x237cec JBE	237d00

(167) 0x237cee ADD	$0x2,%EAX

(167) 0x237cf1 MOV	%R14,%R13

(167) 0x237cf4 JMP	237d0a

0x237cf6 NOPW	%CS:(%RAX,%RAX,1)

(167) 0x237d00 DEC	%EAX

(167) 0x237d02 MOV	%R12,%R13

(167) 0x237d05 MOV	%R14,%R12

(167) 0x237d08 MOV	%EAX,%EBX

(167) 0x237d0a MOV	%R12,%R8

(167) 0x237d0d IMUL	-0x78(%RBP),%R8

(167) 0x237d12 IMUL	%R10,%R12

(167) 0x237d16 CLTQ

(167) 0x237d18 IMUL	%R10,%R13

(167) 0x237d1c VANDPD	%XMM1,%XMM7,%XMM8

(167) 0x237d20 VXORPD	%XMM11,%XMM11,%XMM11

(167) 0x237d25 IMUL	%R10,%RAX

(167) 0x237d29 ADD	%RDX,%R12

(167) 0x237d2c ADD	%RDX,%R13

(167) 0x237d2f VMOVSD	(%R11,%R12,8),%XMM9

(167) 0x237d35 VMOVSD	(%R11,%R13,8),%XMM10

(167) 0x237d3b ADD	%RDX,%RAX

(167) 0x237d3e VSUBSD	(%R11,%RAX,8),%XMM9,%XMM12

(167) 0x237d44 ADD	%RDX,%R8

(167) 0x237d47 VDIVSD	(%R9,%R8,8),%XMM8,%XMM8

(167) 0x237d4d VSUBSD	%XMM9,%XMM10,%XMM10

(167) 0x237d52 VMULSD	%XMM12,%XMM10,%XMM13

(167) 0x237d57 VUCOMISD	%XMM11,%XMM13

(167) 0x237d5c JBE	237c80

(167) 0x237d62 MOV	-0x48(%RBP),%R8

(167) 0x237d66 VSUBSD	%XMM8,%XMM3,%XMM14

(167) 0x237d6b VANDPD	%XMM2,%XMM10,%XMM13

(167) 0x237d6f VANDPD	%XMM2,%XMM12,%XMM12

(167) 0x237d73 MOVSXD	%EBX,%RAX

(167) 0x237d76 VCMPSD	$0x1,%XMM10,%XMM0,%K1

(167) 0x237d7d VMULSD	%XMM14,%XMM13,%XMM14

(167) 0x237d82 VMINSD	%XMM13,%XMM12,%XMM13

(167) 0x237d87 VFMADD213SD	%XMM12,%XMM8,%XMM12

(167) 0x237d8c VMOVSD	(%R8,%R14,8),%XMM11

(167) 0x237d92 VDIVSD	(%R8,%RAX,8),%XMM12,%XMM12

(167) 0x237d98 VDIVSD	%XMM11,%XMM14,%XMM14

(167) 0x237d9d VMULSD	%XMM4,%XMM11,%XMM11

(167) 0x237da1 VADDSD	%XMM14,%XMM12,%XMM12

(167) 0x237da6 VMULSD	%XMM12,%XMM11,%XMM11

(167) 0x237dab VMINSD	%XMM13,%XMM11,%XMM12

(167) 0x237db0 VXORPD	%XMM5,%XMM12,%XMM11

(167) 0x237db4 VMOVSD	%XMM12,%XMM11,%XMM11{%K1}

(167) 0x237dba JMP	237c80

0x237dbf NOP

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run aocc_8

Source file and lines	advec_mom.cpp:180-211
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:180-211

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 16.13 to 5.13 cycles (3.15x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions).

Details

10% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

5% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
14% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
21% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:180
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:180

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVL: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:181
VPBROADCASTD: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:181
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:181
VPBROADCASTQ: 6 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:181
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:181
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:181
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:181
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:181
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:181

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 288 bytes. The binary function is storing 108 bytes.

General properties

nb instructions	121
nb uops	129
loop length	516
used x86 registers	16
used mmx registers	0
used xmm registers	12
used ymm registers	10
used zmm registers	0
nb stack references	18

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	16.13 cycles
front end	16.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	6.50	6.50	6.50	6.50	6.50	6.50	13.25	13.25	13.25	13.25	2.50	5.00	5.00	2.50	0.00	0.00
cycles	6.50	6.50	6.50	6.50	6.50	6.50	13.25	13.25	13.25	13.25	2.50	5.00	5.00	2.50	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	16.13
Dispatch	13.25
Overall L1	16.13

Vectorization ratios

INT

all	10%
load	10%
store	0%
mul	0%
add-sub	14%
fma	NA (no fma vectorizable/vectorized instructions)
other	21%

all	10%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	10%
load	5%
store	0%
mul	0%
add-sub	14%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	21%

Vector efficiency ratios

INT

all	12%
load	14%
store	10%
mul	12%
add-sub	13%
fma	NA (no fma vectorizable/vectorized instructions)
other	14%

all	13%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

INT+FP

all	12%
load	13%
store	10%
mul	12%
add-sub	13%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 16.13 cycles. At this rate:

6% of peak load performance is reached (17.86 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (6.70 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 16.13 to 13.25 cycles (1.22x speedup).

ASM code

In the binary file, the address of the function is: 2376e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x68,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RCX),%R15D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
MOV (%RDX),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
ADD $0x3,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %RAX,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
SUB %EAX,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 237c33 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.20+0x553>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV (%R9),%R12D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
MOV (%R8),%R13D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
INC %R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD $0x3,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CMP %R13D,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 237c33 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.20+0x553>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
SUB %R13D,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVQ $0,-0x58(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOVQ $0x1,-0x88(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOVL $0,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
IMUL %R12,%R15	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
DEC %R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R15,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x40(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x88(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x236b3(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x58(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x38(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %ESI,-0x3c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 259680 <@plt_start@+0x530>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x38(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x58(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
CMP %R15,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMOVL %RAX,%R15	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
MOV %R15,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
CMP %R15,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JG 237c21 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.20+0x541>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x20(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x28(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x18(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x10(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x30(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x8(%RSI),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV (%RDI),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV (%R8),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%R8),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x10(%RDI),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV (%RDX),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%RDX),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV (%RAX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %R15,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RCX,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
INC %R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSI,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x10(%RAX),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RBX,-0x80(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R14,-0x78(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDX,-0x70(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
CMP $0x4,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JB 237c42 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.20+0x562>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VBROADCASTSD -0x266a7(%RIP),%YMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
VPBROADCASTQ %RCX,%YMM0	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPADDQ -0x26525(%RIP),%YMM0,%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	1	0.50	vect (50.0%)
VBROADCASTSD -0x266b6(%RIP),%YMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
VBROADCASTSD -0x266b7(%RIP),%YMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
VPBROADCASTQ -0x26650(%RIP),%YMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	1	0.50	scal (12.5%)
MOV -0x50(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %R8,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
AND $-0x4,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VPBROADCASTQ %R12,%YMM1	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPBROADCASTD %R13D,%XMM26	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (6.3%)
VPBROADCASTQ %RBX,%YMM27	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPBROADCASTQ %R14,%YMM5	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPBROADCASTQ %R10,%YMM6	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPBROADCASTQ %RDX,%YMM7	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VXORPD %XMM9,%XMM9,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VPCMPEQD %XMM10,%XMM10,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (25.0%)
ADD %R8,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VEXTRACTI128 $0x1,%YMM1,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	3	0.50	vect (25.0%)
MOV %R8,-0x60(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
VPBROADCASTD %EAX,%XMM17	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (6.3%)
JMP 2378d5 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.20+0x1f5>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0x60(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
CMP %RAX,-0x30(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JNE 237c42 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.20+0x562>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x3c(%RBP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
LEA 0x231fd(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 259690 <@plt_start@+0x540>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
ADD $0x68,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50	N/A
VMOVDDUP -0x26af2(%RIP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVDDUP -0x26afa(%RIP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVSD -0x26b52(%RIP),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD -0x26a7a(%RIP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VMOVDDUP -0x26af2(%RIP),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVSD -0x26b22(%RIP),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VPXOR %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
MOV %R13D,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOV %R12,-0x68(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
JMP 237cb4 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.20+0x5d4>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run aocc_8

Source file and lines	advec_mom.cpp:180-211
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:180-211

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 16.13 to 5.13 cycles (3.15x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions).

Details

10% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

5% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
14% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
21% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:180
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:180

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVL: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:181
VPBROADCASTD: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:181
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:181
VPBROADCASTQ: 6 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:181
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:181
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:181
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:181
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:181
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:181

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 288 bytes. The binary function is storing 108 bytes.

General properties

nb instructions	121
nb uops	129
loop length	516
used x86 registers	16
used mmx registers	0
used xmm registers	12
used ymm registers	10
used zmm registers	0
nb stack references	18

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	16.13 cycles
front end	16.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	6.50	6.50	6.50	6.50	6.50	6.50	13.25	13.25	13.25	13.25	2.50	5.00	5.00	2.50	0.00	0.00
cycles	6.50	6.50	6.50	6.50	6.50	6.50	13.25	13.25	13.25	13.25	2.50	5.00	5.00	2.50	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	16.13
Dispatch	13.25
Overall L1	16.13

Vectorization ratios

INT

all	10%
load	10%
store	0%
mul	0%
add-sub	14%
fma	NA (no fma vectorizable/vectorized instructions)
other	21%

all	10%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	10%
load	5%
store	0%
mul	0%
add-sub	14%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	21%

Vector efficiency ratios

INT

all	12%
load	14%
store	10%
mul	12%
add-sub	13%
fma	NA (no fma vectorizable/vectorized instructions)
other	14%

all	13%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

INT+FP

all	12%
load	13%
store	10%
mul	12%
add-sub	13%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 16.13 cycles. At this rate:

6% of peak load performance is reached (17.86 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (6.70 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 2376e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x68,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RCX),%R15D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
MOV (%RDX),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
ADD $0x3,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %RAX,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
SUB %EAX,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 237c33 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.20+0x553>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV (%R9),%R12D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
MOV (%R8),%R13D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
INC %R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD $0x3,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CMP %R13D,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 237c33 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.20+0x553>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
SUB %R13D,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVQ $0,-0x58(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOVQ $0x1,-0x88(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOVL $0,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
IMUL %R12,%R15	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
DEC %R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R15,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x40(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x88(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x236b3(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x58(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x38(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %ESI,-0x3c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 259680 <@plt_start@+0x530>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x38(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x58(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
CMP %R15,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMOVL %RAX,%R15	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
MOV %R15,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
CMP %R15,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JG 237c21 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.20+0x541>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x20(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x28(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x18(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x10(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x30(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x8(%RSI),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV (%RDI),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV (%R8),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%R8),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x10(%RDI),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV (%RDX),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%RDX),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV (%RAX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %R15,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RCX,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
INC %R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSI,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x10(%RAX),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RBX,-0x80(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R14,-0x78(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDX,-0x70(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
CMP $0x4,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JB 237c42 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.20+0x562>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VBROADCASTSD -0x266a7(%RIP),%YMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
VPBROADCASTQ %RCX,%YMM0	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPADDQ -0x26525(%RIP),%YMM0,%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	1	0.50	vect (50.0%)
VBROADCASTSD -0x266b6(%RIP),%YMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
VBROADCASTSD -0x266b7(%RIP),%YMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
VPBROADCASTQ -0x26650(%RIP),%YMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	1	0.50	scal (12.5%)
MOV -0x50(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %R8,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
AND $-0x4,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VPBROADCASTQ %R12,%YMM1	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPBROADCASTD %R13D,%XMM26	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (6.3%)
VPBROADCASTQ %RBX,%YMM27	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPBROADCASTQ %R14,%YMM5	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPBROADCASTQ %R10,%YMM6	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPBROADCASTQ %RDX,%YMM7	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VXORPD %XMM9,%XMM9,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VPCMPEQD %XMM10,%XMM10,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (25.0%)
ADD %R8,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VEXTRACTI128 $0x1,%YMM1,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	3	0.50	vect (25.0%)
MOV %R8,-0x60(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
VPBROADCASTD %EAX,%XMM17	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (6.3%)
JMP 2378d5 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.20+0x1f5>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0x60(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
CMP %RAX,-0x30(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JNE 237c42 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.20+0x562>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x3c(%RBP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
LEA 0x231fd(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 259690 <@plt_start@+0x540>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
ADD $0x68,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50	N/A
VMOVDDUP -0x26af2(%RIP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVDDUP -0x26afa(%RIP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVSD -0x26b52(%RIP),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD -0x26a7a(%RIP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VMOVDDUP -0x26af2(%RIP),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVSD -0x26b22(%RIP),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VPXOR %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
MOV %R13D,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOV %R12,-0x68(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
JMP 237cb4 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.20+0x5d4>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	4.37	1.63
○Loop 168 - advec_mom.cpp:181-211 - exec	4.37	1.63
○Loop 167 - advec_mom.cpp:181-211 - exec	0.00	0.00

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512-bits vectorization

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Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

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Cycles summary

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Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code