OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone .omp

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: advec_mom.cpp:167-172 [...]	Coverage (incl. loops): 3.10% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 167 - 172

--------------------------------------------------------------------------------

167: #pragma omp parallel for simd collapse(2)

168:       for (int j = (y_min - 1 + 1); j < (y_max + 2 + 2); j++) {

169:         for (int i = (x_min + 1); i < (x_max + 1 + 2); i++) {

170:           node_mass_post(i, j) = 0.25 * (density1(i + 0, j - 1) * post_vol(i + 0, j - 1) + density1(i, j) * post_vol(i, j) +

171:                                          density1(i - 1, j - 1) * post_vol(i - 1, j - 1) + density1(i - 1, j + 0) * post_vol(i - 1, j + 0));

172:           node_mass_pre(i, j) = node_mass_post(i, j) - node_flux(i + 0, j - 1) + node_flux(i, j);

0x236f20 PUSH	%RBP

0x236f21 MOV	%RSP,%RBP

0x236f24 PUSH	%R15

0x236f26 PUSH	%R14

0x236f28 PUSH	%R13

0x236f2a PUSH	%R12

0x236f2c PUSH	%RBX

0x236f2d SUB	$0x88,%RSP

0x236f34 MOV	(%RCX),%R15D

0x236f37 MOV	(%RDX),%EBX

0x236f39 ADD	$0x4,%R15D

0x236f3d SUB	%EBX,%R15D

0x236f40 JLE	2376c7

0x236f46 MOV	(%R9),%R13D

0x236f49 MOV	(%R8),%R14D

0x236f4c LEA	0x1(%R14),%R12D

0x236f50 ADD	$0x3,%R13D

0x236f54 CMP	%R12D,%R13D

0x236f57 JLE	2376c7

0x236f5d SUB	%R12D,%R13D

0x236f60 MOV	(%RDI),%ESI

0x236f62 MOVQ	$0,-0x68(%RBP)

0x236f6a MOVQ	$0x1,-0xb0(%RBP)

0x236f75 MOVL	$0,-0x50(%RBP)

0x236f7c IMUL	%R13,%R15

0x236f80 DEC	%R15

0x236f83 MOV	%R15,-0x48(%RBP)

0x236f87 SUB	$0x8,%RSP

0x236f8b LEA	-0x50(%RBP),%RCX

0x236f8f LEA	-0xb0(%RBP),%RAX

0x236f96 LEA	0x23e2b(%RIP),%RDI

0x236f9d LEA	-0x68(%RBP),%R8

0x236fa1 LEA	-0x48(%RBP),%R9

0x236fa5 MOV	%ESI,-0x4c(%RBP)

0x236fa8 MOV	$0x22,%EDX

0x236fad PUSH	$0x1

0x236faf PUSH	$0x1

0x236fb1 PUSH	%RAX

0x236fb2 CALL	259680 <@plt_start@+0x530>

0x236fb7 ADD	$0x20,%RSP

0x236fbb MOV	-0x48(%RBP),%RAX

0x236fbf MOV	-0x68(%RBP),%RCX

0x236fc3 CMP	%R15,%RAX

0x236fc6 CMOVL	%RAX,%R15

0x236fca MOV	%R15,-0x48(%RBP)

0x236fce CMP	%R15,%RCX

0x236fd1 JG	2376b5

0x236fd7 MOV	0x20(%RBP),%RSI

0x236fdb MOV	0x18(%RBP),%RDI

0x236fdf MOV	0x30(%RBP),%RAX

0x236fe3 MOV	0x28(%RBP),%RDX

0x236fe7 MOV	0x10(%RBP),%R9

0x236feb MOV	%R14,%R11

0x236fee MOV	%R13,-0x60(%RBP)

0x236ff2 MOV	%R12,-0x30(%RBP)

0x236ff6 MOV	%R11,-0x88(%RBP)

0x236ffd MOV	(%RDI),%R14

0x237000 MOV	0x10(%RDI),%R8

0x237004 MOV	(%RSI),%R12

0x237007 MOV	0x10(%RSI),%R10

0x23700b MOV	(%R9),%RSI

0x23700e MOV	0x10(%R9),%RDI

0x237012 MOV	(%RAX),%R9

0x237015 MOV	0x10(%RAX),%R13

0x237019 MOV	(%RDX),%RAX

0x23701c MOV	%RAX,-0x58(%RBP)

0x237020 MOV	0x10(%RDX),%RAX

0x237024 MOV	%R14,-0xa8(%RBP)

0x23702b MOV	%R12,-0xa0(%RBP)

0x237032 MOV	%RSI,-0x98(%RBP)

0x237039 MOV	%R9,-0x90(%RBP)

0x237040 MOV	%RAX,-0x40(%RBP)

0x237044 MOV	%R15,%RAX

0x237047 SUB	%RCX,%RAX

0x23704a INC	%RAX

0x23704d CMP	$0x4,%RAX

0x237051 JAE	23705f

0x237053 MOV	-0x30(%RBP),%R11

0x237057 MOV	%RDI,%R14

0x23705a JMP	23759b

0x23705f MOV	%RAX,%RDX

0x237062 MOV	%RAX,-0x38(%RBP)

0x237066 MOV	-0x60(%RBP),%RAX

0x23706a VBROADCASTSD	-0x25ee3(%RIP),%YMM12

0x237073 VPBROADCASTQ	%RCX,%YMM0

0x237079 VPADDQ	-0x25da1(%RIP),%YMM0,%YMM0

0x237081 VPBROADCASTQ	-0x25eba(%RIP),%YMM13

0x23708a VPBROADCASTQ	%RSI,%YMM7

0x237090 MOV	-0x58(%RBP),%RSI

0x237094 AND	$-0x4,%RDX

0x237098 VPBROADCASTQ	%R14,%YMM4

0x23709e VPBROADCASTQ	%R9,%YMM8

0x2370a4 VPBROADCASTD	%EBX,%XMM2

0x2370aa VPBROADCASTQ	%R12,%YMM5

0x2370b0 VPBROADCASTD	%R11D,%XMM6

0x2370b6 VPCMPEQD	%XMM11,%XMM11,%XMM11

0x2370bb MOV	%RDI,%R14

0x2370be ADD	%RDX,%RCX

0x2370c1 MOV	%RDX,-0x70(%RBP)

0x2370c5 MOV	%RDX,%R9

0x2370c8 VPBROADCASTQ	%RAX,%YMM1

0x2370ce MOV	-0x30(%RBP),%RAX

0x2370d2 VPBROADCASTQ	%RSI,%YMM9

0x2370d8 VEXTRACTI128	$0x1,%YMM1,%XMM10

0x2370de VPBROADCASTD	%EAX,%XMM3

0x2370e4 NOPW	%CS:(%RAX,%RAX,1)

(165) 0x2370f0 VEXTRACTI128	$0x1,%YMM0,%XMM14

(165) 0x2370f6 VPEXTRQ	$0x1,%XMM10,%RSI

(165) 0x2370fc VMOVQ	%XMM1,%R12

(165) 0x237101 MOV	%R14,%RDI

(165) 0x237104 VPEXTRQ	$0x1,%XMM14,%RAX

(165) 0x23710a CQTO

(165) 0x23710c IDIV	%RSI

(165) 0x23710f VMOVQ	%XMM14,%RDX

(165) 0x237114 VMOVQ	%XMM10,%RSI

(165) 0x237119 VMOVQ	%RAX,%XMM14

(165) 0x23711e MOV	%RDX,%RAX

(165) 0x237121 CQTO

(165) 0x237123 IDIV	%RSI

(165) 0x237126 VPEXTRQ	$0x1,%XMM1,%RSI

(165) 0x23712c VMOVQ	%RAX,%XMM15

(165) 0x237131 VPEXTRQ	$0x1,%XMM0,%RAX

(165) 0x237137 CQTO

(165) 0x237139 VPUNPCKLQDQ	%XMM14,%XMM15,%XMM14

(165) 0x23713e IDIV	%RSI

(165) 0x237141 MOV	%RAX,%RSI

(165) 0x237144 VMOVQ	%XMM0,%RAX

(165) 0x237149 VMOVQ	%RSI,%XMM15

(165) 0x23714e CQTO

(165) 0x237150 IDIV	%R12

(165) 0x237153 ADD	$-0x4,%R9

(165) 0x237157 VMOVQ	%RAX,%XMM16

(165) 0x23715d VPUNPCKLQDQ	%XMM15,%XMM16,%XMM15

(165) 0x237163 VINSERTI128	$0x1,%XMM14,%YMM15,%YMM14

(165) 0x237169 VPMOVQD	%YMM14,%XMM15

(165) 0x23716f VPMULLQ	%YMM1,%YMM14,%YMM14

(165) 0x237175 VPSUBQ	%YMM14,%YMM0,%YMM14

(165) 0x23717a VPADDQ	%YMM0,%YMM13,%YMM0

(165) 0x23717e VPADDD	%XMM15,%XMM2,%XMM16

(165) 0x237184 VPMOVQD	%YMM14,%XMM17

(165) 0x23718a VPADDD	%XMM11,%XMM16,%XMM15

(165) 0x237190 VPMOVSXDQ	%XMM16,%YMM16

(165) 0x237196 VPMOVSXDQ	%XMM15,%YMM15

(165) 0x23719b VPMULLQ	%YMM16,%YMM4,%YMM24

(165) 0x2371a1 VPMULLQ	%YMM16,%YMM5,%YMM30

(165) 0x2371a7 VPADDD	%XMM17,%XMM3,%XMM14

(165) 0x2371ad VPMULLQ	%YMM15,%YMM4,%YMM18

(165) 0x2371b3 VPMULLQ	%YMM15,%YMM5,%YMM21

(165) 0x2371b9 VPADDD	%XMM17,%XMM6,%XMM17

(165) 0x2371bf VPMULLQ	%YMM15,%YMM8,%YMM15

(165) 0x2371c5 VPMOVSXDQ	%XMM14,%YMM14

(165) 0x2371ca VPMOVSXDQ	%XMM17,%YMM17

(165) 0x2371d0 VPADDQ	%YMM14,%YMM18,%YMM19

(165) 0x2371d6 VPADDQ	%YMM14,%YMM21,%YMM22

(165) 0x2371dc VPADDQ	%YMM14,%YMM24,%YMM25

(165) 0x2371e2 VPADDQ	%YMM14,%YMM30,%YMM28

(165) 0x2371e8 VPADDQ	%YMM17,%YMM18,%YMM18

(165) 0x2371ee VPADDQ	%YMM17,%YMM21,%YMM21

(165) 0x2371f4 VPADDQ	%YMM17,%YMM24,%YMM24

(165) 0x2371fa VPADDQ	%YMM17,%YMM30,%YMM17

(165) 0x237200 VPADDQ	%YMM14,%YMM15,%YMM15

(165) 0x237205 VMOVQ	%XMM19,%RDX

(165) 0x23720b VPEXTRQ	$0x1,%XMM19,%RSI

(165) 0x237212 VEXTRACTI32X4	$0x1,%YMM19,%XMM19

(165) 0x237219 VEXTRACTI32X4	$0x1,%YMM25,%XMM26

(165) 0x237220 VMOVSD	(%R8,%RDX,8),%XMM20

(165) 0x237227 VMOVQ	%XMM19,%R12

(165) 0x23722d VMOVQ	%XMM22,%RDX

(165) 0x237233 VPEXTRQ	$0x1,%XMM19,%RAX

(165) 0x23723a VMOVHPD	(%R8,%RSI,8),%XMM20,%XMM20

(165) 0x237241 VPEXTRQ	$0x1,%XMM22,%RSI

(165) 0x237248 VEXTRACTI32X4	$0x1,%YMM22,%XMM22

(165) 0x23724f VMOVSD	(%R8,%R12,8),%XMM19

(165) 0x237256 VMOVQ	%XMM22,%R12

(165) 0x23725c VMOVHPD	(%R8,%RAX,8),%XMM19,%XMM19

(165) 0x237263 VMOVQ	%XMM28,%RAX

(165) 0x237269 VMOVSD	(%R10,%R12,8),%XMM23

(165) 0x237270 VPEXTRQ	$0x1,%XMM22,%R12

(165) 0x237277 VMOVSD	(%R10,%RDX,8),%XMM22

(165) 0x23727e VPEXTRQ	$0x1,%XMM25,%RDX

(165) 0x237285 VMOVHPD	(%R10,%RSI,8),%XMM22,%XMM22

(165) 0x23728c VMOVQ	%XMM26,%RSI

(165) 0x237292 VMOVHPD	(%R10,%R12,8),%XMM23,%XMM23

(165) 0x237299 VMOVSD	(%R8,%RSI,8),%XMM27

(165) 0x2372a0 VMOVQ	%XMM25,%RSI

(165) 0x2372a6 VMOVSD	(%R8,%RSI,8),%XMM25

(165) 0x2372ad VPEXTRQ	$0x1,%XMM26,%RSI

(165) 0x2372b4 VMOVHPD	(%R8,%RDX,8),%XMM25,%XMM25

(165) 0x2372bb VMOVHPD	(%R8,%RSI,8),%XMM27,%XMM27

(165) 0x2372c2 VPEXTRQ	$0x1,%XMM28,%RDX

(165) 0x2372c9 VEXTRACTI32X4	$0x1,%YMM28,%XMM28

(165) 0x2372d0 VMOVQ	%XMM28,%R12

(165) 0x2372d6 VMOVSD	(%R10,%R12,8),%XMM29

(165) 0x2372dd VPEXTRQ	$0x1,%XMM28,%R12

(165) 0x2372e4 VMOVSD	(%R10,%RAX,8),%XMM28

(165) 0x2372eb VMOVQ	%XMM18,%RAX

(165) 0x2372f1 VMOVHPD	(%R10,%RDX,8),%XMM28,%XMM28

(165) 0x2372f8 VPEXTRQ	$0x1,%XMM18,%RDX

(165) 0x2372ff VEXTRACTI32X4	$0x1,%YMM18,%XMM18

(165) 0x237306 VMOVHPD	(%R10,%R12,8),%XMM29,%XMM29

(165) 0x23730d VINSERTF32X4	$0x1,%XMM19,%YMM20,%YMM19

(165) 0x237314 VMOVSD	(%R8,%RAX,8),%XMM20

(165) 0x23731b VMOVQ	%XMM21,%RAX

(165) 0x237321 VMOVQ	%XMM18,%RSI

(165) 0x237327 VPEXTRQ	$0x1,%XMM18,%R12

(165) 0x23732e VMOVHPD	(%R8,%RDX,8),%XMM20,%XMM20

(165) 0x237335 VPEXTRQ	$0x1,%XMM21,%RDX

(165) 0x23733c VEXTRACTI32X4	$0x1,%YMM21,%XMM21

(165) 0x237343 VMOVSD	(%R8,%RSI,8),%XMM18

(165) 0x23734a VMOVQ	%XMM21,%RSI

(165) 0x237350 VINSERTF32X4	$0x1,%XMM23,%YMM22,%YMM22

(165) 0x237357 VMOVHPD	(%R8,%R12,8),%XMM18,%XMM18

(165) 0x23735e VPEXTRQ	$0x1,%XMM21,%R12

(165) 0x237365 VMOVSD	(%R10,%RSI,8),%XMM21

(165) 0x23736c VMOVHPD	(%R10,%R12,8),%XMM21,%XMM21

(165) 0x237373 VMULPD	%YMM19,%YMM22,%YMM19

(165) 0x237379 VINSERTF32X4	$0x1,%XMM27,%YMM25,%YMM23

(165) 0x237380 VMOVSD	(%R10,%RAX,8),%XMM27

(165) 0x237387 VMOVQ	%XMM24,%RAX

(165) 0x23738d VMOVHPD	(%R10,%RDX,8),%XMM27,%XMM27

(165) 0x237394 VPEXTRQ	$0x1,%XMM24,%RDX

(165) 0x23739b VINSERTF32X4	$0x1,%XMM29,%YMM28,%YMM25

(165) 0x2373a2 VFMADD213PD	%YMM19,%YMM23,%YMM25

(165) 0x2373a8 VPMULLQ	%YMM16,%YMM8,%YMM19

(165) 0x2373ae VINSERTF32X4	$0x1,%XMM18,%YMM20,%YMM18

(165) 0x2373b5 VEXTRACTI32X4	$0x1,%YMM24,%XMM20

(165) 0x2373bc VMOVSD	(%R8,%RAX,8),%XMM24

(165) 0x2373c3 VMOVQ	%XMM17,%RAX

(165) 0x2373c9 VMOVQ	%XMM20,%R12

(165) 0x2373cf VPEXTRQ	$0x1,%XMM20,%RSI

(165) 0x2373d6 VMOVHPD	(%R8,%RDX,8),%XMM24,%XMM24

(165) 0x2373dd VPEXTRQ	$0x1,%XMM17,%RDX

(165) 0x2373e4 VEXTRACTI32X4	$0x1,%YMM17,%XMM17

(165) 0x2373eb VMOVSD	(%R8,%R12,8),%XMM20

(165) 0x2373f2 VPEXTRQ	$0x1,%XMM17,%R12

(165) 0x2373f9 VPADDQ	%YMM14,%YMM19,%YMM19

(165) 0x2373ff VINSERTF32X4	$0x1,%XMM21,%YMM27,%YMM21

(165) 0x237406 VMOVHPD	(%R8,%RSI,8),%XMM20,%XMM20

(165) 0x23740d VMOVQ	%XMM17,%RSI

(165) 0x237413 VMOVSD	(%R10,%RSI,8),%XMM17

(165) 0x23741a VFMADD213PD	%YMM25,%YMM18,%YMM21

(165) 0x237420 VMOVSD	(%R10,%RAX,8),%XMM18

(165) 0x237427 VMOVHPD	(%R10,%R12,8),%XMM17,%XMM17

(165) 0x23742e VMOVHPD	(%R10,%RDX,8),%XMM18,%XMM18

(165) 0x237435 VINSERTF32X4	$0x1,%XMM20,%YMM24,%YMM20

(165) 0x23743c VINSERTF32X4	$0x1,%XMM17,%YMM18,%YMM17

(165) 0x237443 VPMULLQ	%YMM16,%YMM7,%YMM18

(165) 0x237449 VPMULLQ	%YMM16,%YMM9,%YMM16

(165) 0x23744f VFMADD213PD	%YMM21,%YMM20,%YMM17

(165) 0x237455 VPADDQ	%YMM14,%YMM18,%YMM18

(165) 0x23745b VPADDQ	%YMM14,%YMM16,%YMM14

(165) 0x237461 VMOVQ	%XMM18,%RAX

(165) 0x237467 VPEXTRQ	$0x1,%XMM18,%RDX

(165) 0x23746e VEXTRACTI32X4	$0x1,%YMM18,%XMM18

(165) 0x237475 VMOVQ	%XMM18,%RSI

(165) 0x23747b VPEXTRQ	$0x1,%XMM18,%R12

(165) 0x237482 VMULPD	%YMM12,%YMM17,%YMM17

(165) 0x237488 VEXTRACTF32X4	$0x1,%YMM17,%XMM18

(165) 0x23748f VMOVLPD	%XMM17,(%R14,%RAX,8)

(165) 0x237496 VMOVHPD	%XMM17,(%R14,%RDX,8)

(165) 0x23749d VPEXTRQ	$0x1,%XMM15,%RAX

(165) 0x2374a3 VMOVQ	%XMM15,%RDX

(165) 0x2374a8 VEXTRACTI128	$0x1,%YMM15,%XMM15

(165) 0x2374ae VMOVLPD	%XMM18,(%R14,%RSI,8)

(165) 0x2374b5 VMOVHPD	%XMM18,(%R14,%R12,8)

(165) 0x2374bc VMOVQ	%XMM15,%RSI

(165) 0x2374c1 VPEXTRQ	$0x1,%XMM15,%R12

(165) 0x2374c7 MOV	-0x40(%RBP),%R14

(165) 0x2374cb VMOVSD	(%R13,%RDX,8),%XMM18

(165) 0x2374d3 VMOVSD	(%R13,%RSI,8),%XMM15

(165) 0x2374da VMOVQ	%XMM19,%RDX

(165) 0x2374e0 VMOVHPD	(%R13,%RAX,8),%XMM18,%XMM18

(165) 0x2374e8 VMOVHPD	(%R13,%R12,8),%XMM15,%XMM15

(165) 0x2374ef VPEXTRQ	$0x1,%XMM19,%RAX

(165) 0x2374f6 VEXTRACTI32X4	$0x1,%YMM19,%XMM19

(165) 0x2374fd VMOVQ	%XMM19,%R12

(165) 0x237503 VPEXTRQ	$0x1,%XMM19,%RSI

(165) 0x23750a VMOVSD	(%R13,%RDX,8),%XMM19

(165) 0x237512 VMOVQ	%XMM14,%RDX

(165) 0x237517 VMOVHPD	(%R13,%RAX,8),%XMM19,%XMM19

(165) 0x23751f VPEXTRQ	$0x1,%XMM14,%RAX

(165) 0x237525 VEXTRACTI128	$0x1,%YMM14,%XMM14

(165) 0x23752b VINSERTF32X4	$0x1,%XMM15,%YMM18,%YMM15

(165) 0x237532 VMOVSD	(%R13,%R12,8),%XMM18

(165) 0x23753a VPEXTRQ	$0x1,%XMM14,%R12

(165) 0x237540 VMOVHPD	(%R13,%RSI,8),%XMM18,%XMM18

(165) 0x237548 VMOVQ	%XMM14,%RSI

(165) 0x23754d VSUBPD	%YMM15,%YMM17,%YMM15

(165) 0x237553 VINSERTF32X4	$0x1,%XMM18,%YMM19,%YMM17

(165) 0x23755a VADDPD	%YMM17,%YMM15,%YMM15

(165) 0x237560 VMOVLPD	%XMM15,(%R14,%RDX,8)

(165) 0x237566 MOV	%RDI,%R14

(165) 0x237569 MOV	-0x40(%RBP),%RDI

(165) 0x23756d VEXTRACTF128	$0x1,%YMM15,%XMM14

(165) 0x237573 VMOVHPD	%XMM15,(%RDI,%RAX,8)

(165) 0x237578 VMOVLPD	%XMM14,(%RDI,%RSI,8)

(165) 0x23757d VMOVHPD	%XMM14,(%RDI,%R12,8)

(165) 0x237583 JNE	2370f0

0x237589 MOV	-0x70(%RBP),%RAX

0x23758d MOV	-0x30(%RBP),%R11

0x237591 CMP	%RAX,-0x38(%RBP)

0x237595 JE	2376b5

0x23759b VMOVSD	-0x26413(%RIP),%XMM0

0x2375a3 MOV	%RBX,-0x80(%RBP)

0x2375a7 MOV	%R14,-0x78(%RBP)

0x2375ab NOPL	(%RAX,%RAX,1)

(166) 0x2375b0 MOV	%RCX,%RAX

(166) 0x2375b3 CQTO

(166) 0x2375b5 IDIVQ	-0x60(%RBP)

(166) 0x2375b9 MOV	-0xa0(%RBP),%R12

(166) 0x2375c0 MOV	-0xa8(%RBP),%RDI

(166) 0x2375c7 MOV	%RDI,%R14

(166) 0x2375ca LEA	(%RBX,%RAX,1),%ESI

(166) 0x2375cd LEA	-0x1(%RBX,%RAX,1),%EAX

(166) 0x2375d1 MOV	%R12,%RBX

(166) 0x2375d4 MOV	%ESI,-0x38(%RBP)

(166) 0x2375d7 LEA	(%R11,%RDX,1),%ESI

(166) 0x2375db ADD	-0x88(%RBP),%EDX

(166) 0x2375e1 MOVSXD	%EAX,%R9

(166) 0x2375e4 MOVSXD	%ESI,%RSI

(166) 0x2375e7 IMUL	%R9,%RBX

(166) 0x2375eb IMUL	%R9,%R14

(166) 0x2375ef LEA	(%RBX,%RSI,1),%R11

(166) 0x2375f3 LEA	(%R14,%RSI,1),%RAX

(166) 0x2375f7 MOVSXD	%EDX,%RDX

(166) 0x2375fa VMOVSD	(%R10,%R11,8),%XMM1

(166) 0x237600 MOV	%RDI,%R11

(166) 0x237603 ADD	%RDX,%RBX

(166) 0x237606 ADD	%RDX,%R14

(166) 0x237609 VMULSD	(%R8,%RAX,8),%XMM1,%XMM1

(166) 0x23760f MOVSXD	-0x38(%RBP),%RAX

(166) 0x237613 IMUL	%RAX,%R12

(166) 0x237617 IMUL	%RAX,%R11

(166) 0x23761b LEA	(%R12,%RSI,1),%RDI

(166) 0x23761f ADD	%RDX,%R12

(166) 0x237622 VMOVSD	(%R10,%RDI,8),%XMM2

(166) 0x237628 LEA	(%R11,%RSI,1),%RDI

(166) 0x23762c ADD	%RDX,%R11

(166) 0x23762f MOV	-0x98(%RBP),%RDX

(166) 0x237636 VFMADD132SD	(%R8,%RDI,8),%XMM1,%XMM2

(166) 0x23763c VMOVSD	(%R10,%RBX,8),%XMM1

(166) 0x237642 MOV	-0x90(%RBP),%RDI

(166) 0x237649 MOV	-0x80(%RBP),%RBX

(166) 0x23764d VFMADD132SD	(%R8,%R14,8),%XMM2,%XMM1

(166) 0x237653 VMOVSD	(%R10,%R12,8),%XMM2

(166) 0x237659 MOV	-0x78(%RBP),%R14

(166) 0x23765d IMUL	%RAX,%RDX

(166) 0x237661 IMUL	%RDI,%R9

(166) 0x237665 ADD	%RSI,%RDX

(166) 0x237668 VFMADD132SD	(%R8,%R11,8),%XMM1,%XMM2

(166) 0x23766e ADD	%RSI,%R9

(166) 0x237671 MOV	-0x30(%RBP),%R11

(166) 0x237675 VMULSD	%XMM0,%XMM2,%XMM1

(166) 0x237679 VMOVSD	%XMM1,(%R14,%RDX,8)

(166) 0x23767f MOV	%RDI,%RDX

(166) 0x237682 IMUL	%RAX,%RDX

(166) 0x237686 IMUL	-0x58(%RBP),%RAX

(166) 0x23768b VSUBSD	(%R13,%R9,8),%XMM1,%XMM1

(166) 0x237692 ADD	%RSI,%RDX

(166) 0x237695 VADDSD	(%R13,%RDX,8),%XMM1,%XMM1

(166) 0x23769c MOV	-0x40(%RBP),%RDX

(166) 0x2376a0 ADD	%RSI,%RAX

(166) 0x2376a3 VMOVSD	%XMM1,(%RDX,%RAX,8)

(166) 0x2376a8 CMP	%R15,%RCX

(166) 0x2376ab LEA	0x1(%RCX),%RCX

(166) 0x2376af JL	2375b0

0x2376b5 MOV	-0x4c(%RBP),%ESI

0x2376b8 LEA	0x23721(%RIP),%RDI

0x2376bf VZEROUPPER

0x2376c2 CALL	259690 <@plt_start@+0x540>

0x2376c7 ADD	$0x88,%RSP

0x2376ce POP	%RBX

0x2376cf POP	%R12

0x2376d1 POP	%R13

0x2376d3 POP	%R14

0x2376d5 POP	%R15

0x2376d7 POP	%RBP

0x2376d8 RET

0x2376d9 NOPL	(%RAX)

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run aocc_8

Source file and lines	advec_mom.cpp:167-172
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:167-172

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 17.13 to 6.00 cycles (2.85x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions).

Details

7% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

7% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
16% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
13% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:167
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:167

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVL: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:168
VPBROADCASTD: 3 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:168
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:168
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:168
VPBROADCASTQ: 7 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:168
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:168
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:168
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:168
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:168
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:168
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:168

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 272 bytes. The binary function is storing 144 bytes.

General properties

nb instructions	127
nb uops	137
loop length	546
used x86 registers	16
used mmx registers	0
used xmm registers	6
used ymm registers	9
used zmm registers	0
nb stack references	23

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	17.13 cycles
front end	17.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	6.33	6.33	6.33	6.33	6.33	6.33	13.75	13.75	13.75	13.75	1.00	6.00	6.00	1.00	0.00	0.00
cycles	6.33	6.33	6.33	6.33	6.33	6.33	13.75	13.75	13.75	13.75	1.00	6.00	6.00	1.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	17.13
Dispatch	13.75
Overall L1	17.13

Vectorization ratios

INT

all	7%
load	9%
store	0%
mul	0%
add-sub	16%
fma	NA (no fma vectorizable/vectorized instructions)
other	14%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	7%
load	7%
store	0%
mul	0%
add-sub	16%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

Vector efficiency ratios

INT

all	12%
load	14%
store	11%
mul	12%
add-sub	14%
fma	NA (no fma vectorizable/vectorized instructions)
other	13%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	12%
load	13%
store	11%
mul	12%
add-sub	14%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 17.13 cycles. At this rate:

6% of peak load performance is reached (15.88 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (8.41 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 17.13 to 13.75 cycles (1.25x speedup).

ASM code

In the binary file, the address of the function is: 236f20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x88,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RCX),%R15D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
MOV (%RDX),%EBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
ADD $0x4,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SUB %EBX,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 2376c7 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.18+0x7a7>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV (%R9),%R13D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
MOV (%R8),%R14D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
LEA 0x1(%R14),%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD $0x3,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CMP %R12D,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 2376c7 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.18+0x7a7>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
SUB %R12D,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVQ $0,-0x68(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOVQ $0x1,-0xb0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOVL $0,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
IMUL %R13,%R15	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
DEC %R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R15,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x50(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0xb0(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x23e2b(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x68(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x48(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %ESI,-0x4c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 259680 <@plt_start@+0x530>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x48(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x68(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
CMP %R15,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMOVL %RAX,%R15	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
MOV %R15,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
CMP %R15,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JG 2376b5 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.18+0x795>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x20(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x18(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x30(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x28(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x10(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %R14,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %R13,-0x60(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R12,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R11,-0x88(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RDI),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x10(%RDI),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV (%RSI),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%RSI),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV (%R9),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x10(%R9),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV (%RAX),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x10(%RAX),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV (%RDX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RAX,-0x58(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x10(%RDX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %R14,-0xa8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R12,-0xa0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %RSI,-0x98(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R9,-0x90(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %RAX,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R15,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RCX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x4,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 23705f <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.18+0x13f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x30(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 23759b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.18+0x67b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
MOV %RAX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV -0x60(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VBROADCASTSD -0x25ee3(%RIP),%YMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
VPBROADCASTQ %RCX,%YMM0	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPADDQ -0x25da1(%RIP),%YMM0,%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	1	0.50	vect (50.0%)
VPBROADCASTQ -0x25eba(%RIP),%YMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	1	0.50	scal (12.5%)
VPBROADCASTQ %RSI,%YMM7	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
MOV -0x58(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
AND $-0x4,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VPBROADCASTQ %R14,%YMM4	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPBROADCASTQ %R9,%YMM8	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPBROADCASTD %EBX,%XMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (6.3%)
VPBROADCASTQ %R12,%YMM5	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPBROADCASTD %R11D,%XMM6	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (6.3%)
VPCMPEQD %XMM11,%XMM11,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (25.0%)
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDX,-0x70(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTQ %RAX,%YMM1	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
MOV -0x30(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VPBROADCASTQ %RSI,%YMM9	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VEXTRACTI128 $0x1,%YMM1,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	3	0.50	vect (25.0%)
VPBROADCASTD %EAX,%XMM3	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (6.3%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0x70(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x30(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
CMP %RAX,-0x38(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JE 2376b5 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.18+0x795>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVSD -0x26413(%RIP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MOV %RBX,-0x80(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R14,-0x78(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0x4c(%RBP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
LEA 0x23721(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 259690 <@plt_start@+0x540>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
ADD $0x88,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run aocc_8

Source file and lines	advec_mom.cpp:167-172
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:167-172

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 17.13 to 6.00 cycles (2.85x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions).

Details

7% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

7% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
16% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
13% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:167
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:167

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVL: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:168
VPBROADCASTD: 3 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:168
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:168
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:168
VPBROADCASTQ: 7 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:168
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:168
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:168
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:168
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:168
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:168
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:168

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 272 bytes. The binary function is storing 144 bytes.

General properties

nb instructions	127
nb uops	137
loop length	546
used x86 registers	16
used mmx registers	0
used xmm registers	6
used ymm registers	9
used zmm registers	0
nb stack references	23

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	17.13 cycles
front end	17.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	6.33	6.33	6.33	6.33	6.33	6.33	13.75	13.75	13.75	13.75	1.00	6.00	6.00	1.00	0.00	0.00
cycles	6.33	6.33	6.33	6.33	6.33	6.33	13.75	13.75	13.75	13.75	1.00	6.00	6.00	1.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	17.13
Dispatch	13.75
Overall L1	17.13

Vectorization ratios

INT

all	7%
load	9%
store	0%
mul	0%
add-sub	16%
fma	NA (no fma vectorizable/vectorized instructions)
other	14%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	7%
load	7%
store	0%
mul	0%
add-sub	16%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

Vector efficiency ratios

INT

all	12%
load	14%
store	11%
mul	12%
add-sub	14%
fma	NA (no fma vectorizable/vectorized instructions)
other	13%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	12%
load	13%
store	11%
mul	12%
add-sub	14%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 17.13 cycles. At this rate:

6% of peak load performance is reached (15.88 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (8.41 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 236f20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x88,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RCX),%R15D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
MOV (%RDX),%EBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
ADD $0x4,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SUB %EBX,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 2376c7 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.18+0x7a7>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV (%R9),%R13D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
MOV (%R8),%R14D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
LEA 0x1(%R14),%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD $0x3,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CMP %R12D,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 2376c7 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.18+0x7a7>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
SUB %R12D,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVQ $0,-0x68(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOVQ $0x1,-0xb0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOVL $0,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
IMUL %R13,%R15	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
DEC %R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R15,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x50(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0xb0(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x23e2b(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x68(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x48(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %ESI,-0x4c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 259680 <@plt_start@+0x530>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x48(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x68(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
CMP %R15,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMOVL %RAX,%R15	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
MOV %R15,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
CMP %R15,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JG 2376b5 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.18+0x795>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x20(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x18(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x30(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x28(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x10(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %R14,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %R13,-0x60(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R12,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R11,-0x88(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RDI),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x10(%RDI),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV (%RSI),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%RSI),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV (%R9),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x10(%R9),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV (%RAX),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x10(%RAX),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV (%RDX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RAX,-0x58(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x10(%RDX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %R14,-0xa8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R12,-0xa0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %RSI,-0x98(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R9,-0x90(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %RAX,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R15,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RCX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x4,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 23705f <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.18+0x13f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x30(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 23759b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.18+0x67b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
MOV %RAX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV -0x60(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VBROADCASTSD -0x25ee3(%RIP),%YMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
VPBROADCASTQ %RCX,%YMM0	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPADDQ -0x25da1(%RIP),%YMM0,%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	1	0.50	vect (50.0%)
VPBROADCASTQ -0x25eba(%RIP),%YMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	1	0.50	scal (12.5%)
VPBROADCASTQ %RSI,%YMM7	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
MOV -0x58(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
AND $-0x4,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VPBROADCASTQ %R14,%YMM4	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPBROADCASTQ %R9,%YMM8	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPBROADCASTD %EBX,%XMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (6.3%)
VPBROADCASTQ %R12,%YMM5	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPBROADCASTD %R11D,%XMM6	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (6.3%)
VPCMPEQD %XMM11,%XMM11,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (25.0%)
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDX,-0x70(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTQ %RAX,%YMM1	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
MOV -0x30(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VPBROADCASTQ %RSI,%YMM9	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VEXTRACTI128 $0x1,%YMM1,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	3	0.50	vect (25.0%)
VPBROADCASTD %EAX,%XMM3	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (6.3%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0x70(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x30(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
CMP %RAX,-0x38(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JE 2376b5 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.18+0x795>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVSD -0x26413(%RIP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MOV %RBX,-0x80(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R14,-0x78(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0x4c(%RBP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
LEA 0x23721(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 259690 <@plt_start@+0x540>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
ADD $0x88,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	3.10	1.16
○Loop 165 - advec_mom.cpp:168-172 - exec	3.10	1.16
○Loop 166 - advec_mom.cpp:168-172 - exec	0.00	0.00

Report Configuration

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Execution units bottlenecks

512-bits vectorization

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Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

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Cycles summary

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Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code