OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone .omp

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: advec_mom.cpp:108-139 [...]	Coverage (incl. loops): 4.33% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 108 - 139

--------------------------------------------------------------------------------

108: #pragma omp parallel for simd collapse(2)

109:     for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) {

110:       for (int i = (x_min - 1 + 1); i < (x_max + 1 + 2); i++)

111:         ({

112:           int upwind, donor, downwind, dif;

113:           double sigma, width, limiter, vdiffuw, vdiffdw, auw, adw, wind, advec_vel_s;

114:           if (node_flux(i, j) < 0.0) {

115:             upwind = i + 2;

116:             donor = i + 1;

117:             downwind = i;

118:             dif = donor;

119:           } else {

120:             upwind = i - 1;

121:             donor = i;

122:             downwind = i + 1;

123:             dif = upwind;

124:           }

125:           sigma = std::fabs(node_flux(i, j)) / (node_mass_pre(donor, j));

126:           width = celldx[i];

127:           vdiffuw = vel1(donor, j) - vel1(upwind, j);

128:           vdiffdw = vel1(downwind, j) - vel1(donor, j);

129:           limiter = 0.0;

130:           if (vdiffuw * vdiffdw > 0.0) {

131:             auw = std::fabs(vdiffuw);

132:             adw = std::fabs(vdiffdw);

133:             wind = 1.0;

134:             if (vdiffdw <= 0.0) wind = -1.0;

135:             limiter =

136:                 wind * std::fmin(std::fmin(width * ((2.0 - sigma) * adw / width + (1.0 + sigma) * auw / celldx[dif]) / 6.0, auw), adw);

137:           }

138:           advec_vel_s = vel1(donor, j) + (1.0 - sigma) * limiter;

139:           mom_flux(i, j) = advec_vel_s * node_flux(i, j);

0x235f50 PUSH	%RBP

0x235f51 MOV	%RSP,%RBP

0x235f54 PUSH	%R15

0x235f56 PUSH	%R14

0x235f58 PUSH	%R13

0x235f5a PUSH	%R12

0x235f5c PUSH	%RBX

0x235f5d SUB	$0x68,%RSP

0x235f61 MOV	(%RCX),%R15D

0x235f64 MOV	(%RDX),%EAX

0x235f66 INC	%EAX

0x235f68 ADD	$0x3,%R15D

0x235f6c SUB	%EAX,%R15D

0x235f6f MOV	%EAX,-0x2c(%RBP)

0x235f72 JLE	23649f

0x235f78 MOV	(%R9),%R13D

0x235f7b MOV	(%R8),%R12D

0x235f7e ADD	$0x3,%R13D

0x235f82 CMP	%R12D,%R13D

0x235f85 JLE	23649f

0x235f8b SUB	%R12D,%R13D

0x235f8e MOV	(%RDI),%ESI

0x235f90 MOVQ	$0,-0x60(%RBP)

0x235f98 MOVQ	$0x1,-0x88(%RBP)

0x235fa3 MOVL	$0,-0x48(%RBP)

0x235faa IMUL	%R13,%R15

0x235fae DEC	%R15

0x235fb1 MOV	%R15,-0x40(%RBP)

0x235fb5 SUB	$0x8,%RSP

0x235fb9 LEA	-0x48(%RBP),%RCX

0x235fbd LEA	-0x88(%RBP),%RAX

0x235fc4 LEA	0x24d25(%RIP),%RDI

0x235fcb LEA	-0x60(%RBP),%R8

0x235fcf LEA	-0x40(%RBP),%R9

0x235fd3 MOV	%ESI,-0x44(%RBP)

0x235fd6 MOV	$0x22,%EDX

0x235fdb PUSH	$0x1

0x235fdd PUSH	$0x1

0x235fdf PUSH	%RAX

0x235fe0 CALL	259680 <@plt_start@+0x530>

0x235fe5 ADD	$0x20,%RSP

0x235fe9 MOV	-0x40(%RBP),%RAX

0x235fed MOV	-0x60(%RBP),%RCX

0x235ff1 CMP	%R15,%RAX

0x235ff4 CMOVL	%RAX,%R15

0x235ff8 MOV	%R15,-0x40(%RBP)

0x235ffc CMP	%R15,%RCX

0x235fff JG	23648d

0x236005 MOV	0x20(%RBP),%RSI

0x236009 MOV	0x28(%RBP),%RDX

0x23600d MOV	0x18(%RBP),%R8

0x236011 MOV	0x10(%RBP),%RDI

0x236015 MOV	0x30(%RBP),%RAX

0x236019 MOV	0x8(%RSI),%RSI

0x23601d MOV	(%RDI),%RBX

0x236020 MOV	(%R8),%R10

0x236023 MOV	0x10(%R8),%R9

0x236027 MOV	(%RDX),%R14

0x23602a MOV	0x10(%RDX),%R11

0x23602e MOV	(%RAX),%RDX

0x236031 MOV	0x10(%RDI),%RDI

0x236035 MOV	0x10(%RAX),%R8

0x236039 MOV	%RSI,-0x50(%RBP)

0x23603d MOV	%R15,%RSI

0x236040 SUB	%RCX,%RSI

0x236043 MOV	%RBX,-0x58(%RBP)

0x236047 MOV	%R10,-0x80(%RBP)

0x23604b MOV	%R14,-0x78(%RBP)

0x23604f MOV	%RDX,-0x70(%RBP)

0x236053 INC	%RSI

0x236056 CMP	$0x4,%RSI

0x23605a JB	2364ae

0x236060 VBROADCASTSD	-0x24f19(%RIP),%YMM13

0x236069 VPBROADCASTQ	%RCX,%YMM0

0x23606f VPADDQ	-0x24d97(%RIP),%YMM0,%YMM0

0x236077 VBROADCASTSD	-0x24f28(%RIP),%YMM11

0x236080 VBROADCASTSD	-0x24f29(%RIP),%YMM12

0x236089 VPBROADCASTQ	-0x24ec2(%RIP),%YMM14

0x236092 MOV	-0x2c(%RBP),%EAX

0x236095 MOV	%RSI,-0x68(%RBP)

0x236099 AND	$-0x4,%RSI

0x23609d VPBROADCASTQ	%R13,%YMM1

0x2360a3 VPBROADCASTD	%R12D,%XMM26

0x2360a9 VPBROADCASTQ	%RBX,%YMM27

0x2360af VPBROADCASTQ	%R10,%YMM5

0x2360b5 VPBROADCASTQ	%R14,%YMM6

0x2360bb VPBROADCASTQ	%RDX,%YMM7

0x2360c1 VXORPD	%XMM9,%XMM9,%XMM9

0x2360c6 VPCMPEQD	%XMM10,%XMM10,%XMM10

0x2360cb ADD	%RSI,%RCX

0x2360ce VEXTRACTI128	$0x1,%YMM1,%XMM8

0x2360d4 MOV	%RSI,-0x38(%RBP)

0x2360d8 VPBROADCASTD	%EAX,%XMM17

0x2360de JMP	236148

(160) 0x2360e0 VSUBPD	%YMM19,%YMM13,%YMM4

(160) 0x2360e6 VMOVAPD	%YMM24,%YMM3{%K1}{z}

(160) 0x2360ec ADD	$-0x4,%RSI

(160) 0x2360f0 VPADDQ	%YMM0,%YMM14,%YMM0

(160) 0x2360f4 VFMADD213PD	%YMM21,%YMM3,%YMM4

(160) 0x2360fa VPMULLQ	%YMM16,%YMM7,%YMM3

(160) 0x236100 VPADDQ	%YMM3,%YMM15,%YMM3

(160) 0x236104 VMULPD	%YMM2,%YMM4,%YMM2

(160) 0x236108 VMOVQ	%XMM3,%RDX

(160) 0x23610d VPEXTRQ	$0x1,%XMM3,%RAX

(160) 0x236113 VEXTRACTI128	$0x1,%YMM3,%XMM3

(160) 0x236119 VMOVQ	%XMM3,%RBX

(160) 0x23611e VPEXTRQ	$0x1,%XMM3,%R14

(160) 0x236124 VMOVLPD	%XMM2,(%R8,%RDX,8)

(160) 0x23612a VMOVHPD	%XMM2,(%R8,%RAX,8)

(160) 0x236130 VEXTRACTF128	$0x1,%YMM2,%XMM2

(160) 0x236136 VMOVLPD	%XMM2,(%R8,%RBX,8)

(160) 0x23613c VMOVHPD	%XMM2,(%R8,%R14,8)

(160) 0x236142 JE	23647f

(160) 0x236148 VEXTRACTI128	$0x1,%YMM0,%XMM2

(160) 0x23614e VPEXTRQ	$0x1,%XMM8,%RBX

(160) 0x236154 VPEXTRQ	$0x1,%XMM2,%RAX

(160) 0x23615a CQTO

(160) 0x23615c IDIV	%RBX

(160) 0x23615f VMOVQ	%XMM8,%RBX

(160) 0x236164 VMOVQ	%RAX,%XMM15

(160) 0x236169 VMOVQ	%XMM2,%RAX

(160) 0x23616e CQTO

(160) 0x236170 IDIV	%RBX

(160) 0x236173 VPEXTRQ	$0x1,%XMM1,%RBX

(160) 0x236179 VMOVQ	%RAX,%XMM2

(160) 0x23617e VPEXTRQ	$0x1,%XMM0,%RAX

(160) 0x236184 CQTO

(160) 0x236186 VPUNPCKLQDQ	%XMM15,%XMM2,%XMM2

(160) 0x23618b IDIV	%RBX

(160) 0x23618e VMOVQ	%XMM1,%RBX

(160) 0x236193 VMOVQ	%RAX,%XMM15

(160) 0x236198 VMOVQ	%XMM0,%RAX

(160) 0x23619d CQTO

(160) 0x23619f IDIV	%RBX

(160) 0x2361a2 VMOVQ	%RAX,%XMM16

(160) 0x2361a8 VPUNPCKLQDQ	%XMM15,%XMM16,%XMM15

(160) 0x2361ae VINSERTI128	$0x1,%XMM2,%YMM15,%YMM2

(160) 0x2361b4 VPMOVQD	%YMM2,%XMM15

(160) 0x2361ba VPMULLQ	%YMM1,%YMM2,%YMM2

(160) 0x2361c0 VPSUBQ	%YMM2,%YMM0,%YMM2

(160) 0x2361c4 VPMOVQD	%YMM2,%XMM2

(160) 0x2361ca VPADDD	%XMM15,%XMM17,%XMM16

(160) 0x2361d0 VPMOVSXDQ	%XMM16,%YMM16

(160) 0x2361d6 VPMULLQ	%YMM16,%YMM5,%YMM24

(160) 0x2361dc VPADDD	%XMM2,%XMM26,%XMM19

(160) 0x2361e2 VPMULLQ	%YMM16,%YMM27,%YMM2

(160) 0x2361e8 VPMOVSXDQ	%XMM19,%YMM15

(160) 0x2361ee VPSUBD	%XMM10,%XMM19,%XMM20

(160) 0x2361f4 VPMOVSXDQ	%XMM20,%YMM23

(160) 0x2361fa VPADDQ	%YMM2,%YMM15,%YMM2

(160) 0x2361fe VMOVQ	%XMM2,%RAX

(160) 0x236203 VPEXTRQ	$0x1,%XMM2,%RDX

(160) 0x236209 VEXTRACTI128	$0x1,%YMM2,%XMM2

(160) 0x23620f VMOVQ	%XMM2,%RBX

(160) 0x236214 VMOVSD	(%RDI,%RAX,8),%XMM18

(160) 0x23621b VPEXTRQ	$0x1,%XMM2,%R14

(160) 0x236221 VMOVSD	(%RDI,%RBX,8),%XMM2

(160) 0x236226 VMOVHPD	(%RDI,%RDX,8),%XMM18,%XMM18

(160) 0x23622d VMOVHPD	(%RDI,%R14,8),%XMM2,%XMM2

(160) 0x236233 VINSERTF32X4	$0x1,%XMM2,%YMM18,%YMM2

(160) 0x23623a VPADDD	%XMM10,%XMM19,%XMM18

(160) 0x236240 VMOVDQA64	%XMM18,%XMM22

(160) 0x236246 VCMPPD	$0x1,%YMM9,%YMM2,%K1

(160) 0x23624d VPBLENDMQ	%YMM23,%YMM15,%YMM21{%K1}

(160) 0x236253 VPADDD	-0x33659(%RIP){1to4},%XMM19,%XMM22{%K1}

(160) 0x23625d VANDPD	%YMM11,%YMM2,%YMM19

(160) 0x236263 VMOVDQA64	%YMM15,%YMM23{%K1}

(160) 0x236269 VPADDQ	%YMM24,%YMM21,%YMM24

(160) 0x23626f VMOVQ	%XMM24,%RDX

(160) 0x236275 VPEXTRQ	$0x1,%XMM24,%RAX

(160) 0x23627c VEXTRACTI32X4	$0x1,%YMM24,%XMM24

(160) 0x236283 VMOVQ	%XMM24,%RBX

(160) 0x236289 VMOVSD	(%R9,%RDX,8),%XMM25

(160) 0x236290 VPEXTRQ	$0x1,%XMM24,%R14

(160) 0x236297 VMOVSD	(%R9,%RBX,8),%XMM24

(160) 0x23629e VMOVHPD	(%R9,%RAX,8),%XMM25,%XMM25

(160) 0x2362a5 VMOVHPD	(%R9,%R14,8),%XMM24,%XMM24

(160) 0x2362ac VPMOVSXDQ	%XMM22,%YMM22

(160) 0x2362b2 VINSERTF32X4	$0x1,%XMM24,%YMM25,%YMM24

(160) 0x2362b9 VDIVPD	%YMM24,%YMM19,%YMM19

(160) 0x2362bf VPMULLQ	%YMM16,%YMM6,%YMM24

(160) 0x2362c5 VPADDQ	%YMM24,%YMM21,%YMM21

(160) 0x2362cb VPADDQ	%YMM22,%YMM24,%YMM22

(160) 0x2362d1 VPADDQ	%YMM24,%YMM23,%YMM23

(160) 0x2362d7 VMOVQ	%XMM21,%RAX

(160) 0x2362dd VPEXTRQ	$0x1,%XMM21,%RDX

(160) 0x2362e4 VEXTRACTI32X4	$0x1,%YMM21,%XMM21

(160) 0x2362eb VMOVQ	%XMM21,%RBX

(160) 0x2362f1 VMOVSD	(%R11,%RAX,8),%XMM25

(160) 0x2362f8 VPEXTRQ	$0x1,%XMM21,%R14

(160) 0x2362ff VMOVQ	%XMM22,%RAX

(160) 0x236305 VMOVSD	(%R11,%RBX,8),%XMM21

(160) 0x23630c VMOVHPD	(%R11,%RDX,8),%XMM25,%XMM25

(160) 0x236313 VPEXTRQ	$0x1,%XMM22,%RDX

(160) 0x23631a VEXTRACTI32X4	$0x1,%YMM22,%XMM22

(160) 0x236321 VMOVHPD	(%R11,%R14,8),%XMM21,%XMM21

(160) 0x236328 VMOVQ	%XMM22,%RBX

(160) 0x23632e VPEXTRQ	$0x1,%XMM22,%R14

(160) 0x236335 VMOVSD	(%R11,%RBX,8),%XMM22

(160) 0x23633c VMOVHPD	(%R11,%R14,8),%XMM22,%XMM22

(160) 0x236343 VINSERTF32X4	$0x1,%XMM21,%YMM25,%YMM21

(160) 0x23634a VMOVSD	(%R11,%RAX,8),%XMM25

(160) 0x236351 VMOVQ	%XMM23,%RAX

(160) 0x236357 VMOVHPD	(%R11,%RDX,8),%XMM25,%XMM25

(160) 0x23635e VPEXTRQ	$0x1,%XMM23,%RDX

(160) 0x236365 VEXTRACTI32X4	$0x1,%YMM23,%XMM23

(160) 0x23636c VMOVSD	(%R11,%RAX,8),%XMM24

(160) 0x236373 VMOVQ	%XMM23,%RBX

(160) 0x236379 VPEXTRQ	$0x1,%XMM23,%R14

(160) 0x236380 VMOVHPD	(%R11,%RDX,8),%XMM24,%XMM24

(160) 0x236387 VMOVSD	(%R11,%RBX,8),%XMM23

(160) 0x23638e VMOVHPD	(%R11,%R14,8),%XMM23,%XMM23

(160) 0x236395 VINSERTF32X4	$0x1,%XMM22,%YMM25,%YMM22

(160) 0x23639c VSUBPD	%YMM22,%YMM21,%YMM22

(160) 0x2363a2 VINSERTF32X4	$0x1,%XMM23,%YMM24,%YMM23

(160) 0x2363a9 VSUBPD	%YMM21,%YMM23,%YMM23

(160) 0x2363af VMULPD	%YMM22,%YMM23,%YMM3

(160) 0x2363b5 VCMPPD	$0x1,%YMM3,%YMM9,%K0

(160) 0x2363bc VCMPPD	$0x1,%YMM3,%YMM9,%YMM3

(160) 0x2363c1 VANDPD	%YMM3,%YMM12,%YMM3

(160) 0x2363c5 KORTESTB	%K0,%K0

(160) 0x2363c9 VPCMPEQQ	%YMM12,%YMM3,%K1

(160) 0x2363cf JE	2360e0

(160) 0x2363d5 VCMPPD	$0x1,%YMM9,%YMM2,%YMM3

(160) 0x2363db MOV	-0x50(%RBP),%RAX

(160) 0x2363df VXORPD	%XMM4,%XMM4,%XMM4

(160) 0x2363e3 KMOVQ	%K1,%K3

(160) 0x2363e8 VANDPD	%YMM3,%YMM12,%YMM3

(160) 0x2363ec VPCMPEQQ	%YMM12,%YMM3,%K2

(160) 0x2363f2 VXORPD	%XMM3,%XMM3,%XMM3

(160) 0x2363f6 VMOVDQA32	%XMM20,%XMM18{%K2}

(160) 0x2363fc KMOVQ	%K1,%K2

(160) 0x236401 VANDPD	%YMM11,%YMM22,%YMM20

(160) 0x236407 VANDPD	%YMM11,%YMM23,%YMM22

(160) 0x23640d VGATHERQPD	(%RAX,%YMM15,8),%YMM3{%K2}

(160) 0x236414 VCMPPD	$0x1,%YMM23,%YMM9,%K2

(160) 0x23641b VBROADCASTSD	-0x2531d(%RIP),%YMM23

(160) 0x236425 VGATHERDPD	(%RAX,%XMM18,8),%YMM4{%K3}

(160) 0x23642c VSUBPD	%YMM19,%YMM23,%YMM23

(160) 0x236432 VMULPD	%YMM23,%YMM22,%YMM23

(160) 0x236438 VMINPD	%YMM22,%YMM20,%YMM22

(160) 0x23643e VFMADD213PD	%YMM20,%YMM19,%YMM20

(160) 0x236444 VDIVPD	%YMM3,%YMM23,%YMM23

(160) 0x23644a VMULPD	-0x2526c(%RIP){1to4},%YMM3,%YMM3

(160) 0x236454 VDIVPD	%YMM4,%YMM20,%YMM4

(160) 0x23645a VADDPD	%YMM23,%YMM4,%YMM4

(160) 0x236460 VMULPD	%YMM4,%YMM3,%YMM3

(160) 0x236464 VMINPD	%YMM22,%YMM3,%YMM3

(160) 0x23646a VXORPD	-0x252fc(%RIP){1to4},%YMM3,%YMM24

(160) 0x236474 VMOVAPD	%YMM3,%YMM24{%K2}

(160) 0x23647a JMP	2360e0

0x23647f MOV	-0x58(%RBP),%RBX

0x236483 MOV	-0x68(%RBP),%RAX

0x236487 CMP	%RAX,-0x38(%RBP)

0x23648b JNE	2364ae

0x23648d MOV	-0x44(%RBP),%ESI

0x236490 LEA	0x24871(%RIP),%RDI

0x236497 VZEROUPPER

0x23649a CALL	259690 <@plt_start@+0x540>

0x23649f ADD	$0x68,%RSP

0x2364a3 POP	%RBX

0x2364a4 POP	%R12

0x2364a6 POP	%R13

0x2364a8 POP	%R14

0x2364aa POP	%R15

0x2364ac POP	%RBP

0x2364ad RET

0x2364ae VMOVDDUP	-0x2535e(%RIP),%XMM1

0x2364b6 VMOVDDUP	-0x25366(%RIP),%XMM2

0x2364be VMOVSD	-0x253be(%RIP),%XMM3

0x2364c6 VMOVSD	-0x252e6(%RIP),%XMM4

0x2364ce VMOVDDUP	-0x2535e(%RIP),%XMM5

0x2364d6 VMOVSD	-0x2538e(%RIP),%XMM6

0x2364de VPXOR	%XMM0,%XMM0,%XMM0

0x2364e2 MOV	%R12,-0x38(%RBP)

0x2364e6 JMP	236524

0x2364e8 NOPL	(%RAX,%RAX,1)

(159) 0x2364f0 VSUBSD	%XMM8,%XMM6,%XMM8

(159) 0x2364f5 IMUL	-0x70(%RBP),%RAX

(159) 0x2364fa MOV	-0x38(%RBP),%R12

(159) 0x2364fe MOV	-0x58(%RBP),%RBX

(159) 0x236502 VFMADD213SD	%XMM9,%XMM11,%XMM8

(159) 0x236507 VMULSD	%XMM7,%XMM8,%XMM7

(159) 0x23650b ADD	%R14,%RAX

(159) 0x23650e CMP	%R15,%RCX

(159) 0x236511 VMOVSD	%XMM7,(%R8,%RAX,8)

(159) 0x236517 LEA	0x1(%RCX),%RAX

(159) 0x23651b MOV	%RAX,%RCX

(159) 0x23651e JGE	23648d

(159) 0x236524 MOV	%RCX,%RAX

(159) 0x236527 CQTO

(159) 0x236529 MOV	%RBX,%RSI

(159) 0x23652c IDIV	%R13

(159) 0x23652f LEA	(%R12,%RDX,1),%R10D

(159) 0x236533 LEA	0x1(%R12,%RDX,1),%EDX

(159) 0x236538 MOVSXD	%R10D,%R14

(159) 0x23653b ADD	-0x2c(%RBP),%EAX

(159) 0x23653e CLTQ

(159) 0x236540 IMUL	%RAX,%RSI

(159) 0x236544 ADD	%R14,%RSI

(159) 0x236547 VMOVSD	(%RDI,%RSI,8),%XMM7

(159) 0x23654c MOVSXD	%EDX,%RSI

(159) 0x23654f VUCOMISD	%XMM7,%XMM0

(159) 0x236553 JBE	236560

(159) 0x236555 ADD	$0x2,%R10D

(159) 0x236559 MOV	%R14,%RBX

(159) 0x23655c JMP	23656c

0x23655e XCHG	%AX,%AX

(159) 0x236560 DEC	%R10D

(159) 0x236563 MOV	%RSI,%RBX

(159) 0x236566 MOV	%R14,%RSI

(159) 0x236569 MOV	%R10D,%EDX

(159) 0x23656c MOV	-0x80(%RBP),%R12

(159) 0x236570 VANDPD	%XMM1,%XMM7,%XMM8

(159) 0x236574 VXORPD	%XMM11,%XMM11,%XMM11

(159) 0x236579 IMUL	%RAX,%R12

(159) 0x23657d ADD	%RSI,%R12

(159) 0x236580 VDIVSD	(%R9,%R12,8),%XMM8,%XMM8

(159) 0x236586 MOV	-0x78(%RBP),%R12

(159) 0x23658a IMUL	%RAX,%R12

(159) 0x23658e ADD	%R12,%RSI

(159) 0x236591 VMOVSD	(%R11,%RSI,8),%XMM9

(159) 0x236597 MOVSXD	%R10D,%RSI

(159) 0x23659a ADD	%R12,%RSI

(159) 0x23659d ADD	%RBX,%R12

(159) 0x2365a0 VMOVSD	(%R11,%R12,8),%XMM10

(159) 0x2365a6 VSUBSD	(%R11,%RSI,8),%XMM9,%XMM12

(159) 0x2365ac VSUBSD	%XMM9,%XMM10,%XMM10

(159) 0x2365b1 VMULSD	%XMM12,%XMM10,%XMM13

(159) 0x2365b6 VUCOMISD	%XMM11,%XMM13

(159) 0x2365bb JBE	2364f0

(159) 0x2365c1 MOV	-0x50(%RBP),%RSI

(159) 0x2365c5 VSUBSD	%XMM8,%XMM3,%XMM14

(159) 0x2365ca VANDPD	%XMM2,%XMM10,%XMM13

(159) 0x2365ce VANDPD	%XMM2,%XMM12,%XMM12

(159) 0x2365d2 MOVSXD	%EDX,%RDX

(159) 0x2365d5 VCMPSD	$0x1,%XMM10,%XMM0,%K1

(159) 0x2365dc VMULSD	%XMM14,%XMM13,%XMM14

(159) 0x2365e1 VMINSD	%XMM13,%XMM12,%XMM13

(159) 0x2365e6 VFMADD213SD	%XMM12,%XMM8,%XMM12

(159) 0x2365eb VMOVSD	(%RSI,%R14,8),%XMM11

(159) 0x2365f1 VDIVSD	(%RSI,%RDX,8),%XMM12,%XMM12

(159) 0x2365f6 VDIVSD	%XMM11,%XMM14,%XMM14

(159) 0x2365fb VMULSD	%XMM4,%XMM11,%XMM11

(159) 0x2365ff VADDSD	%XMM14,%XMM12,%XMM12

(159) 0x236604 VMULSD	%XMM12,%XMM11,%XMM11

(159) 0x236609 VMINSD	%XMM13,%XMM11,%XMM12

(159) 0x23660e VXORPD	%XMM5,%XMM12,%XMM11

(159) 0x236612 VMOVSD	%XMM12,%XMM11,%XMM11{%K1}

(159) 0x236618 JMP	2364f0

0x23661d NOPL	(%RAX)

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run aocc_8

Source file and lines	advec_mom.cpp:108-139
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:108-139

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 16.25 to 5.13 cycles (3.17x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions).

Details

10% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

5% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
16% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
21% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:108
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:108

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVL: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:109
VPBROADCASTD: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:109
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:109
VPBROADCASTQ: 6 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:109
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:109
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:109
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:109
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:109
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:109

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 292 bytes. The binary function is storing 108 bytes.

General properties

nb instructions	122
nb uops	130
loop length	518
used x86 registers	16
used mmx registers	0
used xmm registers	12
used ymm registers	10
used zmm registers	0
nb stack references	18

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	16.25 cycles
front end	16.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	6.50	6.50	6.50	6.50	6.50	6.50	13.50	13.50	13.50	13.50	2.50	5.00	5.00	2.50	0.00	0.00
cycles	6.50	6.50	6.50	6.50	6.50	6.50	13.50	13.50	13.50	13.50	2.50	5.00	5.00	2.50	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	16.25
Dispatch	13.50
Overall L1	16.25

Vectorization ratios

INT

all	10%
load	9%
store	0%
mul	0%
add-sub	16%
fma	NA (no fma vectorizable/vectorized instructions)
other	21%

all	10%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	10%
load	5%
store	0%
mul	0%
add-sub	16%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	21%

Vector efficiency ratios

INT

all	12%
load	14%
store	10%
mul	12%
add-sub	14%
fma	NA (no fma vectorizable/vectorized instructions)
other	14%

all	13%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

INT+FP

all	12%
load	13%
store	10%
mul	12%
add-sub	14%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 16.25 cycles. At this rate:

7% of peak load performance is reached (17.97 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (6.65 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 16.25 to 13.50 cycles (1.20x speedup).

ASM code

In the binary file, the address of the function is: 235f50

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x68,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RCX),%R15D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
MOV (%RDX),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
INC %EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x3,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SUB %EAX,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %EAX,-0x2c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
JLE 23649f <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.12+0x54f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV (%R9),%R13D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
MOV (%R8),%R12D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
ADD $0x3,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CMP %R12D,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 23649f <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.12+0x54f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
SUB %R12D,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVQ $0,-0x60(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOVQ $0x1,-0x88(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOVL $0,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
IMUL %R13,%R15	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
DEC %R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R15,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x48(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x88(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x24d25(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x60(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x40(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %ESI,-0x44(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 259680 <@plt_start@+0x530>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x40(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x60(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
CMP %R15,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMOVL %RAX,%R15	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
MOV %R15,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
CMP %R15,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JG 23648d <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.12+0x53d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x20(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x28(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x18(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x10(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x30(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x8(%RSI),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV (%RDI),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV (%R8),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%R8),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV (%RDX),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%RDX),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV (%RAX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x10(%RDI),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x10(%RAX),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RSI,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R15,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RCX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RBX,-0x58(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R10,-0x80(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R14,-0x78(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDX,-0x70(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
INC %RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x4,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JB 2364ae <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.12+0x55e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VBROADCASTSD -0x24f19(%RIP),%YMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
VPBROADCASTQ %RCX,%YMM0	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPADDQ -0x24d97(%RIP),%YMM0,%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	1	0.50	vect (50.0%)
VBROADCASTSD -0x24f28(%RIP),%YMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
VBROADCASTSD -0x24f29(%RIP),%YMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
VPBROADCASTQ -0x24ec2(%RIP),%YMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	1	0.50	scal (12.5%)
MOV -0x2c(%RBP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RSI,-0x68(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
AND $-0x4,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VPBROADCASTQ %R13,%YMM1	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPBROADCASTD %R12D,%XMM26	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (6.3%)
VPBROADCASTQ %RBX,%YMM27	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPBROADCASTQ %R10,%YMM5	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPBROADCASTQ %R14,%YMM6	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPBROADCASTQ %RDX,%YMM7	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VXORPD %XMM9,%XMM9,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VPCMPEQD %XMM10,%XMM10,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (25.0%)
ADD %RSI,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VEXTRACTI128 $0x1,%YMM1,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	3	0.50	vect (25.0%)
MOV %RSI,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
VPBROADCASTD %EAX,%XMM17	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (6.3%)
JMP 236148 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.12+0x1f8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
MOV -0x58(%RBP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV -0x68(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
CMP %RAX,-0x38(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JNE 2364ae <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.12+0x55e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x44(%RBP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
LEA 0x24871(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 259690 <@plt_start@+0x540>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
ADD $0x68,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50	N/A
VMOVDDUP -0x2535e(%RIP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVDDUP -0x25366(%RIP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVSD -0x253be(%RIP),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD -0x252e6(%RIP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VMOVDDUP -0x2535e(%RIP),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVSD -0x2538e(%RIP),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VPXOR %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
MOV %R12,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
JMP 236524 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.12+0x5d4>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run aocc_8

Source file and lines	advec_mom.cpp:108-139
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:108-139

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 16.25 to 5.13 cycles (3.17x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions).

Details

10% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

5% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
16% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
21% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:108
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:108

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVL: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:109
VPBROADCASTD: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:109
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:109
VPBROADCASTQ: 6 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:109
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:109
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:109
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:109
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:109
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:109

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 292 bytes. The binary function is storing 108 bytes.

General properties

nb instructions	122
nb uops	130
loop length	518
used x86 registers	16
used mmx registers	0
used xmm registers	12
used ymm registers	10
used zmm registers	0
nb stack references	18

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	16.25 cycles
front end	16.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	6.50	6.50	6.50	6.50	6.50	6.50	13.50	13.50	13.50	13.50	2.50	5.00	5.00	2.50	0.00	0.00
cycles	6.50	6.50	6.50	6.50	6.50	6.50	13.50	13.50	13.50	13.50	2.50	5.00	5.00	2.50	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	16.25
Dispatch	13.50
Overall L1	16.25

Vectorization ratios

INT

all	10%
load	9%
store	0%
mul	0%
add-sub	16%
fma	NA (no fma vectorizable/vectorized instructions)
other	21%

all	10%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	10%
load	5%
store	0%
mul	0%
add-sub	16%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	21%

Vector efficiency ratios

INT

all	12%
load	14%
store	10%
mul	12%
add-sub	14%
fma	NA (no fma vectorizable/vectorized instructions)
other	14%

all	13%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

INT+FP

all	12%
load	13%
store	10%
mul	12%
add-sub	14%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 16.25 cycles. At this rate:

7% of peak load performance is reached (17.97 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (6.65 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 235f50

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x68,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RCX),%R15D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
MOV (%RDX),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
INC %EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x3,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SUB %EAX,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %EAX,-0x2c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
JLE 23649f <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.12+0x54f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV (%R9),%R13D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
MOV (%R8),%R12D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
ADD $0x3,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CMP %R12D,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 23649f <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.12+0x54f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
SUB %R12D,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVQ $0,-0x60(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOVQ $0x1,-0x88(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOVL $0,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
IMUL %R13,%R15	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
DEC %R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R15,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x48(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x88(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x24d25(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x60(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x40(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %ESI,-0x44(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 259680 <@plt_start@+0x530>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x40(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x60(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
CMP %R15,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMOVL %RAX,%R15	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
MOV %R15,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
CMP %R15,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JG 23648d <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.12+0x53d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x20(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x28(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x18(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x10(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x30(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x8(%RSI),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV (%RDI),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV (%R8),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%R8),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV (%RDX),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%RDX),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV (%RAX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x10(%RDI),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x10(%RAX),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RSI,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R15,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RCX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RBX,-0x58(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R10,-0x80(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R14,-0x78(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDX,-0x70(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
INC %RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x4,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JB 2364ae <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.12+0x55e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VBROADCASTSD -0x24f19(%RIP),%YMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
VPBROADCASTQ %RCX,%YMM0	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPADDQ -0x24d97(%RIP),%YMM0,%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	1	0.50	vect (50.0%)
VBROADCASTSD -0x24f28(%RIP),%YMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
VBROADCASTSD -0x24f29(%RIP),%YMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
VPBROADCASTQ -0x24ec2(%RIP),%YMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	1	0.50	scal (12.5%)
MOV -0x2c(%RBP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RSI,-0x68(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
AND $-0x4,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VPBROADCASTQ %R13,%YMM1	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPBROADCASTD %R12D,%XMM26	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (6.3%)
VPBROADCASTQ %RBX,%YMM27	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPBROADCASTQ %R10,%YMM5	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPBROADCASTQ %R14,%YMM6	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPBROADCASTQ %RDX,%YMM7	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VXORPD %XMM9,%XMM9,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VPCMPEQD %XMM10,%XMM10,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (25.0%)
ADD %RSI,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VEXTRACTI128 $0x1,%YMM1,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	3	0.50	vect (25.0%)
MOV %RSI,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
VPBROADCASTD %EAX,%XMM17	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (6.3%)
JMP 236148 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.12+0x1f8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
MOV -0x58(%RBP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV -0x68(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
CMP %RAX,-0x38(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JNE 2364ae <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.12+0x55e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x44(%RBP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
LEA 0x24871(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 259690 <@plt_start@+0x540>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
ADD $0x68,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50	N/A
VMOVDDUP -0x2535e(%RIP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVDDUP -0x25366(%RIP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVSD -0x253be(%RIP),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD -0x252e6(%RIP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VMOVDDUP -0x2535e(%RIP),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVSD -0x2538e(%RIP),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VPXOR %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
MOV %R12,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
JMP 236524 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.12+0x5d4>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	4.33	1.62
○Loop 160 - advec_mom.cpp:109-139 - exec	4.33	1.61
○Loop 159 - advec_mom.cpp:109-139 - exec	0.00	0.00

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512-bits vectorization

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Matching between your function (in the source code) and the binary function

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ASM code

Code clean check

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Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code