OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone .omp

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: advec_mom.cpp:95-100 [...]	Coverage (incl. loops): 3.08% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 95 - 100

--------------------------------------------------------------------------------

95: #pragma omp parallel for simd collapse(2)

96:       for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) {

97:         for (int i = (x_min - 1 + 1); i < (x_max + 2 + 2); i++) {

98:           node_mass_post(i, j) = 0.25 * (density1(i + 0, j - 1) * post_vol(i + 0, j - 1) + density1(i, j) * post_vol(i, j) +

99:                                          density1(i - 1, j - 1) * post_vol(i - 1, j - 1) + density1(i - 1, j + 0) * post_vol(i - 1, j + 0));

100:           node_mass_pre(i, j) = node_mass_post(i, j) - node_flux(i - 1, j + 0) + node_flux(i, j);

0x2357b0 PUSH	%RBP

0x2357b1 MOV	%RSP,%RBP

0x2357b4 PUSH	%R15

0x2357b6 PUSH	%R14

0x2357b8 PUSH	%R13

0x2357ba PUSH	%R12

0x2357bc PUSH	%RBX

0x2357bd SUB	$0x78,%RSP

0x2357c1 MOV	(%RCX),%R12D

0x2357c4 MOV	(%RDX),%EAX

0x2357c6 LEA	0x1(%RAX),%R13D

0x2357ca ADD	$0x3,%R12D

0x2357ce SUB	%R13D,%R12D

0x2357d1 JLE	235f36

0x2357d7 MOV	(%R9),%R15D

0x2357da MOV	(%R8),%R14D

0x2357dd ADD	$0x4,%R15D

0x2357e1 CMP	%R14D,%R15D

0x2357e4 JLE	235f36

0x2357ea SUB	%R14D,%R15D

0x2357ed MOV	(%RDI),%ESI

0x2357ef MOV	%RAX,%RBX

0x2357f2 MOVQ	$0,-0x70(%RBP)

0x2357fa MOVQ	$0x1,-0xa0(%RBP)

0x235805 MOVL	$0,-0x48(%RBP)

0x23580c IMUL	%R15,%R12

0x235810 DEC	%R12

0x235813 MOV	%R12,-0x40(%RBP)

0x235817 SUB	$0x8,%RSP

0x23581b LEA	-0x48(%RBP),%RCX

0x23581f LEA	-0xa0(%RBP),%RAX

0x235826 LEA	0x2547b(%RIP),%RDI

0x23582d LEA	-0x70(%RBP),%R8

0x235831 LEA	-0x40(%RBP),%R9

0x235835 MOV	%ESI,-0x44(%RBP)

0x235838 MOV	$0x22,%EDX

0x23583d PUSH	$0x1

0x23583f PUSH	$0x1

0x235841 PUSH	%RAX

0x235842 CALL	259680 <@plt_start@+0x530>

0x235847 ADD	$0x20,%RSP

0x23584b MOV	-0x40(%RBP),%RAX

0x23584f MOV	-0x70(%RBP),%RCX

0x235853 CMP	%R12,%RAX

0x235856 CMOVL	%RAX,%R12

0x23585a MOV	%R12,-0x40(%RBP)

0x23585e CMP	%R12,%RCX

0x235861 JG	235f24

0x235867 MOV	0x30(%RBP),%RAX

0x23586b MOV	0x28(%RBP),%RDX

0x23586f MOV	%R15,-0x58(%RBP)

0x235873 MOV	%R14D,-0x2c(%RBP)

0x235877 MOV	0x20(%RBP),%RSI

0x23587b MOV	0x18(%RBP),%R8

0x23587f MOV	0x10(%RBP),%R11

0x235883 MOV	%R13,-0x60(%RBP)

0x235887 MOV	(%RAX),%R15

0x23588a MOV	0x10(%RAX),%R14

0x23588e MOV	(%RDX),%RAX

0x235891 MOV	(%R8),%RDI

0x235894 MOV	(%RSI),%R9

0x235897 MOV	0x10(%RSI),%R10

0x23589b MOV	(%R11),%RSI

0x23589e MOV	0x10(%R11),%R11

0x2358a2 MOV	0x10(%R8),%R8

0x2358a6 MOV	%RAX,-0x50(%RBP)

0x2358aa MOV	0x10(%RDX),%RAX

0x2358ae MOV	%RDI,-0x98(%RBP)

0x2358b5 MOV	%RSI,-0x90(%RBP)

0x2358bc MOV	%R15,-0x88(%RBP)

0x2358c3 MOV	%R11,-0x68(%RBP)

0x2358c7 MOV	%R9,-0x80(%RBP)

0x2358cb MOV	%RAX,-0x38(%RBP)

0x2358cf MOV	%R12,%RAX

0x2358d2 SUB	%RCX,%RAX

0x2358d5 INC	%RAX

0x2358d8 CMP	$0x4,%RAX

0x2358dc JB	235e10

0x2358e2 VBROADCASTSD	-0x2475b(%RIP),%YMM12

0x2358eb VPBROADCASTQ	%RCX,%YMM0

0x2358f1 VPADDQ	-0x24619(%RIP),%YMM0,%YMM0

0x2358f9 VPBROADCASTQ	-0x24732(%RIP),%YMM13

0x235902 MOV	%RAX,%RDX

0x235905 MOV	%RAX,-0x78(%RBP)

0x235909 MOV	-0x58(%RBP),%RAX

0x23590d MOV	-0x2c(%RBP),%R11D

0x235911 VPBROADCASTQ	%RSI,%YMM7

0x235917 MOV	-0x50(%RBP),%RSI

0x23591b AND	$-0x4,%RDX

0x23591f VPBROADCASTD	%R13D,%XMM2

0x235925 VPBROADCASTQ	%R15,%YMM8

0x23592b VPBROADCASTD	%EBX,%XMM4

0x235931 VPBROADCASTQ	%RDI,%YMM5

0x235937 VPBROADCASTQ	%R9,%YMM6

0x23593d VPCMPEQD	%XMM11,%XMM11,%XMM11

0x235942 ADD	%RDX,%RCX

0x235945 MOV	%RDX,%R15

0x235948 MOV	%RDX,%R13

0x23594b VPBROADCASTQ	%RAX,%YMM1

0x235951 VPBROADCASTD	%R11D,%XMM3

0x235957 VPBROADCASTQ	%RSI,%YMM9

0x23595d VEXTRACTI128	$0x1,%YMM1,%XMM10

0x235963 NOPW	%CS:(%RAX,%RAX,1)

(158) 0x235970 VEXTRACTI128	$0x1,%YMM0,%XMM14

(158) 0x235976 VPEXTRQ	$0x1,%XMM10,%RSI

(158) 0x23597c VMOVQ	%XMM10,%RDI

(158) 0x235981 VPEXTRQ	$0x1,%XMM14,%RAX

(158) 0x235987 CQTO

(158) 0x235989 IDIV	%RSI

(158) 0x23598c MOV	%RAX,%RSI

(158) 0x23598f VMOVQ	%XMM14,%RAX

(158) 0x235994 VMOVQ	%RSI,%XMM14

(158) 0x235999 VPEXTRQ	$0x1,%XMM1,%RSI

(158) 0x23599f CQTO

(158) 0x2359a1 IDIV	%RDI

(158) 0x2359a4 VPEXTRQ	$0x1,%XMM0,%RDX

(158) 0x2359aa VMOVQ	%XMM1,%RDI

(158) 0x2359af VMOVQ	%RAX,%XMM15

(158) 0x2359b4 MOV	%RDX,%RAX

(158) 0x2359b7 CQTO

(158) 0x2359b9 IDIV	%RSI

(158) 0x2359bc VPUNPCKLQDQ	%XMM14,%XMM15,%XMM14

(158) 0x2359c1 MOV	%RAX,%RSI

(158) 0x2359c4 VMOVQ	%XMM0,%RAX

(158) 0x2359c9 VMOVQ	%RSI,%XMM15

(158) 0x2359ce CQTO

(158) 0x2359d0 IDIV	%RDI

(158) 0x2359d3 ADD	$-0x4,%R13

(158) 0x2359d7 VMOVQ	%RAX,%XMM16

(158) 0x2359dd VPUNPCKLQDQ	%XMM15,%XMM16,%XMM15

(158) 0x2359e3 VINSERTI128	$0x1,%XMM14,%YMM15,%YMM14

(158) 0x2359e9 VPMOVQD	%YMM14,%XMM15

(158) 0x2359ef VPMULLQ	%YMM1,%YMM14,%YMM14

(158) 0x2359f5 VPSUBQ	%YMM14,%YMM0,%YMM14

(158) 0x2359fa VPADDQ	%YMM0,%YMM13,%YMM0

(158) 0x2359fe VPMOVQD	%YMM14,%XMM14

(158) 0x235a04 VPADDD	%XMM15,%XMM2,%XMM16

(158) 0x235a0a VPADDD	%XMM14,%XMM3,%XMM17

(158) 0x235a10 VPADDD	%XMM4,%XMM15,%XMM14

(158) 0x235a14 VPMOVSXDQ	%XMM14,%YMM15

(158) 0x235a19 VPMOVSXDQ	%XMM17,%YMM14

(158) 0x235a1f VPMULLQ	%YMM15,%YMM5,%YMM18

(158) 0x235a25 VPMULLQ	%YMM15,%YMM6,%YMM20

(158) 0x235a2b VPADDQ	%YMM14,%YMM18,%YMM19

(158) 0x235a31 VPADDQ	%YMM14,%YMM20,%YMM15

(158) 0x235a37 VMOVQ	%XMM19,%RDX

(158) 0x235a3d VPEXTRQ	$0x1,%XMM19,%RSI

(158) 0x235a44 VEXTRACTI32X4	$0x1,%YMM19,%XMM19

(158) 0x235a4b VMOVQ	%XMM19,%RDI

(158) 0x235a51 VPEXTRQ	$0x1,%XMM19,%RAX

(158) 0x235a58 VMOVSD	(%R8,%RDX,8),%XMM19

(158) 0x235a5f VMOVQ	%XMM15,%RDX

(158) 0x235a64 VMOVSD	(%R8,%RDI,8),%XMM21

(158) 0x235a6b VPEXTRQ	$0x1,%XMM15,%RDI

(158) 0x235a71 VEXTRACTI128	$0x1,%YMM15,%XMM15

(158) 0x235a77 VMOVHPD	(%R8,%RSI,8),%XMM19,%XMM19

(158) 0x235a7e VMOVSD	(%R10,%RDX,8),%XMM22

(158) 0x235a85 VMOVQ	%XMM15,%R9

(158) 0x235a8a VPEXTRQ	$0x1,%XMM15,%RSI

(158) 0x235a90 VPMOVSXDQ	%XMM16,%YMM15

(158) 0x235a96 VMOVHPD	(%R10,%RDI,8),%XMM22,%XMM22

(158) 0x235a9d VMOVHPD	(%R8,%RAX,8),%XMM21,%XMM21

(158) 0x235aa4 VMOVSD	(%R10,%R9,8),%XMM16

(158) 0x235aab VPMULLQ	%YMM15,%YMM5,%YMM23

(158) 0x235ab1 VPMULLQ	%YMM15,%YMM6,%YMM26

(158) 0x235ab7 VMOVHPD	(%R10,%RSI,8),%XMM16,%XMM28

(158) 0x235abe VPADDQ	%YMM14,%YMM23,%YMM24

(158) 0x235ac4 VPADDQ	%YMM14,%YMM26,%YMM27

(158) 0x235aca VMOVQ	%XMM24,%RDX

(158) 0x235ad0 VPEXTRQ	$0x1,%XMM24,%R9

(158) 0x235ad7 VEXTRACTI32X4	$0x1,%YMM24,%XMM24

(158) 0x235ade VEXTRACTI32X4	$0x1,%YMM27,%XMM16

(158) 0x235ae5 VPEXTRQ	$0x1,%XMM27,%RAX

(158) 0x235aec VMOVQ	%XMM24,%RDI

(158) 0x235af2 VMOVQ	%XMM16,%RSI

(158) 0x235af8 VMOVSD	(%R8,%RDI,8),%XMM25

(158) 0x235aff VPEXTRQ	$0x1,%XMM24,%RDI

(158) 0x235b06 VMOVSD	(%R8,%RDX,8),%XMM24

(158) 0x235b0d VMOVQ	%XMM27,%RDX

(158) 0x235b13 VMOVSD	(%R10,%RSI,8),%XMM27

(158) 0x235b1a VINSERTF32X4	$0x1,%XMM21,%YMM19,%YMM19

(158) 0x235b21 VMOVHPD	(%R8,%R9,8),%XMM24,%XMM24

(158) 0x235b28 VPEXTRQ	$0x1,%XMM16,%R9

(158) 0x235b2f VMOVSD	(%R10,%RDX,8),%XMM16

(158) 0x235b36 VMOVHPD	(%R8,%RDI,8),%XMM25,%XMM25

(158) 0x235b3d VMOVHPD	(%R10,%RAX,8),%XMM16,%XMM29

(158) 0x235b44 VPADDD	%XMM11,%XMM17,%XMM16

(158) 0x235b4a VINSERTF32X4	$0x1,%XMM28,%YMM22,%YMM21

(158) 0x235b51 VMOVHPD	(%R10,%R9,8),%XMM27,%XMM17

(158) 0x235b58 MOV	-0x68(%RBP),%R9

(158) 0x235b5c VPMOVSXDQ	%XMM16,%YMM16

(158) 0x235b62 VMULPD	%YMM19,%YMM21,%YMM19

(158) 0x235b68 VPADDQ	%YMM16,%YMM18,%YMM18

(158) 0x235b6e VPADDQ	%YMM16,%YMM20,%YMM20

(158) 0x235b74 VPADDQ	%YMM16,%YMM23,%YMM23

(158) 0x235b7a VMOVQ	%XMM18,%RAX

(158) 0x235b80 VPEXTRQ	$0x1,%XMM18,%RDX

(158) 0x235b87 VEXTRACTI32X4	$0x1,%YMM18,%XMM18

(158) 0x235b8e VMOVQ	%XMM18,%RSI

(158) 0x235b94 VMOVSD	(%R8,%RAX,8),%XMM22

(158) 0x235b9b VPEXTRQ	$0x1,%XMM18,%RDI

(158) 0x235ba2 VPEXTRQ	$0x1,%XMM20,%RAX

(158) 0x235ba9 VMOVSD	(%R8,%RSI,8),%XMM18

(158) 0x235bb0 VMOVHPD	(%R8,%RDX,8),%XMM22,%XMM22

(158) 0x235bb7 VMOVQ	%XMM20,%RDX

(158) 0x235bbd VEXTRACTI32X4	$0x1,%YMM20,%XMM20

(158) 0x235bc4 VMOVHPD	(%R8,%RDI,8),%XMM18,%XMM18

(158) 0x235bcb VINSERTF32X4	$0x1,%XMM25,%YMM24,%YMM24

(158) 0x235bd2 VMOVSD	(%R10,%RDX,8),%XMM25

(158) 0x235bd9 VMOVQ	%XMM20,%RSI

(158) 0x235bdf VPEXTRQ	$0x1,%XMM20,%RDI

(158) 0x235be6 VPEXTRQ	$0x1,%XMM23,%RDX

(158) 0x235bed VMOVSD	(%R10,%RSI,8),%XMM20

(158) 0x235bf4 VMOVHPD	(%R10,%RAX,8),%XMM25,%XMM25

(158) 0x235bfb VMOVQ	%XMM23,%RAX

(158) 0x235c01 VINSERTF32X4	$0x1,%XMM17,%YMM29,%YMM17

(158) 0x235c08 VMOVHPD	(%R10,%RDI,8),%XMM20,%XMM20

(158) 0x235c0f VFMADD213PD	%YMM19,%YMM24,%YMM17

(158) 0x235c15 VINSERTF32X4	$0x1,%XMM18,%YMM22,%YMM18

(158) 0x235c1c VEXTRACTI32X4	$0x1,%YMM23,%XMM22

(158) 0x235c23 VMOVSD	(%R8,%RAX,8),%XMM23

(158) 0x235c2a VMOVQ	%XMM22,%RSI

(158) 0x235c30 VPEXTRQ	$0x1,%XMM22,%RDI

(158) 0x235c37 VMOVHPD	(%R8,%RDX,8),%XMM23,%XMM21

(158) 0x235c3e VMOVSD	(%R8,%RSI,8),%XMM22

(158) 0x235c45 VINSERTF32X4	$0x1,%XMM20,%YMM25,%YMM20

(158) 0x235c4c VMOVHPD	(%R8,%RDI,8),%XMM22,%XMM22

(158) 0x235c53 VFMADD213PD	%YMM17,%YMM18,%YMM20

(158) 0x235c59 VINSERTF32X4	$0x1,%XMM22,%YMM21,%YMM21

(158) 0x235c60 VPADDQ	%YMM16,%YMM26,%YMM22

(158) 0x235c66 VEXTRACTI32X4	$0x1,%YMM22,%XMM19

(158) 0x235c6d VMOVQ	%XMM22,%RDX

(158) 0x235c73 VPEXTRQ	$0x1,%XMM22,%RAX

(158) 0x235c7a VMOVQ	%XMM19,%RSI

(158) 0x235c80 VMOVSD	(%R10,%RDX,8),%XMM18

(158) 0x235c87 VPEXTRQ	$0x1,%XMM19,%RDI

(158) 0x235c8e VPMULLQ	%YMM15,%YMM8,%YMM19

(158) 0x235c94 VMOVSD	(%R10,%RSI,8),%XMM17

(158) 0x235c9b VMOVHPD	(%R10,%RAX,8),%XMM18,%XMM18

(158) 0x235ca2 VMOVHPD	(%R10,%RDI,8),%XMM17,%XMM17

(158) 0x235ca9 VPADDQ	%YMM16,%YMM19,%YMM16

(158) 0x235caf VPADDQ	%YMM14,%YMM19,%YMM19

(158) 0x235cb5 VINSERTF32X4	$0x1,%XMM17,%YMM18,%YMM17

(158) 0x235cbc VPMULLQ	%YMM15,%YMM7,%YMM18

(158) 0x235cc2 VPMULLQ	%YMM15,%YMM9,%YMM15

(158) 0x235cc8 VFMADD213PD	%YMM20,%YMM21,%YMM17

(158) 0x235cce VPADDQ	%YMM14,%YMM18,%YMM18

(158) 0x235cd4 VPADDQ	%YMM14,%YMM15,%YMM14

(158) 0x235cd9 VMOVQ	%XMM18,%RAX

(158) 0x235cdf VPEXTRQ	$0x1,%XMM18,%RDX

(158) 0x235ce6 VEXTRACTI32X4	$0x1,%YMM18,%XMM18

(158) 0x235ced VMOVQ	%XMM18,%RSI

(158) 0x235cf3 VPEXTRQ	$0x1,%XMM18,%RDI

(158) 0x235cfa VMULPD	%YMM12,%YMM17,%YMM17

(158) 0x235d00 VEXTRACTF32X4	$0x1,%YMM17,%XMM18

(158) 0x235d07 VMOVLPD	%XMM17,(%R9,%RAX,8)

(158) 0x235d0e VMOVHPD	%XMM17,(%R9,%RDX,8)

(158) 0x235d15 VMOVQ	%XMM16,%RAX

(158) 0x235d1b VPEXTRQ	$0x1,%XMM16,%RDX

(158) 0x235d22 VEXTRACTI32X4	$0x1,%YMM16,%XMM16

(158) 0x235d29 VMOVLPD	%XMM18,(%R9,%RSI,8)

(158) 0x235d30 VMOVHPD	%XMM18,(%R9,%RDI,8)

(158) 0x235d37 VMOVQ	%XMM16,%RSI

(158) 0x235d3d VPEXTRQ	$0x1,%XMM16,%RDI

(158) 0x235d44 MOV	-0x38(%RBP),%R9

(158) 0x235d48 VMOVSD	(%R14,%RAX,8),%XMM18

(158) 0x235d4f VMOVSD	(%R14,%RSI,8),%XMM16

(158) 0x235d56 VMOVQ	%XMM19,%RAX

(158) 0x235d5c VMOVHPD	(%R14,%RDX,8),%XMM18,%XMM18

(158) 0x235d63 VMOVHPD	(%R14,%RDI,8),%XMM16,%XMM16

(158) 0x235d6a VPEXTRQ	$0x1,%XMM19,%RDX

(158) 0x235d71 VEXTRACTI32X4	$0x1,%YMM19,%XMM19

(158) 0x235d78 VMOVQ	%XMM19,%RDI

(158) 0x235d7e VPEXTRQ	$0x1,%XMM19,%RSI

(158) 0x235d85 VMOVSD	(%R14,%RAX,8),%XMM19

(158) 0x235d8c VPEXTRQ	$0x1,%XMM14,%RAX

(158) 0x235d92 VMOVHPD	(%R14,%RDX,8),%XMM19,%XMM19

(158) 0x235d99 VMOVQ	%XMM14,%RDX

(158) 0x235d9e VEXTRACTI128	$0x1,%YMM14,%XMM14

(158) 0x235da4 VINSERTF32X4	$0x1,%XMM16,%YMM18,%YMM16

(158) 0x235dab VMOVSD	(%R14,%RDI,8),%XMM18

(158) 0x235db2 VPEXTRQ	$0x1,%XMM14,%RDI

(158) 0x235db8 VMOVHPD	(%R14,%RSI,8),%XMM18,%XMM18

(158) 0x235dbf VMOVQ	%XMM14,%RSI

(158) 0x235dc4 VSUBPD	%YMM16,%YMM17,%YMM16

(158) 0x235dca VINSERTF32X4	$0x1,%XMM18,%YMM19,%YMM17

(158) 0x235dd1 VADDPD	%YMM17,%YMM16,%YMM16

(158) 0x235dd7 VMOVLPD	%XMM16,(%R9,%RDX,8)

(158) 0x235dde MOV	-0x38(%RBP),%R9

(158) 0x235de2 VEXTRACTF32X4	$0x1,%YMM16,%XMM14

(158) 0x235de9 VMOVHPD	%XMM16,(%R9,%RAX,8)

(158) 0x235df0 VMOVLPD	%XMM14,(%R9,%RSI,8)

(158) 0x235df6 VMOVHPD	%XMM14,(%R9,%RDI,8)

(158) 0x235dfc JNE	235970

0x235e02 MOV	-0x60(%RBP),%R13

0x235e06 CMP	%R15,-0x78(%RBP)

0x235e0a JE	235f24

0x235e10 VMOVSD	-0x24c88(%RIP),%XMM0

0x235e18 NOPL	(%RAX,%RAX,1)

(157) 0x235e20 MOV	%RCX,%RAX

(157) 0x235e23 CQTO

(157) 0x235e25 MOV	%R12,%R15

(157) 0x235e28 MOV	%RBX,%R12

(157) 0x235e2b IDIVQ	-0x58(%RBP)

(157) 0x235e2f MOV	-0x98(%RBP),%R11

(157) 0x235e36 MOV	-0x80(%RBP),%RBX

(157) 0x235e3a ADD	-0x2c(%RBP),%EDX

(157) 0x235e3d MOV	%R11,%R9

(157) 0x235e40 MOVSXD	%EDX,%RDX

(157) 0x235e43 LEA	(%R13,%RAX,1),%ESI

(157) 0x235e48 ADD	%R12D,%EAX

(157) 0x235e4b MOVSXD	%EAX,%RDI

(157) 0x235e4e IMUL	%RDI,%R9

(157) 0x235e52 IMUL	%RBX,%RDI

(157) 0x235e56 LEA	(%RDI,%RDX,1),%R13

(157) 0x235e5a LEA	(%R9,%RDX,1),%RAX

(157) 0x235e5e LEA	-0x1(%RDI,%RDX,1),%RDI

(157) 0x235e63 VMOVSD	(%R10,%R13,8),%XMM1

(157) 0x235e69 MOV	%RBX,%R13

(157) 0x235e6c VMULSD	(%R8,%RAX,8),%XMM1,%XMM1

(157) 0x235e72 MOVSXD	%ESI,%RAX

(157) 0x235e75 MOV	%R11,%RSI

(157) 0x235e78 MOV	%R12,%R11

(157) 0x235e7b MOV	%R15,%R12

(157) 0x235e7e IMUL	%RAX,%R13

(157) 0x235e82 IMUL	%RAX,%RSI

(157) 0x235e86 LEA	(%R13,%RDX,1),%RBX

(157) 0x235e8b VMOVSD	(%R10,%RBX,8),%XMM2

(157) 0x235e91 LEA	(%RSI,%RDX,1),%RBX

(157) 0x235e95 LEA	-0x1(%RSI,%RDX,1),%RSI

(157) 0x235e9a VFMADD132SD	(%R8,%RBX,8),%XMM1,%XMM2

(157) 0x235ea0 VMOVSD	(%R10,%RDI,8),%XMM1

(157) 0x235ea6 LEA	-0x1(%R9,%RDX,1),%RDI

(157) 0x235eab MOV	-0x90(%RBP),%R9

(157) 0x235eb2 MOV	%R11,%RBX

(157) 0x235eb5 VFMADD132SD	(%R8,%RDI,8),%XMM2,%XMM1

(157) 0x235ebb LEA	-0x1(%R13,%RDX,1),%RDI

(157) 0x235ec0 MOV	-0x60(%RBP),%R13

(157) 0x235ec4 VMOVSD	(%R10,%RDI,8),%XMM2

(157) 0x235eca MOV	-0x68(%RBP),%RDI

(157) 0x235ece VFMADD132SD	(%R8,%RSI,8),%XMM1,%XMM2

(157) 0x235ed4 MOV	%R9,%RSI

(157) 0x235ed7 IMUL	%RAX,%RSI

(157) 0x235edb ADD	%RDX,%RSI

(157) 0x235ede VMULSD	%XMM0,%XMM2,%XMM1

(157) 0x235ee2 VMOVSD	%XMM1,(%RDI,%RSI,8)

(157) 0x235ee7 MOV	-0x88(%RBP),%RSI

(157) 0x235eee IMUL	%RAX,%RSI

(157) 0x235ef2 IMUL	-0x50(%RBP),%RAX

(157) 0x235ef7 LEA	-0x1(%RSI,%RDX,1),%RDI

(157) 0x235efc ADD	%RDX,%RSI

(157) 0x235eff VSUBSD	(%R14,%RDI,8),%XMM1,%XMM1

(157) 0x235f05 ADD	%RDX,%RAX

(157) 0x235f08 MOV	-0x38(%RBP),%RDX

(157) 0x235f0c VADDSD	(%R14,%RSI,8),%XMM1,%XMM1

(157) 0x235f12 VMOVSD	%XMM1,(%RDX,%RAX,8)

(157) 0x235f17 CMP	%R15,%RCX

(157) 0x235f1a LEA	0x1(%RCX),%RCX

(157) 0x235f1e JL	235e20

0x235f24 MOV	-0x44(%RBP),%ESI

0x235f27 LEA	0x24d92(%RIP),%RDI

0x235f2e VZEROUPPER

0x235f31 CALL	259690 <@plt_start@+0x540>

0x235f36 ADD	$0x78,%RSP

0x235f3a POP	%RBX

0x235f3b POP	%R12

0x235f3d POP	%R13

0x235f3f POP	%R14

0x235f41 POP	%R15

0x235f43 POP	%RBP

0x235f44 RET

0x235f45 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run aocc_8

Source file and lines	advec_mom.cpp:95-100
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:95-100

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 16.38 to 6.00 cycles (2.73x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions).

Details

7% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

8% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
16% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
12% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:95
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:95

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVL: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:96
VPBROADCASTD: 3 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:96
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:96
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:96
VPBROADCASTQ: 7 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:96
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:96
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:96
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:96
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:96
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:96
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:96

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 252 bytes. The binary function is storing 124 bytes.

General properties

nb instructions	121
nb uops	131
loop length	522
used x86 registers	16
used mmx registers	0
used xmm registers	6
used ymm registers	9
used zmm registers	0
nb stack references	21

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	16.38 cycles
front end	16.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	6.17	6.17	6.17	6.17	6.17	6.17	12.75	12.75	12.75	12.75	1.00	6.00	6.00	1.00	0.00	0.00
cycles	6.17	6.17	6.17	6.17	6.17	6.17	12.75	12.75	12.75	12.75	1.00	6.00	6.00	1.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	16.38
Dispatch	12.75
Overall L1	16.38

Vectorization ratios

INT

all	7%
load	10%
store	0%
mul	0%
add-sub	16%
fma	NA (no fma vectorizable/vectorized instructions)
other	13%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	7%
load	8%
store	0%
mul	0%
add-sub	16%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Vector efficiency ratios

INT

all	12%
load	14%
store	10%
mul	12%
add-sub	14%
fma	NA (no fma vectorizable/vectorized instructions)
other	13%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	12%
load	14%
store	10%
mul	12%
add-sub	14%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 16.38 cycles. At this rate:

6% of peak load performance is reached (15.39 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (7.57 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 16.38 to 12.75 cycles (1.28x speedup).

ASM code

In the binary file, the address of the function is: 2357b0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x78,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RCX),%R12D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
MOV (%RDX),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
LEA 0x1(%RAX),%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD $0x3,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SUB %R13D,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 235f36 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.10+0x786>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV (%R9),%R15D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
MOV (%R8),%R14D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
ADD $0x4,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CMP %R14D,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 235f36 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.10+0x786>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
SUB %R14D,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOVQ $0,-0x70(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOVQ $0x1,-0xa0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOVL $0,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
IMUL %R15,%R12	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
DEC %R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R12,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x48(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0xa0(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x2547b(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x70(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x40(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %ESI,-0x44(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 259680 <@plt_start@+0x530>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x40(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x70(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
CMP %R12,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMOVL %RAX,%R12	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
MOV %R12,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
CMP %R12,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JG 235f24 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.10+0x774>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x30(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x28(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %R15,-0x58(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R14D,-0x2c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOV 0x20(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x18(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x10(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %R13,-0x60(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RAX),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%RAX),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV (%RDX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV (%R8),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV (%RSI),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x10(%RSI),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV (%R11),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x10(%R11),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x10(%R8),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RAX,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x10(%RDX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RDI,-0x98(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %RSI,-0x90(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R15,-0x88(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R11,-0x68(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R9,-0x80(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %RAX,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R12,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RCX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x4,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JB 235e10 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.10+0x660>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VBROADCASTSD -0x2475b(%RIP),%YMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
VPBROADCASTQ %RCX,%YMM0	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPADDQ -0x24619(%RIP),%YMM0,%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	1	0.50	vect (50.0%)
VPBROADCASTQ -0x24732(%RIP),%YMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	1	0.50	scal (12.5%)
MOV %RAX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,-0x78(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV -0x58(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x2c(%RBP),%R11D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VPBROADCASTQ %RSI,%YMM7	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
MOV -0x50(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
AND $-0x4,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VPBROADCASTD %R13D,%XMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (6.3%)
VPBROADCASTQ %R15,%YMM8	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPBROADCASTD %EBX,%XMM4	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (6.3%)
VPBROADCASTQ %RDI,%YMM5	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPBROADCASTQ %R9,%YMM6	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPCMPEQD %XMM11,%XMM11,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (25.0%)
ADD %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RDX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
VPBROADCASTQ %RAX,%YMM1	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPBROADCASTD %R11D,%XMM3	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (6.3%)
VPBROADCASTQ %RSI,%YMM9	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VEXTRACTI128 $0x1,%YMM1,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	3	0.50	vect (25.0%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0x60(%RBP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
CMP %R15,-0x78(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JE 235f24 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.10+0x774>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVSD -0x24c88(%RIP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0x44(%RBP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
LEA 0x24d92(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 259690 <@plt_start@+0x540>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
ADD $0x78,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run aocc_8

Source file and lines	advec_mom.cpp:95-100
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:95-100

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 16.38 to 6.00 cycles (2.73x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions).

Details

7% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

8% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
16% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
12% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:95
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:95

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVL: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:96
VPBROADCASTD: 3 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:96
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:96
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:96
VPBROADCASTQ: 7 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:96
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:96
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:96
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:96
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:96
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:96
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:96

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 252 bytes. The binary function is storing 124 bytes.

General properties

nb instructions	121
nb uops	131
loop length	522
used x86 registers	16
used mmx registers	0
used xmm registers	6
used ymm registers	9
used zmm registers	0
nb stack references	21

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	16.38 cycles
front end	16.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	6.17	6.17	6.17	6.17	6.17	6.17	12.75	12.75	12.75	12.75	1.00	6.00	6.00	1.00	0.00	0.00
cycles	6.17	6.17	6.17	6.17	6.17	6.17	12.75	12.75	12.75	12.75	1.00	6.00	6.00	1.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	16.38
Dispatch	12.75
Overall L1	16.38

Vectorization ratios

INT

all	7%
load	10%
store	0%
mul	0%
add-sub	16%
fma	NA (no fma vectorizable/vectorized instructions)
other	13%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	7%
load	8%
store	0%
mul	0%
add-sub	16%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Vector efficiency ratios

INT

all	12%
load	14%
store	10%
mul	12%
add-sub	14%
fma	NA (no fma vectorizable/vectorized instructions)
other	13%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	12%
load	14%
store	10%
mul	12%
add-sub	14%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 16.38 cycles. At this rate:

6% of peak load performance is reached (15.39 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (7.57 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 2357b0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x78,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RCX),%R12D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
MOV (%RDX),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
LEA 0x1(%RAX),%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD $0x3,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SUB %R13D,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 235f36 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.10+0x786>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV (%R9),%R15D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
MOV (%R8),%R14D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
ADD $0x4,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CMP %R14D,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 235f36 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.10+0x786>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
SUB %R14D,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOVQ $0,-0x70(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOVQ $0x1,-0xa0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOVL $0,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
IMUL %R15,%R12	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
DEC %R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R12,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x48(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0xa0(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x2547b(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x70(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x40(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %ESI,-0x44(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 259680 <@plt_start@+0x530>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x40(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x70(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
CMP %R12,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMOVL %RAX,%R12	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
MOV %R12,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
CMP %R12,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JG 235f24 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.10+0x774>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x30(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x28(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %R15,-0x58(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R14D,-0x2c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOV 0x20(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x18(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x10(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %R13,-0x60(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RAX),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%RAX),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV (%RDX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV (%R8),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV (%RSI),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x10(%RSI),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV (%R11),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x10(%R11),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x10(%R8),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RAX,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x10(%RDX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RDI,-0x98(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %RSI,-0x90(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R15,-0x88(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R11,-0x68(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R9,-0x80(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %RAX,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R12,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RCX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x4,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JB 235e10 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.10+0x660>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VBROADCASTSD -0x2475b(%RIP),%YMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
VPBROADCASTQ %RCX,%YMM0	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPADDQ -0x24619(%RIP),%YMM0,%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	1	0.50	vect (50.0%)
VPBROADCASTQ -0x24732(%RIP),%YMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	1	0.50	scal (12.5%)
MOV %RAX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,-0x78(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV -0x58(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x2c(%RBP),%R11D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VPBROADCASTQ %RSI,%YMM7	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
MOV -0x50(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
AND $-0x4,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VPBROADCASTD %R13D,%XMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (6.3%)
VPBROADCASTQ %R15,%YMM8	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPBROADCASTD %EBX,%XMM4	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (6.3%)
VPBROADCASTQ %RDI,%YMM5	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPBROADCASTQ %R9,%YMM6	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPCMPEQD %XMM11,%XMM11,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (25.0%)
ADD %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RDX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
VPBROADCASTQ %RAX,%YMM1	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPBROADCASTD %R11D,%XMM3	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (6.3%)
VPBROADCASTQ %RSI,%YMM9	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VEXTRACTI128 $0x1,%YMM1,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	3	0.50	vect (25.0%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0x60(%RBP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
CMP %R15,-0x78(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JE 235f24 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.10+0x774>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVSD -0x24c88(%RIP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0x44(%RBP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
LEA 0x24d92(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 259690 <@plt_start@+0x540>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
ADD $0x78,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	3.08	1.15
○Loop 158 - advec_mom.cpp:96-100 - exec	3.08	1.15
○Loop 157 - advec_mom.cpp:96-100 - exec	0.00	0.00

Report Configuration

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512-bits vectorization

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Matching between your function (in the source code) and the binary function

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ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code