OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone .omp

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: advec_mom.cpp:71-75 [...]	Coverage (incl. loops): 2.63% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 71 - 75

--------------------------------------------------------------------------------

71: #pragma omp parallel for simd collapse(2)

72:     for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) {

73:       for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) {

74:         post_vol(i, j) = volume(i, j);

75:         pre_vol(i, j) = post_vol(i, j) + vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j);

0x234ee0 PUSH	%RBP

0x234ee1 MOV	%RSP,%RBP

0x234ee4 PUSH	%R15

0x234ee6 PUSH	%R14

0x234ee8 PUSH	%R13

0x234eea PUSH	%R12

0x234eec PUSH	%RBX

0x234eed SUB	$0x68,%RSP

0x234ef1 MOV	(%RCX),%R15D

0x234ef4 MOV	(%RDX),%EDX

0x234ef6 ADD	$0x4,%R15D

0x234efa CMP	%R15D,%EDX

0x234efd JG	23532b

0x234f03 MOV	(%R9),%R13D

0x234f06 MOV	(%R8),%EAX

0x234f09 ADD	$0x4,%R13D

0x234f0d CMP	%R13D,%EAX

0x234f10 JG	23532b

0x234f16 DEC	%EDX

0x234f18 LEA	-0x1(%RAX),%EBX

0x234f1b MOV	(%RDI),%ESI

0x234f1d MOVQ	$0,-0x50(%RBP)

0x234f25 MOVQ	$0x1,-0x88(%RBP)

0x234f30 MOVL	$0,-0x40(%RBP)

0x234f37 SUB	%EBX,%R13D

0x234f3a SUB	%EDX,%R15D

0x234f3d IMUL	%R13,%R15

0x234f41 DEC	%R15

0x234f44 MOV	%R15,-0x38(%RBP)

0x234f48 SUB	$0x8,%RSP

0x234f4c LEA	-0x40(%RBP),%RCX

0x234f50 MOV	%RAX,%R14

0x234f53 MOV	%EDX,%R12D

0x234f56 LEA	-0x88(%RBP),%RAX

0x234f5d LEA	0x25cb4(%RIP),%RDI

0x234f64 LEA	-0x50(%RBP),%R8

0x234f68 LEA	-0x38(%RBP),%R9

0x234f6c MOV	%ESI,-0x3c(%RBP)

0x234f6f MOV	$0x22,%EDX

0x234f74 PUSH	$0x1

0x234f76 PUSH	$0x1

0x234f78 PUSH	%RAX

0x234f79 CALL	259680 <@plt_start@+0x530>

0x234f7e ADD	$0x20,%RSP

0x234f82 MOV	-0x38(%RBP),%RAX

0x234f86 MOV	-0x50(%RBP),%RCX

0x234f8a CMP	%R15,%RAX

0x234f8d CMOVL	%RAX,%R15

0x234f91 MOV	%R15,-0x38(%RBP)

0x234f95 CMP	%R15,%RCX

0x234f98 JG	235319

0x234f9e MOV	0x18(%RBP),%RSI

0x234fa2 MOV	0x28(%RBP),%RAX

0x234fa6 MOV	0x10(%RBP),%R8

0x234faa MOV	0x20(%RBP),%RDX

0x234fae MOV	%R12D,-0x2c(%RBP)

0x234fb2 MOV	%R14,-0x48(%RBP)

0x234fb6 MOV	(%RAX),%R12

0x234fb9 MOV	0x10(%RAX),%R11

0x234fbd MOV	(%RSI),%R10

0x234fc0 MOV	0x10(%RSI),%RDI

0x234fc4 MOV	(%R8),%RSI

0x234fc7 MOV	0x10(%R8),%R9

0x234fcb MOV	(%RDX),%R14

0x234fce MOV	0x10(%RDX),%R8

0x234fd2 MOV	%R15,%RAX

0x234fd5 SUB	%RCX,%RAX

0x234fd8 INC	%RAX

0x234fdb MOV	%RSI,-0x80(%RBP)

0x234fdf MOV	%R12,-0x78(%RBP)

0x234fe3 CMP	$0x4,%RAX

0x234fe7 JB	2352a0

0x234fed MOV	%RAX,%RDX

0x234ff0 MOV	%RAX,-0x58(%RBP)

0x234ff4 MOV	-0x2c(%RBP),%EAX

0x234ff7 VPBROADCASTQ	%RCX,%YMM0

0x234ffd VPADDQ	-0x23d25(%RIP),%YMM0,%YMM0

0x235005 VPBROADCASTQ	-0x23e3e(%RIP),%YMM10

0x23500e AND	$-0x4,%RDX

0x235012 VPBROADCASTQ	%R13,%YMM1

0x235018 VPBROADCASTQ	%RSI,%YMM5

0x23501e VPBROADCASTD	%EBX,%XMM3

0x235024 VPBROADCASTQ	%R10,%YMM4

0x23502a VPBROADCASTQ	%R12,%YMM7

0x235030 VPBROADCASTQ	%R14,%YMM8

0x235036 MOV	%R14,-0x68(%RBP)

0x23503a MOV	%RBX,-0x70(%RBP)

0x23503e MOV	%R10,-0x60(%RBP)

0x235042 ADD	%RDX,%RCX

0x235045 VEXTRACTI128	$0x1,%YMM1,%XMM9

0x23504b MOV	%RDX,%R14

0x23504e MOV	%RDX,%RSI

0x235051 VPBROADCASTD	%EAX,%XMM2

0x235057 MOV	-0x48(%RBP),%RAX

0x23505b VPBROADCASTD	%EAX,%XMM6

0x235061 NOPW	%CS:(%RAX,%RAX,1)

(154) 0x235070 VEXTRACTI128	$0x1,%YMM0,%XMM11

(154) 0x235076 VPEXTRQ	$0x1,%XMM9,%R10

(154) 0x23507c VPEXTRQ	$0x1,%XMM11,%RAX

(154) 0x235082 CQTO

(154) 0x235084 IDIV	%R10

(154) 0x235087 VMOVQ	%XMM9,%R10

(154) 0x23508c VMOVQ	%RAX,%XMM12

(154) 0x235091 VMOVQ	%XMM11,%RAX

(154) 0x235096 CQTO

(154) 0x235098 IDIV	%R10

(154) 0x23509b VPEXTRQ	$0x1,%XMM1,%R10

(154) 0x2350a1 VMOVQ	%RAX,%XMM11

(154) 0x2350a6 VPEXTRQ	$0x1,%XMM0,%RAX

(154) 0x2350ac CQTO

(154) 0x2350ae VPUNPCKLQDQ	%XMM12,%XMM11,%XMM11

(154) 0x2350b3 IDIV	%R10

(154) 0x2350b6 VMOVQ	%XMM1,%R10

(154) 0x2350bb VMOVQ	%RAX,%XMM12

(154) 0x2350c0 VMOVQ	%XMM0,%RAX

(154) 0x2350c5 CQTO

(154) 0x2350c7 IDIV	%R10

(154) 0x2350ca ADD	$-0x4,%RSI

(154) 0x2350ce VMOVQ	%RAX,%XMM13

(154) 0x2350d3 VPUNPCKLQDQ	%XMM12,%XMM13,%XMM12

(154) 0x2350d8 VINSERTI128	$0x1,%XMM11,%YMM12,%YMM11

(154) 0x2350de VPMOVQD	%YMM11,%XMM12

(154) 0x2350e4 VPMULLQ	%YMM1,%YMM11,%YMM11

(154) 0x2350ea VPSUBQ	%YMM11,%YMM0,%YMM11

(154) 0x2350ef VPADDQ	%YMM0,%YMM10,%YMM0

(154) 0x2350f3 VPMOVQD	%YMM11,%XMM11

(154) 0x2350f9 VPADDD	%XMM2,%XMM12,%XMM12

(154) 0x2350fd VPMOVSXDQ	%XMM12,%YMM12

(154) 0x235102 VPMULLQ	%YMM12,%YMM4,%YMM14

(154) 0x235108 VPADDD	%XMM3,%XMM11,%XMM13

(154) 0x23510c VPADDD	%XMM6,%XMM11,%XMM11

(154) 0x235110 VPMOVSXDQ	%XMM13,%YMM13

(154) 0x235115 VPMOVSXDQ	%XMM11,%YMM11

(154) 0x23511a VPADDQ	%YMM13,%YMM14,%YMM14

(154) 0x23511f VPEXTRQ	$0x1,%XMM14,%RAX

(154) 0x235125 VMOVQ	%XMM14,%RDX

(154) 0x23512a VEXTRACTI128	$0x1,%YMM14,%XMM14

(154) 0x235130 VMOVQ	%XMM14,%R10

(154) 0x235135 VPEXTRQ	$0x1,%XMM14,%RBX

(154) 0x23513b VMOVSD	(%RDI,%RDX,8),%XMM14

(154) 0x235140 VMOVSD	(%RDI,%RAX,8),%XMM15

(154) 0x235145 VMOVSD	(%RDI,%R10,8),%XMM16

(154) 0x23514c VMOVSD	(%RDI,%RBX,8),%XMM17

(154) 0x235153 VUNPCKLPD	%XMM15,%XMM14,%XMM19

(154) 0x235159 VUNPCKLPD	%XMM17,%XMM16,%XMM18

(154) 0x23515f VINSERTF32X4	$0x1,%XMM18,%YMM19,%YMM18

(154) 0x235166 VPMULLQ	%YMM12,%YMM5,%YMM19

(154) 0x23516c VPADDQ	%YMM13,%YMM19,%YMM19

(154) 0x235172 VMOVQ	%XMM19,%RAX

(154) 0x235178 VPEXTRQ	$0x1,%XMM19,%RDX

(154) 0x23517f VEXTRACTI32X4	$0x1,%YMM19,%XMM19

(154) 0x235186 VMOVSD	%XMM14,(%R9,%RAX,8)

(154) 0x23518c VPMULLQ	%YMM12,%YMM7,%YMM14

(154) 0x235192 VMOVQ	%XMM19,%R10

(154) 0x235198 VMOVSD	%XMM15,(%R9,%RDX,8)

(154) 0x23519e VPEXTRQ	$0x1,%XMM19,%RBX

(154) 0x2351a5 VPMULLQ	%YMM12,%YMM8,%YMM12

(154) 0x2351ab VMOVSD	%XMM16,(%R9,%R10,8)

(154) 0x2351b2 VMOVSD	%XMM17,(%R9,%RBX,8)

(154) 0x2351b9 VPADDQ	%YMM11,%YMM14,%YMM11

(154) 0x2351be VPADDQ	%YMM13,%YMM14,%YMM14

(154) 0x2351c3 VPADDQ	%YMM13,%YMM12,%YMM12

(154) 0x2351c8 VMOVQ	%XMM11,%RAX

(154) 0x2351cd VPEXTRQ	$0x1,%XMM11,%RDX

(154) 0x2351d3 VEXTRACTI128	$0x1,%YMM11,%XMM11

(154) 0x2351d9 VMOVQ	%XMM11,%R10

(154) 0x2351de VMOVSD	(%R11,%RAX,8),%XMM15

(154) 0x2351e4 VPEXTRQ	$0x1,%XMM11,%RBX

(154) 0x2351ea VMOVQ	%XMM14,%RAX

(154) 0x2351ef VMOVSD	(%R11,%R10,8),%XMM11

(154) 0x2351f5 VMOVHPD	(%R11,%RDX,8),%XMM15,%XMM15

(154) 0x2351fb VPEXTRQ	$0x1,%XMM14,%RDX

(154) 0x235201 VEXTRACTI128	$0x1,%YMM14,%XMM14

(154) 0x235207 VMOVHPD	(%R11,%RBX,8),%XMM11,%XMM11

(154) 0x23520d VMOVQ	%XMM14,%R10

(154) 0x235212 VPEXTRQ	$0x1,%XMM14,%RBX

(154) 0x235218 VMOVSD	(%R11,%R10,8),%XMM14

(154) 0x23521e VMOVHPD	(%R11,%RBX,8),%XMM14,%XMM14

(154) 0x235224 VINSERTF128	$0x1,%XMM11,%YMM15,%YMM11

(154) 0x23522a VMOVSD	(%R11,%RAX,8),%XMM15

(154) 0x235230 VPEXTRQ	$0x1,%XMM12,%RAX

(154) 0x235236 VMOVHPD	(%R11,%RDX,8),%XMM15,%XMM15

(154) 0x23523c VMOVQ	%XMM12,%RDX

(154) 0x235241 VEXTRACTI128	$0x1,%YMM12,%XMM12

(154) 0x235247 VADDPD	%YMM18,%YMM11,%YMM11

(154) 0x23524d VMOVQ	%XMM12,%R10

(154) 0x235252 VPEXTRQ	$0x1,%XMM12,%RBX

(154) 0x235258 VINSERTF128	$0x1,%XMM14,%YMM15,%YMM14

(154) 0x23525e VSUBPD	%YMM14,%YMM11,%YMM11

(154) 0x235263 VMOVLPD	%XMM11,(%R8,%RDX,8)

(154) 0x235269 VMOVHPD	%XMM11,(%R8,%RAX,8)

(154) 0x23526f VEXTRACTF128	$0x1,%YMM11,%XMM11

(154) 0x235275 VMOVLPD	%XMM11,(%R8,%R10,8)

(154) 0x23527b VMOVHPD	%XMM11,(%R8,%RBX,8)

(154) 0x235281 JNE	235070

0x235287 MOV	-0x70(%RBP),%RBX

0x23528b MOV	-0x60(%RBP),%R10

0x23528f CMP	%R14,-0x58(%RBP)

0x235293 MOV	-0x68(%RBP),%R14

0x235297 JE	235319

0x23529d NOPL	(%RAX)

(153) 0x2352a0 MOV	%RCX,%RAX

(153) 0x2352a3 CQTO

(153) 0x2352a5 MOV	%R13,%R12

(153) 0x2352a8 IDIV	%R13

(153) 0x2352ab MOV	%RBX,%R13

(153) 0x2352ae LEA	(%RBX,%RDX,1),%ESI

(153) 0x2352b1 MOV	%R10,%RBX

(153) 0x2352b4 ADD	-0x48(%RBP),%EDX

(153) 0x2352b7 MOVSXD	%ESI,%RSI

(153) 0x2352ba MOVSXD	%EDX,%RDX

(153) 0x2352bd ADD	-0x2c(%RBP),%EAX

(153) 0x2352c0 CLTQ

(153) 0x2352c2 IMUL	%RAX,%R10

(153) 0x2352c6 ADD	%RSI,%R10

(153) 0x2352c9 VMOVSD	(%RDI,%R10,8),%XMM0

(153) 0x2352cf MOV	-0x80(%RBP),%R10

(153) 0x2352d3 IMUL	%RAX,%R10

(153) 0x2352d7 ADD	%RSI,%R10

(153) 0x2352da VMOVSD	%XMM0,(%R9,%R10,8)

(153) 0x2352e0 MOV	-0x78(%RBP),%R10

(153) 0x2352e4 IMUL	%RAX,%R10

(153) 0x2352e8 IMUL	%R14,%RAX

(153) 0x2352ec ADD	%R10,%RDX

(153) 0x2352ef ADD	%RSI,%R10

(153) 0x2352f2 ADD	%RSI,%RAX

(153) 0x2352f5 VADDSD	(%R11,%RDX,8),%XMM0,%XMM0

(153) 0x2352fb VSUBSD	(%R11,%R10,8),%XMM0,%XMM0

(153) 0x235301 MOV	%RBX,%R10

(153) 0x235304 MOV	%R13,%RBX

(153) 0x235307 MOV	%R12,%R13

(153) 0x23530a VMOVSD	%XMM0,(%R8,%RAX,8)

(153) 0x235310 CMP	%R15,%RCX

(153) 0x235313 LEA	0x1(%RCX),%RCX

(153) 0x235317 JL	2352a0

0x235319 MOV	-0x3c(%RBP),%ESI

0x23531c LEA	0x2590d(%RIP),%RDI

0x235323 VZEROUPPER

0x235326 CALL	259690 <@plt_start@+0x540>

0x23532b ADD	$0x68,%RSP

0x23532f POP	%RBX

0x235330 POP	%R12

0x235332 POP	%R13

0x235334 POP	%R14

0x235336 POP	%R15

0x235338 POP	%RBP

0x235339 RET

0x23533a NOPW	(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run aocc_8

Source file and lines	advec_mom.cpp:71-75
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:71-75

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 15.50 to 5.50 cycles (2.82x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions).

Details

5% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

8% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
16% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
9% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:71
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:71

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVL: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:72
VPBROADCASTD: 3 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:72
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:72
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:72
VPBROADCASTQ: 6 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:72
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:72
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:72
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:72
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:72
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:72

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 220 bytes. The binary function is storing 100 bytes.

General properties

nb instructions	115
nb uops	124
loop length	464
used x86 registers	16
used mmx registers	0
used xmm registers	4
used ymm registers	7
used zmm registers	0
nb stack references	17

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.50 cycles
front end	15.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	6.50	6.50	6.50	6.50	6.50	6.50	11.00	11.00	11.00	11.00	0.50	5.50	5.50	0.50	0.00	0.00
cycles	6.50	6.50	6.50	6.50	6.50	6.50	11.00	11.00	11.00	11.00	0.50	5.50	5.50	0.50	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	15.50
Dispatch	11.00
Overall L1	15.50

Vectorization ratios

all	5%
load	8%
store	0%
mul	0%
add-sub	16%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	9%

Vector efficiency ratios

all	11%
load	14%
store	10%
mul	12%
add-sub	14%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 15.50 cycles. At this rate:

5% of peak load performance is reached (14.19 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (6.45 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 15.50 to 11.00 cycles (1.41x speedup).

ASM code

In the binary file, the address of the function is: 234ee0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x68,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RCX),%R15D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
MOV (%RDX),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
ADD $0x4,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CMP %R15D,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 23532b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.6+0x44b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV (%R9),%R13D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
MOV (%R8),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
ADD $0x4,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CMP %R13D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 23532b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.6+0x44b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
DEC %EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x1(%RAX),%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVQ $0,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOVQ $0x1,-0x88(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOVL $0,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
SUB %EBX,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SUB %EDX,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
IMUL %R13,%R15	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
DEC %R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R15,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x40(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RAX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %EDX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
LEA -0x88(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x25cb4(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x50(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x38(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %ESI,-0x3c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 259680 <@plt_start@+0x530>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x38(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x50(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
CMP %R15,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMOVL %RAX,%R15	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
MOV %R15,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
CMP %R15,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JG 235319 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.6+0x439>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x18(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x28(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x10(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x20(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %R12D,-0x2c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOV %R14,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RAX),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%RAX),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV (%RSI),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%RSI),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV (%R8),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x10(%R8),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV (%RDX),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%RDX),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %R15,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RCX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSI,-0x80(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R12,-0x78(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
CMP $0x4,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JB 2352a0 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.6+0x3c0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RAX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,-0x58(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV -0x2c(%RBP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VPBROADCASTQ %RCX,%YMM0	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPADDQ -0x23d25(%RIP),%YMM0,%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	1	0.50	vect (50.0%)
VPBROADCASTQ -0x23e3e(%RIP),%YMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	1	0.50	scal (12.5%)
AND $-0x4,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VPBROADCASTQ %R13,%YMM1	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPBROADCASTQ %RSI,%YMM5	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPBROADCASTD %EBX,%XMM3	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (6.3%)
VPBROADCASTQ %R10,%YMM4	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPBROADCASTQ %R12,%YMM7	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPBROADCASTQ %R14,%YMM8	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
MOV %R14,-0x68(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %RBX,-0x70(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R10,-0x60(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
ADD %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VEXTRACTI128 $0x1,%YMM1,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	3	0.50	vect (25.0%)
MOV %RDX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RDX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTD %EAX,%XMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (6.3%)
MOV -0x48(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VPBROADCASTD %EAX,%XMM6	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (6.3%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0x70(%RBP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV -0x60(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
CMP %R14,-0x58(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
MOV -0x68(%RBP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
JE 235319 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.6+0x439>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0x3c(%RBP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
LEA 0x2590d(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 259690 <@plt_start@+0x540>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
ADD $0x68,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run aocc_8

Source file and lines	advec_mom.cpp:71-75
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:71-75

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 15.50 to 5.50 cycles (2.82x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions).

Details

5% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

8% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
16% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
9% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:71
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:71

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVL: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:72
VPBROADCASTD: 3 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:72
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:72
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:72
VPBROADCASTQ: 6 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:72
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:72
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:72
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:72
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:72
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:72

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 220 bytes. The binary function is storing 100 bytes.

General properties

nb instructions	115
nb uops	124
loop length	464
used x86 registers	16
used mmx registers	0
used xmm registers	4
used ymm registers	7
used zmm registers	0
nb stack references	17

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.50 cycles
front end	15.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	6.50	6.50	6.50	6.50	6.50	6.50	11.00	11.00	11.00	11.00	0.50	5.50	5.50	0.50	0.00	0.00
cycles	6.50	6.50	6.50	6.50	6.50	6.50	11.00	11.00	11.00	11.00	0.50	5.50	5.50	0.50	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	15.50
Dispatch	11.00
Overall L1	15.50

Vectorization ratios

all	5%
load	8%
store	0%
mul	0%
add-sub	16%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	9%

Vector efficiency ratios

all	11%
load	14%
store	10%
mul	12%
add-sub	14%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 15.50 cycles. At this rate:

5% of peak load performance is reached (14.19 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (6.45 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 234ee0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x68,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RCX),%R15D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
MOV (%RDX),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
ADD $0x4,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CMP %R15D,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 23532b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.6+0x44b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV (%R9),%R13D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
MOV (%R8),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
ADD $0x4,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CMP %R13D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 23532b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.6+0x44b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
DEC %EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x1(%RAX),%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVQ $0,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOVQ $0x1,-0x88(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOVL $0,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
SUB %EBX,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SUB %EDX,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
IMUL %R13,%R15	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
DEC %R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R15,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x40(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RAX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %EDX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
LEA -0x88(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x25cb4(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x50(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x38(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %ESI,-0x3c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 259680 <@plt_start@+0x530>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x38(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x50(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
CMP %R15,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMOVL %RAX,%R15	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
MOV %R15,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
CMP %R15,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JG 235319 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.6+0x439>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x18(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x28(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x10(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x20(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %R12D,-0x2c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOV %R14,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RAX),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%RAX),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV (%RSI),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%RSI),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV (%R8),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x10(%R8),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV (%RDX),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%RDX),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %R15,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RCX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSI,-0x80(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R12,-0x78(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
CMP $0x4,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JB 2352a0 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.6+0x3c0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RAX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,-0x58(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV -0x2c(%RBP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VPBROADCASTQ %RCX,%YMM0	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPADDQ -0x23d25(%RIP),%YMM0,%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	1	0.50	vect (50.0%)
VPBROADCASTQ -0x23e3e(%RIP),%YMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	1	0.50	scal (12.5%)
AND $-0x4,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VPBROADCASTQ %R13,%YMM1	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPBROADCASTQ %RSI,%YMM5	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPBROADCASTD %EBX,%XMM3	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (6.3%)
VPBROADCASTQ %R10,%YMM4	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPBROADCASTQ %R12,%YMM7	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPBROADCASTQ %R14,%YMM8	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
MOV %R14,-0x68(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %RBX,-0x70(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R10,-0x60(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
ADD %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VEXTRACTI128 $0x1,%YMM1,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	3	0.50	vect (25.0%)
MOV %RDX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RDX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTD %EAX,%XMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (6.3%)
MOV -0x48(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VPBROADCASTD %EAX,%XMM6	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (6.3%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0x70(%RBP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV -0x60(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
CMP %R14,-0x58(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
MOV -0x68(%RBP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
JE 235319 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.6+0x439>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0x3c(%RBP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
LEA 0x2590d(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 259690 <@plt_start@+0x540>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
ADD $0x68,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	2.63	0.98
○Loop 154 - advec_mom.cpp:72-75 - exec	2.63	0.98
○Loop 153 - advec_mom.cpp:72-75 - exec	0.00	0.00

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Execution units bottlenecks

512-bits vectorization

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Complex instructions

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Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code