OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone .omp

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: advec_mom.cpp:53-57 [...]	Coverage (incl. loops): 2.99% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 53 - 57

--------------------------------------------------------------------------------

53: #pragma omp parallel for simd collapse(2)

54:     for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) {

55:       for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) {

56:         post_vol(i, j) = volume(i, j) + vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j);

57:         pre_vol(i, j) = post_vol(i, j) + vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j);

0x2344d0 PUSH	%RBP

0x2344d1 MOV	%RSP,%RBP

0x2344d4 PUSH	%R15

0x2344d6 PUSH	%R14

0x2344d8 PUSH	%R13

0x2344da PUSH	%R12

0x2344dc PUSH	%RBX

0x2344dd SUB	$0x78,%RSP

0x2344e1 MOV	(%RCX),%R15D

0x2344e4 MOV	(%RDX),%EBX

0x2344e6 ADD	$0x4,%R15D

0x2344ea CMP	%R15D,%EBX

0x2344ed JG	234a59

0x2344f3 MOV	(%R9),%ECX

0x2344f6 MOV	(%R8),%EAX

0x2344f9 ADD	$0x4,%ECX

0x2344fc CMP	%ECX,%EAX

0x2344fe JG	234a59

0x234504 LEA	-0x1(%RBX),%R12D

0x234508 LEA	-0x1(%RAX),%R14D

0x23450c MOV	(%RDI),%ESI

0x23450e MOVQ	$0,-0x70(%RBP)

0x234516 MOVQ	$0x1,-0xa0(%RBP)

0x234521 MOVL	$0,-0x48(%RBP)

0x234528 SUB	%R14D,%ECX

0x23452b SUB	%R12D,%R15D

0x23452e IMUL	%RCX,%R15

0x234532 DEC	%R15

0x234535 MOV	%R15,-0x40(%RBP)

0x234539 SUB	$0x8,%RSP

0x23453d MOV	%RCX,%R13

0x234540 LEA	-0x48(%RBP),%RCX

0x234544 MOV	%RAX,-0x68(%RBP)

0x234548 LEA	-0xa0(%RBP),%RAX

0x23454f LEA	0x26632(%RIP),%RDI

0x234556 LEA	-0x70(%RBP),%R8

0x23455a LEA	-0x40(%RBP),%R9

0x23455e MOV	%ESI,-0x44(%RBP)

0x234561 MOV	$0x22,%EDX

0x234566 PUSH	$0x1

0x234568 PUSH	$0x1

0x23456a PUSH	%RAX

0x23456b CALL	259680 <@plt_start@+0x530>

0x234570 ADD	$0x20,%RSP

0x234574 MOV	-0x40(%RBP),%RAX

0x234578 MOV	-0x70(%RBP),%RCX

0x23457c CMP	%R15,%RAX

0x23457f CMOVL	%RAX,%R15

0x234583 MOV	%R15,-0x40(%RBP)

0x234587 CMP	%R15,%RCX

0x23458a JG	234a47

0x234590 MOV	0x20(%RBP),%RSI

0x234594 MOV	0x28(%RBP),%RDX

0x234598 MOV	0x10(%RBP),%R8

0x23459c MOV	0x30(%RBP),%RAX

0x2345a0 MOV	0x18(%RBP),%RDI

0x2345a4 MOV	%R13,-0x30(%RBP)

0x2345a8 MOV	%R14,-0x38(%RBP)

0x2345ac MOV	%RBX,-0x98(%RBP)

0x2345b3 MOV	%R12,-0x60(%RBP)

0x2345b7 MOV	(%RSI),%R9

0x2345ba MOV	(%RDI),%R14

0x2345bd MOV	0x10(%RDI),%RDI

0x2345c1 MOV	0x10(%R8),%R11

0x2345c5 MOV	(%RAX),%R13

0x2345c8 MOV	0x10(%RDX),%R10

0x2345cc MOV	%R9,-0x58(%RBP)

0x2345d0 MOV	0x10(%RSI),%R9

0x2345d4 MOV	(%R8),%RSI

0x2345d7 MOV	0x10(%RAX),%R8

0x2345db MOV	(%RDX),%RAX

0x2345de MOV	%R15,%RDX

0x2345e1 SUB	%RCX,%RDX

0x2345e4 MOV	%R14,-0x90(%RBP)

0x2345eb INC	%RDX

0x2345ee MOV	%RSI,-0x88(%RBP)

0x2345f5 MOV	%RAX,-0x50(%RBP)

0x2345f9 CMP	$0x4,%RDX

0x2345fd JAE	23460c

0x2345ff MOV	-0x38(%RBP),%RSI

0x234603 MOV	-0x30(%RBP),%RBX

0x234607 JMP	2349a0

0x23460c MOV	-0x30(%RBP),%RAX

0x234610 VPBROADCASTQ	%RCX,%YMM0

0x234616 VPADDQ	-0x2333e(%RIP),%YMM0,%YMM0

0x23461e VPBROADCASTQ	-0x23457(%RIP),%YMM12

0x234627 VPBROADCASTQ	%R14,%YMM4

0x23462d MOV	-0x58(%RBP),%R14

0x234631 VPBROADCASTD	%EBX,%XMM8

0x234637 MOV	-0x50(%RBP),%RBX

0x23463b MOV	%RDX,-0x78(%RBP)

0x23463f AND	$-0x4,%RDX

0x234643 VPBROADCASTQ	%RSI,%YMM7

0x234649 VPBROADCASTD	%R12D,%XMM2

0x23464f VPBROADCASTQ	%R13,%YMM9

0x234655 MOV	%R13,-0x80(%RBP)

0x234659 ADD	%RDX,%RCX

0x23465c MOV	%RDX,%RSI

0x23465f VPBROADCASTQ	%RAX,%YMM1

0x234665 MOV	-0x38(%RBP),%RAX

0x234669 VPBROADCASTQ	%RBX,%YMM10

0x23466f VPBROADCASTQ	%R14,%YMM6

0x234675 MOV	%RDX,%RBX

0x234678 VEXTRACTI128	$0x1,%YMM1,%XMM11

0x23467e VPBROADCASTD	%EAX,%XMM3

0x234684 MOV	-0x68(%RBP),%RAX

0x234688 VPBROADCASTD	%EAX,%XMM5

0x23468e XCHG	%AX,%AX

(149) 0x234690 VEXTRACTI128	$0x1,%YMM0,%XMM13

(149) 0x234696 VPEXTRQ	$0x1,%XMM11,%R12

(149) 0x23469c VPEXTRQ	$0x1,%XMM13,%RAX

(149) 0x2346a2 CQTO

(149) 0x2346a4 IDIV	%R12

(149) 0x2346a7 VMOVQ	%XMM11,%R12

(149) 0x2346ac VMOVQ	%RAX,%XMM14

(149) 0x2346b1 VMOVQ	%XMM13,%RAX

(149) 0x2346b6 CQTO

(149) 0x2346b8 IDIV	%R12

(149) 0x2346bb VPEXTRQ	$0x1,%XMM1,%R12

(149) 0x2346c1 VMOVQ	%RAX,%XMM13

(149) 0x2346c6 VPEXTRQ	$0x1,%XMM0,%RAX

(149) 0x2346cc CQTO

(149) 0x2346ce VPUNPCKLQDQ	%XMM14,%XMM13,%XMM13

(149) 0x2346d3 IDIV	%R12

(149) 0x2346d6 VMOVQ	%XMM1,%R12

(149) 0x2346db VMOVQ	%RAX,%XMM14

(149) 0x2346e0 VMOVQ	%XMM0,%RAX

(149) 0x2346e5 CQTO

(149) 0x2346e7 IDIV	%R12

(149) 0x2346ea ADD	$-0x4,%RBX

(149) 0x2346ee VMOVQ	%RAX,%XMM15

(149) 0x2346f3 VPUNPCKLQDQ	%XMM14,%XMM15,%XMM14

(149) 0x2346f8 VINSERTI128	$0x1,%XMM13,%YMM14,%YMM13

(149) 0x2346fe VPMOVQD	%YMM13,%XMM15

(149) 0x234704 VPMULLQ	%YMM1,%YMM13,%YMM13

(149) 0x23470a VPSUBQ	%YMM13,%YMM0,%YMM13

(149) 0x23470f VPADDQ	%YMM0,%YMM12,%YMM0

(149) 0x234713 VPMOVQD	%YMM13,%XMM16

(149) 0x234719 VPADDD	%XMM2,%XMM15,%XMM14

(149) 0x23471d VPADDD	%XMM15,%XMM8,%XMM15

(149) 0x234722 VPMOVSXDQ	%XMM14,%YMM14

(149) 0x234727 VPMOVSXDQ	%XMM15,%YMM15

(149) 0x23472c VPMULLQ	%YMM14,%YMM4,%YMM17

(149) 0x234732 VPMULLQ	%YMM15,%YMM9,%YMM15

(149) 0x234738 VPADDD	%XMM16,%XMM3,%XMM13

(149) 0x23473e VPADDD	%XMM16,%XMM5,%XMM16

(149) 0x234744 VPMOVSXDQ	%XMM13,%YMM13

(149) 0x234749 VPMOVSXDQ	%XMM16,%YMM16

(149) 0x23474f VPADDQ	%YMM13,%YMM17,%YMM17

(149) 0x234755 VPADDQ	%YMM13,%YMM15,%YMM15

(149) 0x23475a VMOVQ	%XMM17,%RAX

(149) 0x234760 VPEXTRQ	$0x1,%XMM17,%RDX

(149) 0x234767 VEXTRACTI32X4	$0x1,%YMM17,%XMM17

(149) 0x23476e VMOVQ	%XMM17,%R12

(149) 0x234774 VMOVSD	(%RDI,%RAX,8),%XMM18

(149) 0x23477b VPEXTRQ	$0x1,%XMM17,%R14

(149) 0x234782 VMOVSD	(%RDI,%R12,8),%XMM17

(149) 0x234789 VMOVHPD	(%RDI,%RDX,8),%XMM18,%XMM18

(149) 0x234790 VMOVHPD	(%RDI,%R14,8),%XMM17,%XMM17

(149) 0x234797 VINSERTF32X4	$0x1,%XMM17,%YMM18,%YMM17

(149) 0x23479e VPMULLQ	%YMM14,%YMM6,%YMM18

(149) 0x2347a4 VPADDQ	%YMM16,%YMM18,%YMM16

(149) 0x2347aa VMOVQ	%XMM16,%RAX

(149) 0x2347b0 VPEXTRQ	$0x1,%XMM16,%RDX

(149) 0x2347b7 VEXTRACTI32X4	$0x1,%YMM16,%XMM16

(149) 0x2347be VMOVQ	%XMM16,%R14

(149) 0x2347c4 VMOVSD	(%R9,%RAX,8),%XMM19

(149) 0x2347cb VPEXTRQ	$0x1,%XMM16,%R12

(149) 0x2347d2 VMOVSD	(%R9,%R14,8),%XMM16

(149) 0x2347d9 VMOVHPD	(%R9,%RDX,8),%XMM19,%XMM19

(149) 0x2347e0 VMOVHPD	(%R9,%R12,8),%XMM16,%XMM16

(149) 0x2347e7 VINSERTF32X4	$0x1,%XMM16,%YMM19,%YMM16

(149) 0x2347ee VADDPD	%YMM17,%YMM16,%YMM16

(149) 0x2347f4 VPADDQ	%YMM13,%YMM18,%YMM17

(149) 0x2347fa VMOVQ	%XMM17,%RAX

(149) 0x234800 VPEXTRQ	$0x1,%XMM17,%RDX

(149) 0x234807 VEXTRACTI32X4	$0x1,%YMM17,%XMM17

(149) 0x23480e VMOVQ	%XMM17,%R14

(149) 0x234814 VMOVSD	(%R9,%RAX,8),%XMM18

(149) 0x23481b VPEXTRQ	$0x1,%XMM17,%R12

(149) 0x234822 VMOVSD	(%R9,%R14,8),%XMM17

(149) 0x234829 VMOVHPD	(%R9,%RDX,8),%XMM18,%XMM18

(149) 0x234830 VMOVHPD	(%R9,%R12,8),%XMM17,%XMM17

(149) 0x234837 VINSERTF32X4	$0x1,%XMM17,%YMM18,%YMM17

(149) 0x23483e VSUBPD	%YMM17,%YMM16,%YMM16

(149) 0x234844 VPMULLQ	%YMM14,%YMM7,%YMM17

(149) 0x23484a VPADDQ	%YMM13,%YMM17,%YMM17

(149) 0x234850 VMOVQ	%XMM17,%RAX

(149) 0x234856 VPEXTRQ	$0x1,%XMM17,%RDX

(149) 0x23485d VEXTRACTI32X4	$0x1,%YMM17,%XMM17

(149) 0x234864 VPEXTRQ	$0x1,%XMM17,%R14

(149) 0x23486b VMOVQ	%XMM17,%R12

(149) 0x234871 VEXTRACTF32X4	$0x1,%YMM16,%XMM17

(149) 0x234878 VMOVLPD	%XMM16,(%R11,%RAX,8)

(149) 0x23487f VMOVHPD	%XMM16,(%R11,%RDX,8)

(149) 0x234886 VPEXTRQ	$0x1,%XMM15,%RAX

(149) 0x23488c VMOVQ	%XMM15,%RDX

(149) 0x234891 VEXTRACTI128	$0x1,%YMM15,%XMM15

(149) 0x234897 VMOVLPD	%XMM17,(%R11,%R12,8)

(149) 0x23489e VMOVHPD	%XMM17,(%R11,%R14,8)

(149) 0x2348a5 VMOVQ	%XMM15,%R14

(149) 0x2348aa VPEXTRQ	$0x1,%XMM15,%R12

(149) 0x2348b0 VMOVSD	(%R8,%R14,8),%XMM15

(149) 0x2348b6 VMOVSD	(%R8,%RDX,8),%XMM17

(149) 0x2348bd VMOVHPD	(%R8,%R12,8),%XMM15,%XMM15

(149) 0x2348c3 VMOVHPD	(%R8,%RAX,8),%XMM17,%XMM17

(149) 0x2348ca VINSERTF32X4	$0x1,%XMM15,%YMM17,%YMM15

(149) 0x2348d1 VADDPD	%YMM16,%YMM15,%YMM15

(149) 0x2348d7 VPMULLQ	%YMM14,%YMM9,%YMM16

(149) 0x2348dd VPMULLQ	%YMM14,%YMM10,%YMM14

(149) 0x2348e3 VPADDQ	%YMM13,%YMM16,%YMM16

(149) 0x2348e9 VPADDQ	%YMM13,%YMM14,%YMM13

(149) 0x2348ee VMOVQ	%XMM16,%RAX

(149) 0x2348f4 VPEXTRQ	$0x1,%XMM16,%RDX

(149) 0x2348fb VEXTRACTI32X4	$0x1,%YMM16,%XMM16

(149) 0x234902 VMOVQ	%XMM16,%R14

(149) 0x234908 VMOVSD	(%R8,%RAX,8),%XMM17

(149) 0x23490f VPEXTRQ	$0x1,%XMM16,%R12

(149) 0x234916 VPEXTRQ	$0x1,%XMM13,%RAX

(149) 0x23491c VMOVSD	(%R8,%R14,8),%XMM16

(149) 0x234923 VMOVHPD	(%R8,%RDX,8),%XMM17,%XMM17

(149) 0x23492a VMOVQ	%XMM13,%RDX

(149) 0x23492f VEXTRACTI128	$0x1,%YMM13,%XMM13

(149) 0x234935 VMOVHPD	(%R8,%R12,8),%XMM16,%XMM16

(149) 0x23493c VMOVQ	%XMM13,%R14

(149) 0x234941 VPEXTRQ	$0x1,%XMM13,%R12

(149) 0x234947 VINSERTF32X4	$0x1,%XMM16,%YMM17,%YMM16

(149) 0x23494e VSUBPD	%YMM16,%YMM15,%YMM15

(149) 0x234954 VEXTRACTF128	$0x1,%YMM15,%XMM13

(149) 0x23495a VMOVLPD	%XMM15,(%R10,%RDX,8)

(149) 0x234960 VMOVHPD	%XMM15,(%R10,%RAX,8)

(149) 0x234966 VMOVLPD	%XMM13,(%R10,%R14,8)

(149) 0x23496c VMOVHPD	%XMM13,(%R10,%R12,8)

(149) 0x234972 JNE	234690

0x234978 MOV	-0x60(%RBP),%R12

0x23497c MOV	-0x30(%RBP),%RBX

0x234980 MOV	-0x80(%RBP),%R13

0x234984 CMP	%RSI,-0x78(%RBP)

0x234988 MOV	-0x38(%RBP),%RSI

0x23498c JE	234a47

0x234992 NOPW	%CS:(%RAX,%RAX,1)

(150) 0x2349a0 MOV	%RCX,%RAX

(150) 0x2349a3 CQTO

(150) 0x2349a5 IDIV	%RBX

(150) 0x2349a8 LEA	(%RSI,%RDX,1),%EBX

(150) 0x2349ab ADD	-0x68(%RBP),%EDX

(150) 0x2349ae MOVSXD	%EBX,%RBX

(150) 0x2349b1 MOVSXD	%EDX,%RDX

(150) 0x2349b4 LEA	(%R12,%RAX,1),%R14D

(150) 0x2349b8 ADD	-0x98(%RBP),%EAX

(150) 0x2349be MOVSXD	%R14D,%R12

(150) 0x2349c1 MOV	-0x58(%RBP),%R14

(150) 0x2349c5 CLTQ

(150) 0x2349c7 IMUL	%R12,%R14

(150) 0x2349cb IMUL	%R13,%RAX

(150) 0x2349cf ADD	%R14,%RDX

(150) 0x2349d2 ADD	%RBX,%R14

(150) 0x2349d5 ADD	%RBX,%RAX

(150) 0x2349d8 VMOVSD	(%R9,%RDX,8),%XMM0

(150) 0x2349de MOV	-0x90(%RBP),%RDX

(150) 0x2349e5 IMUL	%R12,%RDX

(150) 0x2349e9 ADD	%RBX,%RDX

(150) 0x2349ec VADDSD	(%RDI,%RDX,8),%XMM0,%XMM0

(150) 0x2349f1 MOV	-0x88(%RBP),%RDX

(150) 0x2349f8 VSUBSD	(%R9,%R14,8),%XMM0,%XMM0

(150) 0x2349fe IMUL	%R12,%RDX

(150) 0x234a02 ADD	%RBX,%RDX

(150) 0x234a05 VMOVSD	%XMM0,(%R11,%RDX,8)

(150) 0x234a0b VADDSD	(%R8,%RAX,8),%XMM0,%XMM0

(150) 0x234a11 MOV	%R13,%RAX

(150) 0x234a14 IMUL	%R12,%RAX

(150) 0x234a18 ADD	%RBX,%RAX

(150) 0x234a1b VSUBSD	(%R8,%RAX,8),%XMM0,%XMM0

(150) 0x234a21 MOV	-0x50(%RBP),%RAX

(150) 0x234a25 IMUL	%RAX,%R12

(150) 0x234a29 ADD	%RBX,%R12

(150) 0x234a2c MOV	-0x30(%RBP),%RBX

(150) 0x234a30 VMOVSD	%XMM0,(%R10,%R12,8)

(150) 0x234a36 MOV	-0x60(%RBP),%R12

(150) 0x234a3a CMP	%R15,%RCX

(150) 0x234a3d LEA	0x1(%RCX),%RCX

(150) 0x234a41 JL	2349a0

0x234a47 MOV	-0x44(%RBP),%ESI

0x234a4a LEA	0x2614f(%RIP),%RDI

0x234a51 VZEROUPPER

0x234a54 CALL	259690 <@plt_start@+0x540>

0x234a59 ADD	$0x78,%RSP

0x234a5d POP	%RBX

0x234a5e POP	%R12

0x234a60 POP	%R13

0x234a62 POP	%R14

0x234a64 POP	%R15

0x234a66 POP	%RBP

0x234a67 RET

0x234a68 NOPL	(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run aocc_8

Source file and lines	advec_mom.cpp:53-57
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:53-57

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 17.38 to 6.50 cycles (2.67x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions).

Details

5% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

9% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
25% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
9% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:53
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:53

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVL: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:54
VPBROADCASTD: 4 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:54
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:54
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:54
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:54
VPBROADCASTQ: 7 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:54
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:54
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:54
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:54
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:54
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:54
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:54

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 296 bytes. The binary function is storing 128 bytes.

General properties

nb instructions	128
nb uops	139
loop length	529
used x86 registers	16
used mmx registers	0
used xmm registers	5
used ymm registers	8
used zmm registers	0
nb stack references	21

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	17.38 cycles
front end	17.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	6.67	6.67	6.67	6.67	6.67	6.67	14.00	14.00	14.00	14.00	0.50	6.50	6.50	0.50	0.00	0.00
cycles	6.67	6.67	6.67	6.67	6.67	6.67	14.00	14.00	14.00	14.00	0.50	6.50	6.50	0.50	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	17.38
Dispatch	14.00
Overall L1	17.38

Vectorization ratios

all	5%
load	9%
store	0%
mul	0%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	9%

Vector efficiency ratios

all	12%
load	15%
store	11%
mul	12%
add-sub	18%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 17.38 cycles. At this rate:

6% of peak load performance is reached (17.04 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (7.37 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 17.38 to 14.00 cycles (1.24x speedup).

ASM code

In the binary file, the address of the function is: 2344d0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x78,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RCX),%R15D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
MOV (%RDX),%EBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
ADD $0x4,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CMP %R15D,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 234a59 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.2+0x589>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV (%R9),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV (%R8),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
ADD $0x4,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %ECX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 234a59 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.2+0x589>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA -0x1(%RBX),%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x1(%RAX),%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVQ $0,-0x70(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOVQ $0x1,-0xa0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOVL $0,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
SUB %R14D,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %R12D,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
IMUL %RCX,%R15	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
DEC %R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R15,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
LEA -0x48(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RAX,-0x68(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
LEA -0xa0(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x26632(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x70(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x40(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %ESI,-0x44(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 259680 <@plt_start@+0x530>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x40(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x70(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
CMP %R15,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMOVL %RAX,%R15	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
MOV %R15,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
CMP %R15,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JG 234a47 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.2+0x577>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x20(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x28(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x10(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x30(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x18(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %R13,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R14,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %RBX,-0x98(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R12,-0x60(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RSI),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV (%RDI),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%RDI),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x10(%R8),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV (%RAX),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%RDX),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV %R9,-0x58(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x10(%RSI),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV (%R8),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x10(%RAX),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV (%RDX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %R15,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RCX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R14,-0x90(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
INC %RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSI,-0x88(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %RAX,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
CMP $0x4,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 23460c <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.2+0x13c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x38(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x30(%RBP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
JMP 2349a0 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.2+0x4d0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
MOV -0x30(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VPBROADCASTQ %RCX,%YMM0	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPADDQ -0x2333e(%RIP),%YMM0,%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	1	0.50	vect (50.0%)
VPBROADCASTQ -0x23457(%RIP),%YMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	1	0.50	scal (12.5%)
VPBROADCASTQ %R14,%YMM4	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
MOV -0x58(%RBP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
VPBROADCASTD %EBX,%XMM8	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (6.3%)
MOV -0x50(%RBP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RDX,-0x78(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
AND $-0x4,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VPBROADCASTQ %RSI,%YMM7	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPBROADCASTD %R12D,%XMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (6.3%)
VPBROADCASTQ %R13,%YMM9	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
MOV %R13,-0x80(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
ADD %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTQ %RAX,%YMM1	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
MOV -0x38(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VPBROADCASTQ %RBX,%YMM10	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPBROADCASTQ %R14,%YMM6	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
MOV %RDX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VEXTRACTI128 $0x1,%YMM1,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	3	0.50	vect (25.0%)
VPBROADCASTD %EAX,%XMM3	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (6.3%)
MOV -0x68(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VPBROADCASTD %EAX,%XMM5	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (6.3%)
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0x60(%RBP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV -0x30(%RBP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x80(%RBP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
CMP %RSI,-0x78(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
MOV -0x38(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
JE 234a47 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.2+0x577>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0x44(%RBP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
LEA 0x2614f(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 259690 <@plt_start@+0x540>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
ADD $0x78,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run aocc_8

Source file and lines	advec_mom.cpp:53-57
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:53-57

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 17.38 to 6.50 cycles (2.67x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions).

Details

5% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

9% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
25% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
9% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:53
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:53

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVL: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:54
VPBROADCASTD: 4 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:54
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:54
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:54
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:54
VPBROADCASTQ: 7 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:54
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:54
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:54
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:54
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:54
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:54
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:54

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 296 bytes. The binary function is storing 128 bytes.

General properties

nb instructions	128
nb uops	139
loop length	529
used x86 registers	16
used mmx registers	0
used xmm registers	5
used ymm registers	8
used zmm registers	0
nb stack references	21

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	17.38 cycles
front end	17.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	6.67	6.67	6.67	6.67	6.67	6.67	14.00	14.00	14.00	14.00	0.50	6.50	6.50	0.50	0.00	0.00
cycles	6.67	6.67	6.67	6.67	6.67	6.67	14.00	14.00	14.00	14.00	0.50	6.50	6.50	0.50	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	17.38
Dispatch	14.00
Overall L1	17.38

Vectorization ratios

all	5%
load	9%
store	0%
mul	0%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	9%

Vector efficiency ratios

all	12%
load	15%
store	11%
mul	12%
add-sub	18%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 17.38 cycles. At this rate:

6% of peak load performance is reached (17.04 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (7.37 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 2344d0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x78,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RCX),%R15D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
MOV (%RDX),%EBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
ADD $0x4,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CMP %R15D,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 234a59 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.2+0x589>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV (%R9),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV (%R8),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
ADD $0x4,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %ECX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 234a59 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.2+0x589>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA -0x1(%RBX),%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x1(%RAX),%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVQ $0,-0x70(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOVQ $0x1,-0xa0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOVL $0,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
SUB %R14D,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %R12D,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
IMUL %RCX,%R15	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
DEC %R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R15,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
LEA -0x48(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RAX,-0x68(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
LEA -0xa0(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x26632(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x70(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x40(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %ESI,-0x44(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 259680 <@plt_start@+0x530>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x40(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x70(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
CMP %R15,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMOVL %RAX,%R15	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
MOV %R15,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
CMP %R15,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JG 234a47 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.2+0x577>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x20(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x28(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x10(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x30(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x18(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %R13,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R14,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %RBX,-0x98(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R12,-0x60(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RSI),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV (%RDI),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%RDI),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x10(%R8),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV (%RAX),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%RDX),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV %R9,-0x58(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x10(%RSI),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV (%R8),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x10(%RAX),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV (%RDX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %R15,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RCX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R14,-0x90(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
INC %RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSI,-0x88(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %RAX,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
CMP $0x4,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 23460c <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.2+0x13c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x38(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x30(%RBP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
JMP 2349a0 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.2+0x4d0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
MOV -0x30(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VPBROADCASTQ %RCX,%YMM0	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPADDQ -0x2333e(%RIP),%YMM0,%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	1	0.50	vect (50.0%)
VPBROADCASTQ -0x23457(%RIP),%YMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	1	0.50	scal (12.5%)
VPBROADCASTQ %R14,%YMM4	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
MOV -0x58(%RBP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
VPBROADCASTD %EBX,%XMM8	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (6.3%)
MOV -0x50(%RBP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RDX,-0x78(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
AND $-0x4,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VPBROADCASTQ %RSI,%YMM7	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPBROADCASTD %R12D,%XMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (6.3%)
VPBROADCASTQ %R13,%YMM9	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
MOV %R13,-0x80(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
ADD %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTQ %RAX,%YMM1	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
MOV -0x38(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VPBROADCASTQ %RBX,%YMM10	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPBROADCASTQ %R14,%YMM6	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
MOV %RDX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VEXTRACTI128 $0x1,%YMM1,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	3	0.50	vect (25.0%)
VPBROADCASTD %EAX,%XMM3	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (6.3%)
MOV -0x68(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VPBROADCASTD %EAX,%XMM5	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (6.3%)
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0x60(%RBP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV -0x30(%RBP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x80(%RBP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
CMP %RSI,-0x78(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
MOV -0x38(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
JE 234a47 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.2+0x577>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0x44(%RBP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
LEA 0x2614f(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 259690 <@plt_start@+0x540>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
ADD $0x78,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	2.99	1.12
○Loop 149 - advec_mom.cpp:54-57 - exec	2.99	1.11
○Loop 150 - advec_mom.cpp:54-57 - exec	0.00	0.00

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Code clean check

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Vectorization

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Execution units bottlenecks

512-bits vectorization

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CALL instructions

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Complex instructions

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Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code