OV - exec - Loop 258

	Loop Id: 258	Module: exec	Source: :0-0	Coverage: 4.20%

0x42a840 MOVSD	0x1a400(%RIP),%XMM1    [13]

0x42a848 MOVAPD	%XMM4,%XMM0

0x42a84c CALL	4041a0 <fmin@plt>

0x42a851 MOVAPD	%XMM0,%XMM1

0x42a855 MOVSD	0x38(%RSP),%XMM0    [15]

0x42a85b CALL	4041a0 <fmin@plt>

0x42a860 MOVAPD	%XMM0,%XMM1

0x42a864 MOVSD	0x30(%RSP),%XMM0    [15]

0x42a86a CALL	4041a0 <fmin@plt>

0x42a86f MOVSD	0x10(%RSP),%XMM1    [15]

0x42a875 CALL	4041a0 <fmin@plt>

0x42a87a MOVSD	%XMM0,0x10(%RSP)    [15]

0x42a880 CMP	%R13,%R14

0x42a883 JE	42ab8e

0x42a889 MOV	%R13,%RBX

0x42a88c ADD	$0x1,%R13

0x42a890 MOV	0x30(%R15),%RDX    [14]

0x42a894 MOV	0x58(%R15),%RCX    [14]

0x42a898 PXOR	%XMM7,%XMM7

0x42a89c MOV	0x50(%R15),%RSI    [14]

0x42a8a0 MOV	0x8(%RDX),%RDX    [23]

0x42a8a4 MOVSD	(%RDX,%RBX,8),%XMM5    [22]

0x42a8a9 MOV	0x38(%R15),%RDX    [14]

0x42a8ad MOV	0x8(%RDX),%RDX    [21]

0x42a8b1 MOVSD	%XMM5,0x8(%RSP)    [15]

0x42a8b7 MOVSD	(%RDX,%R12,1),%XMM6    [20]

0x42a8bd MOV	(%RCX),%RDX    [19]

0x42a8c0 MOV	0x10(%RCX),%RCX    [19]

0x42a8c4 IMUL	%RBP,%RDX

0x42a8c8 MOVSD	%XMM6,0x18(%RSP)    [15]

0x42a8ce ADD	%RBX,%RDX

0x42a8d1 MOVSD	(%RCX,%RDX,8),%XMM0    [18]

0x42a8d6 MOV	(%RSI),%RDX    [11]

0x42a8d9 MOV	0x48(%R15),%RCX    [14]

0x42a8dd MOV	0x10(%RSI),%RSI    [11]

0x42a8e1 IMUL	%RBP,%RDX

0x42a8e5 MOVAPD	%XMM0,%XMM1

0x42a8e9 MULSD	%XMM0,%XMM1

0x42a8ed ADD	%RBX,%RDX

0x42a8f0 MOVSD	(%RSI,%RDX,8),%XMM0    [10]

0x42a8f5 MOV	(%RCX),%RDX    [17]

0x42a8f8 MOV	0x10(%RCX),%RCX    [17]

0x42a8fc IMUL	%RBP,%RDX

0x42a900 ADDSD	%XMM0,%XMM0

0x42a904 ADD	%RBX,%RDX

0x42a907 DIVSD	(%RCX,%RDX,8),%XMM0    [16]

0x42a90c ADDSD	%XMM1,%XMM0

0x42a910 UCOMISD	%XMM0,%XMM7

0x42a914 JA	42ac0b

0x42a91a SQRTSD	%XMM0,%XMM0

0x42a91e MOVSD	0x19c82(%RIP),%XMM1    [13]

0x42a926 CALL	4043d0 <fmax@plt>

0x42a92b MOVSD	0x18(%RSP),%XMM1    [15]

0x42a931 MOVSD	%XMM0,0x20(%RSP)    [15]

0x42a937 MOVSD	0x8(%RSP),%XMM0    [15]

0x42a93d CALL	4041a0 <fmin@plt>

0x42a942 MOV	0x60(%R15),%RDX    [14]

0x42a946 MOV	0x20(%R15),%RDI    [14]

0x42a94a MOVSD	0x19c56(%RIP),%XMM5    [13]

0x42a952 MULSD	0x50(%RSP),%XMM0    [15]

0x42a958 MOV	0x10(%RDX),%R8    [12]

0x42a95c MOV	(%RDX),%RDX    [12]

0x42a95f MOV	(%RDI),%RAX    [6]

0x42a962 MOV	0x10(%RDI),%RSI    [6]

0x42a966 MOV	%RDX,%RCX

0x42a969 IMUL	%RBP,%RCX

0x42a96d IMUL	%RBP,%RAX

0x42a971 MOVAPD	%XMM0,%XMM6

0x42a975 DIVSD	0x20(%RSP),%XMM6    [15]

0x42a97b MOVSD	%XMM6,0x30(%RSP)    [15]

0x42a981 LEA	(%RCX,%RBX,1),%R10

0x42a985 ADD	%RCX,%RDX

0x42a988 ADD	%R13,%RCX

0x42a98b MOVSD	(%R8,%RCX,8),%XMM2    [2]

0x42a991 LEA	(%RDX,%RBX,1),%R9

0x42a995 MOV	0x40(%R15),%RCX    [14]

0x42a999 ADD	%R13,%RDX

0x42a99c ADDSD	(%R8,%RDX,8),%XMM2    [2]

0x42a9a2 LEA	(%RAX,%R13,1),%RDX

0x42a9a6 MOVSD	(%R8,%R10,8),%XMM4    [2]

0x42a9ac MULSD	(%RSI,%RDX,8),%XMM2    [9]

0x42a9b1 MOV	(%RCX),%RDX    [5]

0x42a9b4 MOV	0x10(%RCX),%RCX    [5]

0x42a9b8 ADDSD	(%R8,%R9,8),%XMM4    [2]

0x42a9be LEA	(%RAX,%RBX,1),%R9

0x42a9c2 IMUL	%RBP,%RDX

0x42a9c6 MULSD	(%RSI,%R9,8),%XMM4    [9]

0x42a9cc ADD	%RBX,%RDX

0x42a9cf MOVAPD	%XMM2,%XMM7

0x42a9d3 ANDPD	0x1a215(%RIP),%XMM7    [13]

0x42a9db MOVSD	%XMM2,0x18(%RSP)    [15]

0x42a9e1 MOVSD	(%RCX,%RDX,8),%XMM3    [4]

0x42a9e6 MOVAPD	%XMM4,%XMM1

0x42a9ea ANDPD	0x1a1fe(%RIP),%XMM1    [13]

0x42a9f2 MOVAPD	%XMM7,%XMM0

0x42a9f6 MOVSD	%XMM4,0x28(%RSP)    [15]

0x42a9fc MULSD	%XMM3,%XMM5

0x42aa00 MOVSD	%XMM3,0x20(%RSP)    [15]

0x42aa06 MOVSD	%XMM5,0x8(%RSP)    [15]

0x42aa0c CALL	4043d0 <fmax@plt>

0x42aa11 MOVAPD	%XMM0,%XMM1

0x42aa15 MOVSD	0x8(%RSP),%XMM0    [15]

0x42aa1b CALL	4043d0 <fmax@plt>

0x42aa20 MOVSD	0x20(%RSP),%XMM3    [15]

0x42aa26 MOVSD	0x48(%RSP),%XMM1    [15]

0x42aa2c PXOR	%XMM5,%XMM5

0x42aa30 MULSD	%XMM3,%XMM1

0x42aa34 DIVSD	%XMM0,%XMM1

0x42aa38 MOVSD	%XMM1,0x38(%RSP)    [15]

0x42aa3e MOV	0x68(%R15),%RDX    [14]

0x42aa42 MOV	0x28(%R15),%RCX    [14]

0x42aa46 MOVSD	0x18(%RSP),%XMM2    [15]

0x42aa4c MOVSD	0x28(%RSP),%XMM4    [15]

0x42aa52 MOV	0x10(%RDX),%RSI    [7]

0x42aa56 MOV	0x10(%RCX),%R8    [3]

0x42aa5a MOV	(%RDX),%RDX    [7]

0x42aa5d MOV	(%RCX),%RCX    [3]

0x42aa60 ADDSD	%XMM5,%XMM2

0x42aa64 MOV	%RDX,%RDI

0x42aa67 MOV	%RCX,%R9

0x42aa6a IMUL	%RBP,%RDI

0x42aa6e SUBSD	%XMM4,%XMM2

0x42aa72 IMUL	%RBP,%R9

0x42aa76 ADD	%RDI,%RDX

0x42aa79 LEA	(%RDI,%RBX,1),%R11

0x42aa7d LEA	(%RDI,%R13,1),%R10

0x42aa81 ADD	%R9,%RCX

0x42aa84 LEA	(%RDX,%RBX,1),%RDI

0x42aa88 ADD	%R13,%RDX

0x42aa8b MOVSD	(%RSI,%R11,8),%XMM1    [8]

0x42aa91 ADD	%RBX,%RCX

0x42aa94 MOVSD	(%RSI,%RDI,8),%XMM0    [8]

0x42aa99 ADDSD	(%RSI,%RDX,8),%XMM0    [8]

0x42aa9e MULSD	(%R8,%RCX,8),%XMM0    [1]

0x42aaa4 ADDSD	(%RSI,%R10,8),%XMM1    [8]

0x42aaaa LEA	(%R9,%RBX,1),%R10

0x42aaae MULSD	(%R8,%R10,8),%XMM1    [1]

0x42aab4 ADDSD	%XMM0,%XMM2

0x42aab8 ANDPD	0x1a130(%RIP),%XMM0    [13]

0x42aac0 SUBSD	%XMM1,%XMM2

0x42aac4 ANDPD	0x1a124(%RIP),%XMM1    [13]

0x42aacc MOVSD	%XMM2,0x18(%RSP)    [15]

0x42aad2 CALL	4043d0 <fmax@plt>

0x42aad7 MOVAPD	%XMM0,%XMM1

0x42aadb MOVSD	0x8(%RSP),%XMM0    [15]

0x42aae1 CALL	4043d0 <fmax@plt>

0x42aae6 MOVSD	0x20(%RSP),%XMM3    [15]

0x42aaec MOVSD	0x40(%RSP),%XMM4    [15]

0x42aaf2 MOVSD	0x18(%RSP),%XMM2    [15]

0x42aaf8 MOVSD	0x1a950(%RIP),%XMM7    [13]

0x42ab00 MULSD	%XMM3,%XMM4

0x42ab04 ADDSD	%XMM3,%XMM3

0x42ab08 DIVSD	%XMM3,%XMM2

0x42ab0c DIVSD	%XMM0,%XMM4

0x42ab10 COMISD	%XMM2,%XMM7

0x42ab14 JBE	42a840

0x42ab1a MOVSD	0x19a7e(%RIP),%XMM0    [13]

0x42ab22 MOVSD	0x1a11e(%RIP),%XMM1    [13]

0x42ab2a MOVSD	%XMM4,0x8(%RSP)    [15]

0x42ab30 DIVSD	%XMM2,%XMM0

0x42ab34 MULSD	0x58(%RSP),%XMM0    [15]

0x42ab3a CALL	4041a0 <fmin@plt>

0x42ab3f MOVSD	0x8(%RSP),%XMM4    [15]

0x42ab45 MOVAPD	%XMM0,%XMM1

0x42ab49 MOVAPD	%XMM4,%XMM0

0x42ab4d CALL	4041a0 <fmin@plt>

0x42ab52 MOVAPD	%XMM0,%XMM1

0x42ab56 MOVSD	0x38(%RSP),%XMM0    [15]

0x42ab5c CALL	4041a0 <fmin@plt>

0x42ab61 MOVAPD	%XMM0,%XMM1

0x42ab65 MOVSD	0x30(%RSP),%XMM0    [15]

0x42ab6b CALL	4041a0 <fmin@plt>

0x42ab70 MOVAPD	%XMM0,%XMM1

0x42ab74 MOVSD	0x10(%RSP),%XMM0    [15]

0x42ab7a CALL	4041a0 <fmin@plt>

0x42ab7f MOVSD	%XMM0,0x10(%RSP)    [15]

0x42ab85 CMP	%R13,%R14

0x42ab88 JNE	42a889

0x42ac0b CALL	4042a0 <sqrt@plt>

0x42ac10 JMP	42a91e

  ***  This Panel is Intentionally Left Blank.  ***

It is due to a lack of debug symbols in the given object
(loop or function).

Coverage (%)	Name	Source Location	Module
►97.04+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►2.87+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	calc_dt_kernel(int, int, int, [...]		exec
○	calc_dt(global_variables&, int[...]		exec
○	timestep(global_variables&, pa[...]		exec
○	hydro(global_variables&, paral[...]		exec
○	main		exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.03
CQA speedup if FP arith vectorized	1.92
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.19
Bottlenecks
Function	calc_dt_kernel(int, int, int, int, double, double, double, double, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, double&, int&, double&, double&, int&, int&, int&) [clone ._omp_fn.0]
Source
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	27.06
CQA cycles if no scalar integer	26.25
CQA cycles if FP arith vectorized	14.09
CQA cycles if fully vectorized	3.38
Front-end cycles	21.66
P0 cycles	7.21
P1 cycles	7.21
P2 cycles	7.21
P3 cycles	7.21
P4 cycles	7.21
P5 cycles	7.21
P6 cycles	23.50
P7 cycles	23.50
P8 cycles	23.50
P9 cycles	23.50
P10 cycles	8.13
P11 cycles	8.13
P12 cycles	8.13
P13 cycles	8.13
P14 cycles	6.75
P15 cycles	6.75
DIV/SQRT cycles	26.25
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	160.50
Nb uops	173.25
Nb loads	71.50
Nb stores	11.50
Nb stack references	10.50
FLOP/cycle	0.98
Nb FLOP add-sub	11.00
Nb FLOP mul	9.50
Nb FLOP fma	0.00
Nb FLOP div	5.50
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.50
Nb FLOP rsqrt	0.00
Bytes/cycle	26.17
Bytes prefetched	0.00
Bytes loaded	604.00
Bytes stored	92.00
Stride 0	3.00
Stride 1	3.00
Stride n	0.00
Stride unknown	16.00
Stride indirect	1.00
Vectorization ratio all	19.87
Vectorization ratio load	9.21
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	87.11
Vector-efficiency ratio all	14.98
Vector-efficiency ratio load	13.65
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	23.39

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	2.23
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.35
Bottlenecks	P10, P11,
Function	calc_dt_kernel(int, int, int, int, double, double, double, double, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, double&, int&, double&, double&, int&, int&, int&) [clone ._omp_fn.0]
Source
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	32.50
CQA cycles if no scalar integer	32.50
CQA cycles if FP arith vectorized	14.59
CQA cycles if fully vectorized	4.06
Front-end cycles	22.00
P0 cycles	7.00
P1 cycles	7.00
P2 cycles	7.00
P3 cycles	7.00
P4 cycles	7.00
P5 cycles	7.00
P6 cycles	24.00
P7 cycles	24.00
P8 cycles	24.00
P9 cycles	24.00
P10 cycles	8.50
P11 cycles	8.50
P12 cycles	8.50
P13 cycles	8.50
P14 cycles	7.00
P15 cycles	7.00
DIV/SQRT cycles	32.50
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	164.00
Nb uops	176.00
Nb loads	73.00
Nb stores	12.00
Nb stack references	11.00
FLOP/cycle	0.86
Nb FLOP add-sub	11.00
Nb FLOP mul	10.00
Nb FLOP fma	0.00
Nb FLOP div	6.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	1.00
Nb FLOP rsqrt	0.00
Bytes/cycle	21.91
Bytes prefetched	0.00
Bytes loaded	616.00
Bytes stored	96.00
Stride 0	3.00
Stride 1	3.00
Stride n	0.00
Stride unknown	16.00
Stride indirect	1.00
Vectorization ratio all	20.22
Vectorization ratio load	8.89
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	90.00
Vector-efficiency ratio all	15.03
Vector-efficiency ratio load	13.61
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	23.75

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	2.10
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.25
Bottlenecks	P10, P11,
Function	calc_dt_kernel(int, int, int, int, double, double, double, double, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, double&, int&, double&, double&, int&, int&, int&) [clone ._omp_fn.0]
Source
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	28.50
CQA cycles if no scalar integer	28.50
CQA cycles if FP arith vectorized	13.56
CQA cycles if fully vectorized	3.56
Front-end cycles	21.00
P0 cycles	7.00
P1 cycles	7.00
P2 cycles	7.00
P3 cycles	7.00
P4 cycles	7.00
P5 cycles	7.00
P6 cycles	22.75
P7 cycles	22.75
P8 cycles	22.75
P9 cycles	22.75
P10 cycles	8.00
P11 cycles	8.00
P12 cycles	8.00
P13 cycles	8.00
P14 cycles	6.50
P15 cycles	6.50
DIV/SQRT cycles	28.50
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	156.00
Nb uops	168.00
Nb loads	70.00
Nb stores	11.00
Nb stack references	10.00
FLOP/cycle	0.91
Nb FLOP add-sub	11.00
Nb FLOP mul	9.00
Nb FLOP fma	0.00
Nb FLOP div	5.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	1.00
Nb FLOP rsqrt	0.00
Bytes/cycle	23.86
Bytes prefetched	0.00
Bytes loaded	592.00
Bytes stored	88.00
Stride 0	3.00
Stride 1	3.00
Stride n	0.00
Stride unknown	16.00
Stride indirect	1.00
Vectorization ratio all	19.28
Vectorization ratio load	9.52
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	84.21
Vector-efficiency ratio all	14.91
Vector-efficiency ratio load	13.69
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	23.03

Metric	Value
CQA speedup if no scalar integer	1.01
CQA speedup if FP arith vectorized	1.66
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	P6, P7, P8, P9,
Function	calc_dt_kernel(int, int, int, int, double, double, double, double, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, double&, int&, double&, double&, int&, int&, int&) [clone ._omp_fn.0]
Source
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	24.25
CQA cycles if no scalar integer	24.00
CQA cycles if FP arith vectorized	14.63
CQA cycles if fully vectorized	3.03
Front-end cycles	22.38
P0 cycles	7.50
P1 cycles	7.50
P2 cycles	7.50
P3 cycles	7.50
P4 cycles	7.50
P5 cycles	7.50
P6 cycles	24.25
P7 cycles	24.25
P8 cycles	24.25
P9 cycles	24.25
P10 cycles	8.25
P11 cycles	8.25
P12 cycles	8.25
P13 cycles	8.25
P14 cycles	7.00
P15 cycles	7.00
DIV/SQRT cycles	24.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	165.00
Nb uops	179.00
Nb loads	73.00
Nb stores	12.00
Nb stack references	11.00
FLOP/cycle	1.11
Nb FLOP add-sub	11.00
Nb FLOP mul	10.00
Nb FLOP fma	0.00
Nb FLOP div	6.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	29.36
Bytes prefetched	0.00
Bytes loaded	616.00
Bytes stored	96.00
Stride 0	3.00
Stride 1	3.00
Stride n	0.00
Stride unknown	16.00
Stride indirect	1.00
Vectorization ratio all	20.45
Vectorization ratio load	8.89
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	90.00
Vector-efficiency ratio all	15.06
Vector-efficiency ratio load	13.61
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	23.75

Metric	Value
CQA speedup if no scalar integer	1.15
CQA speedup if FP arith vectorized	1.69
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.08
Bottlenecks	P6, P7, P8, P9,
Function	calc_dt_kernel(int, int, int, int, double, double, double, double, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, double&, int&, double&, double&, int&, int&, int&) [clone ._omp_fn.0]
Source
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	23.00
CQA cycles if no scalar integer	20.00
CQA cycles if FP arith vectorized	13.59
CQA cycles if fully vectorized	2.88
Front-end cycles	21.25
P0 cycles	7.33
P1 cycles	7.33
P2 cycles	7.33
P3 cycles	7.33
P4 cycles	7.33
P5 cycles	7.33
P6 cycles	23.00
P7 cycles	23.00
P8 cycles	23.00
P9 cycles	23.00
P10 cycles	7.75
P11 cycles	7.75
P12 cycles	7.75
P13 cycles	7.75
P14 cycles	6.50
P15 cycles	6.50
DIV/SQRT cycles	20.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	157.00
Nb uops	170.00
Nb loads	70.00
Nb stores	11.00
Nb stack references	10.00
FLOP/cycle	1.09
Nb FLOP add-sub	11.00
Nb FLOP mul	9.00
Nb FLOP fma	0.00
Nb FLOP div	5.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	29.57
Bytes prefetched	0.00
Bytes loaded	592.00
Bytes stored	88.00
Stride 0	3.00
Stride 1	3.00
Stride n	0.00
Stride unknown	16.00
Stride indirect	1.00
Vectorization ratio all	19.51
Vectorization ratio load	9.52
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	84.21
Vector-efficiency ratio all	14.94
Vector-efficiency ratio load	13.69
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	23.03

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	calc_dt_kernel(int, int, int, int, double, double, double, double, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, double&, int&, double&, double&, int&, int&, int&) [clone ._omp_fn.0]
Source file and lines
Module	exec

This loop has 4 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

gain
potential
hint
expert

Vectorization

Your loop is probably not vectorized. Only 14% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 27.06 to 3.38 cycles (8.00x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 27.06 to 23.00 cycles (1.18x speedup).

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- Please look into your compiler manual for march=native or equivalent
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

fmax@plt: 0 occurrences
fmin@plt: 0 occurrences

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

COMISD: 0 occurrences
UCOMISD: 0 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 16 occurrence(s)
Irregular (variable stride) or indirect: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Type of elements and instruction set

28 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 26.5 FP arithmetical operations:

11: addition or subtraction
9.50: multiply
5.50: divide
0.50: square root

The binary loop is loading 604 bytes (75 double precision FP elements). The binary loop is storing 92 bytes (11 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

General properties

nb instructions	160.50
nb uops	173.25
loop length	754.50
used x86 registers	16
used mmx registers	0
used xmm registers	8
used ymm registers	0
used zmm registers	0
nb stack references	10.50
ADD-SUB / MUL ratio	1.16

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	21.66 cycles
front end	21.66 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	7.21	7.21	7.21	7.21	7.21	7.21	23.50	23.50	23.50	23.50	8.13	8.13	8.13	8.13	6.75	6.75
cycles	7.21	7.21	7.21	7.21	7.21	7.21	23.50	23.50	23.50	23.50	8.13	8.13	8.13	8.13	6.75	6.75

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	26.25
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	21.66
Dispatch	23.50
DIV/SQRT	26.25
Data deps.	0.00
Overall L1	27.06

Vectorization ratios

INT

all	83%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	83%

all	18%
load	9%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	88%

INT+FP

all	19%
load	9%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	87%

Vector efficiency ratios

INT

all	22%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	22%

all	14%
load	13%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	23%

INT+FP

all	14%
load	13%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	23%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 27.06 cycles. At this rate:

8% of peak load performance is reached (22.72 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.46 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Function	calc_dt_kernel(int, int, int, int, double, double, double, double, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, double&, int&, double&, double&, int&, int&, int&) [clone ._omp_fn.0]
Source file and lines
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

gain
potential
hint
expert

Vectorization

Your loop is probably not vectorized. Only 15% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 32.50 to 4.06 cycles (8.00x speedup).

Details

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 32.50 to 24.00 cycles (1.35x speedup).

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact.
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 32.50 to 23.50 cycles (1.38x speedup).

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- Please look into your compiler manual for march=native or equivalent
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

CALL instructions

Detected function call instructions.

Details

fmax@plt: 5 occurrences►
fmin@plt: 6 occurrences►

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

COMISD: 1 occurrences►
UCOMISD: 1 occurrences►

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 16 occurrence(s)
Irregular (variable stride) or indirect: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Type of elements and instruction set

30 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 28 FP arithmetical operations:

11: addition or subtraction
10: multiply
6: divide
1: square root

The binary loop is loading 616 bytes (77 double precision FP elements). The binary loop is storing 96 bytes (12 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

General properties

nb instructions	164
nb uops	176
loop length	773
used x86 registers	16
used mmx registers	0
used xmm registers	8
used ymm registers	0
used zmm registers	0
nb stack references	11
ADD-SUB / MUL ratio	1.10

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	22.00 cycles
front end	22.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	7.00	7.00	7.00	7.00	7.00	7.00	24.00	24.00	24.00	24.00	8.50	8.50	8.50	8.50	7.00	7.00
cycles	7.00	7.00	7.00	7.00	7.00	7.00	24.00	24.00	24.00	24.00	8.50	8.50	8.50	8.50	7.00	7.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	32.50
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	22.00
Dispatch	24.00
DIV/SQRT	32.50
Data deps.	0.00
Overall L1	32.50

Vectorization ratios

INT

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	18%
load	8%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	88%

INT+FP

all	20%
load	8%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	90%

Vector efficiency ratios

INT

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	14%
load	13%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	23%

INT+FP

all	15%
load	13%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	23%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 32.50 cycles. At this rate:

7% of peak load performance is reached (18.95 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (2.95 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 42a890

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
MOV %R13,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x1,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x30(%R15),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x58(%R15),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
PXOR %XMM7,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
MOV 0x50(%R15),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x8(%RDX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOVSD (%RDX,%RBX,8),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x38(%R15),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x8(%RDX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOVSD %XMM5,0x8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVSD (%RDX,%R12,1),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV (%RCX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RCX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
IMUL %RBP,%RDX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
MOVSD %XMM6,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
ADD %RBX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVSD (%RCX,%RDX,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV (%RSI),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x48(%R15),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RSI),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
IMUL %RBP,%RDX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
MOVAPD %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MULSD %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
ADD %RBX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVSD (%RSI,%RDX,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV (%RCX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RCX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
IMUL %RBP,%RDX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADDSD %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
ADD %RBX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
DIVSD (%RCX,%RDX,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
ADDSD %XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
UCOMISD %XMM0,%XMM7	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	7	1	scal (12.5%)
JA 42ac0b <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x54b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
SQRTSD %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	21	8.50	scal (12.5%)
MOVSD 0x19c82(%RIP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
CALL 4043d0 <fmax@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOVSD 0x18(%RSP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVSD %XMM0,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVSD 0x8(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
CALL 4041a0 <fmin@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV 0x60(%R15),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x20(%R15),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOVSD 0x19c56(%RIP),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MULSD 0x50(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
MOV 0x10(%RDX),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RDX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RDI),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RDI),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %RBP,%RCX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
IMUL %RBP,%RAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
MOVAPD %XMM0,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
DIVSD 0x20(%RSP),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
MOVSD %XMM6,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
LEA (%RCX,%RBX,1),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %RCX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %R13,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVSD (%R8,%RCX,8),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
LEA (%RDX,%RBX,1),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV 0x40(%R15),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
ADD %R13,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADDSD (%R8,%RDX,8),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
LEA (%RAX,%R13,1),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVSD (%R8,%R10,8),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MULSD (%RSI,%RDX,8),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
MOV (%RCX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RCX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
ADDSD (%R8,%R9,8),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
LEA (%RAX,%RBX,1),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
IMUL %RBP,%RDX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
MULSD (%RSI,%R9,8),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
ADD %RBX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVAPD %XMM2,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
ANDPD 0x1a215(%RIP),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (25.0%)
MOVSD %XMM2,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVSD (%RCX,%RDX,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVAPD %XMM4,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
ANDPD 0x1a1fe(%RIP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (25.0%)
MOVAPD %XMM7,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOVSD %XMM4,0x28(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MULSD %XMM3,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
MOVSD %XMM3,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVSD %XMM5,0x8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
CALL 4043d0 <fmax@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOVAPD %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOVSD 0x8(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
CALL 4043d0 <fmax@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOVSD 0x20(%RSP),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVSD 0x48(%RSP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
PXOR %XMM5,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
MULSD %XMM3,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
DIVSD %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
MOVSD %XMM1,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV 0x68(%R15),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x28(%R15),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOVSD 0x18(%RSP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVSD 0x28(%RSP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x10(%RDX),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RCX),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RDX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RCX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
ADDSD %XMM5,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
MOV %RDX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %RBP,%RDI	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
SUBSD %XMM4,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
IMUL %RBP,%R9	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADD %RDI,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RDI,%RBX,1),%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RDI,%R13,1),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %R9,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RDX,%RBX,1),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %R13,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVSD (%RSI,%R11,8),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
ADD %RBX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVSD (%RSI,%RDI,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
ADDSD (%RSI,%RDX,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
MULSD (%R8,%RCX,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
ADDSD (%RSI,%R10,8),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
LEA (%R9,%RBX,1),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MULSD (%R8,%R10,8),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
ADDSD %XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
ANDPD 0x1a130(%RIP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (25.0%)
SUBSD %XMM1,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
ANDPD 0x1a124(%RIP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (25.0%)
MOVSD %XMM2,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
CALL 4043d0 <fmax@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOVAPD %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOVSD 0x8(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
CALL 4043d0 <fmax@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOVSD 0x20(%RSP),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVSD 0x40(%RSP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVSD 0x18(%RSP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVSD 0x1a950(%RIP),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MULSD %XMM3,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
ADDSD %XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
DIVSD %XMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
DIVSD %XMM0,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
COMISD %XMM2,%XMM7	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	7	0.50	scal (12.5%)
JBE 42a840 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x180>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOVSD 0x19a7e(%RIP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVSD 0x1a11e(%RIP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVSD %XMM4,0x8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
DIVSD %XMM2,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
MULSD 0x58(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
CALL 4041a0 <fmin@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOVSD 0x8(%RSP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVAPD %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOVAPD %XMM4,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
CALL 4041a0 <fmin@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOVAPD %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOVSD 0x38(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
CALL 4041a0 <fmin@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOVAPD %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOVSD 0x30(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
CALL 4041a0 <fmin@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOVAPD %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOVSD 0x10(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
CALL 4041a0 <fmin@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOVSD %XMM0,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
CMP %R13,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 42a889 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x1c9>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Function	calc_dt_kernel(int, int, int, int, double, double, double, double, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, double&, int&, double&, double&, int&, int&, int&) [clone ._omp_fn.0]
Source file and lines
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact.
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 28.50 to 22.25 cycles (1.28x speedup).

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- Please look into your compiler manual for march=native or equivalent
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

CALL instructions

Detected function call instructions.

Details

fmax@plt: 5 occurrences►
fmin@plt: 5 occurrences►

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

COMISD: 1 occurrences►
UCOMISD: 1 occurrences►

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 16 occurrence(s)
Irregular (variable stride) or indirect: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Type of elements and instruction set

28 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 26 FP arithmetical operations:

11: addition or subtraction
9: multiply
5: divide
1: square root

The binary loop is loading 592 bytes (74 double precision FP elements). The binary loop is storing 88 bytes (11 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

General properties

nb instructions	156
nb uops	168
loop length	730
used x86 registers	16
used mmx registers	0
used xmm registers	8
used ymm registers	0
used zmm registers	0
nb stack references	10
ADD-SUB / MUL ratio	1.22

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	21.00 cycles
front end	21.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	7.00	7.00	7.00	7.00	7.00	7.00	22.75	22.75	22.75	22.75	8.00	8.00	8.00	8.00	6.50	6.50
cycles	7.00	7.00	7.00	7.00	7.00	7.00	22.75	22.75	22.75	22.75	8.00	8.00	8.00	8.00	6.50	6.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	28.50
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	21.00
Dispatch	22.75
DIV/SQRT	28.50
Data deps.	0.00
Overall L1	28.50

Vectorization ratios

INT

all	66%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	66%

all	17%
load	9%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	87%

INT+FP

all	19%
load	9%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	84%

Vector efficiency ratios

INT

all	20%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	20%

all	14%
load	13%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	23%

INT+FP

all	14%
load	13%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	23%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 28.50 cycles. At this rate:

8% of peak load performance is reached (20.77 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.09 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 42a890

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
MOVSD 0x1a400(%RIP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVAPD %XMM4,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
CALL 4041a0 <fmin@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOVAPD %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOVSD 0x38(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
CALL 4041a0 <fmin@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOVAPD %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOVSD 0x30(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
CALL 4041a0 <fmin@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOVSD 0x10(%RSP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
CALL 4041a0 <fmin@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOVSD %XMM0,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
CMP %R13,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 42ab8e <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x4ce>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R13,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x1,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x30(%R15),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x58(%R15),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
PXOR %XMM7,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
MOV 0x50(%R15),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x8(%RDX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOVSD (%RDX,%RBX,8),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x38(%R15),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x8(%RDX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOVSD %XMM5,0x8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVSD (%RDX,%R12,1),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV (%RCX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RCX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
IMUL %RBP,%RDX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
MOVSD %XMM6,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
ADD %RBX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVSD (%RCX,%RDX,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV (%RSI),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x48(%R15),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RSI),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
IMUL %RBP,%RDX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
MOVAPD %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MULSD %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
ADD %RBX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVSD (%RSI,%RDX,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV (%RCX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RCX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
IMUL %RBP,%RDX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADDSD %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
ADD %RBX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
DIVSD (%RCX,%RDX,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
ADDSD %XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
UCOMISD %XMM0,%XMM7	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	7	1	scal (12.5%)
JA 42ac0b <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x54b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
SQRTSD %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	21	8.50	scal (12.5%)
MOVSD 0x19c82(%RIP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
CALL 4043d0 <fmax@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOVSD 0x18(%RSP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVSD %XMM0,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVSD 0x8(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
CALL 4041a0 <fmin@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV 0x60(%R15),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x20(%R15),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOVSD 0x19c56(%RIP),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MULSD 0x50(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
MOV 0x10(%RDX),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RDX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RDI),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RDI),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %RBP,%RCX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
IMUL %RBP,%RAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
MOVAPD %XMM0,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
DIVSD 0x20(%RSP),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
MOVSD %XMM6,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
LEA (%RCX,%RBX,1),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %RCX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %R13,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVSD (%R8,%RCX,8),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
LEA (%RDX,%RBX,1),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV 0x40(%R15),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
ADD %R13,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADDSD (%R8,%RDX,8),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
LEA (%RAX,%R13,1),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVSD (%R8,%R10,8),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MULSD (%RSI,%RDX,8),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
MOV (%RCX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RCX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
ADDSD (%R8,%R9,8),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
LEA (%RAX,%RBX,1),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
IMUL %RBP,%RDX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
MULSD (%RSI,%R9,8),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
ADD %RBX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVAPD %XMM2,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
ANDPD 0x1a215(%RIP),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (25.0%)
MOVSD %XMM2,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVSD (%RCX,%RDX,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVAPD %XMM4,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
ANDPD 0x1a1fe(%RIP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (25.0%)
MOVAPD %XMM7,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOVSD %XMM4,0x28(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MULSD %XMM3,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
MOVSD %XMM3,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVSD %XMM5,0x8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
CALL 4043d0 <fmax@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOVAPD %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOVSD 0x8(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
CALL 4043d0 <fmax@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOVSD 0x20(%RSP),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVSD 0x48(%RSP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
PXOR %XMM5,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
MULSD %XMM3,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
DIVSD %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
MOVSD %XMM1,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV 0x68(%R15),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x28(%R15),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOVSD 0x18(%RSP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVSD 0x28(%RSP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x10(%RDX),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RCX),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RDX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RCX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
ADDSD %XMM5,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
MOV %RDX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %RBP,%RDI	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
SUBSD %XMM4,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
IMUL %RBP,%R9	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADD %RDI,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RDI,%RBX,1),%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RDI,%R13,1),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %R9,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RDX,%RBX,1),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %R13,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVSD (%RSI,%R11,8),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
ADD %RBX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVSD (%RSI,%RDI,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
ADDSD (%RSI,%RDX,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
MULSD (%R8,%RCX,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
ADDSD (%RSI,%R10,8),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
LEA (%R9,%RBX,1),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MULSD (%R8,%R10,8),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
ADDSD %XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
ANDPD 0x1a130(%RIP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (25.0%)
SUBSD %XMM1,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
ANDPD 0x1a124(%RIP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (25.0%)
MOVSD %XMM2,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
CALL 4043d0 <fmax@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOVAPD %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOVSD 0x8(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
CALL 4043d0 <fmax@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOVSD 0x20(%RSP),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVSD 0x40(%RSP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVSD 0x18(%RSP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVSD 0x1a950(%RIP),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MULSD %XMM3,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
ADDSD %XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
DIVSD %XMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
DIVSD %XMM0,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
COMISD %XMM2,%XMM7	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	7	0.50	scal (12.5%)
JBE 42a840 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x180>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Function	calc_dt_kernel(int, int, int, int, double, double, double, double, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, double&, int&, double&, double&, int&, int&, int&) [clone ._omp_fn.0]
Source file and lines
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- Please look into your compiler manual for march=native or equivalent
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

CALL instructions

Detected function call instructions.

Details

fmax@plt: 5 occurrences►
fmin@plt: 6 occurrences►
sqrt@plt: 1 occurrences►

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

COMISD: 1 occurrences►
UCOMISD: 1 occurrences►

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 16 occurrence(s)
Irregular (variable stride) or indirect: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Type of elements and instruction set

29 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 27 FP arithmetical operations:

11: addition or subtraction
10: multiply
6: divide

The binary loop is loading 616 bytes (77 double precision FP elements). The binary loop is storing 96 bytes (12 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

General properties

nb instructions	165
nb uops	179
loop length	779
used x86 registers	16
used mmx registers	0
used xmm registers	8
used ymm registers	0
used zmm registers	0
nb stack references	11
ADD-SUB / MUL ratio	1.10

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	22.38 cycles
front end	22.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	7.50	7.50	7.50	7.50	7.50	7.50	24.25	24.25	24.25	24.25	8.25	8.25	8.25	8.25	7.00	7.00
cycles	7.50	7.50	7.50	7.50	7.50	7.50	24.25	24.25	24.25	24.25	8.25	8.25	8.25	8.25	7.00	7.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	24.00
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	22.38
Dispatch	24.25
DIV/SQRT	24.00
Data deps.	0.00
Overall L1	24.25

Vectorization ratios

INT

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	18%
load	8%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	88%

INT+FP

all	20%
load	8%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	90%

Vector efficiency ratios

INT

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	14%
load	13%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	23%

INT+FP

all	15%
load	13%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	23%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 24.25 cycles. At this rate:

9% of peak load performance is reached (25.40 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (3.96 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 42a890

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
MOV %R13,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x1,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x30(%R15),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x58(%R15),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
PXOR %XMM7,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
MOV 0x50(%R15),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x8(%RDX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOVSD (%RDX,%RBX,8),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x38(%R15),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x8(%RDX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOVSD %XMM5,0x8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVSD (%RDX,%R12,1),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV (%RCX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RCX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
IMUL %RBP,%RDX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
MOVSD %XMM6,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
ADD %RBX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVSD (%RCX,%RDX,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV (%RSI),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x48(%R15),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RSI),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
IMUL %RBP,%RDX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
MOVAPD %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MULSD %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
ADD %RBX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVSD (%RSI,%RDX,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV (%RCX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RCX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
IMUL %RBP,%RDX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADDSD %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
ADD %RBX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
DIVSD (%RCX,%RDX,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
ADDSD %XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
UCOMISD %XMM0,%XMM7	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	7	1	scal (12.5%)
JA 42ac0b <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x54b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOVSD 0x19c82(%RIP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
CALL 4043d0 <fmax@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOVSD 0x18(%RSP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVSD %XMM0,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVSD 0x8(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
CALL 4041a0 <fmin@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV 0x60(%R15),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x20(%R15),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOVSD 0x19c56(%RIP),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MULSD 0x50(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
MOV 0x10(%RDX),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RDX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RDI),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RDI),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %RBP,%RCX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
IMUL %RBP,%RAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
MOVAPD %XMM0,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
DIVSD 0x20(%RSP),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
MOVSD %XMM6,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
LEA (%RCX,%RBX,1),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %RCX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %R13,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVSD (%R8,%RCX,8),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
LEA (%RDX,%RBX,1),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV 0x40(%R15),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
ADD %R13,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADDSD (%R8,%RDX,8),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
LEA (%RAX,%R13,1),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVSD (%R8,%R10,8),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MULSD (%RSI,%RDX,8),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
MOV (%RCX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RCX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
ADDSD (%R8,%R9,8),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
LEA (%RAX,%RBX,1),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
IMUL %RBP,%RDX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
MULSD (%RSI,%R9,8),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
ADD %RBX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVAPD %XMM2,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
ANDPD 0x1a215(%RIP),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (25.0%)
MOVSD %XMM2,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVSD (%RCX,%RDX,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVAPD %XMM4,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
ANDPD 0x1a1fe(%RIP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (25.0%)
MOVAPD %XMM7,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOVSD %XMM4,0x28(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MULSD %XMM3,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
MOVSD %XMM3,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVSD %XMM5,0x8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
CALL 4043d0 <fmax@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOVAPD %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOVSD 0x8(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
CALL 4043d0 <fmax@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOVSD 0x20(%RSP),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVSD 0x48(%RSP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
PXOR %XMM5,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
MULSD %XMM3,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
DIVSD %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
MOVSD %XMM1,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV 0x68(%R15),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x28(%R15),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOVSD 0x18(%RSP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVSD 0x28(%RSP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x10(%RDX),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RCX),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RDX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RCX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
ADDSD %XMM5,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
MOV %RDX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %RBP,%RDI	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
SUBSD %XMM4,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
IMUL %RBP,%R9	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADD %RDI,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RDI,%RBX,1),%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RDI,%R13,1),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %R9,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RDX,%RBX,1),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %R13,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVSD (%RSI,%R11,8),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
ADD %RBX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVSD (%RSI,%RDI,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
ADDSD (%RSI,%RDX,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
MULSD (%R8,%RCX,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
ADDSD (%RSI,%R10,8),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
LEA (%R9,%RBX,1),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MULSD (%R8,%R10,8),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
ADDSD %XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
ANDPD 0x1a130(%RIP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (25.0%)
SUBSD %XMM1,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
ANDPD 0x1a124(%RIP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (25.0%)
MOVSD %XMM2,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
CALL 4043d0 <fmax@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOVAPD %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOVSD 0x8(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
CALL 4043d0 <fmax@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOVSD 0x20(%RSP),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVSD 0x40(%RSP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVSD 0x18(%RSP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVSD 0x1a950(%RIP),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MULSD %XMM3,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
ADDSD %XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
DIVSD %XMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
DIVSD %XMM0,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
COMISD %XMM2,%XMM7	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	7	0.50	scal (12.5%)
JBE 42a840 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x180>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOVSD 0x19a7e(%RIP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVSD 0x1a11e(%RIP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVSD %XMM4,0x8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
DIVSD %XMM2,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
MULSD 0x58(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
CALL 4041a0 <fmin@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOVSD 0x8(%RSP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVAPD %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOVAPD %XMM4,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
CALL 4041a0 <fmin@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOVAPD %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOVSD 0x38(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
CALL 4041a0 <fmin@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOVAPD %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOVSD 0x30(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
CALL 4041a0 <fmin@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOVAPD %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOVSD 0x10(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
CALL 4041a0 <fmin@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOVSD %XMM0,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
CMP %R13,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 42a889 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x1c9>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CALL 4042a0 <sqrt@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
JMP 42a91e <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x25e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A

Function	calc_dt_kernel(int, int, int, int, double, double, double, double, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, double&, int&, double&, double&, int&, int&, int&) [clone ._omp_fn.0]
Source file and lines
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 23.00 to 20.00 cycles (1.15x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 23.00 to 21.25 cycles (1.08x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- Please look into your compiler manual for march=native or equivalent
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

CALL instructions

Detected function call instructions.

Details

fmax@plt: 5 occurrences►
fmin@plt: 5 occurrences►
sqrt@plt: 1 occurrences►

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

COMISD: 1 occurrences►
UCOMISD: 1 occurrences►

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 16 occurrence(s)
Irregular (variable stride) or indirect: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Type of elements and instruction set

27 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 25 FP arithmetical operations:

11: addition or subtraction
9: multiply
5: divide

The binary loop is loading 592 bytes (74 double precision FP elements). The binary loop is storing 88 bytes (11 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

General properties

nb instructions	157
nb uops	170
loop length	736
used x86 registers	16
used mmx registers	0
used xmm registers	8
used ymm registers	0
used zmm registers	0
nb stack references	10
ADD-SUB / MUL ratio	1.22

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	21.25 cycles
front end	21.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	7.33	7.33	7.33	7.33	7.33	7.33	23.00	23.00	23.00	23.00	7.75	7.75	7.75	7.75	6.50	6.50
cycles	7.33	7.33	7.33	7.33	7.33	7.33	23.00	23.00	23.00	23.00	7.75	7.75	7.75	7.75	6.50	6.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	20.00
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	21.25
Dispatch	23.00
DIV/SQRT	20.00
Data deps.	0.00
Overall L1	23.00

Vectorization ratios

INT

all	66%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	66%

all	17%
load	9%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	87%

INT+FP

all	19%
load	9%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	84%

Vector efficiency ratios

INT

all	20%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	20%

all	14%
load	13%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	23%

INT+FP

all	14%
load	13%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	23%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 23.00 cycles. At this rate:

10% of peak load performance is reached (25.74 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.83 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 42a890

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
MOVSD 0x1a400(%RIP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVAPD %XMM4,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
CALL 4041a0 <fmin@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOVAPD %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOVSD 0x38(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
CALL 4041a0 <fmin@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOVAPD %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOVSD 0x30(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
CALL 4041a0 <fmin@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOVSD 0x10(%RSP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
CALL 4041a0 <fmin@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOVSD %XMM0,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
CMP %R13,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 42ab8e <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x4ce>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R13,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x1,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x30(%R15),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x58(%R15),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
PXOR %XMM7,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
MOV 0x50(%R15),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x8(%RDX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOVSD (%RDX,%RBX,8),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x38(%R15),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x8(%RDX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOVSD %XMM5,0x8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVSD (%RDX,%R12,1),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV (%RCX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RCX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
IMUL %RBP,%RDX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
MOVSD %XMM6,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
ADD %RBX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVSD (%RCX,%RDX,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV (%RSI),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x48(%R15),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RSI),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
IMUL %RBP,%RDX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
MOVAPD %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MULSD %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
ADD %RBX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVSD (%RSI,%RDX,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV (%RCX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RCX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
IMUL %RBP,%RDX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADDSD %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
ADD %RBX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
DIVSD (%RCX,%RDX,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
ADDSD %XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
UCOMISD %XMM0,%XMM7	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	7	1	scal (12.5%)
JA 42ac0b <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x54b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOVSD 0x19c82(%RIP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
CALL 4043d0 <fmax@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOVSD 0x18(%RSP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVSD %XMM0,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVSD 0x8(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
CALL 4041a0 <fmin@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV 0x60(%R15),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x20(%R15),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOVSD 0x19c56(%RIP),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MULSD 0x50(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
MOV 0x10(%RDX),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RDX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RDI),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RDI),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %RBP,%RCX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
IMUL %RBP,%RAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
MOVAPD %XMM0,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
DIVSD 0x20(%RSP),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
MOVSD %XMM6,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
LEA (%RCX,%RBX,1),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %RCX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %R13,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVSD (%R8,%RCX,8),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
LEA (%RDX,%RBX,1),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV 0x40(%R15),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
ADD %R13,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADDSD (%R8,%RDX,8),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
LEA (%RAX,%R13,1),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVSD (%R8,%R10,8),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MULSD (%RSI,%RDX,8),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
MOV (%RCX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RCX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
ADDSD (%R8,%R9,8),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
LEA (%RAX,%RBX,1),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
IMUL %RBP,%RDX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
MULSD (%RSI,%R9,8),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
ADD %RBX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVAPD %XMM2,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
ANDPD 0x1a215(%RIP),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (25.0%)
MOVSD %XMM2,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVSD (%RCX,%RDX,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVAPD %XMM4,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
ANDPD 0x1a1fe(%RIP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (25.0%)
MOVAPD %XMM7,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOVSD %XMM4,0x28(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MULSD %XMM3,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
MOVSD %XMM3,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVSD %XMM5,0x8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
CALL 4043d0 <fmax@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOVAPD %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOVSD 0x8(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
CALL 4043d0 <fmax@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOVSD 0x20(%RSP),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVSD 0x48(%RSP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
PXOR %XMM5,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
MULSD %XMM3,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
DIVSD %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
MOVSD %XMM1,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV 0x68(%R15),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x28(%R15),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOVSD 0x18(%RSP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVSD 0x28(%RSP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x10(%RDX),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RCX),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RDX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RCX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
ADDSD %XMM5,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
MOV %RDX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %RBP,%RDI	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
SUBSD %XMM4,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
IMUL %RBP,%R9	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADD %RDI,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RDI,%RBX,1),%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RDI,%R13,1),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %R9,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RDX,%RBX,1),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %R13,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVSD (%RSI,%R11,8),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
ADD %RBX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVSD (%RSI,%RDI,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
ADDSD (%RSI,%RDX,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
MULSD (%R8,%RCX,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
ADDSD (%RSI,%R10,8),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
LEA (%R9,%RBX,1),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MULSD (%R8,%R10,8),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
ADDSD %XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
ANDPD 0x1a130(%RIP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (25.0%)
SUBSD %XMM1,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
ANDPD 0x1a124(%RIP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (25.0%)
MOVSD %XMM2,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
CALL 4043d0 <fmax@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOVAPD %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOVSD 0x8(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
CALL 4043d0 <fmax@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOVSD 0x20(%RSP),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVSD 0x40(%RSP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVSD 0x18(%RSP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVSD 0x1a950(%RIP),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MULSD %XMM3,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
ADDSD %XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
DIVSD %XMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
DIVSD %XMM0,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
COMISD %XMM2,%XMM7	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	7	0.50	scal (12.5%)
JBE 42a840 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x180>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CALL 4042a0 <sqrt@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
JMP 42a91e <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x25e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A

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Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

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Execution units bottlenecks

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Expensive FP math instructions/calls

FMA

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CALL instructions

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Complex instructions

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Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

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Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

FMA

Workaround

CALL instructions

Details

Complex instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details