OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone ._omp

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: :0-0	Coverage (incl. loops): 2.96% \| (excl. loops): 0.00%

  ***  This Panel is Intentionally Left Blank.  ***

It is due to a lack of debug symbols in the given object
(loop or function).

0x426760 PUSH	%R15

0x426762 PUSH	%R14

0x426764 PUSH	%R13

0x426766 PUSH	%R12

0x426768 PUSH	%RBP

0x426769 PUSH	%RBX

0x42676a MOV	%RDI,%RBX

0x42676d SUB	$0x88,%RSP

0x426774 MOV	0x30(%RDI),%EAX

0x426777 MOV	0x28(%RDI),%ESI

0x42677a LEA	-0x1(%RAX),%EBP

0x42677d MOV	0x34(%RDI),%EAX

0x426780 LEA	-0x1(%RSI),%EDI

0x426783 MOV	0x2c(%RBX),%ESI

0x426786 MOV	%EDI,0x4c(%RSP)

0x42678a ADD	$0x4,%EAX

0x42678d MOV	%EAX,0x48(%RSP)

0x426791 CMP	%EAX,%EBP

0x426793 JGE	426a3a

0x426799 MOV	%EAX,%R13D

0x42679c LEA	0x4(%RSI),%R14D

0x4267a0 SUB	%EBP,%R13D

0x4267a3 CMP	%R14D,%EDI

0x4267a6 JGE	426a3a

0x4267ac MOV	%R14D,%R15D

0x4267af SUB	%EDI,%R15D

0x4267b2 MOV	%R15D,0x50(%RSP)

0x4267b7 CALL	404660 <omp_get_num_threads@plt>

0x4267bc MOV	%EAX,%R12D

0x4267bf CALL	404550 <omp_get_thread_num@plt>

0x4267c4 XOR	%EDX,%EDX

0x4267c6 MOV	%EAX,%ECX

0x4267c8 MOV	%R15D,%EAX

0x4267cb IMUL	%R13D,%EAX

0x4267cf DIV	%R12D

0x4267d2 MOV	%EAX,%EDI

0x4267d4 CMP	%EDX,%ECX

0x4267d6 JB	426a4c

0x4267dc IMUL	%EDI,%ECX

0x4267df LEA	(%RCX,%RDX,1),%ESI

0x4267e2 LEA	(%RDI,%RSI,1),%EAX

0x4267e5 MOV	%EAX,0x54(%RSP)

0x4267e9 CMP	%EAX,%ESI

0x4267eb JAE	426a3a

0x4267f1 XOR	%EDX,%EDX

0x4267f3 MOV	%ESI,%EAX

0x4267f5 MOV	0x4c(%RSP),%ECX

0x4267f9 DIVL	0x50(%RSP)

0x4267fd LEA	(%RDX,%RCX,1),%R15D

0x426801 MOV	0x10(%RBX),%RCX

0x426805 MOV	%R14D,%EDX

0x426808 ADD	%EBP,%EAX

0x42680a SUB	%R15D,%EDX

0x42680d MOV	%RCX,0x58(%RSP)

0x426812 MOV	(%RBX),%RCX

0x426815 CMP	%EDX,%EDI

0x426817 CMOVA	%EDX,%EDI

0x42681a MOV	%RCX,0x60(%RSP)

0x42681f MOV	0x20(%RBX),%RCX

0x426823 MOV	%RCX,0x68(%RSP)

0x426828 MOV	0x8(%RBX),%RCX

0x42682c MOV	0x18(%RBX),%RBX

0x426830 MOV	%RCX,0x70(%RSP)

0x426835 MOVSXD	%EAX,%RCX

0x426838 LEA	(%RSI,%RDI,1),%EAX

0x42683b MOV	%RBX,0x78(%RSP)

0x426840 MOV	%EAX,0x2c(%RSP)

0x426844 CMP	%EAX,%ESI

0x426846 JAE	426a26

0x42684c NOPL	(%RAX)

  (218) 0x426850 MOV	0x58(%RSP),%RAX

  (218) 0x426855 MOV	0x10(%RAX),%R9

  (218) 0x426859 MOV	(%RAX),%RSI

  (218) 0x42685c MOV	0x60(%RSP),%RAX

  (218) 0x426861 IMUL	%RCX,%RSI

  (218) 0x426865 MOV	%R9,0x38(%RSP)

  (218) 0x42686a MOV	(%RAX),%R12

  (218) 0x42686d MOV	0x10(%RAX),%R14

  (218) 0x426871 MOV	0x68(%RSP),%RAX

  (218) 0x426876 IMUL	%RCX,%R12

  (218) 0x42687a MOV	%RSI,0x40(%RSP)

  (218) 0x42687f MOV	0x10(%RAX),%RBX

  (218) 0x426883 MOV	(%RAX),%R8

  (218) 0x426886 MOV	0x70(%RSP),%RAX

  (218) 0x42688b MOV	%RBX,0x18(%RSP)

  (218) 0x426890 IMUL	%RCX,%R8

  (218) 0x426894 LEA	0x1(%RCX),%RBX

  (218) 0x426898 MOV	0x10(%RAX),%R13

  (218) 0x42689c MOV	(%RAX),%RAX

  (218) 0x42689f MOV	%RBX,%RBP

  (218) 0x4268a2 MOV	%RBX,0x20(%RSP)

  (218) 0x4268a7 IMUL	%RAX,%RBP

  (218) 0x4268ab MOV	%R8,0x30(%RSP)

  (218) 0x4268b0 MOV	%RBP,%RBX

  (218) 0x4268b3 SUB	%RAX,%RBX

  (218) 0x4268b6 MOV	0x78(%RSP),%RAX

  (218) 0x4268bb MOV	%RBX,0x10(%RSP)

  (218) 0x4268c0 IMUL	(%RAX),%RCX

  (218) 0x4268c4 MOV	0x10(%RAX),%RDX

  (218) 0x4268c8 MOV	%RDX,0x8(%RSP)

  (218) 0x4268cd MOV	%RCX,(%RSP)

  (218) 0x4268d1 CMP	$0x1,%EDI

  (218) 0x4268d4 JE	42698a

  (218) 0x4268da MOVSXD	%R15D,%RAX

  (218) 0x4268dd MOV	%RBX,%RCX

  (218) 0x4268e0 LEA	(%RSI,%RAX,1),%RDX

  (218) 0x4268e4 MOV	0x18(%RSP),%RSI

  (218) 0x4268e9 LEA	(%R9,%RDX,8),%RBX

  (218) 0x4268ed LEA	0x1(%R12,%RAX,1),%RDX

  (218) 0x4268f2 SAL	$0x3,%RDX

  (218) 0x4268f6 LEA	(%R14,%RDX,1),%R11

  (218) 0x4268fa LEA	-0x8(%R14,%RDX,1),%R10

  (218) 0x4268ff LEA	(%R8,%RAX,1),%RDX

  (218) 0x426903 LEA	(%RSI,%RDX,8),%R9

  (218) 0x426907 LEA	(%RBP,%RAX,1),%RDX

  (218) 0x42690c LEA	(%R13,%RDX,8),%R8

  (218) 0x426911 LEA	(%RCX,%RAX,1),%RDX

  (218) 0x426915 MOV	(%RSP),%RCX

  (218) 0x426919 LEA	(%R13,%RDX,8),%RSI

  (218) 0x42691e MOV	0x8(%RSP),%RDX

  (218) 0x426923 ADD	%RCX,%RAX

  (218) 0x426926 LEA	(%RDX,%RAX,8),%RCX

  (218) 0x42692a MOV	%EDI,%EDX

  (218) 0x42692c XOR	%EAX,%EAX

  (218) 0x42692e SHR	$0x1,%EDX

  (218) 0x426930 SAL	$0x4,%RDX

  (218) 0x426934 NOPW	%CS:(%RAX,%RAX,1)

  (218) 0x42693f NOP

    (219) 0x426940 MOVUPD	(%R11,%RAX,1),%XMM0

    (219) 0x426946 MOVUPD	(%RBX,%RAX,1),%XMM1

    (219) 0x42694b MOVUPD	(%R10,%RAX,1),%XMM2

    (219) 0x426951 ADDPD	%XMM1,%XMM0

    (219) 0x426955 SUBPD	%XMM2,%XMM0

    (219) 0x426959 MOVUPS	%XMM0,(%R9,%RAX,1)

    (219) 0x42695e MOVUPD	(%R8,%RAX,1),%XMM3

    (219) 0x426964 MOVUPD	(%RSI,%RAX,1),%XMM4

    (219) 0x426969 ADDPD	%XMM3,%XMM0

    (219) 0x42696d SUBPD	%XMM4,%XMM0

    (219) 0x426971 MOVUPS	%XMM0,(%RCX,%RAX,1)

    (219) 0x426975 ADD	$0x10,%RAX

    (219) 0x426979 CMP	%RAX,%RDX

    (219) 0x42697c JNE	426940

  (218) 0x42697e TEST	$0x1,%DIL

  (218) 0x426982 JE	4269f4

  (218) 0x426984 AND	$-0x2,%EDI

  (218) 0x426987 ADD	%EDI,%R15D

  (218) 0x42698a MOVSXD	%R15D,%RAX

  (218) 0x42698d MOV	0x40(%RSP),%RDX

  (218) 0x426992 ADD	$0x1,%R15D

  (218) 0x426996 MOV	0x38(%RSP),%RDI

  (218) 0x42699b MOVSXD	%R15D,%R15

  (218) 0x42699e MOV	0x18(%RSP),%RBX

  (218) 0x4269a3 ADD	%RAX,%RBP

  (218) 0x4269a6 ADD	%RAX,%RDX

  (218) 0x4269a9 ADD	%R12,%R15

  (218) 0x4269ac ADD	%RAX,%R12

  (218) 0x4269af MOVSD	(%R14,%R15,8),%XMM0

  (218) 0x4269b5 ADDSD	(%RDI,%RDX,8),%XMM0

  (218) 0x4269ba MOV	0x30(%RSP),%RDX

  (218) 0x4269bf SUBSD	(%R14,%R12,8),%XMM0

  (218) 0x4269c5 MOV	0x10(%RSP),%RDI

  (218) 0x4269ca ADD	%RAX,%RDX

  (218) 0x4269cd MOVSD	%XMM0,(%RBX,%RDX,8)

  (218) 0x4269d2 ADD	%RAX,%RDI

  (218) 0x4269d5 MOV	(%RSP),%RDX

  (218) 0x4269d9 ADDSD	(%R13,%RBP,8),%XMM0

  (218) 0x4269e0 SUBSD	(%R13,%RDI,8),%XMM0

  (218) 0x4269e7 ADD	%RAX,%RDX

  (218) 0x4269ea MOV	0x8(%RSP),%RAX

  (218) 0x4269ef MOVSD	%XMM0,(%RAX,%RDX,8)

  (218) 0x4269f4 MOV	0x2c(%RSP),%ESI

  (218) 0x4269f8 MOV	0x20(%RSP),%RCX

  (218) 0x4269fd CMP	%ECX,0x48(%RSP)

  (218) 0x426a01 JLE	426a3a

  (218) 0x426a03 MOV	0x54(%RSP),%EDI

  (218) 0x426a07 MOV	0x50(%RSP),%EDX

  (218) 0x426a0b MOV	0x4c(%RSP),%R15D

  (218) 0x426a10 SUB	%ESI,%EDI

  (218) 0x426a12 CMP	%EDX,%EDI

  (218) 0x426a14 CMOVA	%EDX,%EDI

  (218) 0x426a17 LEA	(%RSI,%RDI,1),%EAX

  (218) 0x426a1a MOV	%EAX,0x2c(%RSP)

  (218) 0x426a1e CMP	%EAX,%ESI

  (218) 0x426a20 JB	426850

(220) 0x426a26 LEA	0x1(%RCX),%RAX

(220) 0x426a2a MOV	%RAX,0x20(%RSP)

(220) 0x426a2f MOV	0x20(%RSP),%RCX

(220) 0x426a34 CMP	%ECX,0x48(%RSP)

(220) 0x426a38 JG	426a03

0x426a3a ADD	$0x88,%RSP

0x426a41 POP	%RBX

0x426a42 POP	%RBP

0x426a43 POP	%R12

0x426a45 POP	%R13

0x426a47 POP	%R14

0x426a49 POP	%R15

0x426a4b RET

0x426a4c ADD	$0x1,%EDI

0x426a4f XOR	%EDX,%EDX

0x426a51 JMP	4267dc

0x426a56 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►96.78+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►1.57+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	advec_mom_kernel(int, int, int[...]		exec
○	advec_mom_driver(global_variab[...]		exec
○	advection(global_variables&)		exec
○	hydro(global_variables&, paral[...]		exec
○	main		exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec
►1.55+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	advec_mom_kernel(int, int, int[...]		exec
○	advec_mom_driver(global_variab[...]		exec
○	advection(global_variables&)		exec
○	hydro(global_variables&, paral[...]		exec
○	main		exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines
Module	exec

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 7% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 12.00 to 0.75 cycles (16.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 12.00 to 10.63 cycles (1.13x speedup).

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 10.38 cycles (1.16x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
omp_get_thread_num@plt: 1 occurrences►

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVA: 1 occurrences►
DIV: 2 occurrences►

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 64 bytes. The binary function is storing 60 bytes.

General properties

nb instructions	82
nb uops	85
loop length	278
used x86 registers	12
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	10

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.63 cycles
front end	10.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	6.50	6.50	6.50	6.50	6.50	6.50	5.75	5.75	5.75	5.75	0.00	0.00	0.00	0.00	0.00	0.00
cycles	6.50	6.50	6.50	6.50	6.50	6.50	5.75	5.75	5.75	5.75	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	10.63
Dispatch	6.50
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

all	7%
load	6%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

2% of peak load performance is reached (5.33 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (5.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 426760

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB $0x88,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0x30(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x28(%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
LEA -0x1(%RAX),%EBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV 0x34(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
LEA -0x1(%RSI),%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV 0x2c(%RBX),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %EDI,0x4c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
ADD $0x4,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %EAX,0x48(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %EAX,%EBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 426a3a <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x2da>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
LEA 0x4(%RSI),%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
SUB %EBP,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMP %R14D,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 426a3a <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x2da>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %R14D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SUB %EDI,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %R15D,0x50(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CALL 404660 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404550 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R13D,%EAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
DIV %R12D	2	0	0	0	2	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV %EAX,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JB 426a4c <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x2ec>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
IMUL %EDI,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
LEA (%RCX,%RDX,1),%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA (%RDI,%RSI,1),%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %EAX,0x54(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %EAX,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JAE 426a3a <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x2da>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %ESI,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x4c(%RSP),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
DIVL 0x50(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	10-17	6	scal (6.3%)
LEA (%RDX,%RCX,1),%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV 0x10(%RBX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %R14D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %EBP,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
SUB %R15D,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %RCX,0x58(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV (%RBX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP %EDX,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMOVA %EDX,%EDI	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	1	0.33	N/A
MOV %RCX,0x60(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x20(%RBX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RCX,0x68(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x8(%RBX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x18(%RBX),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RCX,0x70(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOVSXD %EAX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA (%RSI,%RDI,1),%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %RBX,0x78(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %EAX,0x2c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %EAX,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JAE 426a26 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x2c6>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0x88,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
ADD $0x1,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 4267dc <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x7c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines
Module	exec

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 10.38 cycles (1.16x speedup).

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
omp_get_thread_num@plt: 1 occurrences►

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVA: 1 occurrences►
DIV: 2 occurrences►

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 64 bytes. The binary function is storing 60 bytes.

General properties

nb instructions	82
nb uops	85
loop length	278
used x86 registers	12
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	10

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.63 cycles
front end	10.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	6.50	6.50	6.50	6.50	6.50	6.50	5.75	5.75	5.75	5.75	0.00	0.00	0.00	0.00	0.00	0.00
cycles	6.50	6.50	6.50	6.50	6.50	6.50	5.75	5.75	5.75	5.75	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	10.63
Dispatch	6.50
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

all	7%
load	6%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

2% of peak load performance is reached (5.33 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (5.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 426760

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB $0x88,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0x30(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x28(%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
LEA -0x1(%RAX),%EBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV 0x34(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
LEA -0x1(%RSI),%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV 0x2c(%RBX),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %EDI,0x4c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
ADD $0x4,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %EAX,0x48(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %EAX,%EBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 426a3a <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x2da>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
LEA 0x4(%RSI),%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
SUB %EBP,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMP %R14D,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 426a3a <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x2da>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %R14D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SUB %EDI,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %R15D,0x50(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CALL 404660 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404550 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R13D,%EAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
DIV %R12D	2	0	0	0	2	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV %EAX,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JB 426a4c <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x2ec>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
IMUL %EDI,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
LEA (%RCX,%RDX,1),%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA (%RDI,%RSI,1),%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %EAX,0x54(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %EAX,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JAE 426a3a <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x2da>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %ESI,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x4c(%RSP),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
DIVL 0x50(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	10-17	6	scal (6.3%)
LEA (%RDX,%RCX,1),%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV 0x10(%RBX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %R14D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %EBP,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
SUB %R15D,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %RCX,0x58(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV (%RBX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP %EDX,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMOVA %EDX,%EDI	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	1	0.33	N/A
MOV %RCX,0x60(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x20(%RBX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RCX,0x68(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x8(%RBX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x18(%RBX),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RCX,0x70(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOVSXD %EAX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA (%RSI,%RDI,1),%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %RBX,0x78(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %EAX,0x2c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %EAX,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JAE 426a26 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x2c6>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0x88,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
ADD $0x1,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 4267dc <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x7c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	2.96	1.13
▼Loop 220 - - exec–	0.00	0.00
▼Loop 218 - - exec–	0.01	0.01
○Loop 219 - - exec	2.95	1.13

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Matching between your function (in the source code) and the binary function

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Vector efficiency ratios

Cycles and memory resources usage

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ASM code