OV - exec - Function advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ...	Module: exec	Source: :0-0	Coverage (incl. loops): 3.46% \| (excl. loops): 0.00%

  ***  This Panel is Intentionally Left Blank.  ***

It is due to a lack of debug symbols in the given object
(loop or function).

0x425960 PUSH	%R15

0x425962 PUSH	%R14

0x425964 PUSH	%R13

0x425966 PUSH	%R12

0x425968 PUSH	%RBP

0x425969 MOV	%RDI,%RBP

0x42596c PUSH	%RBX

0x42596d SUB	$0x128,%RSP

0x425974 MOV	0x44(%RDI),%EAX

0x425977 MOV	0x40(%RDI),%EDI

0x42597a MOV	%EAX,0xe4(%RSP)

0x425981 LEA	0x4(%RAX),%R11D

0x425985 MOV	0x38(%RBP),%EAX

0x425988 LEA	0x1(%RDI),%R14D

0x42598c MOV	0x3c(%RBP),%EDI

0x42598f ADD	$0x1,%EAX

0x425992 MOV	%EAX,0xdc(%RSP)

0x425999 CMP	%R11D,%R14D

0x42599c JGE	425f70

0x4259a2 MOV	%R11D,%R12D

0x4259a5 LEA	0x2(%RDI),%R13D

0x4259a9 MOV	%R11D,(%RSP)

0x4259ad SUB	%R14D,%R12D

0x4259b0 CMP	%R13D,%EAX

0x4259b3 JGE	425f70

0x4259b9 MOV	%R13D,%R15D

0x4259bc SUB	%EAX,%R15D

0x4259bf MOV	%R15D,0xe0(%RSP)

0x4259c7 CALL	404660 <omp_get_num_threads@plt>

0x4259cc MOV	%EAX,%EBX

0x4259ce CALL	404550 <omp_get_thread_num@plt>

0x4259d3 XOR	%EDX,%EDX

0x4259d5 MOV	(%RSP),%R11D

0x4259d9 MOV	%EAX,%ECX

0x4259db MOV	%R15D,%EAX

0x4259de IMUL	%R12D,%EAX

0x4259e2 DIV	%EBX

0x4259e4 CMP	%EDX,%ECX

0x4259e6 MOV	%EAX,%ESI

0x4259e8 JB	426009

0x4259ee IMUL	%ESI,%ECX

0x4259f1 ADD	%EDX,%ECX

0x4259f3 LEA	(%RSI,%RCX,1),%EAX

0x4259f6 MOV	%EAX,0xe8(%RSP)

0x4259fd CMP	%EAX,%ECX

0x4259ff JAE	425f70

0x425a05 MOV	%ECX,%EAX

0x425a07 XOR	%EDX,%EDX

0x425a09 MOV	0xdc(%RSP),%EDI

0x425a10 MOV	0x30(%RBP),%R10

0x425a14 DIVL	0xe0(%RSP)

0x425a1b MOV	%R11D,0xec(%RSP)

0x425a23 MOVQ	0x1f1c5(%RIP),%XMM7

0x425a2b MOVSD	0x1f7fd(%RIP),%XMM6

0x425a33 MOV	%R10,%R12

0x425a36 LEA	(%RDX,%RDI,1),%EBX

0x425a39 MOV	0x20(%RBP),%RDI

0x425a3d LEA	(%RAX,%R14,1),%EDX

0x425a41 MOV	%R13D,%EAX

0x425a44 SUB	%EBX,%EAX

0x425a46 LEA	-0x2(%RDX),%R13D

0x425a4a MOV	%RDI,0xf0(%RSP)

0x425a52 MOV	0x28(%RBP),%RDI

0x425a56 MOV	%RDI,0xf8(%RSP)

0x425a5e MOV	(%RBP),%RDI

0x425a62 MOV	%RDI,0x100(%RSP)

0x425a6a MOV	0x8(%RBP),%RDI

0x425a6e MOV	%RDI,0x108(%RSP)

0x425a76 MOV	0x18(%RBP),%RDI

0x425a7a MOV	%RDI,0x110(%RSP)

0x425a82 MOV	0x10(%RBP),%RDI

0x425a86 MOV	%RDI,0x118(%RSP)

0x425a8e MOVSXD	%EDX,%RDI

0x425a91 SUB	$0x1,%RDI

0x425a95 MOV	%RDI,%R10

0x425a98 NOPL	(%RAX,%RAX,1)

(213) 0x425aa0 CMP	%EAX,%ESI

(213) 0x425aa2 LEA	0x3(%R13),%EBP

(213) 0x425aa6 LEA	0x1(%R10),%R11

(213) 0x425aaa CMOVBE	%ESI,%EAX

(213) 0x425aad LEA	(%RCX,%RAX,1),%R9D

(213) 0x425ab1 CMP	%R9D,%ECX

(213) 0x425ab4 JAE	425fd4

(213) 0x425aba MOVSXD	%EBX,%RBX

(213) 0x425abd SUB	$0x1,%EAX

(213) 0x425ac0 MOV	0xf8(%RSP),%RCX

(213) 0x425ac8 MOV	0x100(%RSP),%RDI

(213) 0x425ad0 LEA	0x1(%RBX),%R15

(213) 0x425ad4 MOV	0x118(%RSP),%RDX

(213) 0x425adc PXOR	%XMM5,%XMM5

(213) 0x425ae0 MOV	%R9D,0xd0(%RSP)

(213) 0x425ae8 ADD	%R15,%RAX

(213) 0x425aeb MOV	0x10(%RCX),%RSI

(213) 0x425aef MOV	%R12,0xc8(%RSP)

(213) 0x425af7 MOV	%RAX,0xa0(%RSP)

(213) 0x425aff MOV	0xf0(%RSP),%RAX

(213) 0x425b07 MOV	%RSI,0x80(%RSP)

(213) 0x425b0f MOV	(%RCX),%RSI

(213) 0x425b12 MOV	(%RAX),%R8

(213) 0x425b15 MOV	0x10(%RAX),%RAX

(213) 0x425b19 MOV	%RSI,0x88(%RSP)

(213) 0x425b21 MOV	0x8(%RDI),%RSI

(213) 0x425b25 IMUL	%R11,%R8

(213) 0x425b29 MOV	0x108(%RSP),%RCX

(213) 0x425b31 MOV	(%RDX),%R14

(213) 0x425b34 MOV	%RSI,0x70(%RSP)

(213) 0x425b39 LEA	(%RSI,%R11,8),%RSI

(213) 0x425b3d MOV	0x10(%RCX),%RDI

(213) 0x425b41 MOV	%RSI,0x78(%RSP)

(213) 0x425b46 MOV	%R14,%R9

(213) 0x425b49 LEA	(%RAX,%R8,8),%RAX

(213) 0x425b4d MOV	(%RCX),%RSI

(213) 0x425b50 MOV	0x10(%RDX),%RCX

(213) 0x425b54 MOV	%RAX,0x98(%RSP)

(213) 0x425b5c MOV	0x110(%RSP),%RAX

(213) 0x425b64 MOV	%RCX,%R14

(213) 0x425b67 MOV	(%RAX),%R8

(213) 0x425b6a MOV	0x10(%RAX),%RAX

(213) 0x425b6e IMUL	%R11,%R8

(213) 0x425b72 LEA	(%RAX,%R8,8),%RAX

(213) 0x425b76 MOV	(%R12),%R8

(213) 0x425b7a MOV	%RAX,0x90(%RSP)

(213) 0x425b82 MOV	0x10(%R12),%RAX

(213) 0x425b87 IMUL	%R11,%R8

(213) 0x425b8b LEA	(%RAX,%R8,8),%RAX

(213) 0x425b8f MOV	%R15,%R8

(213) 0x425b92 MOV	%RDI,%R15

(213) 0x425b95 MOV	%RAX,0xa8(%RSP)

(213) 0x425b9d MOVSXD	%R13D,%RAX

(213) 0x425ba0 MOV	%RAX,0xb8(%RSP)

(213) 0x425ba8 MOV	0xe4(%RSP),%EAX

(213) 0x425baf ADD	$0x2,%EAX

(213) 0x425bb2 CMP	%EBP,%EAX

(213) 0x425bb4 CMOVG	%EBP,%EAX

(213) 0x425bb7 CLTQ

(213) 0x425bb9 MOV	%RAX,0xc0(%RSP)

(213) 0x425bc1 MOV	%R13D,0xd4(%RSP)

(213) 0x425bc9 MOV	%RSI,%R13

(213) 0x425bcc MOV	%R10,0xb0(%RSP)

(213) 0x425bd4 MOV	%EBP,0xd8(%RSP)

(213) 0x425bdb MOV	%R11,0x10(%RSP)

(213) 0x425be0 JMP	425f33

0x425be5 NOPL	(%RAX)

  (214) 0x425be8 MOV	0xb0(%RSP),%RBP

  (214) 0x425bf0 MOV	0xb8(%RSP),%RAX

  (214) 0x425bf8 MOV	0x10(%RSP),%R12

  (214) 0x425bfd MOV	%RBP,%RDX

  (214) 0x425c00 MOV	0x78(%RSP),%RSI

  (214) 0x425c05 MOV	0x70(%RSP),%RCX

  (214) 0x425c0a MOVAPD	%XMM9,%XMM8

  (214) 0x425c0f MOV	0x88(%RSP),%R10

  (214) 0x425c17 MOV	0x80(%RSP),%RDI

  (214) 0x425c1f ANDPD	%XMM7,%XMM8

  (214) 0x425c24 MOVSD	(%RSI),%XMM0

  (214) 0x425c28 DIVSD	(%RCX,%RDX,8),%XMM0

  (214) 0x425c2d MOV	%R13,%RDX

  (214) 0x425c30 MOVSD	0x1f748(%RIP),%XMM4

  (214) 0x425c38 MOVSD	0x1e95f(%RIP),%XMM11

  (214) 0x425c41 IMUL	%RBP,%R10

  (214) 0x425c45 IMUL	%RBP,%RDX

  (214) 0x425c49 ADD	%RBX,%R10

  (214) 0x425c4c LEA	(%RDI,%R10,8),%R11

  (214) 0x425c50 ADD	%RBX,%RDX

  (214) 0x425c53 DIVSD	(%R11),%XMM8

  (214) 0x425c58 MOVAPD	%XMM8,%XMM1

  (214) 0x425c5d LEA	(%R15,%RDX,8),%R10

  (214) 0x425c61 MOV	%R13,%RDX

  (214) 0x425c64 ADDSD	%XMM6,%XMM1

  (214) 0x425c68 MOVSD	(%R10),%XMM10

  (214) 0x425c6d SUBSD	%XMM8,%XMM4

  (214) 0x425c72 IMUL	%RAX,%RDX

  (214) 0x425c76 MULSD	%XMM1,%XMM0

  (214) 0x425c7a MOVSD	%XMM4,0x8(%RSP)

  (214) 0x425c80 ADD	%RBX,%RDX

  (214) 0x425c83 MOVSD	%XMM0,(%RSP)

  (214) 0x425c88 MOVAPD	%XMM10,%XMM0

  (214) 0x425c8d SUBSD	(%R15,%RDX,8),%XMM0

  (214) 0x425c93 MOV	%R13,%RDX

  (214) 0x425c96 IMUL	%R12,%RDX

  (214) 0x425c9a MOVAPD	%XMM0,%XMM2

  (214) 0x425c9e ADD	%RBX,%RDX

  (214) 0x425ca1 MOVSD	(%R15,%RDX,8),%XMM1

  (214) 0x425ca7 SUBSD	%XMM10,%XMM1

  (214) 0x425cac MULSD	%XMM1,%XMM2

  (214) 0x425cb0 MOVAPD	%XMM1,%XMM3

  (214) 0x425cb4 CMPSD	$0x2,%XMM5,%XMM3

  (214) 0x425cb9 ANDPD	%XMM3,%XMM11

  (214) 0x425cbe ANDNPD	%XMM6,%XMM3

  (214) 0x425cc2 COMISD	%XMM5,%XMM2

  (214) 0x425cc6 ORPD	%XMM3,%XMM11

  (214) 0x425ccb JBE	426000

  (214) 0x425cd1 MOVAPD	%XMM0,%XMM4

  (214) 0x425cd5 ANDPD	%XMM7,%XMM1

  (214) 0x425cd9 MOV	%R8,0x68(%RSP)

  (214) 0x425cde ANDPD	%XMM7,%XMM4

  (214) 0x425ce2 MOV	%R9,0x60(%RSP)

  (214) 0x425ce7 MOVAPD	%XMM4,%XMM0

  (214) 0x425ceb MOV	%RAX,0x58(%RSP)

  (214) 0x425cf0 MOV	%R11,0x50(%RSP)

  (214) 0x425cf5 MOV	%R10,0x48(%RSP)

  (214) 0x425cfa MOVSD	%XMM10,0x40(%RSP)

  (214) 0x425d01 MOVSD	%XMM8,0x38(%RSP)

  (214) 0x425d08 MOVSD	%XMM9,0x30(%RSP)

  (214) 0x425d0f MOVSD	%XMM11,0x28(%RSP)

  (214) 0x425d16 MOVSD	%XMM1,0x20(%RSP)

  (214) 0x425d1c MOVSD	%XMM4,0x18(%RSP)

  (214) 0x425d22 CALL	4041a0 <fmin@plt>

  (214) 0x425d27 MOVSD	0x18(%RSP),%XMM4

  (214) 0x425d2d MULSD	(%RSP),%XMM4

  (214) 0x425d32 MOVSD	0x20(%RSP),%XMM3

  (214) 0x425d38 MULSD	0x8(%RSP),%XMM3

  (214) 0x425d3e MOVAPD	%XMM0,%XMM1

  (214) 0x425d42 MOVSD	0x1f63e(%RIP),%XMM0

  (214) 0x425d4a ADDSD	%XMM4,%XMM3

  (214) 0x425d4e MULSD	%XMM3,%XMM0

  (214) 0x425d52 CALL	4041a0 <fmin@plt>

  (214) 0x425d57 MOVSD	0x38(%RSP),%XMM8

  (214) 0x425d5e MOVSD	0x1f4ca(%RIP),%XMM6

  (214) 0x425d66 PXOR	%XMM5,%XMM5

  (214) 0x425d6a MOVSD	0x28(%RSP),%XMM11

  (214) 0x425d71 MOVQ	0x1ee77(%RIP),%XMM7

  (214) 0x425d79 MOVAPD	%XMM6,%XMM2

  (214) 0x425d7d MOV	0x48(%RSP),%R10

  (214) 0x425d82 MOV	0x50(%RSP),%R11

  (214) 0x425d87 SUBSD	%XMM8,%XMM2

  (214) 0x425d8c MOV	0x58(%RSP),%RAX

  (214) 0x425d91 MOV	0x60(%RSP),%R9

  (214) 0x425d96 MOVSD	0x30(%RSP),%XMM9

  (214) 0x425d9d MOVSD	0x40(%RSP),%XMM10

  (214) 0x425da4 MOV	0x68(%RSP),%R8

  (214) 0x425da9 MULSD	%XMM11,%XMM2

  (214) 0x425dae MULSD	%XMM0,%XMM2

  (214) 0x425db2 ADDSD	%XMM10,%XMM2

  (214) 0x425db7 MOV	0x90(%RSP),%RDI

  (214) 0x425dbf IMUL	%R9,%RBP

  (214) 0x425dc3 IMUL	%R9,%R12

  (214) 0x425dc7 MULSD	%XMM9,%XMM2

  (214) 0x425dcc IMUL	%R9,%RAX

  (214) 0x425dd0 MOVSD	0x1e7c7(%RIP),%XMM9

  (214) 0x425dd9 ADD	%RBX,%RBP

  (214) 0x425ddc ADD	%RBX,%R12

  (214) 0x425ddf ADD	%RBX,%RAX

  (214) 0x425de2 MOVSD	%XMM2,(%RDI,%RBX,8)

  (214) 0x425de7 MOVSD	(%R14,%RBP,8),%XMM8

  (214) 0x425ded MOVSD	(%R14,%R12,8),%XMM1

  (214) 0x425df3 SUBSD	%XMM8,%XMM1

  (214) 0x425df8 MOVAPD	%XMM8,%XMM0

  (214) 0x425dfd SUBSD	(%R14,%RAX,8),%XMM0

  (214) 0x425e03 MOVAPD	%XMM1,%XMM3

  (214) 0x425e07 CMPSD	$0x2,%XMM5,%XMM3

  (214) 0x425e0c ANDPD	%XMM3,%XMM9

  (214) 0x425e11 ANDNPD	%XMM6,%XMM3

  (214) 0x425e15 ORPD	%XMM3,%XMM9

  (214) 0x425e1a MOVAPD	%XMM0,%XMM3

  (214) 0x425e1e MULSD	%XMM1,%XMM3

  (214) 0x425e22 COMISD	%XMM5,%XMM3

  (214) 0x425e26 JBE	425f88

  (214) 0x425e2c MOVAPD	%XMM0,%XMM4

  (214) 0x425e30 ANDPD	%XMM7,%XMM1

  (214) 0x425e34 MOV	%R8,0x58(%RSP)

  (214) 0x425e39 ANDPD	%XMM7,%XMM4

  (214) 0x425e3d MOV	%R9,0x50(%RSP)

  (214) 0x425e42 MOVAPD	%XMM4,%XMM0

  (214) 0x425e46 MOV	%R11,0x48(%RSP)

  (214) 0x425e4b MOV	%R10,0x40(%RSP)

  (214) 0x425e50 MOVSD	%XMM8,0x38(%RSP)

  (214) 0x425e57 MOVSD	%XMM2,0x30(%RSP)

  (214) 0x425e5d MOVSD	%XMM9,0x28(%RSP)

  (214) 0x425e64 MOVSD	%XMM1,0x20(%RSP)

  (214) 0x425e6a MOVSD	%XMM4,0x18(%RSP)

  (214) 0x425e70 CALL	4041a0 <fmin@plt>

  (214) 0x425e75 MOVSD	0x18(%RSP),%XMM4

  (214) 0x425e7b MULSD	(%RSP),%XMM4

  (214) 0x425e80 MOVSD	0x20(%RSP),%XMM3

  (214) 0x425e86 MULSD	0x8(%RSP),%XMM3

  (214) 0x425e8c MOVAPD	%XMM0,%XMM1

  (214) 0x425e90 MOVSD	0x1f4f0(%RIP),%XMM0

  (214) 0x425e98 ADDSD	%XMM4,%XMM3

  (214) 0x425e9c MULSD	%XMM3,%XMM0

  (214) 0x425ea0 CALL	4041a0 <fmin@plt>

  (214) 0x425ea5 MOV	0x40(%RSP),%R10

  (214) 0x425eaa MOV	0x48(%RSP),%R11

  (214) 0x425eaf PXOR	%XMM5,%XMM5

  (214) 0x425eb3 MOVAPD	%XMM0,%XMM3

  (214) 0x425eb7 MOVSD	0x30(%RSP),%XMM2

  (214) 0x425ebd MOVQ	0x1ed2b(%RIP),%XMM7

  (214) 0x425ec5 MOVSD	(%R10),%XMM0

  (214) 0x425eca MULSD	(%R11),%XMM0

  (214) 0x425ecf MOVAPD	%XMM2,%XMM1

  (214) 0x425ed3 MOVSD	0x1f355(%RIP),%XMM6

  (214) 0x425edb MOVSD	0x28(%RSP),%XMM9

  (214) 0x425ee2 ANDPD	%XMM7,%XMM1

  (214) 0x425ee6 MOVSD	0x38(%RSP),%XMM8

  (214) 0x425eed MOV	0x58(%RSP),%R8

  (214) 0x425ef2 MOV	0xa8(%RSP),%RAX

  (214) 0x425efa CMP	%R8,0xa0(%RSP)

  (214) 0x425f02 MOV	0x50(%RSP),%R9

  (214) 0x425f07 DIVSD	%XMM0,%XMM1

  (214) 0x425f0b MOVAPD	%XMM6,%XMM0

  (214) 0x425f0f SUBSD	%XMM1,%XMM0

  (214) 0x425f13 MULSD	%XMM9,%XMM0

  (214) 0x425f18 MULSD	%XMM3,%XMM0

  (214) 0x425f1c ADDSD	%XMM8,%XMM0

  (214) 0x425f21 MULSD	%XMM0,%XMM2

  (214) 0x425f25 MOVSD	%XMM2,(%RAX,%RBX,8)

  (214) 0x425f2a MOV	%R8,%RBX

  (214) 0x425f2d JE	425fad

  (214) 0x425f2f ADD	$0x1,%R8

  (214) 0x425f33 MOV	0x98(%RSP),%RAX

  (214) 0x425f3b MOVSD	(%RAX,%RBX,8),%XMM9

  (214) 0x425f41 COMISD	%XMM5,%XMM9

  (214) 0x425f46 JA	425be8

  (214) 0x425f4c MOV	0xc0(%RSP),%RAX

  (214) 0x425f54 MOV	0xb0(%RSP),%R12

  (214) 0x425f5c MOV	0x10(%RSP),%RBP

  (214) 0x425f61 MOV	%RAX,%RDX

  (214) 0x425f64 JMP	425c00

0x425f69 NOPL	(%RAX)

0x425f70 ADD	$0x128,%RSP

0x425f77 POP	%RBX

0x425f78 POP	%RBP

0x425f79 POP	%R12

0x425f7b POP	%R13

0x425f7d POP	%R14

0x425f7f POP	%R15

0x425f81 RET

0x425f82 NOPW	(%RAX,%RAX,1)

  (214) 0x425f88 ADDSD	%XMM5,%XMM8

  (214) 0x425f8d MOV	0xa8(%RSP),%RAX

  (214) 0x425f95 MULSD	%XMM2,%XMM8

  (214) 0x425f9a MOVSD	%XMM8,(%RAX,%RBX,8)

  (214) 0x425fa0 MOV	%R8,%RBX

  (214) 0x425fa3 CMP	%R8,0xa0(%RSP)

  (214) 0x425fab JNE	425f2f

(213) 0x425fad MOV	0xd0(%RSP),%R9D

(213) 0x425fb5 MOV	0xc8(%RSP),%R12

(213) 0x425fbd MOV	0xd4(%RSP),%R13D

(213) 0x425fc5 MOV	0xd8(%RSP),%EBP

(213) 0x425fcc MOV	0x10(%RSP),%R11

(213) 0x425fd1 MOV	%R9D,%ECX

(213) 0x425fd4 MOV	%R11,%R10

(213) 0x425fd7 ADD	$0x1,%R13D

(213) 0x425fdb CMP	%EBP,0xec(%RSP)

(213) 0x425fe2 JLE	425f70

(213) 0x425fe4 MOV	0xe8(%RSP),%ESI

(213) 0x425feb MOV	0xe0(%RSP),%EAX

(213) 0x425ff2 MOV	0xdc(%RSP),%EBX

(213) 0x425ff9 SUB	%ECX,%ESI

(213) 0x425ffb JMP	425aa0

  (214) 0x426000 PXOR	%XMM2,%XMM2

  (214) 0x426004 JMP	425db2

0x426009 ADD	$0x1,%ESI

0x42600c XOR	%EDX,%EDX

0x42600e JMP	4259ee

0x426013 NOPW	%CS:(%RAX,%RAX,1)

0x42601e XCHG	%AX,%AX

Coverage (%)	Name	Source Location	Module
►96.84+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►1.58+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	advec_cell_kernel(int, int, in[...]		exec
○	advec_cell_driver(global_varia[...]		exec
○	advection(global_variables&)		exec
○	hydro(global_variables&, paral[...]		exec
○	main		exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec
►1.53+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	advec_cell_kernel(int, int, in[...]		exec
○	advec_cell_driver(global_varia[...]		exec
○	advection(global_variables&)		exec
○	hydro(global_variables&, paral[...]		exec
○	main		exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines
Module	exec

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.00 to 1.33 cycles (9.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 8% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 12.00 to 0.77 cycles (15.55x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 12.00 to 11.25 cycles (1.07x speedup).

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 11.00 cycles (1.09x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
omp_get_thread_num@plt: 1 occurrences►

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 100 bytes. The binary function is storing 72 bytes.

General properties

nb instructions	92
nb uops	90
loop length	377
used x86 registers	14
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	21

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	11.25 cycles
front end	11.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.83	5.83	5.83	5.83	5.83	5.83	7.50	7.50	7.50	7.50	0.00	0.00	0.00	0.00	0.00	0.00
cycles	5.83	5.83	5.83	5.83	5.83	5.83	7.50	7.50	7.50	7.50	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	11.25
Dispatch	7.50
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	8%
load	9%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	8%
load	10%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

3% of peak load performance is reached (8.33 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (6.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 425960

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x128,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0x44(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x40(%RDI),%EDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %EAX,0xe4(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
LEA 0x4(%RAX),%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV 0x38(%RBP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
LEA 0x1(%RDI),%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV 0x3c(%RBP),%EDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD $0x1,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %EAX,0xdc(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %R11D,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 425f70 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.6+0x610>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %R11D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
LEA 0x2(%RDI),%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %R11D,(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
SUB %R14D,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMP %R13D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 425f70 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.6+0x610>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %R13D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SUB %EAX,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %R15D,0xe0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CALL 404660 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV %EAX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404550 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV (%RSP),%R11D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R12D,%EAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
DIV %EBX	2	0	0	0	2	0	0	0	0	0	0	10-17	6	scal (6.3%)
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JB 426009 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.6+0x6a9>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
IMUL %ESI,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
ADD %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA (%RSI,%RCX,1),%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %EAX,0xe8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %EAX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JAE 425f70 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.6+0x610>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0xdc(%RSP),%EDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x30(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
DIVL 0xe0(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	10-17	6	scal (6.3%)
MOV %R11D,0xec(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVQ 0x1f1c5(%RIP),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOVSD 0x1f7fd(%RIP),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
MOV %R10,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
LEA (%RDX,%RDI,1),%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV 0x20(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
LEA (%RAX,%R14,1),%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %R13D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %EBX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA -0x2(%RDX),%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %RDI,0xf0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x28(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDI,0xf8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV (%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDI,0x100(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x8(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDI,0x108(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x18(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDI,0x110(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x10(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDI,0x118(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOVSXD %EDX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
SUB $0x1,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %RDI,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0x128,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0x1,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 4259ee <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.6+0x8e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines
Module	exec

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.00 to 1.33 cycles (9.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 11.00 cycles (1.09x speedup).

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
omp_get_thread_num@plt: 1 occurrences►

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 100 bytes. The binary function is storing 72 bytes.

General properties

nb instructions	92
nb uops	90
loop length	377
used x86 registers	14
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	21

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	11.25 cycles
front end	11.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.83	5.83	5.83	5.83	5.83	5.83	7.50	7.50	7.50	7.50	0.00	0.00	0.00	0.00	0.00	0.00
cycles	5.83	5.83	5.83	5.83	5.83	5.83	7.50	7.50	7.50	7.50	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	11.25
Dispatch	7.50
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	8%
load	9%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	8%
load	10%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

3% of peak load performance is reached (8.33 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (6.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 425960

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x128,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0x44(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x40(%RDI),%EDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %EAX,0xe4(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
LEA 0x4(%RAX),%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV 0x38(%RBP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
LEA 0x1(%RDI),%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV 0x3c(%RBP),%EDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD $0x1,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %EAX,0xdc(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %R11D,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 425f70 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.6+0x610>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %R11D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
LEA 0x2(%RDI),%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %R11D,(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
SUB %R14D,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMP %R13D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 425f70 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.6+0x610>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %R13D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SUB %EAX,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %R15D,0xe0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CALL 404660 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV %EAX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404550 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV (%RSP),%R11D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R12D,%EAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
DIV %EBX	2	0	0	0	2	0	0	0	0	0	0	10-17	6	scal (6.3%)
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JB 426009 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.6+0x6a9>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
IMUL %ESI,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
ADD %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA (%RSI,%RCX,1),%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %EAX,0xe8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %EAX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JAE 425f70 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.6+0x610>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0xdc(%RSP),%EDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x30(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
DIVL 0xe0(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	10-17	6	scal (6.3%)
MOV %R11D,0xec(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVQ 0x1f1c5(%RIP),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOVSD 0x1f7fd(%RIP),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
MOV %R10,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
LEA (%RDX,%RDI,1),%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV 0x20(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
LEA (%RAX,%R14,1),%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %R13D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %EBX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA -0x2(%RDX),%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %RDI,0xf0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x28(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDI,0xf8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV (%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDI,0x100(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x8(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDI,0x108(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x18(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDI,0x110(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x10(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDI,0x118(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOVSXD %EDX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
SUB $0x1,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %RDI,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0x128,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0x1,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 4259ee <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.6+0x8e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	3.46	1.32
▼Loop 213 - - exec–	0.01	0.01
○Loop 214 - - exec	3.45	1.32

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

CALL instructions

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Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code