OV - exec - Function advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ...	Module: exec	Source: :0-0	Coverage (incl. loops): 3.41% \| (excl. loops): 0.00%

  ***  This Panel is Intentionally Left Blank.  ***

It is due to a lack of debug symbols in the given object
(loop or function).

0x425300 PUSH	%R15

0x425302 PUSH	%R14

0x425304 PUSH	%R13

0x425306 PUSH	%R12

0x425308 PUSH	%RBP

0x425309 PUSH	%RBX

0x42530a SUB	$0x108,%RSP

0x425311 MOV	0x40(%RDI),%EAX

0x425314 MOV	0x38(%RDI),%EDX

0x425317 MOV	0x3c(%RDI),%ECX

0x42531a LEA	0x1(%RAX),%R12D

0x42531e MOV	0x44(%RDI),%EAX

0x425321 ADD	$0x1,%EDX

0x425324 MOV	%ECX,0xd8(%RSP)

0x42532b ADD	$0x2,%EAX

0x42532e MOV	%EDX,0xd0(%RSP)

0x425335 MOV	%EAX,0xcc(%RSP)

0x42533c CMP	%EAX,%R12D

0x42533f JGE	4258a8

0x425345 MOV	%EAX,%R13D

0x425348 LEA	0x4(%RCX),%R14D

0x42534c SUB	%R12D,%R13D

0x42534f CMP	%R14D,%EDX

0x425352 JGE	4258a8

0x425358 MOV	%R14D,%R15D

0x42535b MOV	%RDI,%RBP

0x42535e SUB	%EDX,%R15D

0x425361 MOV	%R15D,0xd4(%RSP)

0x425369 CALL	404660 <omp_get_num_threads@plt>

0x42536e MOV	%EAX,%EBX

0x425370 CALL	404550 <omp_get_thread_num@plt>

0x425375 XOR	%EDX,%EDX

0x425377 MOV	%EAX,%ECX

0x425379 MOV	%R15D,%EAX

0x42537c IMUL	%R13D,%EAX

0x425380 DIV	%EBX

0x425382 MOV	%EAX,%ESI

0x425384 CMP	%EDX,%ECX

0x425386 JB	425949

0x42538c IMUL	%ESI,%ECX

0x42538f ADD	%EDX,%ECX

0x425391 LEA	(%RSI,%RCX,1),%EAX

0x425394 MOV	%EAX,0xdc(%RSP)

0x42539b CMP	%EAX,%ECX

0x42539d JAE	4258a8

0x4253a3 MOV	%ECX,%EAX

0x4253a5 XOR	%EDX,%EDX

0x4253a7 MOV	0xd0(%RSP),%EDI

0x4253ae MOV	0x20(%RBP),%R13

0x4253b2 DIVL	0xd4(%RSP)

0x4253b9 MOVQ	0x1f82f(%RIP),%XMM7

0x4253c1 MOVSD	0x1fe67(%RIP),%XMM6

0x4253c9 MOV	0x18(%RBP),%R11

0x4253cd LEA	(%RDX,%RDI,1),%EBX

0x4253d0 MOV	0x28(%RBP),%RDX

0x4253d4 ADD	%R12D,%EAX

0x4253d7 MOVSXD	%EAX,%R12

0x4253da SUB	%EBX,%R14D

0x4253dd MOV	%RDX,0xe0(%RSP)

0x4253e5 MOV	(%RBP),%RDX

0x4253e9 MOV	%R14D,%R8D

0x4253ec MOV	%RDX,0xe8(%RSP)

0x4253f4 MOV	0x8(%RBP),%RDX

0x4253f8 MOV	%RDX,0xf0(%RSP)

0x425400 MOV	0x10(%RBP),%RDX

0x425404 MOV	%RDX,0xf8(%RSP)

0x42540c MOV	0x30(%RBP),%RDX

0x425410 MOV	%R12,%RBP

0x425413 MOV	%RDX,%R12

0x425416 NOPW	%CS:(%RAX,%RAX,1)

(211) 0x425420 CMP	%R8D,%ESI

(211) 0x425423 CMOVBE	%ESI,%R8D

(211) 0x425427 LEA	(%RCX,%R8,1),%EAX

(211) 0x42542b MOV	%EAX,0xc8(%RSP)

(211) 0x425432 CMP	%EAX,%ECX

(211) 0x425434 JAE	425910

(211) 0x42543a MOV	(%R13),%R9

(211) 0x42543e MOVSXD	%EBX,%RBX

(211) 0x425441 SUB	$0x1,%R8D

(211) 0x425445 PXOR	%XMM5,%XMM5

(211) 0x425449 MOV	0xe0(%RSP),%RAX

(211) 0x425451 LEA	0x1(%RBX),%R14

(211) 0x425455 MOV	%R13,0xa8(%RSP)

(211) 0x42545d IMUL	%RBP,%R9

(211) 0x425461 MOV	%R11,0xb0(%RSP)

(211) 0x425469 MOV	0x10(%RAX),%RDX

(211) 0x42546d MOV	%R12,0xb8(%RSP)

(211) 0x425475 MOV	%RBP,0xc0(%RSP)

(211) 0x42547d MOV	%RDX,0x70(%RSP)

(211) 0x425482 MOV	(%RAX),%RDX

(211) 0x425485 MOV	0xe8(%RSP),%RAX

(211) 0x42548d IMUL	%RBP,%RDX

(211) 0x425491 MOV	0x8(%RAX),%R10

(211) 0x425495 MOV	0xf0(%RSP),%RAX

(211) 0x42549d MOV	0x10(%RAX),%RDI

(211) 0x4254a1 MOV	(%RAX),%RSI

(211) 0x4254a4 MOV	%RDX,0x78(%RSP)

(211) 0x4254a9 MOV	0xf8(%RSP),%RAX

(211) 0x4254b1 IMUL	%RBP,%RSI

(211) 0x4254b5 MOV	(%RAX),%R15

(211) 0x4254b8 MOV	0x10(%RAX),%RCX

(211) 0x4254bc LEA	(%R14,%R8,1),%RAX

(211) 0x4254c0 MOV	0x10(%R13),%R8

(211) 0x4254c4 MOV	%RAX,0x90(%RSP)

(211) 0x4254cc IMUL	%RBP,%R15

(211) 0x4254d0 LEA	(%R8,%R9,8),%RAX

(211) 0x4254d4 MOV	(%R11),%R9

(211) 0x4254d7 MOV	0x10(%R11),%R8

(211) 0x4254db MOV	%RAX,0x88(%RSP)

(211) 0x4254e3 IMUL	%RBP,%R9

(211) 0x4254e7 MOV	%R15,%RDX

(211) 0x4254ea MOV	%RSI,%R15

(211) 0x4254ed LEA	(%R8,%R9,8),%RAX

(211) 0x4254f1 MOV	(%R12),%R9

(211) 0x4254f5 MOV	0x10(%R12),%R8

(211) 0x4254fa MOV	%RAX,0x80(%RSP)

(211) 0x425502 IMUL	%RBP,%R9

(211) 0x425506 LEA	(%R8,%R9,8),%RAX

(211) 0x42550a MOV	%RAX,0x98(%RSP)

(211) 0x425512 MOV	0xd8(%RSP),%EAX

(211) 0x425519 ADD	$0x2,%EAX

(211) 0x42551c MOV	%EAX,0xa4(%RSP)

(211) 0x425523 MOV	%R14,%RAX

(211) 0x425526 MOV	%RDI,%R14

(211) 0x425529 JMP	425868

0x42552e XCHG	%AX,%AX

  (212) 0x425530 LEA	-0x1(%RBX),%RBP

  (212) 0x425534 LEA	-0x2(%RBX),%R12D

  (212) 0x425538 MOV	%RBX,%R13

  (212) 0x42553b MOVSXD	%R12D,%R12

  (212) 0x42553e MOV	%RBP,%R8

  (212) 0x425541 MOV	0x78(%RSP),%RSI

  (212) 0x425546 MOV	0x70(%RSP),%RDI

  (212) 0x42554b MOVAPD	%XMM9,%XMM8

  (212) 0x425550 LEA	(%R15,%R12,1),%R11

  (212) 0x425554 ANDPD	%XMM7,%XMM8

  (212) 0x425559 MOVSD	(%R10,%RBX,8),%XMM0

  (212) 0x42555f DIVSD	(%R10,%R8,8),%XMM0

  (212) 0x425565 LEA	(%R15,%RBP,1),%R8

  (212) 0x425569 LEA	(%RSI,%RBP,1),%R9

  (212) 0x42556d LEA	(%R14,%R8,8),%R8

  (212) 0x425571 MOVSD	0x1fe07(%RIP),%XMM4

  (212) 0x425579 MOVSD	0x1f01e(%RIP),%XMM11

  (212) 0x425582 LEA	(%RDI,%R9,8),%R9

  (212) 0x425586 MOVSD	(%R8),%XMM10

  (212) 0x42558b DIVSD	(%R9),%XMM8

  (212) 0x425590 MOVAPD	%XMM8,%XMM1

  (212) 0x425595 SUBSD	%XMM8,%XMM4

  (212) 0x42559a ADDSD	%XMM6,%XMM1

  (212) 0x42559e MOVSD	%XMM4,0x8(%RSP)

  (212) 0x4255a4 MULSD	%XMM1,%XMM0

  (212) 0x4255a8 MOVSD	%XMM0,(%RSP)

  (212) 0x4255ad MOVAPD	%XMM10,%XMM0

  (212) 0x4255b2 SUBSD	(%R14,%R11,8),%XMM0

  (212) 0x4255b8 LEA	(%R15,%R13,1),%R11

  (212) 0x4255bc MOVSD	(%R14,%R11,8),%XMM1

  (212) 0x4255c2 SUBSD	%XMM10,%XMM1

  (212) 0x4255c7 MOVAPD	%XMM0,%XMM2

  (212) 0x4255cb MULSD	%XMM1,%XMM2

  (212) 0x4255cf MOVAPD	%XMM1,%XMM3

  (212) 0x4255d3 CMPSD	$0x2,%XMM5,%XMM3

  (212) 0x4255d8 ANDPD	%XMM3,%XMM11

  (212) 0x4255dd ANDNPD	%XMM6,%XMM3

  (212) 0x4255e1 COMISD	%XMM5,%XMM2

  (212) 0x4255e5 ORPD	%XMM3,%XMM11

  (212) 0x4255ea JBE	425940

  (212) 0x4255f0 MOVAPD	%XMM0,%XMM4

  (212) 0x4255f4 ANDPD	%XMM7,%XMM1

  (212) 0x4255f8 MOV	%RAX,0x68(%RSP)

  (212) 0x4255fd ANDPD	%XMM7,%XMM4

  (212) 0x425601 MOV	%RDX,0x60(%RSP)

  (212) 0x425606 MOVAPD	%XMM4,%XMM0

  (212) 0x42560a MOV	%RCX,0x58(%RSP)

  (212) 0x42560f MOV	%R10,0x50(%RSP)

  (212) 0x425614 MOV	%R9,0x48(%RSP)

  (212) 0x425619 MOV	%R8,0x40(%RSP)

  (212) 0x42561e MOVSD	%XMM10,0x38(%RSP)

  (212) 0x425625 MOVSD	%XMM8,0x30(%RSP)

  (212) 0x42562c MOVSD	%XMM9,0x28(%RSP)

  (212) 0x425633 MOVSD	%XMM11,0x20(%RSP)

  (212) 0x42563a MOVSD	%XMM1,0x18(%RSP)

  (212) 0x425640 MOVSD	%XMM4,0x10(%RSP)

  (212) 0x425646 CALL	4041a0 <fmin@plt>

  (212) 0x42564b MOVSD	0x10(%RSP),%XMM4

  (212) 0x425651 MULSD	(%RSP),%XMM4

  (212) 0x425656 MOVSD	0x18(%RSP),%XMM3

  (212) 0x42565c MULSD	0x8(%RSP),%XMM3

  (212) 0x425662 MOVAPD	%XMM0,%XMM1

  (212) 0x425666 MOVSD	0x1fd1a(%RIP),%XMM0

  (212) 0x42566e ADDSD	%XMM4,%XMM3

  (212) 0x425672 MULSD	%XMM3,%XMM0

  (212) 0x425676 CALL	4041a0 <fmin@plt>

  (212) 0x42567b MOVSD	0x30(%RSP),%XMM8

  (212) 0x425682 MOVSD	0x1fba6(%RIP),%XMM6

  (212) 0x42568a PXOR	%XMM5,%XMM5

  (212) 0x42568e MOVSD	0x20(%RSP),%XMM11

  (212) 0x425695 MOVQ	0x1f553(%RIP),%XMM7

  (212) 0x42569d MOVAPD	%XMM6,%XMM2

  (212) 0x4256a1 MOV	0x40(%RSP),%R8

  (212) 0x4256a6 MOV	0x48(%RSP),%R9

  (212) 0x4256ab SUBSD	%XMM8,%XMM2

  (212) 0x4256b0 MOV	0x50(%RSP),%R10

  (212) 0x4256b5 MOV	0x58(%RSP),%RCX

  (212) 0x4256ba MOVSD	0x28(%RSP),%XMM9

  (212) 0x4256c1 MOVSD	0x38(%RSP),%XMM10

  (212) 0x4256c8 MOV	0x60(%RSP),%RDX

  (212) 0x4256cd MOV	0x68(%RSP),%RAX

  (212) 0x4256d2 MULSD	%XMM11,%XMM2

  (212) 0x4256d7 MULSD	%XMM0,%XMM2

  (212) 0x4256db ADDSD	%XMM10,%XMM2

  (212) 0x4256e0 ADD	%RDX,%RBP

  (212) 0x4256e3 ADD	%RDX,%R13

  (212) 0x4256e6 ADD	%RDX,%R12

  (212) 0x4256e9 MOV	0x80(%RSP),%RSI

  (212) 0x4256f1 MULSD	%XMM9,%XMM2

  (212) 0x4256f6 MOVSD	0x1eea1(%RIP),%XMM9

  (212) 0x4256ff MOVSD	%XMM2,(%RSI,%RBX,8)

  (212) 0x425704 MOVSD	(%RCX,%RBP,8),%XMM8

  (212) 0x42570a MOVSD	(%RCX,%R13,8),%XMM1

  (212) 0x425710 SUBSD	%XMM8,%XMM1

  (212) 0x425715 MOVAPD	%XMM8,%XMM0

  (212) 0x42571a SUBSD	(%RCX,%R12,8),%XMM0

  (212) 0x425720 MOVAPD	%XMM1,%XMM3

  (212) 0x425724 CMPSD	$0x2,%XMM5,%XMM3

  (212) 0x425729 ANDPD	%XMM3,%XMM9

  (212) 0x42572e ANDNPD	%XMM6,%XMM3

  (212) 0x425732 ORPD	%XMM3,%XMM9

  (212) 0x425737 MOVAPD	%XMM0,%XMM3

  (212) 0x42573b MULSD	%XMM1,%XMM3

  (212) 0x42573f COMISD	%XMM5,%XMM3

  (212) 0x425743 JBE	4258c0

  (212) 0x425749 MOVAPD	%XMM0,%XMM4

  (212) 0x42574d ANDPD	%XMM7,%XMM1

  (212) 0x425751 MOV	%RAX,0x60(%RSP)

  (212) 0x425756 ANDPD	%XMM7,%XMM4

  (212) 0x42575a MOV	%RDX,0x58(%RSP)

  (212) 0x42575f MOVAPD	%XMM4,%XMM0

  (212) 0x425763 MOV	%RCX,0x50(%RSP)

  (212) 0x425768 MOV	%R10,0x48(%RSP)

  (212) 0x42576d MOV	%R9,0x40(%RSP)

  (212) 0x425772 MOV	%R8,0x38(%RSP)

  (212) 0x425777 MOVSD	%XMM8,0x30(%RSP)

  (212) 0x42577e MOVSD	%XMM2,0x28(%RSP)

  (212) 0x425784 MOVSD	%XMM9,0x20(%RSP)

  (212) 0x42578b MOVSD	%XMM1,0x18(%RSP)

  (212) 0x425791 MOVSD	%XMM4,0x10(%RSP)

  (212) 0x425797 CALL	4041a0 <fmin@plt>

  (212) 0x42579c MOVSD	0x10(%RSP),%XMM4

  (212) 0x4257a2 MULSD	(%RSP),%XMM4

  (212) 0x4257a7 MOVSD	0x18(%RSP),%XMM3

  (212) 0x4257ad MULSD	0x8(%RSP),%XMM3

  (212) 0x4257b3 MOVAPD	%XMM0,%XMM1

  (212) 0x4257b7 MOVSD	0x1fbc9(%RIP),%XMM0

  (212) 0x4257bf ADDSD	%XMM4,%XMM3

  (212) 0x4257c3 MULSD	%XMM3,%XMM0

  (212) 0x4257c7 CALL	4041a0 <fmin@plt>

  (212) 0x4257cc MOV	0x38(%RSP),%R8

  (212) 0x4257d1 MOV	0x40(%RSP),%R9

  (212) 0x4257d6 PXOR	%XMM5,%XMM5

  (212) 0x4257da MOVAPD	%XMM0,%XMM3

  (212) 0x4257de MOVSD	0x28(%RSP),%XMM2

  (212) 0x4257e4 MOVQ	0x1f404(%RIP),%XMM7

  (212) 0x4257ec MOVSD	(%R8),%XMM0

  (212) 0x4257f1 MULSD	(%R9),%XMM0

  (212) 0x4257f6 MOVAPD	%XMM2,%XMM1

  (212) 0x4257fa MOVSD	0x1fa2e(%RIP),%XMM6

  (212) 0x425802 MOVSD	0x20(%RSP),%XMM9

  (212) 0x425809 ANDPD	%XMM7,%XMM1

  (212) 0x42580d MOV	0x48(%RSP),%R10

  (212) 0x425812 MOV	0x50(%RSP),%RCX

  (212) 0x425817 MOVSD	0x30(%RSP),%XMM8

  (212) 0x42581e MOV	0x98(%RSP),%RAX

  (212) 0x425826 MOV	0x58(%RSP),%RDX

  (212) 0x42582b DIVSD	%XMM0,%XMM1

  (212) 0x42582f MOVAPD	%XMM6,%XMM0

  (212) 0x425833 SUBSD	%XMM1,%XMM0

  (212) 0x425837 MULSD	%XMM9,%XMM0

  (212) 0x42583c MULSD	%XMM3,%XMM0

  (212) 0x425840 ADDSD	%XMM8,%XMM0

  (212) 0x425845 MULSD	%XMM0,%XMM2

  (212) 0x425849 MOVSD	%XMM2,(%RAX,%RBX,8)

  (212) 0x42584e MOV	0x60(%RSP),%RAX

  (212) 0x425853 CMP	%RAX,0x90(%RSP)

  (212) 0x42585b MOV	%RAX,%RBX

  (212) 0x42585e JE	4258e9

  (212) 0x425864 ADD	$0x1,%RAX

  (212) 0x425868 MOV	0x88(%RSP),%RDI

  (212) 0x425870 MOVSD	(%RDI,%RBX,8),%XMM9

  (212) 0x425876 COMISD	%XMM5,%XMM9

  (212) 0x42587b JA	425530

  (212) 0x425881 MOV	0xa4(%RSP),%EDI

  (212) 0x425888 LEA	0x1(%RBX),%R8D

  (212) 0x42588c LEA	-0x1(%RBX),%R13

  (212) 0x425890 MOV	%RBX,%RBP

  (212) 0x425893 CMP	%R8D,%EDI

  (212) 0x425896 CMOVLE	%EDI,%R8D

  (212) 0x42589a MOVSXD	%R8D,%R8

  (212) 0x42589d MOV	%R8,%R12

  (212) 0x4258a0 JMP	425541

0x4258a5 NOPL	(%RAX)

0x4258a8 ADD	$0x108,%RSP

0x4258af POP	%RBX

0x4258b0 POP	%RBP

0x4258b1 POP	%R12

0x4258b3 POP	%R13

0x4258b5 POP	%R14

0x4258b7 POP	%R15

0x4258b9 RET

0x4258ba NOPW	(%RAX,%RAX,1)

  (212) 0x4258c0 ADDSD	%XMM5,%XMM8

  (212) 0x4258c5 MOV	0x98(%RSP),%RSI

  (212) 0x4258cd MULSD	%XMM2,%XMM8

  (212) 0x4258d2 MOVSD	%XMM8,(%RSI,%RBX,8)

  (212) 0x4258d8 MOV	%RAX,%RBX

  (212) 0x4258db CMP	%RAX,0x90(%RSP)

  (212) 0x4258e3 JNE	425864

(211) 0x4258e9 MOV	0xa8(%RSP),%R13

(211) 0x4258f1 MOV	0xb0(%RSP),%R11

(211) 0x4258f9 MOV	0xb8(%RSP),%R12

(211) 0x425901 MOV	0xc0(%RSP),%RBP

(211) 0x425909 MOV	0xc8(%RSP),%ECX

(211) 0x425910 ADD	$0x1,%RBP

(211) 0x425914 CMP	%EBP,0xcc(%RSP)

(211) 0x42591b JLE	4258a8

(211) 0x42591d MOV	0xdc(%RSP),%ESI

(211) 0x425924 MOV	0xd4(%RSP),%R8D

(211) 0x42592c MOV	0xd0(%RSP),%EBX

(211) 0x425933 SUB	%ECX,%ESI

(211) 0x425935 JMP	425420

0x42593a NOPW	(%RAX,%RAX,1)

  (212) 0x425940 PXOR	%XMM2,%XMM2

  (212) 0x425944 JMP	4256db

0x425949 ADD	$0x1,%ESI

0x42594c XOR	%EDX,%EDX

0x42594e JMP	42538c

0x425953 NOPW	%CS:(%RAX,%RAX,1)

0x42595e XCHG	%AX,%AX

Coverage (%)	Name	Source Location	Module
►96.89+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►1.57+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	advec_cell_kernel(int, int, in[...]		exec
○	advec_cell_driver(global_varia[...]		exec
○	advection(global_variables&)		exec
○	hydro(global_variables&, paral[...]		exec
○	main		exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec
►1.54+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	advec_cell_kernel(int, int, in[...]		exec
○	advec_cell_driver(global_varia[...]		exec
○	advection(global_variables&)		exec
○	hydro(global_variables&, paral[...]		exec
○	main		exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines
Module	exec

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.00 to 1.33 cycles (9.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 8% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 12.00 to 0.75 cycles (16.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 12.00 to 10.50 cycles (1.14x speedup).

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 10.25 cycles (1.17x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
omp_get_thread_num@plt: 1 occurrences►

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 96 bytes. The binary function is storing 52 bytes.

General properties

nb instructions	87
nb uops	84
loop length	346
used x86 registers	14
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	16

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.50 cycles
front end	10.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.50	5.50	5.50	5.50	5.50	5.50	6.50	6.50	6.50	6.50	0.00	0.00	0.00	0.00	0.00	0.00
cycles	5.50	5.50	5.50	5.50	5.50	5.50	6.50	6.50	6.50	6.50	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	10.50
Dispatch	6.50
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	8%
load	10%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	8%
load	11%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

3% of peak load performance is reached (8.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.33 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 425300

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x108,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0x40(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x38(%RDI),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x3c(%RDI),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
LEA 0x1(%RAX),%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV 0x44(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD $0x1,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %ECX,0xd8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
ADD $0x2,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %EDX,0xd0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %EAX,0xcc(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %EAX,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 4258a8 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x5a8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
LEA 0x4(%RCX),%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
SUB %R12D,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMP %R14D,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 4258a8 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x5a8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %R14D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV %RDI,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %EDX,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %R15D,0xd4(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CALL 404660 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV %EAX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404550 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R13D,%EAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
DIV %EBX	2	0	0	0	2	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JB 425949 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x649>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
IMUL %ESI,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
ADD %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA (%RSI,%RCX,1),%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %EAX,0xdc(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %EAX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JAE 4258a8 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x5a8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0xd0(%RSP),%EDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x20(%RBP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
DIVL 0xd4(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	10-17	6	scal (6.3%)
MOVQ 0x1f82f(%RIP),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOVSD 0x1fe67(%RIP),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
MOV 0x18(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
LEA (%RDX,%RDI,1),%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV 0x28(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %R12D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOVSXD %EAX,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
SUB %EBX,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %RDX,0xe0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV (%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %R14D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV %RDX,0xe8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x8(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDX,0xf0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x10(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDX,0xf8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x30(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %R12,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0x108,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0x1,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 42538c <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x8c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines
Module	exec

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.00 to 1.33 cycles (9.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 10.25 cycles (1.17x speedup).

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
omp_get_thread_num@plt: 1 occurrences►

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 96 bytes. The binary function is storing 52 bytes.

General properties

nb instructions	87
nb uops	84
loop length	346
used x86 registers	14
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	16

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.50 cycles
front end	10.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.50	5.50	5.50	5.50	5.50	5.50	6.50	6.50	6.50	6.50	0.00	0.00	0.00	0.00	0.00	0.00
cycles	5.50	5.50	5.50	5.50	5.50	5.50	6.50	6.50	6.50	6.50	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	10.50
Dispatch	6.50
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	8%
load	10%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	8%
load	11%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

3% of peak load performance is reached (8.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.33 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 425300

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x108,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0x40(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x38(%RDI),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x3c(%RDI),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
LEA 0x1(%RAX),%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV 0x44(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD $0x1,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %ECX,0xd8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
ADD $0x2,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %EDX,0xd0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %EAX,0xcc(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %EAX,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 4258a8 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x5a8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
LEA 0x4(%RCX),%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
SUB %R12D,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMP %R14D,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 4258a8 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x5a8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %R14D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV %RDI,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %EDX,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %R15D,0xd4(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CALL 404660 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV %EAX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404550 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R13D,%EAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
DIV %EBX	2	0	0	0	2	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JB 425949 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x649>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
IMUL %ESI,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
ADD %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA (%RSI,%RCX,1),%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %EAX,0xdc(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %EAX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JAE 4258a8 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x5a8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0xd0(%RSP),%EDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x20(%RBP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
DIVL 0xd4(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	10-17	6	scal (6.3%)
MOVQ 0x1f82f(%RIP),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOVSD 0x1fe67(%RIP),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
MOV 0x18(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
LEA (%RDX,%RDI,1),%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV 0x28(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %R12D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOVSXD %EAX,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
SUB %EBX,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %RDX,0xe0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV (%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %R14D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV %RDX,0xe8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x8(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDX,0xf0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x10(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDX,0xf8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x30(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %R12,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0x108,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0x1,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 42538c <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x8c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	3.41	1.31
▼Loop 211 - - exec–	0.01	0.01
○Loop 212 - - exec	3.40	1.30

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Expensive FP math instructions/calls

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Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

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Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code