OV - exec - Function advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ...	Module: exec	Source: :0-0	Coverage (incl. loops): 3.40% \| (excl. loops): 0.00%

  ***  This Panel is Intentionally Left Blank.  ***

It is due to a lack of debug symbols in the given object
(loop or function).

0x424f30 PUSH	%R15

0x424f32 PUSH	%R14

0x424f34 PUSH	%R13

0x424f36 PUSH	%R12

0x424f38 PUSH	%RBP

0x424f39 PUSH	%RBX

0x424f3a MOV	%RDI,%RBX

0x424f3d SUB	$0xb8,%RSP

0x424f44 MOV	0x38(%RDI),%EAX

0x424f47 MOV	0x34(%RBX),%EDX

0x424f4a LEA	0x1(%RAX),%EBP

0x424f4d MOV	0x3c(%RDI),%EAX

0x424f50 MOV	0x30(%RDI),%EDI

0x424f53 ADD	$0x2,%EAX

0x424f56 ADD	$0x1,%EDI

0x424f59 MOV	%EAX,0x70(%RSP)

0x424f5d MOV	%EDI,0x74(%RSP)

0x424f61 CMP	%EAX,%EBP

0x424f63 JGE	4252d8

0x424f69 MOV	%EAX,%R13D

0x424f6c LEA	0x2(%RDX),%R14D

0x424f70 SUB	%EBP,%R13D

0x424f73 CMP	%R14D,%EDI

0x424f76 JGE	4252d8

0x424f7c MOV	%R14D,%R15D

0x424f7f SUB	%EDI,%R15D

0x424f82 MOV	%R15D,0x78(%RSP)

0x424f87 CALL	404660 <omp_get_num_threads@plt>

0x424f8c MOV	%EAX,%R12D

0x424f8f CALL	404550 <omp_get_thread_num@plt>

0x424f94 XOR	%EDX,%EDX

0x424f96 MOV	%EAX,%ECX

0x424f98 MOV	%R15D,%EAX

0x424f9b IMUL	%R13D,%EAX

0x424f9f DIV	%R12D

0x424fa2 MOV	%EAX,%EDI

0x424fa4 CMP	%EDX,%ECX

0x424fa6 JB	4252ea

0x424fac IMUL	%EDI,%ECX

0x424faf ADD	%EDX,%ECX

0x424fb1 LEA	(%RDI,%RCX,1),%EAX

0x424fb4 MOV	%EAX,0x7c(%RSP)

0x424fb8 CMP	%EAX,%ECX

0x424fba JAE	4252d8

0x424fc0 MOV	%ECX,%EAX

0x424fc2 XOR	%EDX,%EDX

0x424fc4 MOV	0x74(%RSP),%ESI

0x424fc8 DIVL	0x78(%RSP)

0x424fcc ADD	%ESI,%EDX

0x424fce MOV	%R14D,%ESI

0x424fd1 ADD	%EBP,%EAX

0x424fd3 MOV	%EDX,0x28(%RSP)

0x424fd7 SUB	%EDX,%ESI

0x424fd9 MOV	(%RBX),%RDX

0x424fdc MOVSXD	%EAX,%R13

0x424fdf MOV	%RDX,0x80(%RSP)

0x424fe7 MOV	0x20(%RBX),%RDX

0x424feb MOV	%RDX,0x88(%RSP)

0x424ff3 MOV	0x10(%RBX),%RDX

0x424ff7 MOV	%RDX,0x90(%RSP)

0x424fff MOV	0x8(%RBX),%RDX

0x425003 MOV	%RDX,0x98(%RSP)

0x42500b MOV	0x28(%RBX),%RDX

0x42500f MOV	0x18(%RBX),%RBX

0x425013 MOV	%RDX,0xa0(%RSP)

0x42501b MOV	%RBX,0xa8(%RSP)

0x425023 NOPW	%CS:(%RAX,%RAX,1)

0x42502e XCHG	%AX,%AX

(209) 0x425030 CMP	%ESI,%EDI

(209) 0x425032 CMOVA	%ESI,%EDI

(209) 0x425035 LEA	(%RCX,%RDI,1),%EAX

(209) 0x425038 MOV	%EAX,0x2c(%RSP)

(209) 0x42503c CMP	%EAX,%ECX

(209) 0x42503e JAE	4252b0

(209) 0x425044 MOV	0x80(%RSP),%RAX

(209) 0x42504c MOV	0x10(%RAX),%RCX

(209) 0x425050 MOV	(%RAX),%RDX

(209) 0x425053 MOV	0x88(%RSP),%RAX

(209) 0x42505b IMUL	%R13,%RDX

(209) 0x42505f MOV	%RCX,0x60(%RSP)

(209) 0x425064 MOV	0x10(%RAX),%R11

(209) 0x425068 MOV	(%RAX),%R9

(209) 0x42506b MOV	0x90(%RSP),%RAX

(209) 0x425073 IMUL	%R13,%R9

(209) 0x425077 MOV	%RDX,0x68(%RSP)

(209) 0x42507c MOV	0x10(%RAX),%R15

(209) 0x425080 MOV	(%RAX),%RAX

(209) 0x425083 MOV	%R11,0x50(%RSP)

(209) 0x425088 MOV	%RAX,%RBX

(209) 0x42508b MOV	%R9,0x58(%RSP)

(209) 0x425090 IMUL	%R13,%RBX

(209) 0x425094 ADD	%RBX,%RAX

(209) 0x425097 MOV	%RBX,0x48(%RSP)

(209) 0x42509c MOV	%RAX,0x20(%RSP)

(209) 0x4250a1 MOV	0x98(%RSP),%RAX

(209) 0x4250a9 MOV	0x10(%RAX),%RSI

(209) 0x4250ad MOV	(%RAX),%R10

(209) 0x4250b0 MOV	0xa0(%RSP),%RAX

(209) 0x4250b8 MOV	%RSI,0x18(%RSP)

(209) 0x4250bd IMUL	%R13,%R10

(209) 0x4250c1 MOV	0x10(%RAX),%R14

(209) 0x4250c5 MOV	(%RAX),%RAX

(209) 0x4250c8 MOV	%RAX,%RSI

(209) 0x4250cb MOV	%R10,0x40(%RSP)

(209) 0x4250d0 IMUL	%R13,%RSI

(209) 0x4250d4 LEA	(%RAX,%RSI,1),%R8

(209) 0x4250d8 MOV	0xa8(%RSP),%RAX

(209) 0x4250e0 MOV	%RSI,0x38(%RSP)

(209) 0x4250e5 MOV	%R8,0x10(%RSP)

(209) 0x4250ea MOV	0x10(%RAX),%R8

(209) 0x4250ee MOV	(%RAX),%RAX

(209) 0x4250f1 MOV	%R8,0x8(%RSP)

(209) 0x4250f6 MOV	%RAX,%R8

(209) 0x4250f9 IMUL	%R13,%R8

(209) 0x4250fd LEA	(%RAX,%R8,1),%RBP

(209) 0x425101 MOV	%R8,0x30(%RSP)

(209) 0x425106 MOV	%RBP,(%RSP)

(209) 0x42510a CMP	$0x1,%EDI

(209) 0x42510d JE	4251fd

(209) 0x425113 MOVSXD	0x28(%RSP),%RAX

(209) 0x425118 ADD	%RAX,%RDX

(209) 0x42511b ADD	%RAX,%RSI

(209) 0x42511e LEA	(%RCX,%RDX,8),%RCX

(209) 0x425122 LEA	(%R9,%RAX,1),%RDX

(209) 0x425126 LEA	(%R11,%RDX,8),%R12

(209) 0x42512a LEA	(%RBX,%RAX,1),%RDX

(209) 0x42512e MOV	0x20(%RSP),%RBX

(209) 0x425133 MOV	0x18(%RSP),%R11

(209) 0x425138 LEA	(%R15,%RDX,8),%RBP

(209) 0x42513c LEA	(%RBX,%RAX,1),%RDX

(209) 0x425140 LEA	(%R15,%RDX,8),%RBX

(209) 0x425144 LEA	(%R10,%RAX,1),%RDX

(209) 0x425148 LEA	(%R11,%RDX,8),%RDX

(209) 0x42514c LEA	(%R14,%RSI,8),%R11

(209) 0x425150 MOV	0x10(%RSP),%RSI

(209) 0x425155 ADD	%RAX,%RSI

(209) 0x425158 LEA	(%R14,%RSI,8),%R10

(209) 0x42515c LEA	(%R8,%RAX,1),%RSI

(209) 0x425160 MOV	0x8(%RSP),%R8

(209) 0x425165 LEA	(%R8,%RSI,8),%R9

(209) 0x425169 MOV	(%RSP),%RSI

(209) 0x42516d ADD	%RSI,%RAX

(209) 0x425170 MOV	%EDI,%ESI

(209) 0x425172 SHR	$0x1,%ESI

(209) 0x425174 LEA	(%R8,%RAX,8),%R8

(209) 0x425178 XOR	%EAX,%EAX

(209) 0x42517a SAL	$0x4,%RSI

(209) 0x42517e XCHG	%AX,%AX

  (210) 0x425180 MOVUPD	(%R12,%RAX,1),%XMM2

  (210) 0x425186 MOVUPD	(%RCX,%RAX,1),%XMM0

  (210) 0x42518b MOVUPD	(%RBP,%RAX,1),%XMM1

  (210) 0x425191 MOVUPD	(%RDX,%RAX,1),%XMM4

  (210) 0x425196 MULPD	%XMM2,%XMM0

  (210) 0x42519a MOVUPD	(%R11,%RAX,1),%XMM5

  (210) 0x4251a0 MOVUPD	(%RBX,%RAX,1),%XMM3

  (210) 0x4251a5 MOVUPD	(%R9,%RAX,1),%XMM7

  (210) 0x4251ab MOVUPD	(%R10,%RAX,1),%XMM6

  (210) 0x4251b1 ADDPD	%XMM7,%XMM2

  (210) 0x4251b5 ADDPD	%XMM0,%XMM1

  (210) 0x4251b9 MULPD	%XMM4,%XMM0

  (210) 0x4251bd SUBPD	%XMM3,%XMM1

  (210) 0x4251c1 MOVUPD	(%R8,%RAX,1),%XMM3

  (210) 0x4251c7 ADDPD	%XMM5,%XMM0

  (210) 0x4251cb SUBPD	%XMM3,%XMM2

  (210) 0x4251cf SUBPD	%XMM6,%XMM0

  (210) 0x4251d3 DIVPD	%XMM1,%XMM0

  (210) 0x4251d7 DIVPD	%XMM2,%XMM1

  (210) 0x4251db MOVUPS	%XMM1,(%RCX,%RAX,1)

  (210) 0x4251df MOVUPS	%XMM0,(%RDX,%RAX,1)

  (210) 0x4251e3 ADD	$0x10,%RAX

  (210) 0x4251e7 CMP	%RAX,%RSI

  (210) 0x4251ea JNE	425180

(209) 0x4251ec TEST	$0x1,%DIL

(209) 0x4251f0 JE	4252ac

(209) 0x4251f6 AND	$-0x2,%EDI

(209) 0x4251f9 ADD	%EDI,0x28(%RSP)

(209) 0x4251fd MOVSXD	0x28(%RSP),%RAX

(209) 0x425202 MOV	0x68(%RSP),%RDX

(209) 0x425207 MOV	0x60(%RSP),%RDI

(209) 0x42520c MOV	0x58(%RSP),%RCX

(209) 0x425211 ADD	%RAX,%RDX

(209) 0x425214 MOV	0x38(%RSP),%RSI

(209) 0x425219 MOV	(%RSP),%RBX

(209) 0x42521d LEA	(%RDI,%RDX,8),%RDX

(209) 0x425221 MOV	0x50(%RSP),%RDI

(209) 0x425226 ADD	%RAX,%RCX

(209) 0x425229 MOVSD	(%RDX),%XMM0

(209) 0x42522d ADD	%RAX,%RSI

(209) 0x425230 ADD	%RAX,%RBX

(209) 0x425233 MOVSD	(%RDI,%RCX,8),%XMM2

(209) 0x425238 MOV	0x48(%RSP),%RCX

(209) 0x42523d MOV	0x18(%RSP),%RDI

(209) 0x425242 MULSD	%XMM2,%XMM0

(209) 0x425246 ADD	%RAX,%RCX

(209) 0x425249 MOVSD	(%R15,%RCX,8),%XMM1

(209) 0x42524f MOV	0x20(%RSP),%RCX

(209) 0x425254 ADD	%RAX,%RCX

(209) 0x425257 ADDSD	%XMM0,%XMM1

(209) 0x42525b SUBSD	(%R15,%RCX,8),%XMM1

(209) 0x425261 MOV	0x40(%RSP),%RCX

(209) 0x425266 ADD	%RAX,%RCX

(209) 0x425269 LEA	(%RDI,%RCX,8),%RCX

(209) 0x42526d MOV	0x8(%RSP),%RDI

(209) 0x425272 MULSD	(%RCX),%XMM0

(209) 0x425276 ADDSD	(%R14,%RSI,8),%XMM0

(209) 0x42527c MOV	0x10(%RSP),%RSI

(209) 0x425281 ADD	%RAX,%RSI

(209) 0x425284 SUBSD	(%R14,%RSI,8),%XMM0

(209) 0x42528a MOV	0x30(%RSP),%RSI

(209) 0x42528f ADD	%RAX,%RSI

(209) 0x425292 ADDSD	(%RDI,%RSI,8),%XMM2

(209) 0x425297 SUBSD	(%RDI,%RBX,8),%XMM2

(209) 0x42529c DIVSD	%XMM1,%XMM0

(209) 0x4252a0 DIVSD	%XMM2,%XMM1

(209) 0x4252a4 MOVSD	%XMM1,(%RDX)

(209) 0x4252a8 MOVSD	%XMM0,(%RCX)

(209) 0x4252ac MOV	0x2c(%RSP),%ECX

(209) 0x4252b0 ADD	$0x1,%R13

(209) 0x4252b4 CMP	%R13D,0x70(%RSP)

(209) 0x4252b9 JLE	4252d8

(209) 0x4252bb MOV	0x7c(%RSP),%EDI

(209) 0x4252bf MOV	0x74(%RSP),%EAX

(209) 0x4252c3 MOV	0x78(%RSP),%ESI

(209) 0x4252c7 MOV	%EAX,0x28(%RSP)

(209) 0x4252cb SUB	%ECX,%EDI

(209) 0x4252cd JMP	425030

0x4252d2 NOPW	(%RAX,%RAX,1)

0x4252d8 ADD	$0xb8,%RSP

0x4252df POP	%RBX

0x4252e0 POP	%RBP

0x4252e1 POP	%R12

0x4252e3 POP	%R13

0x4252e5 POP	%R14

0x4252e7 POP	%R15

0x4252e9 RET

0x4252ea ADD	$0x1,%EDI

0x4252ed XOR	%EDX,%EDX

0x4252ef JMP	424fac

0x4252f4 NOPW	%CS:(%RAX,%RAX,1)

0x4252ff NOP

Coverage (%)	Name	Source Location	Module
►96.87+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►1.58+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	advec_cell_kernel(int, int, in[...]		exec
○	advec_cell_driver(global_varia[...]		exec
○	advection(global_variables&)		exec
○	hydro(global_variables&, paral[...]		exec
○	main		exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec
►1.54+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	advec_cell_kernel(int, int, in[...]		exec
○	advec_cell_driver(global_varia[...]		exec
○	advection(global_variables&)		exec
○	hydro(global_variables&, paral[...]		exec
○	main		exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines
Module	exec

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 7% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 12.00 to 0.75 cycles (16.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 12.00 to 10.13 cycles (1.19x speedup).

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 9.88 cycles (1.22x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
omp_get_thread_num@plt: 1 occurrences►

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 72 bytes. The binary function is storing 68 bytes.

General properties

nb instructions	82
nb uops	81
loop length	302
used x86 registers	12
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	11

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.13 cycles
front end	10.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.50	5.50	5.50	5.50	5.50	5.50	6.25	6.25	6.25	6.25	0.00	0.00	0.00	0.00	0.00	0.00
cycles	5.50	5.50	5.50	5.50	5.50	5.50	6.25	6.25	6.25	6.25	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	10.13
Dispatch	6.25
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

all	7%
load	6%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

2% of peak load performance is reached (6.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (5.67 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 424f30

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB $0xb8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0x38(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x34(%RBX),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
LEA 0x1(%RAX),%EBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV 0x3c(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x30(%RDI),%EDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD $0x2,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD $0x1,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %EAX,0x70(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %EDI,0x74(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %EAX,%EBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 4252d8 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7+0x3a8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
LEA 0x2(%RDX),%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
SUB %EBP,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMP %R14D,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 4252d8 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7+0x3a8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %R14D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SUB %EDI,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %R15D,0x78(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CALL 404660 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404550 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R13D,%EAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
DIV %R12D	2	0	0	0	2	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV %EAX,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JB 4252ea <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7+0x3ba>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
IMUL %EDI,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
ADD %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA (%RDI,%RCX,1),%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %EAX,0x7c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %EAX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JAE 4252d8 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7+0x3a8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x74(%RSP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
DIVL 0x78(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	10-17	6	scal (6.3%)
ADD %ESI,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
ADD %EBP,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %EDX,0x28(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
SUB %EDX,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV (%RBX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOVSXD %EAX,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %RDX,0x80(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x20(%RBX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDX,0x88(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x10(%RBX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDX,0x90(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x8(%RBX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDX,0x98(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x28(%RBX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x18(%RBX),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDX,0xa0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %RBX,0xa8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0xb8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
ADD $0x1,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 424fac <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7+0x7c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines
Module	exec

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 9.88 cycles (1.22x speedup).

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
omp_get_thread_num@plt: 1 occurrences►

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 72 bytes. The binary function is storing 68 bytes.

General properties

nb instructions	82
nb uops	81
loop length	302
used x86 registers	12
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	11

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.13 cycles
front end	10.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.50	5.50	5.50	5.50	5.50	5.50	6.25	6.25	6.25	6.25	0.00	0.00	0.00	0.00	0.00	0.00
cycles	5.50	5.50	5.50	5.50	5.50	5.50	6.25	6.25	6.25	6.25	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	10.13
Dispatch	6.25
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

all	7%
load	6%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

2% of peak load performance is reached (6.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (5.67 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 424f30

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB $0xb8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0x38(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x34(%RBX),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
LEA 0x1(%RAX),%EBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV 0x3c(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x30(%RDI),%EDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD $0x2,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD $0x1,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %EAX,0x70(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %EDI,0x74(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %EAX,%EBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 4252d8 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7+0x3a8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
LEA 0x2(%RDX),%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
SUB %EBP,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMP %R14D,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 4252d8 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7+0x3a8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %R14D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SUB %EDI,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %R15D,0x78(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CALL 404660 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404550 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R13D,%EAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
DIV %R12D	2	0	0	0	2	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV %EAX,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JB 4252ea <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7+0x3ba>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
IMUL %EDI,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
ADD %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA (%RDI,%RCX,1),%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %EAX,0x7c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %EAX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JAE 4252d8 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7+0x3a8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x74(%RSP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
DIVL 0x78(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	10-17	6	scal (6.3%)
ADD %ESI,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
ADD %EBP,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %EDX,0x28(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
SUB %EDX,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV (%RBX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOVSXD %EAX,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %RDX,0x80(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x20(%RBX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDX,0x88(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x10(%RBX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDX,0x90(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x8(%RBX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDX,0x98(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x28(%RBX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x18(%RBX),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDX,0xa0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %RBX,0xa8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0xb8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
ADD $0x1,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 424fac <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7+0x7c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	3.40	1.30
▼Loop 209 - - exec–	0.01	0.01
○Loop 210 - - exec	3.39	1.30

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Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code