OV - exec - Function advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ...	Module: exec	Source: :0-0	Coverage (incl. loops): 1.46% \| (excl. loops): 0.00%

  ***  This Panel is Intentionally Left Blank.  ***

It is due to a lack of debug symbols in the given object
(loop or function).

0x424960 PUSH	%R15

0x424962 PUSH	%R14

0x424964 PUSH	%R13

0x424966 PUSH	%R12

0x424968 PUSH	%RBP

0x424969 PUSH	%RBX

0x42496a MOV	%RDI,%RBX

0x42496d SUB	$0x88,%RSP

0x424974 MOV	0x30(%RDI),%EAX

0x424977 MOV	0x2c(%RBX),%ECX

0x42497a LEA	-0x1(%RAX),%EBP

0x42497d MOV	0x34(%RDI),%EAX

0x424980 MOV	0x28(%RDI),%EDI

0x424983 ADD	$0x4,%EAX

0x424986 SUB	$0x1,%EDI

0x424989 MOV	%EAX,0x48(%RSP)

0x42498d MOV	%EDI,0x4c(%RSP)

0x424991 CMP	%EAX,%EBP

0x424993 JGE	424c53

0x424999 MOV	%EAX,%R13D

0x42499c LEA	0x4(%RCX),%R14D

0x4249a0 SUB	%EBP,%R13D

0x4249a3 CMP	%R14D,%EDI

0x4249a6 JGE	424c53

0x4249ac MOV	%R14D,%R15D

0x4249af SUB	%EDI,%R15D

0x4249b2 MOV	%R15D,0x50(%RSP)

0x4249b7 CALL	404660 <omp_get_num_threads@plt>

0x4249bc MOV	%EAX,%R12D

0x4249bf CALL	404550 <omp_get_thread_num@plt>

0x4249c4 XOR	%EDX,%EDX

0x4249c6 MOV	%EAX,%ECX

0x4249c8 MOV	%R15D,%EAX

0x4249cb IMUL	%R13D,%EAX

0x4249cf DIV	%R12D

0x4249d2 MOV	%EAX,%EDI

0x4249d4 CMP	%EDX,%ECX

0x4249d6 JB	424c65

0x4249dc IMUL	%EDI,%ECX

0x4249df ADD	%EDX,%ECX

0x4249e1 LEA	(%RDI,%RCX,1),%EAX

0x4249e4 MOV	%EAX,0x54(%RSP)

0x4249e8 CMP	%EAX,%ECX

0x4249ea JAE	424c53

0x4249f0 XOR	%EDX,%EDX

0x4249f2 MOV	%ECX,%EAX

0x4249f4 MOV	0x4c(%RSP),%ESI

0x4249f8 DIVL	0x50(%RSP)

0x4249fc LEA	(%RDX,%RSI,1),%R15D

0x424a00 MOV	(%RBX),%RDX

0x424a03 MOV	%R14D,%ESI

0x424a06 ADD	%EBP,%EAX

0x424a08 SUB	%R15D,%ESI

0x424a0b MOV	%RDX,0x58(%RSP)

0x424a10 MOV	0x10(%RBX),%RDX

0x424a14 CMP	%ESI,%EDI

0x424a16 CMOVA	%ESI,%EDI

0x424a19 MOV	%RDX,0x60(%RSP)

0x424a1e MOV	0x8(%RBX),%RDX

0x424a22 MOV	%RDX,0x68(%RSP)

0x424a27 MOV	0x18(%RBX),%RDX

0x424a2b MOV	0x20(%RBX),%RBX

0x424a2f MOV	%RDX,0x70(%RSP)

0x424a34 MOVSXD	%EAX,%RDX

0x424a37 LEA	(%RCX,%RDI,1),%EAX

0x424a3a MOV	%RBX,0x78(%RSP)

0x424a3f MOV	%EAX,0x24(%RSP)

0x424a43 CMP	%EAX,%ECX

0x424a45 JAE	424c3f

0x424a4b NOPL	(%RAX,%RAX,1)

  (203) 0x424a50 MOV	0x58(%RSP),%RAX

  (203) 0x424a55 LEA	0x1(%RDX),%RBX

  (203) 0x424a59 MOV	%RBX,%RBP

  (203) 0x424a5c MOV	%RBX,0x18(%RSP)

  (203) 0x424a61 MOV	0x10(%RAX),%R9

  (203) 0x424a65 MOV	(%RAX),%RCX

  (203) 0x424a68 MOV	0x60(%RSP),%RAX

  (203) 0x424a6d IMUL	%RDX,%RCX

  (203) 0x424a71 MOV	%R9,0x38(%RSP)

  (203) 0x424a76 MOV	0x10(%RAX),%R14

  (203) 0x424a7a MOV	(%RAX),%RAX

  (203) 0x424a7d IMUL	%RAX,%RBP

  (203) 0x424a81 MOV	%RCX,0x40(%RSP)

  (203) 0x424a86 MOV	%RBP,%RSI

  (203) 0x424a89 SUB	%RAX,%RSI

  (203) 0x424a8c MOV	0x68(%RSP),%RAX

  (203) 0x424a91 MOV	%RSI,0x30(%RSP)

  (203) 0x424a96 MOV	(%RAX),%R12

  (203) 0x424a99 MOV	0x10(%RAX),%R13

  (203) 0x424a9d MOV	0x70(%RSP),%RAX

  (203) 0x424aa2 IMUL	%RDX,%R12

  (203) 0x424aa6 MOV	0x10(%RAX),%RBX

  (203) 0x424aaa MOV	(%RAX),%R8

  (203) 0x424aad MOV	0x78(%RSP),%RAX

  (203) 0x424ab2 IMUL	%RDX,%R8

  (203) 0x424ab6 MOV	%RBX,0x10(%RSP)

  (203) 0x424abb IMUL	(%RAX),%RDX

  (203) 0x424abf MOV	0x10(%RAX),%R10

  (203) 0x424ac3 MOV	%R8,0x28(%RSP)

  (203) 0x424ac8 MOV	%R10,0x8(%RSP)

  (203) 0x424acd MOV	%RDX,(%RSP)

  (203) 0x424ad1 CMP	$0x1,%EDI

  (203) 0x424ad4 JE	424b90

  (203) 0x424ada MOVSXD	%R15D,%RAX

  (203) 0x424add LEA	(%RCX,%RAX,1),%RDX

  (203) 0x424ae1 LEA	(%R9,%RDX,8),%RBX

  (203) 0x424ae5 LEA	(%RBP,%RAX,1),%RDX

  (203) 0x424aea MOV	0x10(%RSP),%R9

  (203) 0x424aef LEA	(%R14,%RDX,8),%RCX

  (203) 0x424af3 LEA	(%RSI,%RAX,1),%RDX

  (203) 0x424af7 LEA	0x1(%R12,%RAX,1),%RSI

  (203) 0x424afc LEA	(%R14,%RDX,8),%RDX

  (203) 0x424b00 SAL	$0x3,%RSI

  (203) 0x424b04 LEA	(%R13,%RSI,1),%R11

  (203) 0x424b09 LEA	-0x8(%R13,%RSI,1),%R10

  (203) 0x424b0e LEA	(%R8,%RAX,1),%RSI

  (203) 0x424b12 LEA	(%R9,%RSI,8),%R9

  (203) 0x424b16 MOV	(%RSP),%RSI

  (203) 0x424b1a ADD	%RSI,%RAX

  (203) 0x424b1d MOV	0x8(%RSP),%RSI

  (203) 0x424b22 LEA	(%RSI,%RAX,8),%R8

  (203) 0x424b26 MOV	%EDI,%ESI

  (203) 0x424b28 XOR	%EAX,%EAX

  (203) 0x424b2a SHR	$0x1,%ESI

  (203) 0x424b2c SAL	$0x4,%RSI

    (204) 0x424b30 MOVUPD	(%RCX,%RAX,1),%XMM0

    (204) 0x424b35 MOVUPD	(%RDX,%RAX,1),%XMM2

    (204) 0x424b3a MOVUPD	(%R11,%RAX,1),%XMM3

    (204) 0x424b40 MOVUPD	(%R10,%RAX,1),%XMM4

    (204) 0x424b46 SUBPD	%XMM2,%XMM0

    (204) 0x424b4a MOVUPD	(%RBX,%RAX,1),%XMM5

    (204) 0x424b4f ADDPD	%XMM3,%XMM0

    (204) 0x424b53 SUBPD	%XMM4,%XMM0

    (204) 0x424b57 ADDPD	%XMM5,%XMM0

    (204) 0x424b5b MOVUPS	%XMM0,(%R9,%RAX,1)

    (204) 0x424b60 MOVUPD	(%RCX,%RAX,1),%XMM1

    (204) 0x424b65 MOVUPD	(%RDX,%RAX,1),%XMM6

    (204) 0x424b6a SUBPD	%XMM6,%XMM1

    (204) 0x424b6e SUBPD	%XMM1,%XMM0

    (204) 0x424b72 MOVUPS	%XMM0,(%R8,%RAX,1)

    (204) 0x424b77 ADD	$0x10,%RAX

    (204) 0x424b7b CMP	%RAX,%RSI

    (204) 0x424b7e JNE	424b30

  (203) 0x424b80 TEST	$0x1,%DIL

  (203) 0x424b84 JE	424c0d

  (203) 0x424b8a AND	$-0x2,%EDI

  (203) 0x424b8d ADD	%EDI,%R15D

  (203) 0x424b90 MOV	0x30(%RSP),%RDX

  (203) 0x424b95 MOVSXD	%R15D,%RAX

  (203) 0x424b98 MOV	0x40(%RSP),%RSI

  (203) 0x424b9d ADD	$0x1,%R15D

  (203) 0x424ba1 MOV	0x38(%RSP),%RBX

  (203) 0x424ba6 ADD	%RAX,%RBP

  (203) 0x424ba9 MOVSXD	%R15D,%R15

  (203) 0x424bac MOV	(%RSP),%RDI

  (203) 0x424bb0 ADD	%RAX,%RDX

  (203) 0x424bb3 ADD	%RAX,%RSI

  (203) 0x424bb6 LEA	(%R14,%RBP,8),%RCX

  (203) 0x424bba ADD	%R12,%R15

  (203) 0x424bbd LEA	(%R14,%RDX,8),%RDX

  (203) 0x424bc1 ADD	%RAX,%R12

  (203) 0x424bc4 MOVSD	(%RCX),%XMM0

  (203) 0x424bc8 ADD	%RAX,%RDI

  (203) 0x424bcb SUBSD	(%RDX),%XMM0

  (203) 0x424bcf ADDSD	(%R13,%R15,8),%XMM0

  (203) 0x424bd6 SUBSD	(%R13,%R12,8),%XMM0

  (203) 0x424bdd ADDSD	(%RBX,%RSI,8),%XMM0

  (203) 0x424be2 MOV	0x28(%RSP),%RSI

  (203) 0x424be7 MOV	0x10(%RSP),%RBX

  (203) 0x424bec ADD	%RAX,%RSI

  (203) 0x424bef MOV	%RDI,%RAX

  (203) 0x424bf2 MOV	0x8(%RSP),%RDI

  (203) 0x424bf7 MOVSD	%XMM0,(%RBX,%RSI,8)

  (203) 0x424bfc MOVSD	(%RCX),%XMM1

  (203) 0x424c00 SUBSD	(%RDX),%XMM1

  (203) 0x424c04 SUBSD	%XMM1,%XMM0

  (203) 0x424c08 MOVSD	%XMM0,(%RDI,%RAX,8)

  (203) 0x424c0d MOV	0x24(%RSP),%ECX

  (203) 0x424c11 MOV	0x18(%RSP),%RDX

  (203) 0x424c16 CMP	%EDX,0x48(%RSP)

  (203) 0x424c1a JLE	424c53

  (203) 0x424c1c MOV	0x54(%RSP),%EDI

  (203) 0x424c20 MOV	0x50(%RSP),%ESI

  (203) 0x424c24 MOV	0x4c(%RSP),%R15D

  (203) 0x424c29 SUB	%ECX,%EDI

  (203) 0x424c2b CMP	%ESI,%EDI

  (203) 0x424c2d CMOVA	%ESI,%EDI

  (203) 0x424c30 LEA	(%RCX,%RDI,1),%EAX

  (203) 0x424c33 MOV	%EAX,0x24(%RSP)

  (203) 0x424c37 CMP	%EAX,%ECX

  (203) 0x424c39 JB	424a50

(205) 0x424c3f LEA	0x1(%RDX),%RAX

(205) 0x424c43 MOV	%RAX,0x18(%RSP)

(205) 0x424c48 MOV	0x18(%RSP),%RDX

(205) 0x424c4d CMP	%EDX,0x48(%RSP)

(205) 0x424c51 JG	424c1c

0x424c53 ADD	$0x88,%RSP

0x424c5a POP	%RBX

0x424c5b POP	%RBP

0x424c5c POP	%R12

0x424c5e POP	%R13

0x424c60 POP	%R14

0x424c62 POP	%R15

0x424c64 RET

0x424c65 ADD	$0x1,%EDI

0x424c68 XOR	%EDX,%EDX

0x424c6a JMP	4249dc

0x424c6f NOP

Coverage (%)	Name	Source Location	Module
►96.90+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►3.08+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	advec_cell_kernel(int, int, in[...]		exec
○	advec_cell_driver(global_varia[...]		exec
○	advection(global_variables&)		exec
○	hydro(global_variables&, paral[...]		exec
○	main		exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines
Module	exec

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 7% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 12.00 to 0.75 cycles (16.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 12.00 to 10.63 cycles (1.13x speedup).

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 10.38 cycles (1.16x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
omp_get_thread_num@plt: 1 occurrences►

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVA: 1 occurrences►
DIV: 2 occurrences►

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 64 bytes. The binary function is storing 60 bytes.

General properties

nb instructions	82
nb uops	85
loop length	269
used x86 registers	12
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	10

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.63 cycles
front end	10.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	6.50	6.50	6.50	6.50	6.50	6.50	5.75	5.75	5.75	5.75	0.00	0.00	0.00	0.00	0.00	0.00
cycles	6.50	6.50	6.50	6.50	6.50	6.50	5.75	5.75	5.75	5.75	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	10.63
Dispatch	6.50
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

all	7%
load	6%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

2% of peak load performance is reached (5.33 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (5.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 424960

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB $0x88,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0x30(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x2c(%RBX),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
LEA -0x1(%RAX),%EBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV 0x34(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x28(%RDI),%EDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD $0x4,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
SUB $0x1,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %EAX,0x48(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %EDI,0x4c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %EAX,%EBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 424c53 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4+0x2f3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
LEA 0x4(%RCX),%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
SUB %EBP,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMP %R14D,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 424c53 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4+0x2f3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %R14D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SUB %EDI,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %R15D,0x50(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CALL 404660 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404550 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R13D,%EAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
DIV %R12D	2	0	0	0	2	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV %EAX,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JB 424c65 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4+0x305>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
IMUL %EDI,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
ADD %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA (%RDI,%RCX,1),%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %EAX,0x54(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %EAX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JAE 424c53 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4+0x2f3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x4c(%RSP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
DIVL 0x50(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	10-17	6	scal (6.3%)
LEA (%RDX,%RSI,1),%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV (%RBX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %EBP,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
SUB %R15D,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %RDX,0x58(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x10(%RBX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP %ESI,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMOVA %ESI,%EDI	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	1	0.33	N/A
MOV %RDX,0x60(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x8(%RBX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDX,0x68(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x18(%RBX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x20(%RBX),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDX,0x70(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOVSXD %EAX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA (%RCX,%RDI,1),%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %RBX,0x78(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %EAX,0x24(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %EAX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JAE 424c3f <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4+0x2df>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0x88,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
ADD $0x1,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 4249dc <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4+0x7c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines
Module	exec

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 10.38 cycles (1.16x speedup).

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
omp_get_thread_num@plt: 1 occurrences►

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVA: 1 occurrences►
DIV: 2 occurrences►

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 64 bytes. The binary function is storing 60 bytes.

General properties

nb instructions	82
nb uops	85
loop length	269
used x86 registers	12
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	10

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.63 cycles
front end	10.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	6.50	6.50	6.50	6.50	6.50	6.50	5.75	5.75	5.75	5.75	0.00	0.00	0.00	0.00	0.00	0.00
cycles	6.50	6.50	6.50	6.50	6.50	6.50	5.75	5.75	5.75	5.75	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	10.63
Dispatch	6.50
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

all	7%
load	6%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

2% of peak load performance is reached (5.33 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (5.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 424960

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB $0x88,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0x30(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x2c(%RBX),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
LEA -0x1(%RAX),%EBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV 0x34(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x28(%RDI),%EDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD $0x4,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
SUB $0x1,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %EAX,0x48(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %EDI,0x4c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %EAX,%EBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 424c53 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4+0x2f3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
LEA 0x4(%RCX),%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
SUB %EBP,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMP %R14D,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 424c53 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4+0x2f3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %R14D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SUB %EDI,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %R15D,0x50(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CALL 404660 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404550 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R13D,%EAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
DIV %R12D	2	0	0	0	2	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV %EAX,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JB 424c65 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4+0x305>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
IMUL %EDI,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
ADD %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA (%RDI,%RCX,1),%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %EAX,0x54(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %EAX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JAE 424c53 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4+0x2f3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x4c(%RSP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
DIVL 0x50(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	10-17	6	scal (6.3%)
LEA (%RDX,%RSI,1),%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV (%RBX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %EBP,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
SUB %R15D,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %RDX,0x58(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x10(%RBX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP %ESI,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMOVA %ESI,%EDI	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	1	0.33	N/A
MOV %RDX,0x60(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x8(%RBX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDX,0x68(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x18(%RBX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x20(%RBX),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDX,0x70(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOVSXD %EAX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA (%RCX,%RDI,1),%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %RBX,0x78(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %EAX,0x24(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %EAX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JAE 424c3f <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4+0x2df>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0x88,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
ADD $0x1,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 4249dc <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4+0x7c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	1.46	0.56
▼Loop 205 - - exec–	0.00	0.00
▼Loop 203 - - exec–	0.00	0.00
○Loop 204 - - exec	1.46	0.56

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Matching between your function (in the source code) and the binary function

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Vector efficiency ratios

Cycles and memory resources usage

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