OV - exec - Function advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ...	Module: exec	Source: :0-0	Coverage (incl. loops): 3.41% \| (excl. loops): 0.00%

  ***  This Panel is Intentionally Left Blank.  ***

It is due to a lack of debug symbols in the given object
(loop or function).

0x4245d0 PUSH	%R15

0x4245d2 PUSH	%R14

0x4245d4 PUSH	%R13

0x4245d6 PUSH	%R12

0x4245d8 PUSH	%RBP

0x4245d9 PUSH	%RBX

0x4245da MOV	%RDI,%RBX

0x4245dd SUB	$0xa8,%RSP

0x4245e4 MOV	0x38(%RDI),%EAX

0x4245e7 MOV	0x30(%RDI),%EDX

0x4245ea LEA	0x1(%RAX),%EBP

0x4245ed MOV	0x3c(%RDI),%EAX

0x4245f0 LEA	0x1(%RDX),%EDI

0x4245f3 MOV	0x34(%RBX),%EDX

0x4245f6 MOV	%EDI,0x64(%RSP)

0x4245fa ADD	$0x2,%EAX

0x4245fd MOV	%EAX,0x60(%RSP)

0x424601 CMP	%EAX,%EBP

0x424603 JGE	424940

0x424609 MOV	%EAX,%R13D

0x42460c LEA	0x2(%RDX),%R14D

0x424610 SUB	%EBP,%R13D

0x424613 CMP	%R14D,%EDI

0x424616 JGE	424940

0x42461c MOV	%R14D,%R15D

0x42461f SUB	%EDI,%R15D

0x424622 MOV	%R15D,0x68(%RSP)

0x424627 CALL	404660 <omp_get_num_threads@plt>

0x42462c MOV	%EAX,%R12D

0x42462f CALL	404550 <omp_get_thread_num@plt>

0x424634 XOR	%EDX,%EDX

0x424636 MOV	%EAX,%ECX

0x424638 MOV	%R15D,%EAX

0x42463b IMUL	%R13D,%EAX

0x42463f DIV	%R12D

0x424642 MOV	%EAX,%EDI

0x424644 CMP	%EDX,%ECX

0x424646 JB	424952

0x42464c IMUL	%EDI,%ECX

0x42464f ADD	%EDX,%ECX

0x424651 LEA	(%RDI,%RCX,1),%EAX

0x424654 MOV	%EAX,0x6c(%RSP)

0x424658 CMP	%EAX,%ECX

0x42465a JAE	424940

0x424660 MOV	%ECX,%EAX

0x424662 XOR	%EDX,%EDX

0x424664 MOV	0x64(%RSP),%ESI

0x424668 DIVL	0x68(%RSP)

0x42466c ADD	%ESI,%EDX

0x42466e MOV	%R14D,%ESI

0x424671 ADD	%EBP,%EAX

0x424673 MOV	%EDX,0x20(%RSP)

0x424677 SUB	%EDX,%ESI

0x424679 MOV	(%RBX),%RDX

0x42467c MOVSXD	%EAX,%R13

0x42467f MOV	%RDX,0x70(%RSP)

0x424684 MOV	0x20(%RBX),%RDX

0x424688 MOV	%RDX,0x78(%RSP)

0x42468d MOV	0x10(%RBX),%RDX

0x424691 MOV	%RDX,0x80(%RSP)

0x424699 MOV	0x8(%RBX),%RDX

0x42469d MOV	%RDX,0x88(%RSP)

0x4246a5 MOV	0x28(%RBX),%RDX

0x4246a9 MOV	0x18(%RBX),%RBX

0x4246ad MOV	%RDX,0x90(%RSP)

0x4246b5 MOV	%RBX,0x98(%RSP)

0x4246bd NOPL	(%RAX)

(201) 0x4246c0 CMP	%ESI,%EDI

(201) 0x4246c2 CMOVA	%ESI,%EDI

(201) 0x4246c5 LEA	(%RCX,%RDI,1),%EAX

(201) 0x4246c8 MOV	%EAX,0x24(%RSP)

(201) 0x4246cc CMP	%EAX,%ECX

(201) 0x4246ce JAE	42491d

(201) 0x4246d4 MOV	0x70(%RSP),%RAX

(201) 0x4246d9 MOV	0x98(%RSP),%RCX

(201) 0x4246e1 MOV	0x10(%RAX),%R11

(201) 0x4246e5 MOV	(%RAX),%RBX

(201) 0x4246e8 MOV	0x78(%RSP),%RAX

(201) 0x4246ed IMUL	%R13,%RBX

(201) 0x4246f1 MOV	%R11,0x50(%RSP)

(201) 0x4246f6 MOV	0x10(%RAX),%RBP

(201) 0x4246fa MOV	(%RAX),%RSI

(201) 0x4246fd MOV	0x80(%RSP),%RAX

(201) 0x424705 IMUL	%R13,%RSI

(201) 0x424709 MOV	%RBX,0x58(%RSP)

(201) 0x42470e MOV	(%RAX),%R8

(201) 0x424711 MOV	0x10(%RAX),%R15

(201) 0x424715 MOV	%RBP,0x40(%RSP)

(201) 0x42471a MOV	0x88(%RSP),%RAX

(201) 0x424722 IMUL	%R13,%R8

(201) 0x424726 MOV	%RSI,0x48(%RSP)

(201) 0x42472b MOV	0x10(%RAX),%RDX

(201) 0x42472f MOV	(%RAX),%R9

(201) 0x424732 MOV	0x90(%RSP),%RAX

(201) 0x42473a IMUL	%R13,%R9

(201) 0x42473e MOV	%R8,0x38(%RSP)

(201) 0x424743 MOV	(%RAX),%R10

(201) 0x424746 MOV	0x10(%RAX),%R14

(201) 0x42474a MOV	%RDX,0x18(%RSP)

(201) 0x42474f MOV	0x10(%RCX),%RAX

(201) 0x424753 IMUL	%R13,%R10

(201) 0x424757 MOV	%R9,0x30(%RSP)

(201) 0x42475c MOV	%RAX,0x8(%RSP)

(201) 0x424761 MOV	(%RCX),%RAX

(201) 0x424764 IMUL	%R13,%RAX

(201) 0x424768 MOV	%R10,0x28(%RSP)

(201) 0x42476d MOV	%RAX,0x10(%RSP)

(201) 0x424772 CMP	$0x1,%EDI

(201) 0x424775 JE	42486d

(201) 0x42477b MOVSXD	0x20(%RSP),%RAX

(201) 0x424780 LEA	(%RBX,%RAX,1),%RDX

(201) 0x424784 LEA	(%R11,%RDX,8),%RCX

(201) 0x424788 LEA	(%RSI,%RAX,1),%RDX

(201) 0x42478c MOV	0x18(%RSP),%R11

(201) 0x424791 LEA	(%RBP,%RDX,8),%R12

(201) 0x424796 LEA	(%R8,%RAX,1),%RDX

(201) 0x42479a SAL	$0x3,%RDX

(201) 0x42479e LEA	(%R10,%RAX,1),%RSI

(201) 0x4247a2 SAL	$0x3,%RSI

(201) 0x4247a6 LEA	(%R15,%RDX,1),%RBP

(201) 0x4247aa LEA	0x8(%R15,%RDX,1),%RBX

(201) 0x4247af LEA	(%R9,%RAX,1),%RDX

(201) 0x4247b3 LEA	0x8(%R14,%RSI,1),%R10

(201) 0x4247b8 LEA	(%R11,%RDX,8),%RDX

(201) 0x4247bc LEA	(%R14,%RSI,1),%R11

(201) 0x4247c0 MOV	0x10(%RSP),%RSI

(201) 0x4247c5 ADD	%RSI,%RAX

(201) 0x4247c8 MOV	0x8(%RSP),%RSI

(201) 0x4247cd SAL	$0x3,%RAX

(201) 0x4247d1 LEA	(%RSI,%RAX,1),%R9

(201) 0x4247d5 LEA	0x8(%RSI,%RAX,1),%R8

(201) 0x4247da MOV	%EDI,%ESI

(201) 0x4247dc XOR	%EAX,%EAX

(201) 0x4247de SHR	$0x1,%ESI

(201) 0x4247e0 SAL	$0x4,%RSI

(201) 0x4247e4 NOPW	%CS:(%RAX,%RAX,1)

(201) 0x4247ef NOP

  (202) 0x4247f0 MOVUPD	(%R12,%RAX,1),%XMM2

  (202) 0x4247f6 MOVUPD	(%RCX,%RAX,1),%XMM0

  (202) 0x4247fb MOVUPD	(%RBP,%RAX,1),%XMM1

  (202) 0x424801 MOVUPD	(%RDX,%RAX,1),%XMM4

  (202) 0x424806 MULPD	%XMM2,%XMM0

  (202) 0x42480a MOVUPD	(%R11,%RAX,1),%XMM5

  (202) 0x424810 MOVUPD	(%RBX,%RAX,1),%XMM3

  (202) 0x424815 MOVUPD	(%R9,%RAX,1),%XMM7

  (202) 0x42481b MOVUPD	(%R10,%RAX,1),%XMM6

  (202) 0x424821 ADDPD	%XMM7,%XMM2

  (202) 0x424825 ADDPD	%XMM0,%XMM1

  (202) 0x424829 MULPD	%XMM4,%XMM0

  (202) 0x42482d SUBPD	%XMM3,%XMM1

  (202) 0x424831 MOVUPD	(%R8,%RAX,1),%XMM3

  (202) 0x424837 ADDPD	%XMM5,%XMM0

  (202) 0x42483b SUBPD	%XMM3,%XMM2

  (202) 0x42483f SUBPD	%XMM6,%XMM0

  (202) 0x424843 DIVPD	%XMM1,%XMM0

  (202) 0x424847 DIVPD	%XMM2,%XMM1

  (202) 0x42484b MOVUPS	%XMM1,(%RCX,%RAX,1)

  (202) 0x42484f MOVUPS	%XMM0,(%RDX,%RAX,1)

  (202) 0x424853 ADD	$0x10,%RAX

  (202) 0x424857 CMP	%RSI,%RAX

  (202) 0x42485a JNE	4247f0

(201) 0x42485c TEST	$0x1,%DIL

(201) 0x424860 JE	424919

(201) 0x424866 AND	$-0x2,%EDI

(201) 0x424869 ADD	%EDI,0x20(%RSP)

(201) 0x42486d MOVSXD	0x20(%RSP),%RAX

(201) 0x424872 MOV	0x58(%RSP),%RDX

(201) 0x424877 MOV	0x50(%RSP),%RDI

(201) 0x42487c MOV	0x48(%RSP),%RCX

(201) 0x424881 ADD	%RAX,%RDX

(201) 0x424884 MOV	0x28(%RSP),%RBX

(201) 0x424889 LEA	(%RDI,%RDX,8),%RDX

(201) 0x42488d MOV	0x40(%RSP),%RDI

(201) 0x424892 ADD	%RAX,%RCX

(201) 0x424895 MOVSD	(%RDX),%XMM0

(201) 0x424899 MOVSD	(%RDI,%RCX,8),%XMM2

(201) 0x42489e MOV	0x38(%RSP),%RDI

(201) 0x4248a3 LEA	0x1(%RAX),%ECX

(201) 0x4248a6 MOVSXD	%ECX,%RCX

(201) 0x4248a9 MULSD	%XMM2,%XMM0

(201) 0x4248ad LEA	(%RDI,%RAX,1),%RSI

(201) 0x4248b1 MOVSD	(%R15,%RSI,8),%XMM1

(201) 0x4248b7 LEA	(%RDI,%RCX,1),%RSI

(201) 0x4248bb MOV	0x18(%RSP),%RDI

(201) 0x4248c0 ADDSD	%XMM0,%XMM1

(201) 0x4248c4 SUBSD	(%R15,%RSI,8),%XMM1

(201) 0x4248ca MOV	0x30(%RSP),%RSI

(201) 0x4248cf ADD	%RAX,%RSI

(201) 0x4248d2 LEA	(%RDI,%RSI,8),%RSI

(201) 0x4248d6 LEA	(%RBX,%RAX,1),%RDI

(201) 0x4248da MULSD	(%RSI),%XMM0

(201) 0x4248de ADDSD	(%R14,%RDI,8),%XMM0

(201) 0x4248e4 LEA	(%RBX,%RCX,1),%RDI

(201) 0x4248e8 MOV	0x8(%RSP),%RBX

(201) 0x4248ed SUBSD	(%R14,%RDI,8),%XMM0

(201) 0x4248f3 MOV	0x10(%RSP),%RDI

(201) 0x4248f8 ADD	%RDI,%RAX

(201) 0x4248fb ADDSD	(%RBX,%RAX,8),%XMM2

(201) 0x424900 LEA	(%RDI,%RCX,1),%RAX

(201) 0x424904 DIVSD	%XMM1,%XMM0

(201) 0x424908 SUBSD	(%RBX,%RAX,8),%XMM2

(201) 0x42490d DIVSD	%XMM2,%XMM1

(201) 0x424911 MOVSD	%XMM1,(%RDX)

(201) 0x424915 MOVSD	%XMM0,(%RSI)

(201) 0x424919 MOV	0x24(%RSP),%ECX

(201) 0x42491d ADD	$0x1,%R13

(201) 0x424921 CMP	%R13D,0x60(%RSP)

(201) 0x424926 JLE	424940

(201) 0x424928 MOV	0x6c(%RSP),%EDI

(201) 0x42492c MOV	0x64(%RSP),%EAX

(201) 0x424930 MOV	0x68(%RSP),%ESI

(201) 0x424934 MOV	%EAX,0x20(%RSP)

(201) 0x424938 SUB	%ECX,%EDI

(201) 0x42493a JMP	4246c0

0x42493f NOP

0x424940 ADD	$0xa8,%RSP

0x424947 POP	%RBX

0x424948 POP	%RBP

0x424949 POP	%R12

0x42494b POP	%R13

0x42494d POP	%R14

0x42494f POP	%R15

0x424951 RET

0x424952 ADD	$0x1,%EDI

0x424955 XOR	%EDX,%EDX

0x424957 JMP	42464c

0x42495c NOPL	(%RAX)

Coverage (%)	Name	Source Location	Module
►96.85+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►1.57+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	advec_cell_kernel(int, int, in[...]		exec
○	advec_cell_driver(global_varia[...]		exec
○	advection(global_variables&)		exec
○	hydro(global_variables&, paral[...]		exec
○	main		exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec
►1.54+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	advec_cell_kernel(int, int, in[...]		exec
○	advec_cell_driver(global_varia[...]		exec
○	advection(global_variables&)		exec
○	hydro(global_variables&, paral[...]		exec
○	main		exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines
Module	exec

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 7% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 12.00 to 0.75 cycles (16.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 12.00 to 10.13 cycles (1.19x speedup).

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 9.88 cycles (1.22x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
omp_get_thread_num@plt: 1 occurrences►

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 72 bytes. The binary function is storing 68 bytes.

General properties

nb instructions	80
nb uops	81
loop length	273
used x86 registers	12
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	11

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.13 cycles
front end	10.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.50	5.50	5.50	5.50	5.50	5.50	6.25	6.25	6.25	6.25	0.00	0.00	0.00	0.00	0.00	0.00
cycles	5.50	5.50	5.50	5.50	5.50	5.50	6.25	6.25	6.25	6.25	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	10.13
Dispatch	6.25
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

all	7%
load	6%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

2% of peak load performance is reached (6.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (5.67 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4245d0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB $0xa8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0x38(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x30(%RDI),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
LEA 0x1(%RAX),%EBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV 0x3c(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
LEA 0x1(%RDX),%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV 0x34(%RBX),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %EDI,0x64(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
ADD $0x2,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %EAX,0x60(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %EAX,%EBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 424940 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x370>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
LEA 0x2(%RDX),%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
SUB %EBP,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMP %R14D,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 424940 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x370>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %R14D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SUB %EDI,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %R15D,0x68(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CALL 404660 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404550 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R13D,%EAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
DIV %R12D	2	0	0	0	2	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV %EAX,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JB 424952 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x382>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
IMUL %EDI,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
ADD %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA (%RDI,%RCX,1),%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %EAX,0x6c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %EAX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JAE 424940 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x370>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x64(%RSP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
DIVL 0x68(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	10-17	6	scal (6.3%)
ADD %ESI,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
ADD %EBP,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %EDX,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
SUB %EDX,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV (%RBX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOVSXD %EAX,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %RDX,0x70(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x20(%RBX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDX,0x78(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x10(%RBX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDX,0x80(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x8(%RBX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDX,0x88(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x28(%RBX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x18(%RBX),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDX,0x90(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %RBX,0x98(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0xa8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
ADD $0x1,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 42464c <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x7c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines
Module	exec

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 9.88 cycles (1.22x speedup).

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
omp_get_thread_num@plt: 1 occurrences►

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 72 bytes. The binary function is storing 68 bytes.

General properties

nb instructions	80
nb uops	81
loop length	273
used x86 registers	12
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	11

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.13 cycles
front end	10.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.50	5.50	5.50	5.50	5.50	5.50	6.25	6.25	6.25	6.25	0.00	0.00	0.00	0.00	0.00	0.00
cycles	5.50	5.50	5.50	5.50	5.50	5.50	6.25	6.25	6.25	6.25	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	10.13
Dispatch	6.25
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

all	7%
load	6%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

2% of peak load performance is reached (6.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (5.67 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4245d0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB $0xa8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0x38(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x30(%RDI),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
LEA 0x1(%RAX),%EBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV 0x3c(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
LEA 0x1(%RDX),%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV 0x34(%RBX),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %EDI,0x64(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
ADD $0x2,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %EAX,0x60(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %EAX,%EBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 424940 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x370>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
LEA 0x2(%RDX),%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
SUB %EBP,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMP %R14D,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 424940 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x370>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %R14D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SUB %EDI,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %R15D,0x68(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CALL 404660 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404550 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R13D,%EAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
DIV %R12D	2	0	0	0	2	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV %EAX,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JB 424952 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x382>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
IMUL %EDI,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
ADD %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA (%RDI,%RCX,1),%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %EAX,0x6c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %EAX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JAE 424940 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x370>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x64(%RSP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
DIVL 0x68(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	10-17	6	scal (6.3%)
ADD %ESI,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
ADD %EBP,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %EDX,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
SUB %EDX,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV (%RBX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOVSXD %EAX,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %RDX,0x70(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x20(%RBX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDX,0x78(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x10(%RBX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDX,0x80(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x8(%RBX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDX,0x88(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x28(%RBX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x18(%RBX),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDX,0x90(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %RBX,0x98(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0xa8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
ADD $0x1,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 42464c <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x7c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	3.41	1.31
▼Loop 201 - - exec–	0.00	0.01
○Loop 202 - - exec	3.41	1.30

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Matching between your function (in the source code) and the binary function

General properties

Front-end

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Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

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ASM code