OV - exec - Function advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ...	Module: exec	Source: :0-0	Coverage (incl. loops): 1.50% \| (excl. loops): 0.00%

  ***  This Panel is Intentionally Left Blank.  ***

It is due to a lack of debug symbols in the given object
(loop or function).

0x424040 PUSH	%R15

0x424042 PUSH	%R14

0x424044 PUSH	%R13

0x424046 PUSH	%R12

0x424048 PUSH	%RBP

0x424049 PUSH	%RBX

0x42404a MOV	%RDI,%RBX

0x42404d SUB	$0x88,%RSP

0x424054 MOV	0x30(%RDI),%EAX

0x424057 MOV	0x2c(%RBX),%ECX

0x42405a LEA	-0x1(%RAX),%EBP

0x42405d MOV	0x34(%RDI),%EAX

0x424060 MOV	0x28(%RDI),%EDI

0x424063 ADD	$0x4,%EAX

0x424066 SUB	$0x1,%EDI

0x424069 MOV	%EAX,0x48(%RSP)

0x42406d MOV	%EDI,0x4c(%RSP)

0x424071 CMP	%EAX,%EBP

0x424073 JGE	424343

0x424079 MOV	%EAX,%R13D

0x42407c LEA	0x4(%RCX),%R14D

0x424080 SUB	%EBP,%R13D

0x424083 CMP	%R14D,%EDI

0x424086 JGE	424343

0x42408c MOV	%R14D,%R15D

0x42408f SUB	%EDI,%R15D

0x424092 MOV	%R15D,0x50(%RSP)

0x424097 CALL	404660 <omp_get_num_threads@plt>

0x42409c MOV	%EAX,%R12D

0x42409f CALL	404550 <omp_get_thread_num@plt>

0x4240a4 XOR	%EDX,%EDX

0x4240a6 MOV	%EAX,%ECX

0x4240a8 MOV	%R15D,%EAX

0x4240ab IMUL	%R13D,%EAX

0x4240af DIV	%R12D

0x4240b2 MOV	%EAX,%EDI

0x4240b4 CMP	%EDX,%ECX

0x4240b6 JB	424355

0x4240bc IMUL	%EDI,%ECX

0x4240bf ADD	%EDX,%ECX

0x4240c1 LEA	(%RDI,%RCX,1),%EAX

0x4240c4 MOV	%EAX,0x54(%RSP)

0x4240c8 CMP	%EAX,%ECX

0x4240ca JAE	424343

0x4240d0 XOR	%EDX,%EDX

0x4240d2 MOV	%ECX,%EAX

0x4240d4 MOV	0x4c(%RSP),%ESI

0x4240d8 DIVL	0x50(%RSP)

0x4240dc LEA	(%RDX,%RSI,1),%R15D

0x4240e0 MOV	(%RBX),%RDX

0x4240e3 MOV	%R14D,%ESI

0x4240e6 ADD	%EBP,%EAX

0x4240e8 SUB	%R15D,%ESI

0x4240eb MOV	%RDX,0x58(%RSP)

0x4240f0 MOV	0x8(%RBX),%RDX

0x4240f4 CMP	%ESI,%EDI

0x4240f6 CMOVA	%ESI,%EDI

0x4240f9 MOV	%RDX,0x60(%RSP)

0x4240fe MOV	0x10(%RBX),%RDX

0x424102 MOV	%RDX,0x68(%RSP)

0x424107 MOV	0x18(%RBX),%RDX

0x42410b MOV	0x20(%RBX),%RBX

0x42410f MOV	%RDX,0x70(%RSP)

0x424114 MOVSXD	%EAX,%RDX

0x424117 LEA	(%RCX,%RDI,1),%EAX

0x42411a MOV	%RBX,0x78(%RSP)

0x42411f MOV	%EAX,0x24(%RSP)

0x424123 CMP	%EAX,%ECX

0x424125 JAE	42432f

0x42412b NOPL	(%RAX,%RAX,1)

  (196) 0x424130 MOV	0x58(%RSP),%RAX

  (196) 0x424135 LEA	0x1(%RDX),%RBX

  (196) 0x424139 MOV	%RBX,%RBP

  (196) 0x42413c MOV	%RBX,0x18(%RSP)

  (196) 0x424141 MOV	0x10(%RAX),%R10

  (196) 0x424145 MOV	(%RAX),%RCX

  (196) 0x424148 MOV	0x60(%RSP),%RAX

  (196) 0x42414d IMUL	%RDX,%RCX

  (196) 0x424151 MOV	%R10,0x38(%RSP)

  (196) 0x424156 MOV	(%RAX),%R12

  (196) 0x424159 MOV	0x10(%RAX),%R14

  (196) 0x42415d MOV	0x68(%RSP),%RAX

  (196) 0x424162 IMUL	%RDX,%R12

  (196) 0x424166 MOV	%RCX,0x40(%RSP)

  (196) 0x42416b MOV	0x10(%RAX),%R13

  (196) 0x42416f MOV	(%RAX),%RAX

  (196) 0x424172 IMUL	%RAX,%RBP

  (196) 0x424176 MOV	%RBP,%R8

  (196) 0x424179 SUB	%RAX,%R8

  (196) 0x42417c MOV	0x70(%RSP),%RAX

  (196) 0x424181 MOV	%R8,0x30(%RSP)

  (196) 0x424186 MOV	0x10(%RAX),%RBX

  (196) 0x42418a MOV	(%RAX),%R9

  (196) 0x42418d MOV	0x78(%RSP),%RAX

  (196) 0x424192 IMUL	%RDX,%R9

  (196) 0x424196 MOV	%RBX,0x10(%RSP)

  (196) 0x42419b IMUL	(%RAX),%RDX

  (196) 0x42419f MOV	0x10(%RAX),%RSI

  (196) 0x4241a3 MOV	%R9,0x28(%RSP)

  (196) 0x4241a8 MOV	%RSI,0x8(%RSP)

  (196) 0x4241ad MOV	%RDX,(%RSP)

  (196) 0x4241b1 CMP	$0x1,%EDI

  (196) 0x4241b4 JE	424280

  (196) 0x4241ba MOVSXD	%R15D,%RAX

  (196) 0x4241bd LEA	(%RBP,%RAX,1),%RSI

  (196) 0x4241c2 LEA	(%RCX,%RAX,1),%RDX

  (196) 0x4241c6 LEA	(%R13,%RSI,8),%R11

  (196) 0x4241cb LEA	(%R8,%RAX,1),%RSI

  (196) 0x4241cf MOV	0x10(%RSP),%R8

  (196) 0x4241d4 LEA	(%R10,%RDX,8),%RBX

  (196) 0x4241d8 LEA	(%R13,%RSI,8),%R10

  (196) 0x4241dd LEA	(%R9,%RAX,1),%RSI

  (196) 0x4241e1 LEA	0x1(%R12,%RAX,1),%RDX

  (196) 0x4241e6 LEA	(%R8,%RSI,8),%R9

  (196) 0x4241ea MOV	(%RSP),%RSI

  (196) 0x4241ee SAL	$0x3,%RDX

  (196) 0x4241f2 LEA	(%R14,%RDX,1),%RCX

  (196) 0x4241f6 LEA	-0x8(%R14,%RDX,1),%RDX

  (196) 0x4241fb ADD	%RSI,%RAX

  (196) 0x4241fe MOV	0x8(%RSP),%RSI

  (196) 0x424203 LEA	(%RSI,%RAX,8),%R8

  (196) 0x424207 MOV	%EDI,%ESI

  (196) 0x424209 XOR	%EAX,%EAX

  (196) 0x42420b SHR	$0x1,%ESI

  (196) 0x42420d SAL	$0x4,%RSI

  (196) 0x424211 NOPW	%CS:(%RAX,%RAX,1)

  (196) 0x42421c NOPL	(%RAX)

    (197) 0x424220 MOVUPD	(%RCX,%RAX,1),%XMM0

    (197) 0x424225 MOVUPD	(%RDX,%RAX,1),%XMM2

    (197) 0x42422a MOVUPD	(%R11,%RAX,1),%XMM3

    (197) 0x424230 MOVUPD	(%R10,%RAX,1),%XMM4

    (197) 0x424236 SUBPD	%XMM2,%XMM0

    (197) 0x42423a MOVUPD	(%RBX,%RAX,1),%XMM5

    (197) 0x42423f ADDPD	%XMM3,%XMM0

    (197) 0x424243 SUBPD	%XMM4,%XMM0

    (197) 0x424247 ADDPD	%XMM5,%XMM0

    (197) 0x42424b MOVUPS	%XMM0,(%R9,%RAX,1)

    (197) 0x424250 MOVUPD	(%RCX,%RAX,1),%XMM1

    (197) 0x424255 MOVUPD	(%RDX,%RAX,1),%XMM6

    (197) 0x42425a SUBPD	%XMM6,%XMM1

    (197) 0x42425e SUBPD	%XMM1,%XMM0

    (197) 0x424262 MOVUPS	%XMM0,(%R8,%RAX,1)

    (197) 0x424267 ADD	$0x10,%RAX

    (197) 0x42426b CMP	%RAX,%RSI

    (197) 0x42426e JNE	424220

  (196) 0x424270 TEST	$0x1,%DIL

  (196) 0x424274 JE	4242fd

  (196) 0x42427a AND	$-0x2,%EDI

  (196) 0x42427d ADD	%EDI,%R15D

  (196) 0x424280 MOVSXD	%R15D,%RAX

  (196) 0x424283 ADD	$0x1,%R15D

  (196) 0x424287 MOV	0x30(%RSP),%RSI

  (196) 0x42428c MOV	(%RSP),%RDI

  (196) 0x424290 MOVSXD	%R15D,%R15

  (196) 0x424293 ADD	%RAX,%RBP

  (196) 0x424296 MOV	0x38(%RSP),%RBX

  (196) 0x42429b ADD	%R12,%R15

  (196) 0x42429e ADD	%RAX,%R12

  (196) 0x4242a1 ADD	%RAX,%RSI

  (196) 0x4242a4 ADD	%RAX,%RDI

  (196) 0x4242a7 LEA	(%R14,%R15,8),%RDX

  (196) 0x4242ab LEA	(%R14,%R12,8),%RCX

  (196) 0x4242af MOVSD	(%RDX),%XMM0

  (196) 0x4242b3 SUBSD	(%RCX),%XMM0

  (196) 0x4242b7 ADDSD	(%R13,%RBP,8),%XMM0

  (196) 0x4242be SUBSD	(%R13,%RSI,8),%XMM0

  (196) 0x4242c5 MOV	0x40(%RSP),%RSI

  (196) 0x4242ca ADD	%RAX,%RSI

  (196) 0x4242cd ADDSD	(%RBX,%RSI,8),%XMM0

  (196) 0x4242d2 MOV	0x28(%RSP),%RSI

  (196) 0x4242d7 MOV	0x10(%RSP),%RBX

  (196) 0x4242dc ADD	%RAX,%RSI

  (196) 0x4242df MOV	%RDI,%RAX

  (196) 0x4242e2 MOV	0x8(%RSP),%RDI

  (196) 0x4242e7 MOVSD	%XMM0,(%RBX,%RSI,8)

  (196) 0x4242ec MOVSD	(%RDX),%XMM1

  (196) 0x4242f0 SUBSD	(%RCX),%XMM1

  (196) 0x4242f4 SUBSD	%XMM1,%XMM0

  (196) 0x4242f8 MOVSD	%XMM0,(%RDI,%RAX,8)

  (196) 0x4242fd MOV	0x24(%RSP),%ECX

  (196) 0x424301 MOV	0x18(%RSP),%RDX

  (196) 0x424306 CMP	%EDX,0x48(%RSP)

  (196) 0x42430a JLE	424343

  (196) 0x42430c MOV	0x54(%RSP),%EDI

  (196) 0x424310 MOV	0x50(%RSP),%ESI

  (196) 0x424314 MOV	0x4c(%RSP),%R15D

  (196) 0x424319 SUB	%ECX,%EDI

  (196) 0x42431b CMP	%ESI,%EDI

  (196) 0x42431d CMOVA	%ESI,%EDI

  (196) 0x424320 LEA	(%RCX,%RDI,1),%EAX

  (196) 0x424323 MOV	%EAX,0x24(%RSP)

  (196) 0x424327 CMP	%EAX,%ECX

  (196) 0x424329 JB	424130

(198) 0x42432f LEA	0x1(%RDX),%RAX

(198) 0x424333 MOV	%RAX,0x18(%RSP)

(198) 0x424338 MOV	0x18(%RSP),%RDX

(198) 0x42433d CMP	%EDX,0x48(%RSP)

(198) 0x424341 JG	42430c

0x424343 ADD	$0x88,%RSP

0x42434a POP	%RBX

0x42434b POP	%RBP

0x42434c POP	%R12

0x42434e POP	%R13

0x424350 POP	%R14

0x424352 POP	%R15

0x424354 RET

0x424355 ADD	$0x1,%EDI

0x424358 XOR	%EDX,%EDX

0x42435a JMP	4240bc

0x42435f NOP

Coverage (%)	Name	Source Location	Module
►96.85+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►3.12+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	advec_cell_kernel(int, int, in[...]		exec
○	advec_cell_driver(global_varia[...]		exec
○	advection(global_variables&)		exec
○	hydro(global_variables&, paral[...]		exec
○	main		exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines
Module	exec

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 7% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 12.00 to 0.75 cycles (16.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 12.00 to 10.63 cycles (1.13x speedup).

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 10.38 cycles (1.16x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
omp_get_thread_num@plt: 1 occurrences►

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVA: 1 occurrences►
DIV: 2 occurrences►

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 64 bytes. The binary function is storing 60 bytes.

General properties

nb instructions	82
nb uops	85
loop length	269
used x86 registers	12
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	10

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.63 cycles
front end	10.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	6.50	6.50	6.50	6.50	6.50	6.50	5.75	5.75	5.75	5.75	0.00	0.00	0.00	0.00	0.00	0.00
cycles	6.50	6.50	6.50	6.50	6.50	6.50	5.75	5.75	5.75	5.75	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	10.63
Dispatch	6.50
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

all	7%
load	6%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

2% of peak load performance is reached (5.33 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (5.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 424040

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB $0x88,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0x30(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x2c(%RBX),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
LEA -0x1(%RAX),%EBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV 0x34(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x28(%RDI),%EDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD $0x4,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
SUB $0x1,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %EAX,0x48(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %EDI,0x4c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %EAX,%EBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 424343 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x303>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
LEA 0x4(%RCX),%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
SUB %EBP,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMP %R14D,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 424343 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x303>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %R14D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SUB %EDI,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %R15D,0x50(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CALL 404660 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404550 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R13D,%EAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
DIV %R12D	2	0	0	0	2	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV %EAX,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JB 424355 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x315>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
IMUL %EDI,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
ADD %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA (%RDI,%RCX,1),%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %EAX,0x54(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %EAX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JAE 424343 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x303>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x4c(%RSP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
DIVL 0x50(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	10-17	6	scal (6.3%)
LEA (%RDX,%RSI,1),%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV (%RBX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %EBP,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
SUB %R15D,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %RDX,0x58(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x8(%RBX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP %ESI,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMOVA %ESI,%EDI	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	1	0.33	N/A
MOV %RDX,0x60(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x10(%RBX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDX,0x68(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x18(%RBX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x20(%RBX),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDX,0x70(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOVSXD %EAX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA (%RCX,%RDI,1),%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %RBX,0x78(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %EAX,0x24(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %EAX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JAE 42432f <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x2ef>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0x88,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
ADD $0x1,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 4240bc <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x7c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines
Module	exec

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 10.38 cycles (1.16x speedup).

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
omp_get_thread_num@plt: 1 occurrences►

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVA: 1 occurrences►
DIV: 2 occurrences►

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 64 bytes. The binary function is storing 60 bytes.

General properties

nb instructions	82
nb uops	85
loop length	269
used x86 registers	12
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	10

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.63 cycles
front end	10.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	6.50	6.50	6.50	6.50	6.50	6.50	5.75	5.75	5.75	5.75	0.00	0.00	0.00	0.00	0.00	0.00
cycles	6.50	6.50	6.50	6.50	6.50	6.50	5.75	5.75	5.75	5.75	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	10.63
Dispatch	6.50
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

all	7%
load	6%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

2% of peak load performance is reached (5.33 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (5.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 424040

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB $0x88,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0x30(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x2c(%RBX),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
LEA -0x1(%RAX),%EBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV 0x34(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x28(%RDI),%EDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD $0x4,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
SUB $0x1,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %EAX,0x48(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %EDI,0x4c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %EAX,%EBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 424343 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x303>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
LEA 0x4(%RCX),%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
SUB %EBP,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMP %R14D,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 424343 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x303>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %R14D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SUB %EDI,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %R15D,0x50(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CALL 404660 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404550 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R13D,%EAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
DIV %R12D	2	0	0	0	2	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV %EAX,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JB 424355 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x315>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
IMUL %EDI,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
ADD %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA (%RDI,%RCX,1),%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %EAX,0x54(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %EAX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JAE 424343 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x303>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x4c(%RSP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
DIVL 0x50(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	10-17	6	scal (6.3%)
LEA (%RDX,%RSI,1),%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV (%RBX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %EBP,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
SUB %R15D,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %RDX,0x58(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x8(%RBX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP %ESI,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMOVA %ESI,%EDI	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	1	0.33	N/A
MOV %RDX,0x60(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x10(%RBX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDX,0x68(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x18(%RBX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x20(%RBX),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDX,0x70(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOVSXD %EAX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA (%RCX,%RDI,1),%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %RBX,0x78(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %EAX,0x24(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %EAX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JAE 42432f <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x2ef>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0x88,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
ADD $0x1,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 4240bc <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x7c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	1.50	0.57
▼Loop 198 - - exec–	0.00	0.00
▼Loop 196 - - exec–	0.00	0.00
○Loop 197 - - exec	1.50	0.57

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code