OV - exec - Function accelerate_kernel(int, int, int, int, double, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: accelerate_kernel(int, int, int, int, double, clover::Buffer2D<double>&, clover::Buffer2D< ...	Module: exec	Source: :0-0	Coverage (incl. loops): 5.10% \| (excl. loops): 0.00%

  ***  This Panel is Intentionally Left Blank.  ***

It is due to a lack of debug symbols in the given object
(loop or function).

0x423450 PUSH	%R15

0x423452 PUSH	%R14

0x423454 PUSH	%R13

0x423456 PUSH	%R12

0x423458 PUSH	%RBP

0x423459 PUSH	%RBX

0x42345a MOV	%RDI,%RBX

0x42345d SUB	$0x1c8,%RSP

0x423464 MOV	0x60(%RDI),%EAX

0x423467 MOV	0x5c(%RBX),%ECX

0x42346a LEA	0x1(%RAX),%EBP

0x42346d MOV	0x64(%RDI),%EAX

0x423470 MOV	0x58(%RDI),%EDI

0x423473 ADD	$0x3,%EAX

0x423476 ADD	$0x1,%EDI

0x423479 MOV	%EAX,0x160(%RSP)

0x423480 MOV	%EDI,0x164(%RSP)

0x423487 CMP	%EAX,%EBP

0x423489 JGE	423df8

0x42348f MOV	%EAX,%R13D

0x423492 LEA	0x3(%RCX),%R14D

0x423496 SUB	%EBP,%R13D

0x423499 CMP	%R14D,%EDI

0x42349c JGE	423df8

0x4234a2 MOV	%R14D,%R15D

0x4234a5 SUB	%EDI,%R15D

0x4234a8 MOV	%R15D,0x168(%RSP)

0x4234b0 CALL	404660 <omp_get_num_threads@plt>

0x4234b5 MOV	%EAX,%R12D

0x4234b8 CALL	404550 <omp_get_thread_num@plt>

0x4234bd XOR	%EDX,%EDX

0x4234bf MOV	%EAX,%ECX

0x4234c1 MOV	%R15D,%EAX

0x4234c4 IMUL	%R13D,%EAX

0x4234c8 DIV	%R12D

0x4234cb MOV	%EAX,%ESI

0x4234cd CMP	%EDX,%ECX

0x4234cf JB	423e0a

0x4234d5 IMUL	%ESI,%ECX

0x4234d8 ADD	%EDX,%ECX

0x4234da LEA	(%RSI,%RCX,1),%EAX

0x4234dd MOV	%EAX,0x16c(%RSP)

0x4234e4 CMP	%EAX,%ECX

0x4234e6 JAE	423df8

0x4234ec MOV	%ECX,%EAX

0x4234ee XOR	%EDX,%EDX

0x4234f0 MOV	0x164(%RSP),%EDI

0x4234f7 MOVSD	0x50(%RBX),%XMM3

0x4234fc DIVL	0x168(%RSP)

0x423503 MOVSD	0x21e6d(%RIP),%XMM4

0x42350b MOVAPD	%XMM3,%XMM2

0x42350f MOVAPD	%XMM4,%XMM1

0x423513 UNPCKLPD	%XMM2,%XMM2

0x423517 UNPCKLPD	%XMM1,%XMM1

0x42351b ADD	%EDX,%EDI

0x42351d MOV	%R14D,%EDX

0x423520 ADD	%EBP,%EAX

0x423522 MOV	%EDI,0x108(%RSP)

0x423529 SUB	%EDI,%EDX

0x42352b MOV	0x18(%RBX),%RDI

0x42352f CLTQ

0x423531 MOV	%RAX,0x80(%RSP)

0x423539 MOV	%RDI,0x170(%RSP)

0x423541 MOV	0x10(%RBX),%RDI

0x423545 MOV	%RDI,0x178(%RSP)

0x42354d MOV	0x30(%RBX),%RDI

0x423551 MOV	%RDI,0x180(%RSP)

0x423559 MOV	(%RBX),%RDI

0x42355c MOV	%RDI,0x188(%RSP)

0x423564 MOV	0x20(%RBX),%RDI

0x423568 MOV	%RDI,0x190(%RSP)

0x423570 MOV	0x40(%RBX),%RDI

0x423574 MOV	%RDI,0x198(%RSP)

0x42357c MOV	0x38(%RBX),%RDI

0x423580 MOV	%RDI,0x1a0(%RSP)

0x423588 MOV	0x8(%RBX),%RDI

0x42358c MOV	%RDI,0x1a8(%RSP)

0x423594 MOV	0x48(%RBX),%RDI

0x423598 MOV	%RDI,0x1b0(%RSP)

0x4235a0 MOV	0x28(%RBX),%RDI

0x4235a4 MOV	%RDI,0x1b8(%RSP)

0x4235ac NOPL	(%RAX)

(193) 0x4235b0 CMP	%EDX,%ESI

(193) 0x4235b2 CMOVBE	%ESI,%EDX

(193) 0x4235b5 LEA	(%RCX,%RDX,1),%EAX

(193) 0x4235b8 MOV	%EDX,0x8c(%RSP)

(193) 0x4235bf MOV	%EAX,0x10c(%RSP)

(193) 0x4235c6 CMP	%EAX,%ECX

(193) 0x4235c8 JAE	423db7

(193) 0x4235ce MOV	0x80(%RSP),%R10

(193) 0x4235d6 MOV	0x170(%RSP),%RDI

(193) 0x4235de MOV	0x180(%RSP),%RBX

(193) 0x4235e6 MOV	0x188(%RSP),%R11

(193) 0x4235ee MOV	(%RDI),%RCX

(193) 0x4235f1 MOV	0x10(%RDI),%RSI

(193) 0x4235f5 MOV	%R10D,%EAX

(193) 0x4235f8 MOV	%R10,%R14

(193) 0x4235fb MOV	0x178(%RSP),%RDI

(193) 0x423603 SUB	$0x1,%EAX

(193) 0x423606 MOV	0x10(%RBX),%R15

(193) 0x42360a CLTQ

(193) 0x42360c MOV	0x190(%RSP),%R8

(193) 0x423614 MOV	(%RBX),%RBX

(193) 0x423617 MOV	%RSI,0x150(%RSP)

(193) 0x42361f MOV	(%RDI),%RDX

(193) 0x423622 MOV	0x10(%RDI),%RBP

(193) 0x423626 MOV	%RAX,%RDI

(193) 0x423629 MOV	%RAX,%R13

(193) 0x42362c IMUL	%RCX,%R13

(193) 0x423630 MOV	%R15,0xe8(%RSP)

(193) 0x423638 MOV	0x10(%R11),%R15

(193) 0x42363c IMUL	%RDX,%RDI

(193) 0x423640 MOV	0x10(%R8),%R12

(193) 0x423644 MOV	%RBP,0x148(%RSP)

(193) 0x42364c IMUL	%R10,%RDX

(193) 0x423650 MOV	%R15,0xe0(%RSP)

(193) 0x423658 MOV	%R10,%R15

(193) 0x42365b IMUL	%R10,%RCX

(193) 0x42365f MOV	%R13,0x158(%RSP)

(193) 0x423667 IMUL	%R10,%RBX

(193) 0x42366b MOV	%RDI,0x100(%RSP)

(193) 0x423673 MOV	%RDX,0xf0(%RSP)

(193) 0x42367b MOV	(%R8),%RDX

(193) 0x42367e MOV	%RCX,0xf8(%RSP)

(193) 0x423686 MOV	(%R11),%RCX

(193) 0x423689 MOV	%RDX,%R8

(193) 0x42368c MOV	0x198(%RSP),%R11

(193) 0x423694 IMUL	%RDX,%R14

(193) 0x423698 MOV	%RBX,0x140(%RSP)

(193) 0x4236a0 IMUL	%RAX,%R8

(193) 0x4236a4 MOV	%R12,0xd8(%RSP)

(193) 0x4236ac IMUL	%RCX,%R15

(193) 0x4236b0 MOV	0x10(%R11),%R9

(193) 0x4236b4 IMUL	%RAX,%RCX

(193) 0x4236b8 MOV	%R14,0x130(%RSP)

(193) 0x4236c0 MOV	%R8,0xc8(%RSP)

(193) 0x4236c8 MOV	%R15,0x138(%RSP)

(193) 0x4236d0 MOV	%RCX,0xd0(%RSP)

(193) 0x4236d8 MOV	%R9,0xc0(%RSP)

(193) 0x4236e0 MOV	%R10,%R9

(193) 0x4236e3 IMUL	(%R11),%R10

(193) 0x4236e7 MOV	0x1a0(%RSP),%R11

(193) 0x4236ef MOV	0x1a8(%RSP),%R8

(193) 0x4236f7 MOV	0x1b8(%RSP),%RDX

(193) 0x4236ff MOV	0x10(%R11),%RDI

(193) 0x423703 MOV	%R10,0x128(%RSP)

(193) 0x42370b MOV	%RDI,0xb0(%RSP)

(193) 0x423713 MOV	(%R11),%RDI

(193) 0x423716 MOV	0x10(%R8),%R11

(193) 0x42371a IMUL	%R9,%RDI

(193) 0x42371e MOV	%R11,0xa8(%RSP)

(193) 0x423726 MOV	(%R8),%R11

(193) 0x423729 MOV	0x1b0(%RSP),%R8

(193) 0x423731 IMUL	%R9,%R11

(193) 0x423735 MOV	%RDI,0xb8(%RSP)

(193) 0x42373d MOV	0x10(%R8),%RCX

(193) 0x423741 MOV	(%R8),%R8

(193) 0x423744 MOV	%RCX,0xa0(%RSP)

(193) 0x42374c MOV	0x10(%RDX),%RCX

(193) 0x423750 IMUL	%R9,%R8

(193) 0x423754 MOV	(%RDX),%RDX

(193) 0x423757 MOV	%R11,0x120(%RSP)

(193) 0x42375f MOV	%RCX,0x98(%RSP)

(193) 0x423767 IMUL	%RDX,%R9

(193) 0x42376b MOV	%R8,0x118(%RSP)

(193) 0x423773 IMUL	%RDX,%RAX

(193) 0x423777 CMPL	$0x1,0x8c(%RSP)

(193) 0x42377f MOV	%R9,0x110(%RSP)

(193) 0x423787 MOV	%RAX,0x90(%RSP)

(193) 0x42378f JE	423b41

(193) 0x423795 MOVSXD	0x108(%RSP),%RAX

(193) 0x42379d MOV	0x100(%RSP),%RDX

(193) 0x4237a5 LEA	(%R13,%RAX,1),%RCX

(193) 0x4237aa ADD	%RAX,%RDX

(193) 0x4237ad SAL	$0x3,%RCX

(193) 0x4237b1 SAL	$0x3,%RDX

(193) 0x4237b5 LEA	-0x8(%RSI,%RCX,1),%R13

(193) 0x4237ba MOV	%R13,0x70(%RSP)

(193) 0x4237bf MOV	%RBP,%R13

(193) 0x4237c2 LEA	-0x8(%RBP,%RDX,1),%RBP

(193) 0x4237c7 MOV	%RBP,0x68(%RSP)

(193) 0x4237cc MOV	0xf8(%RSP),%RBP

(193) 0x4237d4 LEA	(%RBP,%RAX,1),%RDI

(193) 0x4237d9 MOV	%RSI,%RBP

(193) 0x4237dc SAL	$0x3,%RDI

(193) 0x4237e0 LEA	-0x8(%RSI,%RDI,1),%RSI

(193) 0x4237e5 MOV	%RSI,0x60(%RSP)

(193) 0x4237ea MOV	0xf0(%RSP),%RSI

(193) 0x4237f2 ADD	%RAX,%RSI

(193) 0x4237f5 SAL	$0x3,%RSI

(193) 0x4237f9 LEA	-0x8(%R13,%RSI,1),%R12

(193) 0x4237fe MOV	%R12,0x58(%RSP)

(193) 0x423803 LEA	(%RBP,%RDI,1),%R12

(193) 0x423808 MOV	0xb8(%RSP),%RDI

(193) 0x423810 MOV	%R12,0x50(%RSP)

(193) 0x423815 LEA	(%R13,%RSI,1),%R12

(193) 0x42381a MOV	0xc0(%RSP),%RSI

(193) 0x423822 MOV	%R12,0x48(%RSP)

(193) 0x423827 LEA	(%RBP,%RCX,1),%R12

(193) 0x42382c MOV	0xe0(%RSP),%RBP

(193) 0x423834 MOV	%R12,0x40(%RSP)

(193) 0x423839 LEA	(%R13,%RDX,1),%R12

(193) 0x42383e LEA	(%RBX,%RAX,1),%RDX

(193) 0x423842 MOV	0xe8(%RSP),%RBX

(193) 0x42384a MOV	%R12,0x38(%RSP)

(193) 0x42384f LEA	(%RBX,%RDX,8),%RBX

(193) 0x423853 LEA	(%R15,%RAX,1),%RDX

(193) 0x423857 LEA	(%RBP,%RDX,8),%R15

(193) 0x42385c MOV	%RBX,0x30(%RSP)

(193) 0x423861 LEA	(%R14,%RAX,1),%RDX

(193) 0x423865 MOV	0xd8(%RSP),%RBX

(193) 0x42386d SAL	$0x3,%RDX

(193) 0x423871 LEA	(%RBX,%RDX,1),%R14

(193) 0x423875 LEA	-0x8(%RBX,%RDX,1),%R13

(193) 0x42387a MOV	0xd0(%RSP),%RDX

(193) 0x423882 ADD	%RAX,%RDX

(193) 0x423885 LEA	(%RBP,%RDX,8),%R12

(193) 0x42388a MOV	0xc8(%RSP),%RDX

(193) 0x423892 ADD	%RAX,%RDX

(193) 0x423895 SAL	$0x3,%RDX

(193) 0x423899 LEA	(%RBX,%RDX,1),%RBP

(193) 0x42389d LEA	-0x8(%RBX,%RDX,1),%RBX

(193) 0x4238a2 LEA	(%R10,%RAX,1),%RDX

(193) 0x4238a6 MOV	0xa8(%RSP),%R10

(193) 0x4238ae LEA	(%RSI,%RDX,8),%RCX

(193) 0x4238b2 LEA	(%RDI,%RAX,1),%RDX

(193) 0x4238b6 MOV	0xb0(%RSP),%RDI

(193) 0x4238be LEA	(%R9,%RAX,1),%RSI

(193) 0x4238c2 LEA	(%RDI,%RDX,8),%RDX

(193) 0x4238c6 MOV	0x98(%RSP),%RDI

(193) 0x4238ce SAL	$0x3,%RSI

(193) 0x4238d2 MOV	%RDX,0x28(%RSP)

(193) 0x4238d7 LEA	(%R11,%RAX,1),%RDX

(193) 0x4238db SAL	$0x3,%RDX

(193) 0x4238df LEA	(%RDI,%RSI,1),%R9

(193) 0x4238e3 LEA	(%R10,%RDX,1),%R11

(193) 0x4238e7 LEA	-0x8(%R10,%RDX,1),%R10

(193) 0x4238ec LEA	(%R8,%RAX,1),%RDX

(193) 0x4238f0 MOV	0xa0(%RSP),%R8

(193) 0x4238f8 LEA	(%R8,%RDX,8),%RDX

(193) 0x4238fc LEA	-0x8(%RDI,%RSI,1),%R8

(193) 0x423901 MOV	0x90(%RSP),%RSI

(193) 0x423909 ADD	%RSI,%RAX

(193) 0x42390c MOV	%RDI,%RSI

(193) 0x42390f SAL	$0x3,%RAX

(193) 0x423913 LEA	-0x8(%RSI,%RAX,1),%RSI

(193) 0x423918 LEA	(%RDI,%RAX,1),%RDI

(193) 0x42391c MOV	0x8c(%RSP),%EAX

(193) 0x423923 MOV	%RSI,0x78(%RSP)

(193) 0x423928 SHR	$0x1,%EAX

(193) 0x42392a SAL	$0x4,%RAX

(193) 0x42392e MOV	%RAX,0x20(%RSP)

(193) 0x423933 XOR	%EAX,%EAX

(193) 0x423935 NOPW	%CS:(%RAX,%RAX,1)

  (194) 0x423940 MOV	0x58(%RSP),%RSI

  (194) 0x423945 MOVUPD	(%RBX,%RAX,1),%XMM6

  (194) 0x42394a MOVUPD	(%R13,%RAX,1),%XMM8

  (194) 0x423951 MOVUPD	(%R15,%RAX,1),%XMM9

  (194) 0x423957 MOVUPD	(%RSI,%RAX,1),%XMM7

  (194) 0x42395c MOV	0x60(%RSP),%RSI

  (194) 0x423961 MOVAPS	%XMM7,(%RSP)

  (194) 0x423965 MOVUPD	(%RSI,%RAX,1),%XMM7

  (194) 0x42396a MOVAPD	(%RSP),%XMM0

  (194) 0x42396f MOV	0x68(%RSP),%RSI

  (194) 0x423974 MULPD	%XMM7,%XMM0

  (194) 0x423978 MOVUPD	(%RSI,%RAX,1),%XMM7

  (194) 0x42397d MOV	0x70(%RSP),%RSI

  (194) 0x423982 MOVUPD	(%RSI,%RAX,1),%XMM5

  (194) 0x423987 MOV	0x48(%RSP),%RSI

  (194) 0x42398c MOVAPS	%XMM5,0x10(%RSP)

  (194) 0x423991 MOVAPD	0x10(%RSP),%XMM5

  (194) 0x423997 MULPD	%XMM7,%XMM5

  (194) 0x42399b ADDPD	%XMM5,%XMM0

  (194) 0x42399f MOVUPD	(%RSI,%RAX,1),%XMM5

  (194) 0x4239a4 MOV	0x50(%RSP),%RSI

  (194) 0x4239a9 MOVUPD	(%RSI,%RAX,1),%XMM7

  (194) 0x4239ae MOV	0x38(%RSP),%RSI

  (194) 0x4239b3 MULPD	%XMM7,%XMM5

  (194) 0x4239b7 ADDPD	%XMM5,%XMM0

  (194) 0x4239bb MOVUPD	(%RSI,%RAX,1),%XMM5

  (194) 0x4239c0 MOV	0x40(%RSP),%RSI

  (194) 0x4239c5 MOVAPS	%XMM5,(%RSP)

  (194) 0x4239c9 MOVUPD	(%RSI,%RAX,1),%XMM5

  (194) 0x4239ce MOV	0x30(%RSP),%RSI

  (194) 0x4239d3 MOVAPS	%XMM5,0x10(%RSP)

  (194) 0x4239d8 MOVAPD	(%RSP),%XMM5

  (194) 0x4239dd MULPD	0x10(%RSP),%XMM5

  (194) 0x4239e3 MOVUPD	(%RSI,%RAX,1),%XMM7

  (194) 0x4239e8 ADDPD	%XMM5,%XMM0

  (194) 0x4239ec MOVAPD	%XMM2,%XMM5

  (194) 0x4239f0 MULPD	%XMM1,%XMM0

  (194) 0x4239f4 DIVPD	%XMM0,%XMM5

  (194) 0x4239f8 MOVUPD	(%RBP,%RAX,1),%XMM0

  (194) 0x4239fe SUBPD	%XMM6,%XMM0

  (194) 0x423a02 MOVUPD	(%R12,%RAX,1),%XMM6

  (194) 0x423a08 MULPD	%XMM6,%XMM0

  (194) 0x423a0c MOVUPD	(%R14,%RAX,1),%XMM6

  (194) 0x423a12 SUBPD	%XMM8,%XMM6

  (194) 0x423a17 MULPD	%XMM9,%XMM6

  (194) 0x423a1c ADDPD	%XMM6,%XMM0

  (194) 0x423a20 MULPD	%XMM5,%XMM0

  (194) 0x423a24 SUBPD	%XMM0,%XMM7

  (194) 0x423a28 MOVUPS	%XMM7,(%RCX,%RAX,1)

  (194) 0x423a2c MOVUPD	(%RBX,%RAX,1),%XMM6

  (194) 0x423a31 MOVUPD	(%R11,%RAX,1),%XMM11

  (194) 0x423a37 MOVUPD	(%R13,%RAX,1),%XMM0

  (194) 0x423a3e MOVUPD	(%RBP,%RAX,1),%XMM10

  (194) 0x423a45 MOV	0x28(%RSP),%RSI

  (194) 0x423a4a SUBPD	%XMM6,%XMM0

  (194) 0x423a4e MOVUPD	(%R10,%RAX,1),%XMM6

  (194) 0x423a54 MOVUPD	(%RSI,%RAX,1),%XMM7

  (194) 0x423a59 MOV	0x78(%RSP),%RSI

  (194) 0x423a5e MULPD	%XMM6,%XMM0

  (194) 0x423a62 MOVUPD	(%R14,%RAX,1),%XMM6

  (194) 0x423a68 SUBPD	%XMM10,%XMM6

  (194) 0x423a6d MULPD	%XMM11,%XMM6

  (194) 0x423a72 ADDPD	%XMM6,%XMM0

  (194) 0x423a76 MULPD	%XMM5,%XMM0

  (194) 0x423a7a SUBPD	%XMM0,%XMM7

  (194) 0x423a7e MOVUPS	%XMM7,(%RDX,%RAX,1)

  (194) 0x423a82 MOVUPD	(%R8,%RAX,1),%XMM6

  (194) 0x423a88 MOVUPD	(%R9,%RAX,1),%XMM0

  (194) 0x423a8e MOVUPD	(%RSI,%RAX,1),%XMM12

  (194) 0x423a94 MOVUPD	(%R12,%RAX,1),%XMM13

  (194) 0x423a9a SUBPD	%XMM6,%XMM0

  (194) 0x423a9e MOVUPD	(%R15,%RAX,1),%XMM6

  (194) 0x423aa4 MOVUPD	(%RCX,%RAX,1),%XMM7

  (194) 0x423aa9 MULPD	%XMM6,%XMM0

  (194) 0x423aad MOVUPD	(%RDI,%RAX,1),%XMM6

  (194) 0x423ab2 SUBPD	%XMM12,%XMM6

  (194) 0x423ab7 MULPD	%XMM13,%XMM6

  (194) 0x423abc ADDPD	%XMM6,%XMM0

  (194) 0x423ac0 MULPD	%XMM5,%XMM0

  (194) 0x423ac4 SUBPD	%XMM0,%XMM7

  (194) 0x423ac8 MOVUPS	%XMM7,(%RCX,%RAX,1)

  (194) 0x423acc MOVUPD	(%RDI,%RAX,1),%XMM6

  (194) 0x423ad1 MOVUPD	(%R9,%RAX,1),%XMM0

  (194) 0x423ad7 MOVUPD	(%RSI,%RAX,1),%XMM14

  (194) 0x423add MOVUPD	(%R10,%RAX,1),%XMM15

  (194) 0x423ae3 SUBPD	%XMM6,%XMM0

  (194) 0x423ae7 MOVUPD	(%R11,%RAX,1),%XMM6

  (194) 0x423aed MOVUPD	(%RDX,%RAX,1),%XMM7

  (194) 0x423af2 MOV	0x20(%RSP),%RSI

  (194) 0x423af7 MULPD	%XMM6,%XMM0

  (194) 0x423afb MOVUPD	(%R8,%RAX,1),%XMM6

  (194) 0x423b01 SUBPD	%XMM14,%XMM6

  (194) 0x423b06 MULPD	%XMM15,%XMM6

  (194) 0x423b0b ADDPD	%XMM6,%XMM0

  (194) 0x423b0f MULPD	%XMM5,%XMM0

  (194) 0x423b13 SUBPD	%XMM0,%XMM7

  (194) 0x423b17 MOVUPS	%XMM7,(%RDX,%RAX,1)

  (194) 0x423b1b ADD	$0x10,%RAX

  (194) 0x423b1f CMP	%RSI,%RAX

  (194) 0x423b22 JNE	423940

(193) 0x423b28 MOV	0x8c(%RSP),%EAX

(193) 0x423b2f TEST	$0x1,%AL

(193) 0x423b31 JE	423db0

(193) 0x423b37 AND	$-0x2,%EAX

(193) 0x423b3a ADD	%EAX,0x108(%RSP)

(193) 0x423b41 MOVSXD	0x108(%RSP),%RAX

(193) 0x423b49 MOV	0xf0(%RSP),%R15

(193) 0x423b51 MOV	0xf8(%RSP),%R14

(193) 0x423b59 MOV	0x148(%RSP),%RDI

(193) 0x423b61 LEA	-0x1(%RAX),%EDX

(193) 0x423b64 MOV	0x150(%RSP),%RBX

(193) 0x423b6c MOV	0x100(%RSP),%R9

(193) 0x423b74 MOVSXD	%EDX,%RDX

(193) 0x423b77 MOV	0x158(%RSP),%R11

(193) 0x423b7f LEA	(%R15,%RDX,1),%RSI

(193) 0x423b83 LEA	(%R14,%RDX,1),%RCX

(193) 0x423b87 MOVSD	(%RDI,%RSI,8),%XMM0

(193) 0x423b8c LEA	(%R9,%RDX,1),%RSI

(193) 0x423b90 MULSD	(%RBX,%RCX,8),%XMM0

(193) 0x423b95 LEA	(%R11,%RDX,1),%RCX

(193) 0x423b99 MOVSD	(%RDI,%RSI,8),%XMM5

(193) 0x423b9e MULSD	(%RBX,%RCX,8),%XMM5

(193) 0x423ba3 LEA	(%R14,%RAX,1),%RSI

(193) 0x423ba7 LEA	(%R15,%RAX,1),%RCX

(193) 0x423bab MOV	0x130(%RSP),%R15

(193) 0x423bb3 ADDSD	%XMM5,%XMM0

(193) 0x423bb7 MOVSD	(%RDI,%RCX,8),%XMM5

(193) 0x423bbc MULSD	(%RBX,%RSI,8),%XMM5

(193) 0x423bc1 LEA	(%R9,%RAX,1),%RCX

(193) 0x423bc5 LEA	(%R11,%RAX,1),%RSI

(193) 0x423bc9 ADDSD	%XMM5,%XMM0

(193) 0x423bcd MOVSD	(%RDI,%RCX,8),%XMM5

(193) 0x423bd2 MULSD	(%RBX,%RSI,8),%XMM5

(193) 0x423bd7 MOV	0x138(%RSP),%RCX

(193) 0x423bdf MOV	0xe0(%RSP),%RSI

(193) 0x423be7 MOV	0xd8(%RSP),%RBX

(193) 0x423bef ADD	%RAX,%RCX

(193) 0x423bf2 LEA	(%RSI,%RCX,8),%RDI

(193) 0x423bf6 LEA	(%R15,%RAX,1),%RCX

(193) 0x423bfa ADDSD	%XMM5,%XMM0

(193) 0x423bfe MOVAPD	%XMM3,%XMM5

(193) 0x423c02 LEA	(%RBX,%RCX,8),%R9

(193) 0x423c06 LEA	(%R15,%RDX,1),%RCX

(193) 0x423c0a MOVSD	(%R9),%XMM6

(193) 0x423c0f LEA	(%RBX,%RCX,8),%R10

(193) 0x423c13 MOV	0xd0(%RSP),%RCX

(193) 0x423c1b MULSD	%XMM4,%XMM0

(193) 0x423c1f SUBSD	(%R10),%XMM6

(193) 0x423c24 MULSD	(%RDI),%XMM6

(193) 0x423c28 ADD	%RAX,%RCX

(193) 0x423c2b LEA	(%RSI,%RCX,8),%R8

(193) 0x423c2f MOV	0xc8(%RSP),%RSI

(193) 0x423c37 LEA	(%RSI,%RAX,1),%RCX

(193) 0x423c3b DIVSD	%XMM0,%XMM5

(193) 0x423c3f LEA	(%RBX,%RCX,8),%R11

(193) 0x423c43 LEA	(%RSI,%RDX,1),%RCX

(193) 0x423c47 LEA	(%RBX,%RCX,8),%RBP

(193) 0x423c4b MOVSD	(%R11),%XMM0

(193) 0x423c50 MOV	0x128(%RSP),%RCX

(193) 0x423c58 SUBSD	(%RBP),%XMM0

(193) 0x423c5d MULSD	(%R8),%XMM0

(193) 0x423c62 MOV	0xc0(%RSP),%RBX

(193) 0x423c6a ADD	%RAX,%RCX

(193) 0x423c6d LEA	(%RBX,%RCX,8),%RSI

(193) 0x423c71 MOV	0x140(%RSP),%RCX

(193) 0x423c79 MOV	0xe8(%RSP),%RBX

(193) 0x423c81 ADDSD	%XMM6,%XMM0

(193) 0x423c85 ADD	%RAX,%RCX

(193) 0x423c88 MOVSD	(%RBX,%RCX,8),%XMM6

(193) 0x423c8d MULSD	%XMM5,%XMM0

(193) 0x423c91 SUBSD	%XMM0,%XMM6

(193) 0x423c95 MOVSD	%XMM6,(%RSI)

(193) 0x423c99 MOVSD	(%R9),%XMM6

(193) 0x423c9e MOVSD	(%R10),%XMM0

(193) 0x423ca3 MOV	0x120(%RSP),%R15

(193) 0x423cab MOV	0xa8(%RSP),%R14

(193) 0x423cb3 SUBSD	(%RBP),%XMM0

(193) 0x423cb8 SUBSD	(%R11),%XMM6

(193) 0x423cbd LEA	(%R15,%RAX,1),%RCX

(193) 0x423cc1 LEA	(%R14,%RCX,8),%RBX

(193) 0x423cc5 LEA	(%R15,%RDX,1),%RCX

(193) 0x423cc9 MOV	0x110(%RSP),%R15

(193) 0x423cd1 LEA	(%R14,%RCX,8),%R13

(193) 0x423cd5 MULSD	(%RBX),%XMM6

(193) 0x423cd9 MOV	0x118(%RSP),%RCX

(193) 0x423ce1 MULSD	(%R13),%XMM0

(193) 0x423ce7 MOV	0xa0(%RSP),%R14

(193) 0x423cef LEA	(%R15,%RDX,1),%R9

(193) 0x423cf3 ADD	%RAX,%RCX

(193) 0x423cf6 LEA	(%R14,%RCX,8),%R12

(193) 0x423cfa MOV	0xb8(%RSP),%RCX

(193) 0x423d02 MOV	0xb0(%RSP),%R14

(193) 0x423d0a ADD	%RAX,%RCX

(193) 0x423d0d ADDSD	%XMM6,%XMM0

(193) 0x423d11 MOVSD	(%R14,%RCX,8),%XMM6

(193) 0x423d17 LEA	(%R15,%RAX,1),%RCX

(193) 0x423d1b MOV	0x90(%RSP),%R15

(193) 0x423d23 MOV	0x98(%RSP),%R14

(193) 0x423d2b ADD	%R15,%RAX

(193) 0x423d2e ADD	%R15,%RDX

(193) 0x423d31 MULSD	%XMM5,%XMM0

(193) 0x423d35 LEA	(%R14,%RCX,8),%RCX

(193) 0x423d39 LEA	(%R14,%R9,8),%R9

(193) 0x423d3d LEA	(%R14,%RAX,8),%RAX

(193) 0x423d41 LEA	(%R14,%RDX,8),%RDX

(193) 0x423d45 SUBSD	%XMM0,%XMM6

(193) 0x423d49 MOVSD	%XMM6,(%R12)

(193) 0x423d4f MOVSD	(%RAX),%XMM0

(193) 0x423d53 MOVSD	(%RCX),%XMM6

(193) 0x423d57 SUBSD	(%RDX),%XMM0

(193) 0x423d5b SUBSD	(%R9),%XMM6

(193) 0x423d60 MULSD	(%R8),%XMM0

(193) 0x423d65 MULSD	(%RDI),%XMM6

(193) 0x423d69 ADDSD	%XMM6,%XMM0

(193) 0x423d6d MOVSD	(%RSI),%XMM6

(193) 0x423d71 MULSD	%XMM5,%XMM0

(193) 0x423d75 SUBSD	%XMM0,%XMM6

(193) 0x423d79 MOVSD	%XMM6,(%RSI)

(193) 0x423d7d MOVSD	(%R9),%XMM0

(193) 0x423d82 MOVSD	(%RCX),%XMM6

(193) 0x423d86 SUBSD	(%RDX),%XMM0

(193) 0x423d8a SUBSD	(%RAX),%XMM6

(193) 0x423d8e MULSD	(%R13),%XMM0

(193) 0x423d94 MULSD	(%RBX),%XMM6

(193) 0x423d98 ADDSD	%XMM6,%XMM0

(193) 0x423d9c MULSD	%XMM5,%XMM0

(193) 0x423da0 MOVSD	(%R12),%XMM5

(193) 0x423da6 SUBSD	%XMM0,%XMM5

(193) 0x423daa MOVSD	%XMM5,(%R12)

(193) 0x423db0 MOV	0x10c(%RSP),%ECX

(193) 0x423db7 ADDQ	$0x1,0x80(%RSP)

(193) 0x423dc0 MOV	0x80(%RSP),%RAX

(193) 0x423dc8 CMP	%EAX,0x160(%RSP)

(193) 0x423dcf JLE	423df8

(193) 0x423dd1 MOV	0x16c(%RSP),%ESI

(193) 0x423dd8 MOV	0x164(%RSP),%EAX

(193) 0x423ddf MOV	0x168(%RSP),%EDX

(193) 0x423de6 MOV	%EAX,0x108(%RSP)

(193) 0x423ded SUB	%ECX,%ESI

(193) 0x423def JMP	4235b0

0x423df4 NOPL	(%RAX)

0x423df8 ADD	$0x1c8,%RSP

0x423dff POP	%RBX

0x423e00 POP	%RBP

0x423e01 POP	%R12

0x423e03 POP	%R13

0x423e05 POP	%R14

0x423e07 POP	%R15

0x423e09 RET

0x423e0a ADD	$0x1,%ESI

0x423e0d XOR	%EDX,%EDX

0x423e0f JMP	4234d5

0x423e14 NOPW	%CS:(%RAX,%RAX,1)

0x423e1f NOP

Coverage (%)	Name	Source Location	Module
►96.60+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►3.14+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	accelerate(global_variables&)		exec
○	hydro(global_variables&, paral[...]		exec
○	main		exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines
Module	exec

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.00 to 1.50 cycles (8.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 9% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 12.00 to 0.87 cycles (13.86x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck).

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
omp_get_thread_num@plt: 1 occurrences►

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►

Conversion instructions

Detected expensive conversion instructions.

Details

CLTQ: 1 occurrences►

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 120 bytes. The binary function is storing 108 bytes.

General properties

nb instructions	96
nb uops	95
loop length	396
used x86 registers	12
used mmx registers	0
used xmm registers	4
used ymm registers	0
used zmm registers	0
nb stack references	16

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	11.88 cycles
front end	11.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.33	5.33	5.33	5.33	5.33	5.33	9.00	9.00	9.00	9.00	0.50	0.50	0.50	0.50	0.00	0.00
cycles	5.33	5.33	5.33	5.33	5.33	5.33	9.00	9.00	9.00	9.00	0.50	0.50	0.50	0.50	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	11.88
Dispatch	9.00
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	33%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	5%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	12%

Vector efficiency ratios

INT

all	8%
load	6%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	16%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

INT+FP

all	9%
load	10%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

3% of peak load performance is reached (10.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (9.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 423450

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB $0x1c8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x60(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x5c(%RBX),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA 0x1(%RAX),%EBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV 0x64(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x58(%RDI),%EDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
ADD $0x3,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x1,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EAX,0x160(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV %EDI,0x164(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
CMP %EAX,%EBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 423df8 <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x9a8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
LEA 0x3(%RCX),%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB %EBP,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CMP %R14D,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 423df8 <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x9a8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R14D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SUB %EDI,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %R15D,0x168(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
CALL 404660 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404550 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R13D,%EAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
DIV %R12D	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JB 423e0a <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x9ba>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %ESI,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADD %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RSI,%RCX,1),%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %EAX,0x16c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
CMP %EAX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JAE 423df8 <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x9a8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV 0x164(%RSP),%EDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOVSD 0x50(%RBX),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
DIVL 0x168(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOVSD 0x21e6d(%RIP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVAPD %XMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOVAPD %XMM4,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
UNPCKLPD %XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
UNPCKLPD %XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
ADD %EDX,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R14D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
ADD %EBP,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EDI,0x108(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
SUB %EDI,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV 0x18(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CLTQ																				scal (12.5%)
MOV %RAX,0x80(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDI,0x170(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x10(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,0x178(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x30(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,0x180(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,0x188(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x20(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,0x190(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x40(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,0x198(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x38(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,0x1a0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x8(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,0x1a8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x48(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,0x1b0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x28(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,0x1b8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0x1c8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD $0x1,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
JMP 4234d5 <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x85>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines
Module	exec

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.00 to 1.50 cycles (8.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck).

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact.

No data for this section

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
omp_get_thread_num@plt: 1 occurrences►

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►

Conversion instructions

Detected expensive conversion instructions.

Details

CLTQ: 1 occurrences►

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 120 bytes. The binary function is storing 108 bytes.

General properties

nb instructions	96
nb uops	95
loop length	396
used x86 registers	12
used mmx registers	0
used xmm registers	4
used ymm registers	0
used zmm registers	0
nb stack references	16

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	11.88 cycles
front end	11.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.33	5.33	5.33	5.33	5.33	5.33	9.00	9.00	9.00	9.00	0.50	0.50	0.50	0.50	0.00	0.00
cycles	5.33	5.33	5.33	5.33	5.33	5.33	9.00	9.00	9.00	9.00	0.50	0.50	0.50	0.50	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	11.88
Dispatch	9.00
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	33%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	5%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	12%

Vector efficiency ratios

INT

all	8%
load	6%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	16%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

INT+FP

all	9%
load	10%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

3% of peak load performance is reached (10.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (9.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 423450

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB $0x1c8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x60(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x5c(%RBX),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA 0x1(%RAX),%EBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV 0x64(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x58(%RDI),%EDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
ADD $0x3,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x1,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EAX,0x160(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV %EDI,0x164(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
CMP %EAX,%EBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 423df8 <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x9a8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
LEA 0x3(%RCX),%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB %EBP,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CMP %R14D,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 423df8 <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x9a8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R14D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SUB %EDI,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %R15D,0x168(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
CALL 404660 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404550 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R13D,%EAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
DIV %R12D	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JB 423e0a <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x9ba>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %ESI,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADD %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RSI,%RCX,1),%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %EAX,0x16c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
CMP %EAX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JAE 423df8 <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x9a8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV 0x164(%RSP),%EDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOVSD 0x50(%RBX),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
DIVL 0x168(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOVSD 0x21e6d(%RIP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVAPD %XMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOVAPD %XMM4,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
UNPCKLPD %XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
UNPCKLPD %XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
ADD %EDX,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R14D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
ADD %EBP,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EDI,0x108(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
SUB %EDI,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV 0x18(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CLTQ																				scal (12.5%)
MOV %RAX,0x80(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDI,0x170(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x10(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,0x178(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x30(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,0x180(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,0x188(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x20(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,0x190(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x40(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,0x198(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x38(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,0x1a0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x8(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,0x1a8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x48(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,0x1b0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x28(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,0x1b8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0x1c8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD $0x1,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
JMP 4234d5 <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x85>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼accelerate_kernel(int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	5.10	1.95
▼Loop 193 - - exec–	0.01	0.01
○Loop 194 - - exec	5.09	1.95

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Matching between your function (in the source code) and the binary function

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Code clean check

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Vectorization

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Execution units bottlenecks

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CALL instructions

Details

Complex instructions

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Conversion instructions

Details

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Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code