OV - exec - Function PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D<double>&, clover::Buffer2D<d ...	Module: exec	Source: :0-0	Coverage (incl. loops): 6.36% \| (excl. loops): 0.00%

  ***  This Panel is Intentionally Left Blank.  ***

It is due to a lack of debug symbols in the given object
(loop or function).

0x4333e0 PUSH	%R15

0x4333e2 PUSH	%R14

0x4333e4 PUSH	%R13

0x4333e6 PUSH	%R12

0x4333e8 PUSH	%RBP

0x4333e9 PUSH	%RBX

0x4333ea MOV	%RDI,%RBX

0x4333ed SUB	$0x238,%RSP

0x4333f4 MOV	0x78(%RDI),%EAX

0x4333f7 MOV	0x70(%RDI),%ESI

0x4333fa LEA	0x1(%RAX),%EBP

0x4333fd MOV	0x7c(%RDI),%EAX

0x433400 ADD	$0x1,%ESI

0x433403 MOV	0x74(%RDI),%EDI

0x433406 MOV	%ESI,0x1bc(%RSP)

0x43340d ADD	$0x2,%EAX

0x433410 MOV	%EAX,0x1b8(%RSP)

0x433417 CMP	%EAX,%EBP

0x433419 JGE	433e70

0x43341f MOV	%EAX,%R13D

0x433422 LEA	0x2(%RDI),%R14D

0x433426 SUB	%EBP,%R13D

0x433429 CMP	%R14D,%ESI

0x43342c JGE	433e70

0x433432 MOV	%R14D,%R15D

0x433435 SUB	%ESI,%R15D

0x433438 MOV	%R15D,0x1c0(%RSP)

0x433440 CALL	404660 <omp_get_num_threads@plt>

0x433445 MOV	%EAX,%R12D

0x433448 CALL	404550 <omp_get_thread_num@plt>

0x43344d XOR	%EDX,%EDX

0x43344f MOV	%EAX,%ECX

0x433451 MOV	%R15D,%EAX

0x433454 IMUL	%R13D,%EAX

0x433458 DIV	%R12D

0x43345b MOV	%EAX,%ESI

0x43345d CMP	%EDX,%ECX

0x43345f JB	433e82

0x433465 IMUL	%ESI,%ECX

0x433468 ADD	%EDX,%ECX

0x43346a LEA	(%RSI,%RCX,1),%EAX

0x43346d MOV	%EAX,0x1c4(%RSP)

0x433474 CMP	%EAX,%ECX

0x433476 JAE	433e70

0x43347c MOV	%ECX,%EAX

0x43347e XOR	%EDX,%EDX

0x433480 MOV	0x1bc(%RSP),%EDI

0x433487 MOVSD	(%RBX),%XMM5

0x43348b DIVL	0x1c0(%RSP)

0x433492 MOVSD	0x11ede(%RIP),%XMM6

0x43349a MOVAPD	%XMM5,%XMM3

0x43349e MOVAPD	%XMM6,%XMM2

0x4334a2 UNPCKLPD	%XMM3,%XMM3

0x4334a6 UNPCKLPD	%XMM2,%XMM2

0x4334aa ADD	%EDX,%EDI

0x4334ac MOV	%R14D,%EDX

0x4334af ADD	%EBP,%EAX

0x4334b1 MOV	%EDI,0x158(%RSP)

0x4334b8 SUB	%EDI,%EDX

0x4334ba MOV	0x8(%RBX),%RDI

0x4334be MOVSXD	%EAX,%R9

0x4334c1 MOV	%R9,%R15

0x4334c4 MOV	%RDI,0x1c8(%RSP)

0x4334cc MOV	0x50(%RBX),%RDI

0x4334d0 MOV	%RDI,0x1d0(%RSP)

0x4334d8 MOV	0x58(%RBX),%RDI

0x4334dc MOV	%RDI,0x1d8(%RSP)

0x4334e4 MOV	0x10(%RBX),%RDI

0x4334e8 MOV	%RDI,0x1e0(%RSP)

0x4334f0 MOV	0x60(%RBX),%RDI

0x4334f4 MOV	%RDI,0x1e8(%RSP)

0x4334fc MOV	0x68(%RBX),%RDI

0x433500 MOV	%RDI,0x1f0(%RSP)

0x433508 MOV	0x18(%RBX),%RDI

0x43350c MOV	%RDI,0x1f8(%RSP)

0x433514 MOV	0x40(%RBX),%RDI

0x433518 MOV	%RDI,0x200(%RSP)

0x433520 MOV	0x20(%RBX),%RDI

0x433524 MOV	%RDI,0x208(%RSP)

0x43352c MOV	0x48(%RBX),%RDI

0x433530 MOV	%RDI,0x210(%RSP)

0x433538 MOV	0x30(%RBX),%RDI

0x43353c MOV	%RDI,0x218(%RSP)

0x433544 MOV	0x38(%RBX),%RDI

0x433548 MOV	0x28(%RBX),%RBX

0x43354c MOV	%RDI,0x220(%RSP)

0x433554 MOV	%RBX,0x228(%RSP)

0x43355c MOVSD	0x11ccc(%RIP),%XMM7

0x433564 MOVAPD	%XMM7,%XMM4

0x433568 UNPCKLPD	%XMM4,%XMM4

0x43356c NOPL	(%RAX)

(338) 0x433570 CMP	%EDX,%ESI

(338) 0x433572 CMOVBE	%ESI,%EDX

(338) 0x433575 LEA	(%RCX,%RDX,1),%EAX

(338) 0x433578 MOV	%EDX,0xa4(%RSP)

(338) 0x43357f MOV	%EAX,0x15c(%RSP)

(338) 0x433586 CMP	%EAX,%ECX

(338) 0x433588 JAE	433e36

(338) 0x43358e MOV	0x1c8(%RSP),%RAX

(338) 0x433596 MOV	0x10(%RAX),%R13

(338) 0x43359a MOV	(%RAX),%R8

(338) 0x43359d MOV	0x1d0(%RSP),%RAX

(338) 0x4335a5 IMUL	%R15,%R8

(338) 0x4335a9 MOV	%R13,0x150(%RSP)

(338) 0x4335b1 MOV	0x10(%RAX),%RBX

(338) 0x4335b5 MOV	(%RAX),%RAX

(338) 0x4335b8 MOV	%RAX,%RSI

(338) 0x4335bb MOV	%R8,0x1b0(%RSP)

(338) 0x4335c3 IMUL	%R15,%RSI

(338) 0x4335c7 MOV	%RBX,0x1a0(%RSP)

(338) 0x4335cf ADD	%RSI,%RAX

(338) 0x4335d2 MOV	%RSI,0x1a8(%RSP)

(338) 0x4335da MOV	%RAX,0x148(%RSP)

(338) 0x4335e2 MOV	0x1d8(%RSP),%RAX

(338) 0x4335ea MOV	0x10(%RAX),%R10

(338) 0x4335ee MOV	(%RAX),%RAX

(338) 0x4335f1 MOV	%RAX,%R14

(338) 0x4335f4 MOV	%R10,0x190(%RSP)

(338) 0x4335fc IMUL	%R15,%R14

(338) 0x433600 LEA	(%RAX,%R14,1),%RDI

(338) 0x433604 MOV	%R14,0x198(%RSP)

(338) 0x43360c MOV	%RDI,0x140(%RSP)

(338) 0x433614 MOV	0x1e0(%RSP),%RDI

(338) 0x43361c MOV	0x10(%RDI),%RAX

(338) 0x433620 MOV	(%RDI),%RCX

(338) 0x433623 MOV	0x1e8(%RSP),%RDI

(338) 0x43362b MOV	%RAX,0x138(%RSP)

(338) 0x433633 MOV	%RCX,%RBP

(338) 0x433636 MOV	(%RDI),%RDX

(338) 0x433639 MOV	0x10(%RDI),%R11

(338) 0x43363d IMUL	%R15,%RBP

(338) 0x433641 MOV	0x1f0(%RSP),%RDI

(338) 0x433649 MOV	%RDX,%R12

(338) 0x43364c MOV	%R11,0x178(%RSP)

(338) 0x433654 MOV	(%RDI),%RAX

(338) 0x433657 IMUL	%R15,%R12

(338) 0x43365b MOV	0x10(%RDI),%R9

(338) 0x43365f ADD	%RBP,%RCX

(338) 0x433662 MOV	%RCX,0x130(%RSP)

(338) 0x43366a MOV	%RAX,%RDI

(338) 0x43366d MOV	%RBP,0x188(%RSP)

(338) 0x433675 IMUL	%R15,%RDI

(338) 0x433679 ADD	%R12,%RDX

(338) 0x43367c MOV	%R12,0x180(%RSP)

(338) 0x433684 MOV	%R9,0x170(%RSP)

(338) 0x43368c MOV	%RDX,0x128(%RSP)

(338) 0x433694 LEA	(%RAX,%RDI,1),%RDX

(338) 0x433698 MOV	%RDI,0xa8(%RSP)

(338) 0x4336a0 MOV	%RDX,0x120(%RSP)

(338) 0x4336a8 MOV	0x1f8(%RSP),%RDX

(338) 0x4336b0 MOV	0x10(%RDX),%RCX

(338) 0x4336b4 MOV	(%RDX),%RAX

(338) 0x4336b7 MOV	0x200(%RSP),%RDX

(338) 0x4336bf MOV	%RCX,0x110(%RSP)

(338) 0x4336c7 MOV	0x208(%RSP),%RCX

(338) 0x4336cf IMUL	%R15,%RAX

(338) 0x4336d3 MOV	0x10(%RDX),%R13

(338) 0x4336d7 MOV	(%RDX),%RDX

(338) 0x4336da IMUL	%R15,%RDX

(338) 0x4336de MOV	%R13,0x100(%RSP)

(338) 0x4336e6 MOV	0x10(%RCX),%R13

(338) 0x4336ea MOV	(%RCX),%RCX

(338) 0x4336ed MOV	%RAX,0x118(%RSP)

(338) 0x4336f5 MOV	%R13,0xf0(%RSP)

(338) 0x4336fd MOV	%RDX,0x108(%RSP)

(338) 0x433705 MOV	0x210(%RSP),%RDX

(338) 0x43370d IMUL	%R15,%RCX

(338) 0x433711 MOV	(%RDX),%R13

(338) 0x433714 MOV	0x10(%RDX),%RAX

(338) 0x433718 MOV	0x218(%RSP),%RDX

(338) 0x433720 MOV	%RCX,0xf8(%RSP)

(338) 0x433728 IMUL	%R15,%R13

(338) 0x43372c MOV	%RAX,0xb0(%RSP)

(338) 0x433734 MOV	0x10(%RDX),%RCX

(338) 0x433738 MOV	(%RDX),%RAX

(338) 0x43373b MOV	0x220(%RSP),%RDX

(338) 0x433743 IMUL	%R15,%RAX

(338) 0x433747 MOV	%R13,0xe8(%RSP)

(338) 0x43374f MOV	(%RDX),%R13

(338) 0x433752 MOV	%RCX,0xc0(%RSP)

(338) 0x43375a IMUL	%R15,%R13

(338) 0x43375e MOV	%RAX,0xb8(%RSP)

(338) 0x433766 MOV	0x10(%RDX),%RAX

(338) 0x43376a MOV	%RAX,0xd0(%RSP)

(338) 0x433772 MOV	%R13,0xc8(%RSP)

(338) 0x43377a MOV	0x228(%RSP),%RDX

(338) 0x433782 MOV	0x10(%RDX),%RCX

(338) 0x433786 MOV	(%RDX),%RDX

(338) 0x433789 IMUL	%R15,%RDX

(338) 0x43378d CMPL	$0x1,0xa4(%RSP)

(338) 0x433795 MOV	%RCX,0xe0(%RSP)

(338) 0x43379d MOV	%RDX,0xd8(%RSP)

(338) 0x4337a5 JE	433bd3

(338) 0x4337ab MOVSXD	0x158(%RSP),%RAX

(338) 0x4337b3 MOV	0x150(%RSP),%R13

(338) 0x4337bb LEA	(%RSI,%RAX,1),%RDI

(338) 0x4337bf LEA	(%R14,%RAX,1),%RCX

(338) 0x4337c3 ADD	%RAX,%R8

(338) 0x4337c6 SAL	$0x3,%RDI

(338) 0x4337ca SAL	$0x3,%RCX

(338) 0x4337ce LEA	(%RBX,%RDI,1),%RSI

(338) 0x4337d2 LEA	(%R10,%RCX,1),%R14

(338) 0x4337d6 SAL	$0x3,%R8

(338) 0x4337da MOV	%RSI,0x88(%RSP)

(338) 0x4337e2 MOV	0x148(%RSP),%RSI

(338) 0x4337ea LEA	(%R13,%R8,1),%RDX

(338) 0x4337ef MOV	%R14,0x78(%RSP)

(338) 0x4337f4 MOV	0x140(%RSP),%R14

(338) 0x4337fc ADD	%RAX,%RSI

(338) 0x4337ff MOV	%RDX,0x160(%RSP)

(338) 0x433807 SAL	$0x3,%RSI

(338) 0x43380b LEA	(%RBX,%RSI,1),%RDX

(338) 0x43380f MOV	%RDX,0x80(%RSP)

(338) 0x433817 LEA	(%R14,%RAX,1),%RDX

(338) 0x43381b SAL	$0x3,%RDX

(338) 0x43381f LEA	(%R10,%RDX,1),%R14

(338) 0x433823 MOV	%R14,0x70(%RSP)

(338) 0x433828 LEA	0x8(%R13,%R8,1),%R14

(338) 0x43382d MOV	0x130(%RSP),%R8

(338) 0x433835 MOV	%R14,0x68(%RSP)

(338) 0x43383a LEA	0x8(%RBX,%RDI,1),%R14

(338) 0x43383f MOV	0xa8(%RSP),%RDI

(338) 0x433847 MOV	%R14,0x60(%RSP)

(338) 0x43384c LEA	0x8(%RBX,%RSI,1),%R14

(338) 0x433851 MOV	0x138(%RSP),%RBX

(338) 0x433859 MOV	%R14,0x58(%RSP)

(338) 0x43385e LEA	0x8(%R10,%RCX,1),%R14

(338) 0x433863 LEA	0x8(%R10,%RDX,1),%R10

(338) 0x433868 MOV	0xf8(%RSP),%RCX

(338) 0x433870 LEA	(%RBP,%RAX,1),%RDX

(338) 0x433875 MOV	%R10,0x48(%RSP)

(338) 0x43387a LEA	(%RBX,%RDX,8),%R10

(338) 0x43387e LEA	(%R12,%RAX,1),%RDX

(338) 0x433882 MOV	%R14,0x50(%RSP)

(338) 0x433887 SAL	$0x3,%RDX

(338) 0x43388b MOV	%R10,0x40(%RSP)

(338) 0x433890 LEA	0x8(%R11,%RDX,1),%RSI

(338) 0x433895 LEA	(%R11,%RDX,1),%R14

(338) 0x433899 LEA	(%RDI,%RAX,1),%RDX

(338) 0x43389d MOV	%R11,%RDI

(338) 0x4338a0 MOV	%RSI,0x10(%RSP)

(338) 0x4338a5 MOV	0xf0(%RSP),%RSI

(338) 0x4338ad SAL	$0x3,%RDX

(338) 0x4338b1 LEA	(%R9,%RDX,1),%R12

(338) 0x4338b5 LEA	0x8(%R9,%RDX,1),%RBP

(338) 0x4338ba LEA	(%R8,%RAX,1),%RDX

(338) 0x4338be MOV	0x128(%RSP),%R8

(338) 0x4338c6 LEA	(%RBX,%RDX,8),%RBX

(338) 0x4338ca LEA	(%R8,%RAX,1),%RDX

(338) 0x4338ce MOV	0x120(%RSP),%R8

(338) 0x4338d6 SAL	$0x3,%RDX

(338) 0x4338da LEA	0x8(%RDI,%RDX,1),%R10

(338) 0x4338df LEA	(%R11,%RDX,1),%R11

(338) 0x4338e3 MOV	%R9,%RDI

(338) 0x4338e6 LEA	(%R8,%RAX,1),%RDX

(338) 0x4338ea SAL	$0x3,%RDX

(338) 0x4338ee LEA	0x8(%RDI,%RDX,1),%R8

(338) 0x4338f3 MOV	0x118(%RSP),%RDI

(338) 0x4338fb LEA	(%R9,%RDX,1),%R9

(338) 0x4338ff LEA	(%RDI,%RAX,1),%RDX

(338) 0x433903 MOV	0x110(%RSP),%RDI

(338) 0x43390b LEA	(%RDI,%RDX,8),%RDI

(338) 0x43390f MOV	0x108(%RSP),%RDX

(338) 0x433917 MOV	%RDI,0x38(%RSP)

(338) 0x43391c MOV	0x100(%RSP),%RDI

(338) 0x433924 ADD	%RAX,%RDX

(338) 0x433927 LEA	(%RDI,%RDX,8),%RDI

(338) 0x43392b LEA	(%RCX,%RAX,1),%RDX

(338) 0x43392f LEA	(%RSI,%RDX,8),%RDX

(338) 0x433933 MOV	0xe8(%RSP),%RSI

(338) 0x43393b LEA	(%RSI,%RAX,1),%RCX

(338) 0x43393f MOV	0xb0(%RSP),%RSI

(338) 0x433947 LEA	(%RSI,%RCX,8),%RSI

(338) 0x43394b MOV	0xb8(%RSP),%RCX

(338) 0x433953 MOV	%RSI,(%RSP)

(338) 0x433957 MOV	0xc0(%RSP),%R13

(338) 0x43395f ADD	%RAX,%RCX

(338) 0x433962 MOV	%R15,0x168(%RSP)

(338) 0x43396a MOV	0x160(%RSP),%R15

(338) 0x433972 LEA	(%R13,%RCX,8),%RCX

(338) 0x433977 MOV	0xc8(%RSP),%R13

(338) 0x43397f MOV	%RCX,0x98(%RSP)

(338) 0x433987 ADD	%RAX,%R13

(338) 0x43398a MOV	%R13,%RSI

(338) 0x43398d MOV	0xd0(%RSP),%R13

(338) 0x433995 LEA	(%R13,%RSI,8),%RSI

(338) 0x43399a MOV	0xd8(%RSP),%R13

(338) 0x4339a2 MOV	%RSI,0x30(%RSP)

(338) 0x4339a7 ADD	%R13,%RAX

(338) 0x4339aa MOV	0xe0(%RSP),%R13

(338) 0x4339b2 LEA	(%R13,%RAX,8),%RSI

(338) 0x4339b7 MOV	0xa4(%RSP),%EAX

(338) 0x4339be MOV	0x10(%RSP),%R13

(338) 0x4339c3 MOV	%RSI,0x28(%RSP)

(338) 0x4339c8 MOV	(%RSP),%RSI

(338) 0x4339cc SHR	$0x1,%EAX

(338) 0x4339ce SAL	$0x4,%RAX

(338) 0x4339d2 MOV	%RAX,0x90(%RSP)

(338) 0x4339da XOR	%EAX,%EAX

(338) 0x4339dc NOPL	(%RAX)

  (339) 0x4339e0 MOV	0x58(%RSP),%RCX

  (339) 0x4339e5 MOVUPD	(%R11,%RAX,1),%XMM14

  (339) 0x4339eb MOVUPD	(%R8,%RAX,1),%XMM11

  (339) 0x4339f1 MOVUPD	(%RBX,%RAX,1),%XMM12

  (339) 0x4339f7 MOVUPD	(%RCX,%RAX,1),%XMM0

  (339) 0x4339fc MOV	0x60(%RSP),%RCX

  (339) 0x433a01 MOVAPS	%XMM0,(%RSP)

  (339) 0x433a05 MOVUPD	(%RCX,%RAX,1),%XMM0

  (339) 0x433a0a MOV	0x50(%RSP),%RCX

  (339) 0x433a0f MOVAPS	%XMM0,0x10(%RSP)

  (339) 0x433a14 MOVAPD	(%RSP),%XMM0

  (339) 0x433a19 ADDPD	0x10(%RSP),%XMM0

  (339) 0x433a1f MOVUPD	(%RCX,%RAX,1),%XMM1

  (339) 0x433a24 MOV	0x48(%RSP),%RCX

  (339) 0x433a29 ADDPD	%XMM1,%XMM0

  (339) 0x433a2d MOVUPD	(%RCX,%RAX,1),%XMM1

  (339) 0x433a32 MOV	0x68(%RSP),%RCX

  (339) 0x433a37 ADDPD	%XMM1,%XMM0

  (339) 0x433a3b MOVUPD	(%RCX,%RAX,1),%XMM1

  (339) 0x433a40 MOV	0x80(%RSP),%RCX

  (339) 0x433a48 MULPD	%XMM1,%XMM0

  (339) 0x433a4c MOVUPD	(%RCX,%RAX,1),%XMM1

  (339) 0x433a51 MOV	0x88(%RSP),%RCX

  (339) 0x433a59 MOVAPS	%XMM1,(%RSP)

  (339) 0x433a5d MOVUPD	(%RCX,%RAX,1),%XMM1

  (339) 0x433a62 MOV	0x78(%RSP),%RCX

  (339) 0x433a67 MOVAPS	%XMM1,0x10(%RSP)

  (339) 0x433a6c MOVAPD	(%RSP),%XMM1

  (339) 0x433a71 ADDPD	0x10(%RSP),%XMM1

  (339) 0x433a77 MOVUPD	(%RCX,%RAX,1),%XMM13

  (339) 0x433a7d MOV	0x70(%RSP),%RCX

  (339) 0x433a82 MULPD	%XMM2,%XMM0

  (339) 0x433a86 ADDPD	%XMM13,%XMM1

  (339) 0x433a8b MOVUPD	(%RCX,%RAX,1),%XMM15

  (339) 0x433a91 MOVUPD	(%R15,%RAX,1),%XMM13

  (339) 0x433a97 ADDPD	%XMM15,%XMM1

  (339) 0x433a9c MULPD	%XMM3,%XMM0

  (339) 0x433aa0 MOVUPD	(%R9,%RAX,1),%XMM15

  (339) 0x433aa6 MULPD	%XMM13,%XMM1

  (339) 0x433aab MULPD	%XMM2,%XMM1

  (339) 0x433aaf MULPD	%XMM3,%XMM1

  (339) 0x433ab3 SUBPD	%XMM1,%XMM0

  (339) 0x433ab7 MOVUPD	(%R10,%RAX,1),%XMM1

  (339) 0x433abd ADDPD	%XMM14,%XMM1

  (339) 0x433ac2 ADDPD	%XMM15,%XMM1

  (339) 0x433ac7 ADDPD	%XMM11,%XMM1

  (339) 0x433acc MULPD	%XMM12,%XMM1

  (339) 0x433ad1 MULPD	%XMM2,%XMM1

  (339) 0x433ad5 MULPD	%XMM3,%XMM1

  (339) 0x433ad9 ADDPD	%XMM1,%XMM0

  (339) 0x433add MOVUPD	(%R13,%RAX,1),%XMM1

  (339) 0x433ae4 MOV	0x40(%RSP),%RCX

  (339) 0x433ae9 MOVUPD	(%R14,%RAX,1),%XMM13

  (339) 0x433aef MOVUPD	(%R12,%RAX,1),%XMM14

  (339) 0x433af5 MOVUPD	(%RBP,%RAX,1),%XMM15

  (339) 0x433afc MOVUPD	(%RCX,%RAX,1),%XMM9

  (339) 0x433b02 ADDPD	%XMM13,%XMM1

  (339) 0x433b07 MOVUPD	(%RDX,%RAX,1),%XMM11

  (339) 0x433b0d MOVUPD	(%RDI,%RAX,1),%XMM10

  (339) 0x433b13 MOV	0x38(%RSP),%RCX

  (339) 0x433b18 MOVAPS	%XMM9,(%RSP)

  (339) 0x433b1d DIVPD	%XMM11,%XMM10

  (339) 0x433b22 ADDPD	%XMM14,%XMM1

  (339) 0x433b27 MOVUPD	(%RCX,%RAX,1),%XMM8

  (339) 0x433b2d MOV	0x98(%RSP),%RCX

  (339) 0x433b35 ADDPD	%XMM15,%XMM1

  (339) 0x433b3a MULPD	%XMM9,%XMM1

  (339) 0x433b3f MOVUPD	(%RCX,%RAX,1),%XMM9

  (339) 0x433b45 MOV	0x30(%RSP),%RCX

  (339) 0x433b4a MULPD	%XMM2,%XMM1

  (339) 0x433b4e MULPD	%XMM3,%XMM1

  (339) 0x433b52 SUBPD	%XMM1,%XMM0

  (339) 0x433b56 MOVUPD	(%RSI,%RAX,1),%XMM1

  (339) 0x433b5b DIVPD	%XMM11,%XMM1

  (339) 0x433b60 ADDPD	%XMM10,%XMM1

  (339) 0x433b65 MOVAPD	%XMM4,%XMM10

  (339) 0x433b6a DIVPD	%XMM8,%XMM10

  (339) 0x433b6f MULPD	%XMM0,%XMM1

  (339) 0x433b73 ADDPD	%XMM8,%XMM0

  (339) 0x433b78 DIVPD	%XMM0,%XMM8

  (339) 0x433b7d MULPD	%XMM10,%XMM1

  (339) 0x433b82 SUBPD	%XMM1,%XMM9

  (339) 0x433b87 MOVUPS	%XMM9,(%RCX,%RAX,1)

  (339) 0x433b8c MOVUPD	(%RDX,%RAX,1),%XMM0

  (339) 0x433b91 MOV	0x28(%RSP),%RCX

  (339) 0x433b96 MULPD	%XMM0,%XMM8

  (339) 0x433b9b MOVUPS	%XMM8,(%RCX,%RAX,1)

  (339) 0x433ba0 ADD	$0x10,%RAX

  (339) 0x433ba4 CMP	%RAX,0x90(%RSP)

  (339) 0x433bac JNE	4339e0

(338) 0x433bb2 MOV	0xa4(%RSP),%EAX

(338) 0x433bb9 MOV	0x168(%RSP),%R15

(338) 0x433bc1 TEST	$0x1,%AL

(338) 0x433bc3 JE	433e2f

(338) 0x433bc9 AND	$-0x2,%EAX

(338) 0x433bcc ADD	%EAX,0x158(%RSP)

(338) 0x433bd3 MOVSXD	0x158(%RSP),%RAX

(338) 0x433bdb MOV	0x148(%RSP),%R11

(338) 0x433be3 MOV	0x1a8(%RSP),%R9

(338) 0x433beb MOV	0x1a0(%RSP),%RBX

(338) 0x433bf3 LEA	0x1(%RAX),%EDX

(338) 0x433bf6 MOV	0x198(%RSP),%R14

(338) 0x433bfe MOV	0x190(%RSP),%RDI

(338) 0x433c06 MOVSXD	%EDX,%RDX

(338) 0x433c09 MOV	0x140(%RSP),%R8

(338) 0x433c11 MOV	0x1b0(%RSP),%R10

(338) 0x433c19 LEA	(%R11,%RDX,1),%RSI

(338) 0x433c1d LEA	(%R9,%RDX,1),%RCX

(338) 0x433c21 MOV	0x150(%RSP),%RBP

(338) 0x433c29 MOVSD	(%RBX,%RSI,8),%XMM0

(338) 0x433c2e ADDSD	(%RBX,%RCX,8),%XMM0

(338) 0x433c33 LEA	(%R14,%RDX,1),%RCX

(338) 0x433c37 ADDSD	(%RDI,%RCX,8),%XMM0

(338) 0x433c3c LEA	(%R8,%RDX,1),%RCX

(338) 0x433c40 ADDSD	(%RDI,%RCX,8),%XMM0

(338) 0x433c45 LEA	(%R10,%RDX,1),%RCX

(338) 0x433c49 MULSD	(%RBP,%RCX,8),%XMM0

(338) 0x433c4f LEA	(%R11,%RAX,1),%RCX

(338) 0x433c53 LEA	(%R9,%RAX,1),%RSI

(338) 0x433c57 MOV	0x138(%RSP),%R11

(338) 0x433c5f MOVSD	(%RBX,%RCX,8),%XMM1

(338) 0x433c64 LEA	(%R14,%RAX,1),%RCX

(338) 0x433c68 ADDSD	(%RBX,%RSI,8),%XMM1

(338) 0x433c6d ADDSD	(%RDI,%RCX,8),%XMM1

(338) 0x433c72 LEA	(%R8,%RAX,1),%RCX

(338) 0x433c76 MOV	0x128(%RSP),%RSI

(338) 0x433c7e ADDSD	(%RDI,%RCX,8),%XMM1

(338) 0x433c83 LEA	(%R10,%RAX,1),%RCX

(338) 0x433c87 MOV	0x178(%RSP),%RBX

(338) 0x433c8f MULSD	(%RBP,%RCX,8),%XMM1

(338) 0x433c95 LEA	(%RSI,%RDX,1),%RCX

(338) 0x433c99 ADD	%RAX,%RSI

(338) 0x433c9c MOV	0x170(%RSP),%RDI

(338) 0x433ca4 MULSD	%XMM6,%XMM0

(338) 0x433ca8 MULSD	%XMM6,%XMM1

(338) 0x433cac MULSD	%XMM5,%XMM0

(338) 0x433cb0 MULSD	%XMM5,%XMM1

(338) 0x433cb4 SUBSD	%XMM1,%XMM0

(338) 0x433cb8 MOVSD	(%RBX,%RCX,8),%XMM1

(338) 0x433cbd ADDSD	(%RBX,%RSI,8),%XMM1

(338) 0x433cc2 MOV	0x120(%RSP),%RSI

(338) 0x433cca LEA	(%RSI,%RAX,1),%RCX

(338) 0x433cce ADDSD	(%RDI,%RCX,8),%XMM1

(338) 0x433cd3 LEA	(%RSI,%RDX,1),%RCX

(338) 0x433cd7 MOV	0x180(%RSP),%RSI

(338) 0x433cdf ADDSD	(%RDI,%RCX,8),%XMM1

(338) 0x433ce4 MOV	0x130(%RSP),%RCX

(338) 0x433cec ADD	%RAX,%RCX

(338) 0x433cef MULSD	(%R11,%RCX,8),%XMM1

(338) 0x433cf5 LEA	(%RSI,%RDX,1),%RCX

(338) 0x433cf9 ADD	%RAX,%RSI

(338) 0x433cfc MULSD	%XMM6,%XMM1

(338) 0x433d00 MULSD	%XMM5,%XMM1

(338) 0x433d04 ADDSD	%XMM1,%XMM0

(338) 0x433d08 MOVSD	(%RBX,%RCX,8),%XMM1

(338) 0x433d0d ADDSD	(%RBX,%RSI,8),%XMM1

(338) 0x433d12 MOV	0xa8(%RSP),%RBX

(338) 0x433d1a MOV	0xe8(%RSP),%RSI

(338) 0x433d22 LEA	(%RBX,%RAX,1),%RCX

(338) 0x433d26 ADD	%RBX,%RDX

(338) 0x433d29 MOV	0x110(%RSP),%RBX

(338) 0x433d31 ADD	%RAX,%RSI

(338) 0x433d34 ADDSD	(%RDI,%RCX,8),%XMM1

(338) 0x433d39 ADDSD	(%RDI,%RDX,8),%XMM1

(338) 0x433d3e MOV	0x188(%RSP),%RDX

(338) 0x433d46 MOV	0xb8(%RSP),%RCX

(338) 0x433d4e ADD	%RAX,%RDX

(338) 0x433d51 ADD	%RAX,%RCX

(338) 0x433d54 MULSD	(%R11,%RDX,8),%XMM1

(338) 0x433d5a MOV	0x118(%RSP),%RDX

(338) 0x433d62 ADD	%RAX,%RDX

(338) 0x433d65 MOVSD	(%RBX,%RDX,8),%XMM8

(338) 0x433d6b MOV	0xf8(%RSP),%RDX

(338) 0x433d73 MOV	0xf0(%RSP),%RBX

(338) 0x433d7b MULSD	%XMM6,%XMM1

(338) 0x433d7f ADD	%RAX,%RDX

(338) 0x433d82 LEA	(%RBX,%RDX,8),%RDI

(338) 0x433d86 MOV	0xb0(%RSP),%RBX

(338) 0x433d8e MOV	0xc8(%RSP),%RDX

(338) 0x433d96 MOVSD	(%RDI),%XMM10

(338) 0x433d9b ADD	%RAX,%RDX

(338) 0x433d9e MULSD	%XMM5,%XMM1

(338) 0x433da2 SUBSD	%XMM1,%XMM0

(338) 0x433da6 MOVSD	(%RBX,%RSI,8),%XMM1

(338) 0x433dab MOV	0x108(%RSP),%RSI

(338) 0x433db3 MOV	0x100(%RSP),%RBX

(338) 0x433dbb DIVSD	%XMM10,%XMM1

(338) 0x433dc0 ADD	%RAX,%RSI

(338) 0x433dc3 MOVSD	(%RBX,%RSI,8),%XMM9

(338) 0x433dc9 MOV	0xc0(%RSP),%RBX

(338) 0x433dd1 MOV	0xe0(%RSP),%RSI

(338) 0x433dd9 DIVSD	%XMM10,%XMM9

(338) 0x433dde ADDSD	%XMM9,%XMM1

(338) 0x433de3 MOVAPD	%XMM7,%XMM9

(338) 0x433de8 DIVSD	%XMM8,%XMM9

(338) 0x433ded MULSD	%XMM0,%XMM1

(338) 0x433df1 ADDSD	%XMM8,%XMM0

(338) 0x433df6 DIVSD	%XMM0,%XMM8

(338) 0x433dfb MULSD	%XMM9,%XMM1

(338) 0x433e00 MOVSD	(%RBX,%RCX,8),%XMM9

(338) 0x433e06 MOV	0xd0(%RSP),%RBX

(338) 0x433e0e SUBSD	%XMM1,%XMM9

(338) 0x433e13 MOVSD	%XMM9,(%RBX,%RDX,8)

(338) 0x433e19 MOV	0xd8(%RSP),%RBX

(338) 0x433e21 ADD	%RAX,%RBX

(338) 0x433e24 MULSD	(%RDI),%XMM8

(338) 0x433e29 MOVSD	%XMM8,(%RSI,%RBX,8)

(338) 0x433e2f MOV	0x15c(%RSP),%ECX

(338) 0x433e36 ADD	$0x1,%R15

(338) 0x433e3a CMP	%R15D,0x1b8(%RSP)

(338) 0x433e42 JLE	433e70

(338) 0x433e44 MOV	0x1c4(%RSP),%ESI

(338) 0x433e4b MOV	0x1bc(%RSP),%EAX

(338) 0x433e52 MOV	0x1c0(%RSP),%EDX

(338) 0x433e59 MOV	%EAX,0x158(%RSP)

(338) 0x433e60 SUB	%ECX,%ESI

(338) 0x433e62 JMP	433570

0x433e67 NOPW	(%RAX,%RAX,1)

0x433e70 ADD	$0x238,%RSP

0x433e77 POP	%RBX

0x433e78 POP	%RBP

0x433e79 POP	%R12

0x433e7b POP	%R13

0x433e7d POP	%R14

0x433e7f POP	%R15

0x433e81 RET

0x433e82 ADD	$0x1,%ESI

0x433e85 XOR	%EDX,%EDX

0x433e87 JMP	433465

0x433e8c NOPL	(%RAX)

Coverage (%)	Name	Source Location	Module
►96.86+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►3.11+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	PdV(global_variables&, bool)		exec
○	hydro(global_variables&, paral[...]		exec
○	main		exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines
Module	exec

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 13.13 to 2.25 cycles (5.83x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 13.13 to 0.97 cycles (13.53x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
omp_get_thread_num@plt: 1 occurrences►

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 152 bytes. The binary function is storing 124 bytes.

General properties

nb instructions	104
nb uops	105
loop length	441
used x86 registers	13
used mmx registers	0
used xmm registers	6
used ymm registers	0
used zmm registers	0
nb stack references	18

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	13.13 cycles
front end	13.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.50	5.50	5.50	5.50	5.50	5.50	10.50	10.50	10.50	10.50	0.75	0.75	0.75	0.75	0.00	0.00
cycles	5.50	5.50	5.50	5.50	5.50	5.50	10.50	10.50	10.50	10.50	0.75	0.75	0.75	0.75	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	13.13
Dispatch	10.50
DIV/SQRT	12.00
Overall L1	13.13

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	33%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	6%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	15%

Vector efficiency ratios

INT

all	8%
load	6%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	16%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

INT+FP

all	10%
load	10%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 13.13 cycles. At this rate:

4% of peak load performance is reached (11.58 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (9.45 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 4333e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	Latency	Recip. throughput	Vectorization
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB $0x238,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x78(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x70(%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
LEA 0x1(%RAX),%EBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV 0x7c(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
ADD $0x1,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x74(%RDI),%EDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %ESI,0x1bc(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
ADD $0x2,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EAX,0x1b8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
CMP %EAX,%EBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 433e70 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0xa90>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
LEA 0x2(%RDI),%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB %EBP,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CMP %R14D,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 433e70 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0xa90>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R14D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SUB %ESI,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %R15D,0x1c0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
CALL 404660 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404550 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R13D,%EAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
DIV %R12D	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JB 433e82 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0xaa2>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %ESI,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADD %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RSI,%RCX,1),%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %EAX,0x1c4(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
CMP %EAX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JAE 433e70 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0xa90>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV 0x1bc(%RSP),%EDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVSD (%RBX),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
DIVL 0x1c0(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	0	0	0	0	10-17	6	scal (6.3%)
MOVSD 0x11ede(%RIP),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MOVAPD %XMM5,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOVAPD %XMM6,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
UNPCKLPD %XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
UNPCKLPD %XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
ADD %EDX,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R14D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
ADD %EBP,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EDI,0x158(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
SUB %EDI,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV 0x8(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVSXD %EAX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %R9,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RDI,0x1c8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x50(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RDI,0x1d0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x58(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RDI,0x1d8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x10(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RDI,0x1e0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x60(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RDI,0x1e8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x68(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RDI,0x1f0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x18(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RDI,0x1f8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x40(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RDI,0x200(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x20(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RDI,0x208(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x48(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RDI,0x210(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x30(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RDI,0x218(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x38(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x28(%RBX),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RDI,0x220(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %RBX,0x228(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOVSD 0x11ccc(%RIP),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MOVAPD %XMM7,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
UNPCKLPD %XMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0x238,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD $0x1,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
JMP 433465 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x85>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines
Module	exec

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 13.13 to 2.25 cycles (5.83x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
omp_get_thread_num@plt: 1 occurrences►

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 152 bytes. The binary function is storing 124 bytes.

General properties

nb instructions	104
nb uops	105
loop length	441
used x86 registers	13
used mmx registers	0
used xmm registers	6
used ymm registers	0
used zmm registers	0
nb stack references	18

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	13.13 cycles
front end	13.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.50	5.50	5.50	5.50	5.50	5.50	10.50	10.50	10.50	10.50	0.75	0.75	0.75	0.75	0.00	0.00
cycles	5.50	5.50	5.50	5.50	5.50	5.50	10.50	10.50	10.50	10.50	0.75	0.75	0.75	0.75	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	13.13
Dispatch	10.50
DIV/SQRT	12.00
Overall L1	13.13

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	33%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	6%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	15%

Vector efficiency ratios

INT

all	8%
load	6%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	16%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

INT+FP

all	10%
load	10%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 13.13 cycles. At this rate:

4% of peak load performance is reached (11.58 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (9.45 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 4333e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	Latency	Recip. throughput	Vectorization
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB $0x238,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x78(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x70(%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
LEA 0x1(%RAX),%EBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV 0x7c(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
ADD $0x1,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x74(%RDI),%EDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %ESI,0x1bc(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
ADD $0x2,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EAX,0x1b8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
CMP %EAX,%EBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 433e70 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0xa90>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
LEA 0x2(%RDI),%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB %EBP,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CMP %R14D,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 433e70 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0xa90>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R14D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SUB %ESI,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %R15D,0x1c0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
CALL 404660 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404550 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R13D,%EAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
DIV %R12D	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JB 433e82 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0xaa2>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %ESI,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADD %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RSI,%RCX,1),%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %EAX,0x1c4(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
CMP %EAX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JAE 433e70 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0xa90>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV 0x1bc(%RSP),%EDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVSD (%RBX),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
DIVL 0x1c0(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	0	0	0	0	10-17	6	scal (6.3%)
MOVSD 0x11ede(%RIP),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MOVAPD %XMM5,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOVAPD %XMM6,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
UNPCKLPD %XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
UNPCKLPD %XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
ADD %EDX,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R14D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
ADD %EBP,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EDI,0x158(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
SUB %EDI,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV 0x8(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVSXD %EAX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %R9,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RDI,0x1c8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x50(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RDI,0x1d0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x58(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RDI,0x1d8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x10(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RDI,0x1e0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x60(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RDI,0x1e8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x68(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RDI,0x1f0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x18(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RDI,0x1f8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x40(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RDI,0x200(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x20(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RDI,0x208(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x48(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RDI,0x210(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x30(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RDI,0x218(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x38(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x28(%RBX),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RDI,0x220(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %RBX,0x228(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOVSD 0x11ccc(%RIP),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MOVAPD %XMM7,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
UNPCKLPD %XMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0x238,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD $0x1,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
JMP 433465 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x85>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	6.36	2.44
▼Loop 338 - - exec–	0.00	0.01
○Loop 339 - - exec	6.36	2.43

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Matching between your function (in the source code) and the binary function

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Code clean check

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Vectorization

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Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code