OV - exec - Function PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D<double>&, clover::Buffer2D<d ...	Module: exec	Source: :0-0	Coverage (incl. loops): 5.39% \| (excl. loops): 0.00%

  ***  This Panel is Intentionally Left Blank.  ***

It is due to a lack of debug symbols in the given object
(loop or function).

0x432af0 PUSH	%R15

0x432af2 PUSH	%R14

0x432af4 PUSH	%R13

0x432af6 PUSH	%R12

0x432af8 PUSH	%RBP

0x432af9 PUSH	%RBX

0x432afa MOV	%RDI,%RBX

0x432afd SUB	$0x1a8,%RSP

0x432b04 MOV	0x68(%RDI),%EAX

0x432b07 LEA	0x1(%RAX),%EBP

0x432b0a MOV	0x6c(%RDI),%EAX

0x432b0d MOV	0x60(%RDI),%EDI

0x432b10 ADD	$0x2,%EAX

0x432b13 LEA	0x1(%RDI),%ESI

0x432b16 MOV	0x64(%RBX),%EDI

0x432b19 MOV	%EAX,0x138(%RSP)

0x432b20 MOV	%ESI,0x13c(%RSP)

0x432b27 CMP	%EAX,%EBP

0x432b29 JGE	4333b8

0x432b2f MOV	%EAX,%R13D

0x432b32 LEA	0x2(%RDI),%R14D

0x432b36 SUB	%EBP,%R13D

0x432b39 CMP	%R14D,%ESI

0x432b3c JGE	4333b8

0x432b42 MOV	%R14D,%R15D

0x432b45 SUB	%ESI,%R15D

0x432b48 MOV	%R15D,0x140(%RSP)

0x432b50 CALL	404660 <omp_get_num_threads@plt>

0x432b55 MOV	%EAX,%R12D

0x432b58 CALL	404550 <omp_get_thread_num@plt>

0x432b5d XOR	%EDX,%EDX

0x432b5f MOV	%EAX,%ECX

0x432b61 MOV	%R15D,%EAX

0x432b64 IMUL	%R13D,%EAX

0x432b68 DIV	%R12D

0x432b6b MOV	%EAX,%ESI

0x432b6d CMP	%EDX,%ECX

0x432b6f JB	4333ca

0x432b75 IMUL	%ESI,%ECX

0x432b78 ADD	%EDX,%ECX

0x432b7a LEA	(%RSI,%RCX,1),%EAX

0x432b7d MOV	%EAX,0x144(%RSP)

0x432b84 CMP	%EAX,%ECX

0x432b86 JAE	4333b8

0x432b8c MOV	%ECX,%EAX

0x432b8e XOR	%EDX,%EDX

0x432b90 MOV	0x13c(%RSP),%EDI

0x432b97 MOVSD	(%RBX),%XMM5

0x432b9b DIVL	0x140(%RSP)

0x432ba2 MOVSD	0x127cd(%RIP),%XMM14

0x432bab MOVSD	0x11dd4(%RIP),%XMM13

0x432bb4 MOVSD	0x12673(%RIP),%XMM12

0x432bbd MOVAPD	%XMM5,%XMM3

0x432bc1 MOVAPD	%XMM14,%XMM2

0x432bc6 MOVAPD	%XMM13,%XMM1

0x432bcb UNPCKLPD	%XMM3,%XMM3

0x432bcf UNPCKLPD	%XMM2,%XMM2

0x432bd3 UNPCKLPD	%XMM1,%XMM1

0x432bd7 UNPCKLPD	%XMM12,%XMM12

0x432bdc ADD	%EDX,%EDI

0x432bde MOV	%R14D,%EDX

0x432be1 ADD	%EBP,%EAX

0x432be3 MOV	%EDI,0xe0(%RSP)

0x432bea SUB	%EDI,%EDX

0x432bec MOV	0x8(%RBX),%RDI

0x432bf0 CLTQ

0x432bf2 MOV	%RAX,0x50(%RSP)

0x432bf7 MOV	%RDI,0x148(%RSP)

0x432bff MOV	0x50(%RBX),%RDI

0x432c03 MOV	%RDI,0x150(%RSP)

0x432c0b MOV	0x10(%RBX),%RDI

0x432c0f MOV	%RDI,0x158(%RSP)

0x432c17 MOV	0x58(%RBX),%RDI

0x432c1b MOV	%RDI,0x160(%RSP)

0x432c23 MOV	0x18(%RBX),%RDI

0x432c27 MOV	%RDI,0x168(%RSP)

0x432c2f MOV	0x40(%RBX),%RDI

0x432c33 MOV	%RDI,0x170(%RSP)

0x432c3b MOV	0x20(%RBX),%RDI

0x432c3f MOV	%RDI,0x178(%RSP)

0x432c47 MOV	0x48(%RBX),%RDI

0x432c4b MOV	%RDI,0x180(%RSP)

0x432c53 MOV	0x30(%RBX),%RDI

0x432c57 MOV	%RDI,0x188(%RSP)

0x432c5f MOV	0x38(%RBX),%RDI

0x432c63 MOV	0x28(%RBX),%RBX

0x432c67 MOV	%RDI,0x190(%RSP)

0x432c6f MOV	%RBX,0x198(%RSP)

0x432c77 NOPW	(%RAX,%RAX,1)

(336) 0x432c80 CMP	%EDX,%ESI

(336) 0x432c82 CMOVBE	%ESI,%EDX

(336) 0x432c85 LEA	(%RCX,%RDX,1),%EAX

(336) 0x432c88 MOV	%EDX,0x5c(%RSP)

(336) 0x432c8c MOV	%EAX,0xe4(%RSP)

(336) 0x432c93 CMP	%EAX,%ECX

(336) 0x432c95 JAE	43337d

(336) 0x432c9b MOV	0x148(%RSP),%RAX

(336) 0x432ca3 MOV	0x50(%RSP),%RDI

(336) 0x432ca8 MOV	0x158(%RSP),%RBX

(336) 0x432cb0 MOV	0x10(%RAX),%RBP

(336) 0x432cb4 MOV	(%RAX),%RSI

(336) 0x432cb7 MOV	%RDI,%RCX

(336) 0x432cba MOV	%RDI,%R8

(336) 0x432cbd MOV	0x150(%RSP),%RAX

(336) 0x432cc5 MOV	(%RBX),%RDX

(336) 0x432cc8 IMUL	%RDI,%RSI

(336) 0x432ccc MOV	%RBP,0x128(%RSP)

(336) 0x432cd4 MOV	0x10(%RAX),%R14

(336) 0x432cd8 MOV	(%RAX),%RAX

(336) 0x432cdb IMUL	%RDX,%R8

(336) 0x432cdf IMUL	%RAX,%RCX

(336) 0x432ce3 MOV	%RSI,0x130(%RSP)

(336) 0x432ceb ADD	%R8,%RDX

(336) 0x432cee MOV	%R14,0x118(%RSP)

(336) 0x432cf6 MOV	%RDX,0xc0(%RSP)

(336) 0x432cfe MOV	0x168(%RSP),%RDX

(336) 0x432d06 ADD	%RCX,%RAX

(336) 0x432d09 MOV	%RCX,0x120(%RSP)

(336) 0x432d11 MOV	%RAX,0xd8(%RSP)

(336) 0x432d19 MOV	0x10(%RBX),%RAX

(336) 0x432d1d MOV	0x160(%RSP),%RBX

(336) 0x432d25 MOV	0x10(%RDX),%R10

(336) 0x432d29 MOV	%R8,0x110(%RSP)

(336) 0x432d31 MOV	%RAX,0xd0(%RSP)

(336) 0x432d39 MOV	0x10(%RBX),%RAX

(336) 0x432d3d MOV	%R10,0xa8(%RSP)

(336) 0x432d45 MOV	%RAX,0xc8(%RSP)

(336) 0x432d4d MOV	(%RBX),%RAX

(336) 0x432d50 MOV	%RDI,%RBX

(336) 0x432d53 IMUL	%RAX,%RBX

(336) 0x432d57 LEA	(%RAX,%RBX,1),%R9

(336) 0x432d5b MOV	%RDI,%RAX

(336) 0x432d5e MOV	%RBX,0x108(%RSP)

(336) 0x432d66 IMUL	(%RDX),%RDI

(336) 0x432d6a MOV	0x170(%RSP),%RDX

(336) 0x432d72 MOV	%R9,0xb8(%RSP)

(336) 0x432d7a MOV	0x10(%RDX),%R11

(336) 0x432d7e MOV	%RDI,0xb0(%RSP)

(336) 0x432d86 MOV	%R11,0xa0(%RSP)

(336) 0x432d8e MOV	(%RDX),%RDX

(336) 0x432d91 MOV	0x188(%RSP),%R10

(336) 0x432d99 MOV	0x190(%RSP),%R11

(336) 0x432da1 IMUL	%RAX,%RDX

(336) 0x432da5 MOV	0x10(%R11),%R12

(336) 0x432da9 MOV	(%R11),%R11

(336) 0x432dac MOV	%RDX,0x100(%RSP)

(336) 0x432db4 MOV	%RDX,%RDI

(336) 0x432db7 MOV	0x178(%RSP),%RDX

(336) 0x432dbf IMUL	%RAX,%R11

(336) 0x432dc3 MOV	%R12,0x70(%RSP)

(336) 0x432dc8 MOV	0x10(%RDX),%R15

(336) 0x432dcc MOV	(%RDX),%RDX

(336) 0x432dcf MOV	%R11,0xf8(%RSP)

(336) 0x432dd7 MOV	%R15,0x90(%RSP)

(336) 0x432ddf MOV	0x180(%RSP),%R15

(336) 0x432de7 IMUL	%RAX,%RDX

(336) 0x432deb MOV	(%R15),%R9

(336) 0x432dee MOV	0x10(%R15),%R13

(336) 0x432df2 MOV	0x198(%RSP),%R15

(336) 0x432dfa MOV	%RDX,0x98(%RSP)

(336) 0x432e02 IMUL	%RAX,%R9

(336) 0x432e06 MOV	%R13,0x60(%RSP)

(336) 0x432e0b MOV	0x10(%R15),%R13

(336) 0x432e0f MOV	(%R15),%R15

(336) 0x432e12 MOV	%R9,0x88(%RSP)

(336) 0x432e1a MOV	0x10(%R10),%R9

(336) 0x432e1e IMUL	%RAX,%R15

(336) 0x432e22 MOV	(%R10),%R10

(336) 0x432e25 MOV	%R13,0x80(%RSP)

(336) 0x432e2d MOV	%R9,0xf0(%RSP)

(336) 0x432e35 IMUL	%RAX,%R10

(336) 0x432e39 CMPL	$0x1,0x5c(%RSP)

(336) 0x432e3e MOV	%R15,0x78(%RSP)

(336) 0x432e43 MOV	%R10,0x68(%RSP)

(336) 0x432e48 MOV	%R11,%R10

(336) 0x432e4b JE	433142

(336) 0x432e51 MOVSXD	0xe0(%RSP),%RDX

(336) 0x432e59 MOV	%RBP,%R12

(336) 0x432e5c ADD	%RDX,%RSI

(336) 0x432e5f ADD	%RDX,%RCX

(336) 0x432e62 SAL	$0x3,%RSI

(336) 0x432e66 SAL	$0x3,%RCX

(336) 0x432e6a LEA	(%RBP,%RSI,1),%RBP

(336) 0x432e6f LEA	0x8(%R12,%RSI,1),%R13

(336) 0x432e74 MOV	0xd0(%RSP),%RSI

(336) 0x432e7c MOV	%RBP,0x38(%RSP)

(336) 0x432e81 LEA	(%R14,%RCX,1),%RBP

(336) 0x432e85 MOV	%RBP,0x30(%RSP)

(336) 0x432e8a MOV	0xd8(%RSP),%RBP

(336) 0x432e92 LEA	(%RBP,%RDX,1),%RAX

(336) 0x432e97 MOV	%R14,%RBP

(336) 0x432e9a SAL	$0x3,%RAX

(336) 0x432e9e LEA	0x8(%RBP,%RCX,1),%R12

(336) 0x432ea3 MOV	0xc0(%RSP),%RCX

(336) 0x432eab LEA	0x8(%RBP,%RAX,1),%R15

(336) 0x432eb0 LEA	(%R14,%RAX,1),%R14

(336) 0x432eb4 LEA	(%R8,%RDX,1),%RAX

(336) 0x432eb8 MOV	0xc8(%RSP),%R8

(336) 0x432ec0 LEA	(%RSI,%RAX,8),%RBP

(336) 0x432ec4 LEA	(%RBX,%RDX,1),%RAX

(336) 0x432ec8 SAL	$0x3,%RAX

(336) 0x432ecc LEA	(%R8,%RAX,1),%RBX

(336) 0x432ed0 LEA	0x8(%R8,%RAX,1),%R11

(336) 0x432ed5 LEA	(%RCX,%RDX,1),%RAX

(336) 0x432ed9 LEA	(%RSI,%RAX,8),%RSI

(336) 0x432edd MOV	%RSI,0xe8(%RSP)

(336) 0x432ee5 MOV	0xb8(%RSP),%RSI

(336) 0x432eed LEA	(%RSI,%RDX,1),%RAX

(336) 0x432ef1 SAL	$0x3,%RAX

(336) 0x432ef5 LEA	(%R8,%RAX,1),%RSI

(336) 0x432ef9 LEA	0x8(%R8,%RAX,1),%R8

(336) 0x432efe MOV	%RSI,(%RSP)

(336) 0x432f02 MOV	0xb0(%RSP),%RSI

(336) 0x432f0a LEA	(%RSI,%RDX,1),%RAX

(336) 0x432f0e MOV	0xa8(%RSP),%RSI

(336) 0x432f16 LEA	(%RSI,%RAX,8),%RCX

(336) 0x432f1a LEA	(%RDI,%RDX,1),%RAX

(336) 0x432f1e MOV	0x98(%RSP),%RSI

(336) 0x432f26 MOV	0xa0(%RSP),%RDI

(336) 0x432f2e MOV	%RCX,0x28(%RSP)

(336) 0x432f33 LEA	(%RDI,%RAX,8),%RDI

(336) 0x432f37 LEA	(%RSI,%RDX,1),%RAX

(336) 0x432f3b MOV	0x90(%RSP),%RSI

(336) 0x432f43 LEA	(%RSI,%RAX,8),%RAX

(336) 0x432f47 MOV	0x88(%RSP),%RSI

(336) 0x432f4f LEA	(%RSI,%RDX,1),%RCX

(336) 0x432f53 MOV	0x60(%RSP),%RSI

(336) 0x432f58 LEA	(%RSI,%RCX,8),%RSI

(336) 0x432f5c MOV	0x68(%RSP),%RCX

(336) 0x432f61 ADD	%RDX,%RCX

(336) 0x432f64 LEA	(%R9,%RCX,8),%RCX

(336) 0x432f68 MOV	%R10,%R9

(336) 0x432f6b ADD	%RDX,%R9

(336) 0x432f6e MOV	%RCX,0x48(%RSP)

(336) 0x432f73 MOV	%R9,%R10

(336) 0x432f76 MOV	0x70(%RSP),%R9

(336) 0x432f7b LEA	(%R9,%R10,8),%R10

(336) 0x432f7f MOV	0x78(%RSP),%R9

(336) 0x432f84 MOV	%R10,0x20(%RSP)

(336) 0x432f89 ADD	%R9,%RDX

(336) 0x432f8c MOV	0x80(%RSP),%R9

(336) 0x432f94 LEA	(%R9,%RDX,8),%R10

(336) 0x432f98 MOV	0x5c(%RSP),%EDX

(336) 0x432f9c MOV	(%RSP),%R9

(336) 0x432fa0 MOV	%R10,0x18(%RSP)

(336) 0x432fa5 MOV	0xe8(%RSP),%R10

(336) 0x432fad SHR	$0x1,%EDX

(336) 0x432faf SAL	$0x4,%RDX

(336) 0x432fb3 MOV	%RDX,0x40(%RSP)

(336) 0x432fb8 XOR	%EDX,%EDX

(336) 0x432fba NOPW	(%RAX,%RAX,1)

  (337) 0x432fc0 MOVUPD	(%R15,%RDX,1),%XMM4

  (337) 0x432fc6 MOVUPD	(%R12,%RDX,1),%XMM15

  (337) 0x432fcc MOV	0x30(%RSP),%RCX

  (337) 0x432fd1 MOVUPD	(%R14,%RDX,1),%XMM10

  (337) 0x432fd7 MOVAPD	%XMM4,%XMM0

  (337) 0x432fdb MOVUPD	(%R8,%RDX,1),%XMM8

  (337) 0x432fe1 MOVUPD	(%RBX,%RDX,1),%XMM7

  (337) 0x432fe6 ADDPD	%XMM15,%XMM0

  (337) 0x432feb MOVUPD	(%RCX,%RDX,1),%XMM11

  (337) 0x432ff1 MOV	0x38(%RSP),%RCX

  (337) 0x432ff6 MOVUPD	(%R9,%RDX,1),%XMM9

  (337) 0x432ffc MOVUPD	(%R11,%RDX,1),%XMM6

  (337) 0x433002 ADDPD	%XMM15,%XMM0

  (337) 0x433007 MOVUPD	(%R10,%RDX,1),%XMM15

  (337) 0x43300d ADDPD	%XMM4,%XMM0

  (337) 0x433011 MOVUPD	(%R13,%RDX,1),%XMM4

  (337) 0x433018 MULPD	%XMM4,%XMM0

  (337) 0x43301c MOVAPD	%XMM10,%XMM4

  (337) 0x433021 ADDPD	%XMM11,%XMM4

  (337) 0x433026 ADDPD	%XMM11,%XMM4

  (337) 0x43302b MULPD	%XMM2,%XMM0

  (337) 0x43302f ADDPD	%XMM10,%XMM4

  (337) 0x433034 MOVUPD	(%RCX,%RDX,1),%XMM10

  (337) 0x43303a MOV	0x28(%RSP),%RCX

  (337) 0x43303f MOVAPS	%XMM10,(%RSP)

  (337) 0x433044 MULPD	%XMM10,%XMM4

  (337) 0x433049 MULPD	%XMM3,%XMM0

  (337) 0x43304d MULPD	%XMM2,%XMM4

  (337) 0x433051 MULPD	%XMM1,%XMM0

  (337) 0x433055 MULPD	%XMM3,%XMM4

  (337) 0x433059 MULPD	%XMM1,%XMM4

  (337) 0x43305d SUBPD	%XMM4,%XMM0

  (337) 0x433061 MOVAPD	%XMM8,%XMM4

  (337) 0x433066 ADDPD	%XMM9,%XMM4

  (337) 0x43306b ADDPD	%XMM9,%XMM4

  (337) 0x433070 MOVUPD	(%RAX,%RDX,1),%XMM9

  (337) 0x433076 ADDPD	%XMM8,%XMM4

  (337) 0x43307b MOVUPD	(%RDI,%RDX,1),%XMM8

  (337) 0x433081 DIVPD	%XMM9,%XMM8

  (337) 0x433086 MULPD	%XMM15,%XMM4

  (337) 0x43308b MULPD	%XMM2,%XMM4

  (337) 0x43308f MULPD	%XMM3,%XMM4

  (337) 0x433093 MULPD	%XMM1,%XMM4

  (337) 0x433097 ADDPD	%XMM4,%XMM0

  (337) 0x43309b MOVAPD	%XMM6,%XMM4

  (337) 0x43309f ADDPD	%XMM7,%XMM4

  (337) 0x4330a3 ADDPD	%XMM7,%XMM4

  (337) 0x4330a7 MOVUPD	(%RBP,%RDX,1),%XMM7

  (337) 0x4330ad ADDPD	%XMM6,%XMM4

  (337) 0x4330b1 MOVUPD	(%RCX,%RDX,1),%XMM6

  (337) 0x4330b6 MOV	0x48(%RSP),%RCX

  (337) 0x4330bb MULPD	%XMM7,%XMM4

  (337) 0x4330bf MOVUPD	(%RCX,%RDX,1),%XMM7

  (337) 0x4330c4 MOV	0x20(%RSP),%RCX

  (337) 0x4330c9 MULPD	%XMM2,%XMM4

  (337) 0x4330cd MULPD	%XMM3,%XMM4

  (337) 0x4330d1 MULPD	%XMM1,%XMM4

  (337) 0x4330d5 SUBPD	%XMM4,%XMM0

  (337) 0x4330d9 MOVUPD	(%RSI,%RDX,1),%XMM4

  (337) 0x4330de DIVPD	%XMM9,%XMM4

  (337) 0x4330e3 ADDPD	%XMM8,%XMM4

  (337) 0x4330e8 MOVAPD	%XMM12,%XMM8

  (337) 0x4330ed DIVPD	%XMM6,%XMM8

  (337) 0x4330f2 MULPD	%XMM0,%XMM4

  (337) 0x4330f6 ADDPD	%XMM6,%XMM0

  (337) 0x4330fa DIVPD	%XMM0,%XMM6

  (337) 0x4330fe MULPD	%XMM8,%XMM4

  (337) 0x433103 SUBPD	%XMM4,%XMM7

  (337) 0x433107 MOVUPS	%XMM7,(%RCX,%RDX,1)

  (337) 0x43310b MOVUPD	(%RAX,%RDX,1),%XMM7

  (337) 0x433110 MOV	0x18(%RSP),%RCX

  (337) 0x433115 MULPD	%XMM7,%XMM6

  (337) 0x433119 MOVUPS	%XMM6,(%RCX,%RDX,1)

  (337) 0x43311d ADD	$0x10,%RDX

  (337) 0x433121 CMP	%RDX,0x40(%RSP)

  (337) 0x433126 JNE	432fc0

(336) 0x43312c MOV	0x5c(%RSP),%EAX

(336) 0x433130 TEST	$0x1,%AL

(336) 0x433132 JE	433376

(336) 0x433138 AND	$-0x2,%EAX

(336) 0x43313b ADD	%EAX,0xe0(%RSP)

(336) 0x433142 MOVSXD	0xe0(%RSP),%RAX

(336) 0x43314a MOV	0x120(%RSP),%RSI

(336) 0x433152 MOV	0x118(%RSP),%RBX

(336) 0x43315a MOV	0xd8(%RSP),%R14

(336) 0x433162 LEA	(%RSI,%RAX,1),%RDX

(336) 0x433166 MOV	0xc8(%RSP),%RDI

(336) 0x43316e MOVSD	(%RBX,%RDX,8),%XMM11

(336) 0x433174 LEA	(%R14,%RAX,1),%RDX

(336) 0x433178 MOVSD	(%RBX,%RDX,8),%XMM10

(336) 0x43317e LEA	0x1(%RAX),%EDX

(336) 0x433181 MOVSXD	%EDX,%RDX

(336) 0x433184 LEA	(%RSI,%RDX,1),%RCX

(336) 0x433188 MOV	0xb8(%RSP),%RSI

(336) 0x433190 MOVSD	(%RBX,%RCX,8),%XMM0

(336) 0x433195 LEA	(%R14,%RDX,1),%RCX

(336) 0x433199 MOVSD	(%RBX,%RCX,8),%XMM15

(336) 0x43319f MOV	0x108(%RSP),%RBX

(336) 0x4331a7 MOVAPD	%XMM15,%XMM4

(336) 0x4331ac LEA	(%RBX,%RAX,1),%RCX

(336) 0x4331b0 ADDSD	%XMM0,%XMM4

(336) 0x4331b4 MOVSD	(%RDI,%RCX,8),%XMM7

(336) 0x4331b9 LEA	(%RBX,%RDX,1),%RCX

(336) 0x4331bd MOV	0x128(%RSP),%RBX

(336) 0x4331c5 MOVSD	(%RDI,%RCX,8),%XMM6

(336) 0x4331ca LEA	(%RSI,%RAX,1),%RCX

(336) 0x4331ce MOVSD	(%RDI,%RCX,8),%XMM9

(336) 0x4331d4 LEA	(%RSI,%RDX,1),%RCX

(336) 0x4331d8 MOV	0x90(%RSP),%RSI

(336) 0x4331e0 ADDSD	%XMM4,%XMM0

(336) 0x4331e4 MOVAPD	%XMM10,%XMM4

(336) 0x4331e9 MOVSD	(%RDI,%RCX,8),%XMM8

(336) 0x4331ef MOV	0x130(%RSP),%RDI

(336) 0x4331f7 ADDSD	%XMM11,%XMM4

(336) 0x4331fc MOV	0xf8(%RSP),%RCX

(336) 0x433204 ADD	%RDI,%RDX

(336) 0x433207 ADDSD	%XMM15,%XMM0

(336) 0x43320c MULSD	(%RBX,%RDX,8),%XMM0

(336) 0x433211 LEA	(%RDI,%RAX,1),%RDX

(336) 0x433215 ADD	%RAX,%RCX

(336) 0x433218 ADDSD	%XMM11,%XMM4

(336) 0x43321d MOV	0xd0(%RSP),%RDI

(336) 0x433225 ADDSD	%XMM10,%XMM4

(336) 0x43322a MULSD	(%RBX,%RDX,8),%XMM4

(336) 0x43322f MOV	0xc0(%RSP),%RDX

(336) 0x433237 MULSD	%XMM14,%XMM0

(336) 0x43323c MOV	0xa8(%RSP),%RBX

(336) 0x433244 ADD	%RAX,%RDX

(336) 0x433247 MULSD	%XMM14,%XMM4

(336) 0x43324c MULSD	%XMM5,%XMM0

(336) 0x433250 MULSD	%XMM5,%XMM4

(336) 0x433254 MULSD	%XMM13,%XMM0

(336) 0x433259 MULSD	%XMM13,%XMM4

(336) 0x43325e SUBSD	%XMM4,%XMM0

(336) 0x433262 MOVAPD	%XMM8,%XMM4

(336) 0x433267 ADDSD	%XMM9,%XMM4

(336) 0x43326c ADDSD	%XMM9,%XMM4

(336) 0x433271 ADDSD	%XMM8,%XMM4

(336) 0x433276 MULSD	(%RDI,%RDX,8),%XMM4

(336) 0x43327b MOV	0x110(%RSP),%RDX

(336) 0x433283 ADD	%RAX,%RDX

(336) 0x433286 MULSD	%XMM14,%XMM4

(336) 0x43328b MULSD	%XMM5,%XMM4

(336) 0x43328f MULSD	%XMM13,%XMM4

(336) 0x433294 ADDSD	%XMM4,%XMM0

(336) 0x433298 MOVAPD	%XMM6,%XMM4

(336) 0x43329c ADDSD	%XMM7,%XMM4

(336) 0x4332a0 ADDSD	%XMM7,%XMM4

(336) 0x4332a4 ADDSD	%XMM6,%XMM4

(336) 0x4332a8 MULSD	(%RDI,%RDX,8),%XMM4

(336) 0x4332ad MOV	0xb0(%RSP),%RDX

(336) 0x4332b5 ADD	%RAX,%RDX

(336) 0x4332b8 MOVSD	(%RBX,%RDX,8),%XMM6

(336) 0x4332bd MOV	0x98(%RSP),%RDX

(336) 0x4332c5 MULSD	%XMM14,%XMM4

(336) 0x4332ca ADD	%RAX,%RDX

(336) 0x4332cd LEA	(%RSI,%RDX,8),%RDX

(336) 0x4332d1 MOV	0x68(%RSP),%RSI

(336) 0x4332d6 MOVSD	(%RDX),%XMM8

(336) 0x4332db MOV	0x88(%RSP),%RDI

(336) 0x4332e3 MOV	0x60(%RSP),%RBX

(336) 0x4332e8 ADD	%RAX,%RSI

(336) 0x4332eb ADD	%RAX,%RDI

(336) 0x4332ee MULSD	%XMM5,%XMM4

(336) 0x4332f2 MULSD	%XMM13,%XMM4

(336) 0x4332f7 SUBSD	%XMM4,%XMM0

(336) 0x4332fb MOVSD	(%RBX,%RDI,8),%XMM4

(336) 0x433300 MOV	0x100(%RSP),%RDI

(336) 0x433308 MOV	0xa0(%RSP),%RBX

(336) 0x433310 DIVSD	%XMM8,%XMM4

(336) 0x433315 ADD	%RAX,%RDI

(336) 0x433318 MOVSD	(%RBX,%RDI,8),%XMM7

(336) 0x43331d MOV	0xf0(%RSP),%RBX

(336) 0x433325 DIVSD	%XMM8,%XMM7

(336) 0x43332a ADDSD	%XMM7,%XMM4

(336) 0x43332e MOVSD	0x11efa(%RIP),%XMM7

(336) 0x433336 DIVSD	%XMM6,%XMM7

(336) 0x43333a MULSD	%XMM0,%XMM4

(336) 0x43333e ADDSD	%XMM6,%XMM0

(336) 0x433342 DIVSD	%XMM0,%XMM6

(336) 0x433346 MULSD	%XMM7,%XMM4

(336) 0x43334a MOVSD	(%RBX,%RSI,8),%XMM7

(336) 0x43334f MOV	0x70(%RSP),%RSI

(336) 0x433354 MOV	0x78(%RSP),%RBX

(336) 0x433359 ADD	%RAX,%RBX

(336) 0x43335c SUBSD	%XMM4,%XMM7

(336) 0x433360 MOVSD	%XMM7,(%RSI,%RCX,8)

(336) 0x433365 MOV	0x80(%RSP),%RSI

(336) 0x43336d MULSD	(%RDX),%XMM6

(336) 0x433371 MOVSD	%XMM6,(%RSI,%RBX,8)

(336) 0x433376 MOV	0xe4(%RSP),%ECX

(336) 0x43337d ADDQ	$0x1,0x50(%RSP)

(336) 0x433383 MOV	0x50(%RSP),%RAX

(336) 0x433388 CMP	%EAX,0x138(%RSP)

(336) 0x43338f JLE	4333b8

(336) 0x433391 MOV	0x144(%RSP),%ESI

(336) 0x433398 MOV	0x13c(%RSP),%EAX

(336) 0x43339f MOV	0x140(%RSP),%EDX

(336) 0x4333a6 MOV	%EAX,0xe0(%RSP)

(336) 0x4333ad SUB	%ECX,%ESI

(336) 0x4333af JMP	432c80

0x4333b4 NOPL	(%RAX)

0x4333b8 ADD	$0x1a8,%RSP

0x4333bf POP	%RBX

0x4333c0 POP	%RBP

0x4333c1 POP	%R12

0x4333c3 POP	%R13

0x4333c5 POP	%R14

0x4333c7 POP	%R15

0x4333c9 RET

0x4333ca ADD	$0x1,%ESI

0x4333cd XOR	%EDX,%EDX

0x4333cf JMP	432b75

0x4333d4 NOPW	%CS:(%RAX,%RAX,1)

0x4333df NOP

Coverage (%)	Name	Source Location	Module
►96.76+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►3.11+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	PdV(global_variables&, bool)		exec
○	hydro(global_variables&, paral[...]		exec
○	main		exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines
Module	exec

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.75 to 2.25 cycles (5.67x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 12.75 to 0.96 cycles (13.29x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
omp_get_thread_num@plt: 1 occurrences►

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►

Conversion instructions

Detected expensive conversion instructions.

Details

CLTQ: 1 occurrences►

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 144 bytes. The binary function is storing 116 bytes.

General properties

nb instructions	103
nb uops	102
loop length	444
used x86 registers	12
used mmx registers	0
used xmm registers	7
used ymm registers	0
used zmm registers	0
nb stack references	17

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.75 cycles
front end	12.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.33	5.33	5.33	5.33	5.33	5.33	10.00	10.00	10.00	10.00	1.00	1.00	1.00	1.00	0.00	0.00
cycles	5.33	5.33	5.33	5.33	5.33	5.33	10.00	10.00	10.00	10.00	1.00	1.00	1.00	1.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	12.75
Dispatch	10.00
DIV/SQRT	12.00
Overall L1	12.75

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	27%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	42%

INT+FP

all	6%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	15%

Vector efficiency ratios

INT

all	8%
load	6%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	15%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	17%

INT+FP

all	10%
load	11%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.75 cycles. At this rate:

4% of peak load performance is reached (11.29 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (9.10 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 432af0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB $0x1a8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x68(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA 0x1(%RAX),%EBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV 0x6c(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x60(%RDI),%EDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
ADD $0x2,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x1(%RDI),%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV 0x64(%RBX),%EDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %EAX,0x138(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV %ESI,0x13c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
CMP %EAX,%EBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 4333b8 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x8c8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
LEA 0x2(%RDI),%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB %EBP,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CMP %R14D,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 4333b8 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x8c8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R14D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SUB %ESI,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %R15D,0x140(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
CALL 404660 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404550 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R13D,%EAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
DIV %R12D	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JB 4333ca <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x8da>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %ESI,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADD %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RSI,%RCX,1),%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %EAX,0x144(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
CMP %EAX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JAE 4333b8 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x8c8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV 0x13c(%RSP),%EDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOVSD (%RBX),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
DIVL 0x140(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOVSD 0x127cd(%RIP),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVSD 0x11dd4(%RIP),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVSD 0x12673(%RIP),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVAPD %XMM5,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOVAPD %XMM14,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOVAPD %XMM13,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
UNPCKLPD %XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
UNPCKLPD %XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
UNPCKLPD %XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
UNPCKLPD %XMM12,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
ADD %EDX,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R14D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
ADD %EBP,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EDI,0xe0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
SUB %EDI,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV 0x8(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CLTQ																				scal (12.5%)
MOV %RAX,0x50(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDI,0x148(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x50(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,0x150(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x10(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,0x158(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x58(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,0x160(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x18(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,0x168(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x40(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,0x170(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x20(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,0x178(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x48(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,0x180(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x30(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,0x188(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x38(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x28(%RBX),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,0x190(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RBX,0x198(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0x1a8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD $0x1,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
JMP 432b75 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x85>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines
Module	exec

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.75 to 2.25 cycles (5.67x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
omp_get_thread_num@plt: 1 occurrences►

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►

Conversion instructions

Detected expensive conversion instructions.

Details

CLTQ: 1 occurrences►

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 144 bytes. The binary function is storing 116 bytes.

General properties

nb instructions	103
nb uops	102
loop length	444
used x86 registers	12
used mmx registers	0
used xmm registers	7
used ymm registers	0
used zmm registers	0
nb stack references	17

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.75 cycles
front end	12.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.33	5.33	5.33	5.33	5.33	5.33	10.00	10.00	10.00	10.00	1.00	1.00	1.00	1.00	0.00	0.00
cycles	5.33	5.33	5.33	5.33	5.33	5.33	10.00	10.00	10.00	10.00	1.00	1.00	1.00	1.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	12.75
Dispatch	10.00
DIV/SQRT	12.00
Overall L1	12.75

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	27%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	42%

INT+FP

all	6%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	15%

Vector efficiency ratios

INT

all	8%
load	6%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	15%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	17%

INT+FP

all	10%
load	11%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.75 cycles. At this rate:

4% of peak load performance is reached (11.29 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (9.10 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 432af0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB $0x1a8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x68(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA 0x1(%RAX),%EBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV 0x6c(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x60(%RDI),%EDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
ADD $0x2,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x1(%RDI),%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV 0x64(%RBX),%EDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %EAX,0x138(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV %ESI,0x13c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
CMP %EAX,%EBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 4333b8 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x8c8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
LEA 0x2(%RDI),%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB %EBP,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CMP %R14D,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 4333b8 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x8c8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R14D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SUB %ESI,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %R15D,0x140(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
CALL 404660 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404550 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R13D,%EAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
DIV %R12D	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JB 4333ca <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x8da>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %ESI,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADD %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RSI,%RCX,1),%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %EAX,0x144(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
CMP %EAX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JAE 4333b8 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x8c8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV 0x13c(%RSP),%EDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOVSD (%RBX),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
DIVL 0x140(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOVSD 0x127cd(%RIP),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVSD 0x11dd4(%RIP),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVSD 0x12673(%RIP),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVAPD %XMM5,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOVAPD %XMM14,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOVAPD %XMM13,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
UNPCKLPD %XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
UNPCKLPD %XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
UNPCKLPD %XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
UNPCKLPD %XMM12,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
ADD %EDX,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R14D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
ADD %EBP,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EDI,0xe0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
SUB %EDI,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV 0x8(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CLTQ																				scal (12.5%)
MOV %RAX,0x50(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDI,0x148(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x50(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,0x150(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x10(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,0x158(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x58(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,0x160(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x18(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,0x168(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x40(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,0x170(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x20(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,0x178(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x48(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,0x180(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x30(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,0x188(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x38(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x28(%RBX),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,0x190(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RBX,0x198(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0x1a8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD $0x1,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
JMP 432b75 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x85>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	5.39	2.07
▼Loop 336 - - exec–	0.01	0.01
○Loop 337 - - exec	5.38	2.06

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Code clean check

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Execution units bottlenecks

CALL instructions

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Complex instructions

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Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code