OV - exec - Function generate_chunk(int, global_variables&) [clone ._omp

	Function: generate_chunk(int, global_variables&) [clone ._omp_fn.0]	Module: exec	Source: :0-0	Coverage (incl. loops): 0.04% \| (excl. loops): 0.00%

  ***  This Panel is Intentionally Left Blank.  ***

It is due to a lack of debug symbols in the given object
(loop or function).

0x42d400 PUSH	%R15

0x42d402 PUSH	%R14

0x42d404 PUSH	%R13

0x42d406 PUSH	%R12

0x42d408 PUSH	%RBP

0x42d409 PUSH	%RBX

0x42d40a SUB	$0x78,%RSP

0x42d40e MOV	0x2c(%RDI),%R15D

0x42d412 MOV	0x28(%RDI),%R14D

0x42d416 MOV	%R15D,0x44(%RSP)

0x42d41b MOV	%R14D,0x48(%RSP)

0x42d420 TEST	%R15D,%R15D

0x42d423 JLE	42d690

0x42d429 TEST	%R14D,%R14D

0x42d42c JLE	42d690

0x42d432 MOV	%RDI,%RBX

0x42d435 CALL	404660 <omp_get_num_threads@plt>

0x42d43a MOV	%EAX,%EBP

0x42d43c CALL	404550 <omp_get_thread_num@plt>

0x42d441 XOR	%EDX,%EDX

0x42d443 MOV	%EAX,%ECX

0x42d445 MOV	%R15D,%EAX

0x42d448 IMUL	%R14D,%EAX

0x42d44c DIV	%EBP

0x42d44e MOV	%EAX,%ESI

0x42d450 CMP	%EDX,%ECX

0x42d452 JB	42d69f

0x42d458 IMUL	%ESI,%ECX

0x42d45b ADD	%EDX,%ECX

0x42d45d LEA	(%RSI,%RCX,1),%EAX

0x42d460 MOV	%EAX,0x4c(%RSP)

0x42d464 CMP	%EAX,%ECX

0x42d466 JAE	42d690

0x42d46c MOV	0x48(%RSP),%EDI

0x42d470 MOV	%ECX,%EAX

0x42d472 XOR	%EDX,%EDX

0x42d474 MOV	0x20(%RBX),%R14

0x42d478 DIV	%EDI

0x42d47a SUB	%EDX,%EDI

0x42d47c MOV	%EDX,%R15D

0x42d47f MOVSXD	%EAX,%R13

0x42d482 MOV	%EDI,%EDX

0x42d484 MOV	0x8(%RBX),%RDI

0x42d488 MOV	%RDI,0x50(%RSP)

0x42d48d MOV	(%RBX),%RDI

0x42d490 MOV	%RDI,0x58(%RSP)

0x42d495 MOV	0x10(%RBX),%RDI

0x42d499 MOV	%RDI,0x60(%RSP)

0x42d49e MOV	0x18(%RBX),%RDI

0x42d4a2 MOV	%RDI,0x68(%RSP)

0x42d4a7 NOPW	(%RAX,%RAX,1)

(281) 0x42d4b0 CMP	%EDX,%ESI

(281) 0x42d4b2 CMOVA	%EDX,%ESI

(281) 0x42d4b5 LEA	(%RCX,%RSI,1),%R12D

(281) 0x42d4b9 CMP	%R12D,%ECX

(281) 0x42d4bc JAE	42d669

(281) 0x42d4c2 MOV	0x50(%RSP),%RAX

(281) 0x42d4c7 MOV	0x30(%R14),%RBX

(281) 0x42d4cb MOV	(%R14),%R10

(281) 0x42d4ce MOV	0xa8(%R14),%R11

(281) 0x42d4d5 MOV	0x8(%RAX),%R9

(281) 0x42d4d9 MOV	0x58(%RSP),%RAX

(281) 0x42d4de IMUL	%R13,%RBX

(281) 0x42d4e2 MOV	0xb8(%R14),%RCX

(281) 0x42d4e9 MOV	0x68(%RSP),%RDX

(281) 0x42d4ee IMUL	%R13,%R10

(281) 0x42d4f2 MOV	0x8(%RAX),%R8

(281) 0x42d4f6 MOV	0x10(%R14),%RAX

(281) 0x42d4fa IMUL	%R13,%R11

(281) 0x42d4fe MOV	0x40(%R14),%RBP

(281) 0x42d502 MOV	0x60(%RSP),%RDI

(281) 0x42d507 MOV	%RCX,0x10(%RSP)

(281) 0x42d50c MOV	%RAX,0x18(%RSP)

(281) 0x42d511 MOV	0xd8(%R14),%RAX

(281) 0x42d518 MOV	0x8(%RDX),%RCX

(281) 0x42d51c MOV	0xe8(%R14),%RDX

(281) 0x42d523 MOV	%RBP,0x30(%RSP)

(281) 0x42d528 IMUL	%R13,%RAX

(281) 0x42d52c MOV	%RBX,0x38(%RSP)

(281) 0x42d531 MOV	0x8(%RDI),%RDI

(281) 0x42d535 MOV	%R10,0x28(%RSP)

(281) 0x42d53a MOV	%R11,0x20(%RSP)

(281) 0x42d53f MOV	%RDX,0x8(%RSP)

(281) 0x42d544 MOV	%RAX,(%RSP)

(281) 0x42d548 CMP	$0x1,%ESI

(281) 0x42d54b JE	42d60a

(281) 0x42d551 MOVSXD	%R15D,%RAX

(281) 0x42d554 LEA	(%RBX,%RAX,1),%RDX

(281) 0x42d558 MOV	0x18(%RSP),%RBX

(281) 0x42d55d LEA	(%RBP,%RDX,8),%RBP

(281) 0x42d562 LEA	(%R10,%RAX,1),%RDX

(281) 0x42d566 MOV	0x10(%RSP),%R10

(281) 0x42d56b LEA	(%RBX,%RDX,8),%RBX

(281) 0x42d56f LEA	(%R11,%RAX,1),%RDX

(281) 0x42d573 LEA	(%R10,%RDX,8),%R11

(281) 0x42d577 MOV	(%RSP),%RDX

(281) 0x42d57b ADD	%RDX,%RAX

(281) 0x42d57e MOV	0x8(%RSP),%RDX

(281) 0x42d583 LEA	(%RDX,%RAX,8),%R10

(281) 0x42d587 MOV	%ESI,%EDX

(281) 0x42d589 XOR	%EAX,%EAX

(281) 0x42d58b SHR	$0x1,%EDX

(281) 0x42d58d SAL	$0x4,%RDX

(281) 0x42d591 NOPW	%CS:(%RAX,%RAX,1)

(281) 0x42d59c NOPW	%CS:(%RAX,%RAX,1)

(281) 0x42d5a7 NOPW	%CS:(%RAX,%RAX,1)

(281) 0x42d5b2 NOPW	%CS:(%RAX,%RAX,1)

(281) 0x42d5bd NOPL	(%RAX)

  (282) 0x42d5c0 MOVSD	(%R9),%XMM0

  (282) 0x42d5c5 UNPCKLPD	%XMM0,%XMM0

  (282) 0x42d5c9 MOVUPS	%XMM0,(%RBP,%RAX,1)

  (282) 0x42d5ce MOVSD	(%R8),%XMM0

  (282) 0x42d5d3 UNPCKLPD	%XMM0,%XMM0

  (282) 0x42d5d7 MOVUPS	%XMM0,(%RBX,%RAX,1)

  (282) 0x42d5db MOVSD	(%RDI),%XMM0

  (282) 0x42d5df UNPCKLPD	%XMM0,%XMM0

  (282) 0x42d5e3 MOVUPS	%XMM0,(%R11,%RAX,1)

  (282) 0x42d5e8 MOVSD	(%RCX),%XMM0

  (282) 0x42d5ec UNPCKLPD	%XMM0,%XMM0

  (282) 0x42d5f0 MOVUPS	%XMM0,(%R10,%RAX,1)

  (282) 0x42d5f5 ADD	$0x10,%RAX

  (282) 0x42d5f9 CMP	%RDX,%RAX

  (282) 0x42d5fc JNE	42d5c0

(281) 0x42d5fe TEST	$0x1,%SIL

(281) 0x42d602 JE	42d666

(281) 0x42d604 AND	$-0x2,%ESI

(281) 0x42d607 ADD	%ESI,%R15D

(281) 0x42d60a MOV	0x38(%RSP),%RAX

(281) 0x42d60f MOVSD	(%R9),%XMM0

(281) 0x42d614 MOVSXD	%R15D,%R15

(281) 0x42d617 MOV	0x30(%RSP),%RSI

(281) 0x42d61c ADD	%R15,%RAX

(281) 0x42d61f MOVSD	%XMM0,(%RSI,%RAX,8)

(281) 0x42d624 MOV	0x28(%RSP),%RAX

(281) 0x42d629 MOVSD	(%R8),%XMM0

(281) 0x42d62e MOV	0x18(%RSP),%RSI

(281) 0x42d633 ADD	%R15,%RAX

(281) 0x42d636 MOVSD	%XMM0,(%RSI,%RAX,8)

(281) 0x42d63b MOV	0x20(%RSP),%RAX

(281) 0x42d640 MOVSD	(%RDI),%XMM0

(281) 0x42d644 MOV	0x10(%RSP),%RDI

(281) 0x42d649 ADD	%R15,%RAX

(281) 0x42d64c MOVSD	%XMM0,(%RDI,%RAX,8)

(281) 0x42d651 MOV	(%RSP),%RAX

(281) 0x42d655 MOVSD	(%RCX),%XMM0

(281) 0x42d659 MOV	0x8(%RSP),%RDI

(281) 0x42d65e ADD	%R15,%RAX

(281) 0x42d661 MOVSD	%XMM0,(%RDI,%RAX,8)

(281) 0x42d666 MOV	%R12D,%ECX

(281) 0x42d669 ADD	$0x1,%R13

(281) 0x42d66d CMP	%R13D,0x44(%RSP)

(281) 0x42d672 JLE	42d690

(281) 0x42d674 MOV	0x4c(%RSP),%ESI

(281) 0x42d678 MOV	0x48(%RSP),%EDX

(281) 0x42d67c XOR	%R15D,%R15D

(281) 0x42d67f SUB	%ECX,%ESI

(281) 0x42d681 JMP	42d4b0

0x42d686 NOPW	%CS:(%RAX,%RAX,1)

0x42d690 ADD	$0x78,%RSP

0x42d694 POP	%RBX

0x42d695 POP	%RBP

0x42d696 POP	%R12

0x42d698 POP	%R13

0x42d69a POP	%R14

0x42d69c POP	%R15

0x42d69e RET

0x42d69f ADD	$0x1,%ESI

0x42d6a2 XOR	%EDX,%EDX

0x42d6a4 JMP	42d458

0x42d6a9 NOPL	(%RAX)

Coverage (%)	Name	Source Location	Module
►96.87+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►3.13+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	generate_chunk(int, global_var[...]		exec
○	start(parallel_&, global_confi[...]		exec
○	initialise(parallel_&, std::ve[...]		exec
○	main		exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines
Module	exec

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 7% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 12.00 to 0.75 cycles (16.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 12.00 to 8.13 cycles (1.48x speedup).

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 7.88 cycles (1.52x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
omp_get_thread_num@plt: 1 occurrences►

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 52 bytes. The binary function is storing 44 bytes.

General properties

nb instructions	64
nb uops	65
loop length	218
used x86 registers	12
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	7

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.13 cycles
front end	8.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	4.17	4.17	4.17	4.17	4.17	4.17	4.25	4.25	4.25	4.25	0.00	0.00	0.00	0.00	0.00	0.00
cycles	4.17	4.17	4.17	4.17	4.17	4.17	4.25	4.25	4.25	4.25	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	8.13
Dispatch	4.25
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

all	7%
load	8%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

1% of peak load performance is reached (4.33 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.67 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 42d400

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x78,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0x2c(%RDI),%R15D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOV 0x28(%RDI),%R14D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOV %R15D,0x44(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %R14D,0x48(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
TEST %R15D,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JLE 42d690 <_Z14generate_chunkiR16global_variables._omp_fn.0+0x290>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
TEST %R14D,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JLE 42d690 <_Z14generate_chunkiR16global_variables._omp_fn.0+0x290>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 404660 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV %EAX,%EBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404550 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R14D,%EAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
DIV %EBP	2	0	0	0	2	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JB 42d69f <_Z14generate_chunkiR16global_variables._omp_fn.0+0x29f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
IMUL %ESI,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
ADD %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA (%RSI,%RCX,1),%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %EAX,0x4c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %EAX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JAE 42d690 <_Z14generate_chunkiR16global_variables._omp_fn.0+0x290>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV 0x48(%RSP),%EDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV 0x20(%RBX),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
DIV %EDI	2	0	0	0	2	0	0	0	0	0	0	10-17	6	scal (6.3%)
SUB %EDX,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %EDX,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOVSXD %EAX,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %EDI,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV 0x8(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDI,0x50(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV (%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDI,0x58(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x10(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDI,0x60(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x18(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDI,0x68(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0x78,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
ADD $0x1,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
JMP 42d458 <_Z14generate_chunkiR16global_variables._omp_fn.0+0x58>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines
Module	exec

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 7.88 cycles (1.52x speedup).

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
omp_get_thread_num@plt: 1 occurrences►

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 52 bytes. The binary function is storing 44 bytes.

General properties

nb instructions	64
nb uops	65
loop length	218
used x86 registers	12
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	7

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.13 cycles
front end	8.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	4.17	4.17	4.17	4.17	4.17	4.17	4.25	4.25	4.25	4.25	0.00	0.00	0.00	0.00	0.00	0.00
cycles	4.17	4.17	4.17	4.17	4.17	4.17	4.25	4.25	4.25	4.25	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	8.13
Dispatch	4.25
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

all	7%
load	8%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

1% of peak load performance is reached (4.33 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.67 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 42d400

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x78,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0x2c(%RDI),%R15D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOV 0x28(%RDI),%R14D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOV %R15D,0x44(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %R14D,0x48(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
TEST %R15D,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JLE 42d690 <_Z14generate_chunkiR16global_variables._omp_fn.0+0x290>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
TEST %R14D,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JLE 42d690 <_Z14generate_chunkiR16global_variables._omp_fn.0+0x290>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 404660 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV %EAX,%EBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404550 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R14D,%EAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
DIV %EBP	2	0	0	0	2	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JB 42d69f <_Z14generate_chunkiR16global_variables._omp_fn.0+0x29f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
IMUL %ESI,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
ADD %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA (%RSI,%RCX,1),%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %EAX,0x4c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %EAX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JAE 42d690 <_Z14generate_chunkiR16global_variables._omp_fn.0+0x290>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV 0x48(%RSP),%EDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV 0x20(%RBX),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
DIV %EDI	2	0	0	0	2	0	0	0	0	0	0	10-17	6	scal (6.3%)
SUB %EDX,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %EDX,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOVSXD %EAX,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %EDI,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV 0x8(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDI,0x50(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV (%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDI,0x58(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x10(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDI,0x60(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x18(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDI,0x68(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0x78,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
ADD $0x1,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
JMP 42d458 <_Z14generate_chunkiR16global_variables._omp_fn.0+0x58>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼generate_chunk(int, global_variables&) [clone ._omp_fn.0]–	0.04	0.02
▼Loop 281 - - exec–	0.00	0.00
○Loop 282 - - exec	0.04	0.02

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code