OV - exec - Function flux_calc_kernel(int, int, int, int, double, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: flux_calc_kernel(int, int, int, int, double, clover::Buffer2D<double>&, clover::Buffer2D<d ...	Module: exec	Source: :0-0	Coverage (incl. loops): 4.12% \| (excl. loops): 0.00%

  ***  This Panel is Intentionally Left Blank.  ***

It is due to a lack of debug symbols in the given object
(loop or function).

0x42cd40 PUSH	%R15

0x42cd42 PUSH	%R14

0x42cd44 PUSH	%R13

0x42cd46 PUSH	%R12

0x42cd48 PUSH	%RBP

0x42cd49 PUSH	%RBX

0x42cd4a MOV	%RDI,%RBX

0x42cd4d SUB	$0xf8,%RSP

0x42cd54 MOV	0x50(%RDI),%EAX

0x42cd57 LEA	0x1(%RAX),%EBP

0x42cd5a MOV	0x54(%RDI),%EAX

0x42cd5d MOV	0x48(%RDI),%EDI

0x42cd60 ADD	$0x3,%EAX

0x42cd63 LEA	0x1(%RDI),%ECX

0x42cd66 MOV	0x4c(%RBX),%EDI

0x42cd69 MOV	%EAX,0xa0(%RSP)

0x42cd70 MOV	%ECX,0xa4(%RSP)

0x42cd77 CMP	%EAX,%EBP

0x42cd79 JGE	42d1f0

0x42cd7f MOV	%EAX,%R13D

0x42cd82 LEA	0x3(%RDI),%R14D

0x42cd86 SUB	%EBP,%R13D

0x42cd89 CMP	%R14D,%ECX

0x42cd8c JGE	42d1f0

0x42cd92 MOV	%R14D,%R15D

0x42cd95 SUB	%ECX,%R15D

0x42cd98 MOV	%R15D,0xa8(%RSP)

0x42cda0 CALL	404660 <omp_get_num_threads@plt>

0x42cda5 MOV	%EAX,%R12D

0x42cda8 CALL	404550 <omp_get_thread_num@plt>

0x42cdad XOR	%EDX,%EDX

0x42cdaf MOV	%EAX,%ECX

0x42cdb1 MOV	%R15D,%EAX

0x42cdb4 IMUL	%R13D,%EAX

0x42cdb8 DIV	%R12D

0x42cdbb MOV	%EAX,%ESI

0x42cdbd CMP	%EDX,%ECX

0x42cdbf JB	42d202

0x42cdc5 IMUL	%ESI,%ECX

0x42cdc8 ADD	%EDX,%ECX

0x42cdca LEA	(%RSI,%RCX,1),%EAX

0x42cdcd MOV	%EAX,0xac(%RSP)

0x42cdd4 CMP	%EAX,%ECX

0x42cdd6 JAE	42d1f0

0x42cddc MOV	%ECX,%EAX

0x42cdde XOR	%EDX,%EDX

0x42cde0 MOV	0xa4(%RSP),%EDI

0x42cde7 MOVSD	(%RBX),%XMM4

0x42cdeb DIVL	0xa8(%RSP)

0x42cdf2 MOVSD	0x1857e(%RIP),%XMM3

0x42cdfa ADD	%EDX,%EDI

0x42cdfc MOV	%R14D,%EDX

0x42cdff ADD	%EBP,%EAX

0x42ce01 MOV	%EDI,0x50(%RSP)

0x42ce05 SUB	%EDI,%EDX

0x42ce07 MOV	0x8(%RBX),%RDI

0x42ce0b MOV	%RDI,0xb0(%RSP)

0x42ce13 MOV	0x18(%RBX),%RDI

0x42ce17 MOV	%RDI,0xb8(%RSP)

0x42ce1f MOV	0x28(%RBX),%RDI

0x42ce23 MOV	%RDI,0xc0(%RSP)

0x42ce2b MOV	0x38(%RBX),%RDI

0x42ce2f MOV	%RDI,0xc8(%RSP)

0x42ce37 MOV	0x10(%RBX),%RDI

0x42ce3b MOV	%RDI,0xd0(%RSP)

0x42ce43 MOV	0x20(%RBX),%RDI

0x42ce47 MOV	%RDI,0xd8(%RSP)

0x42ce4f MOV	0x30(%RBX),%RDI

0x42ce53 MOV	0x40(%RBX),%RBX

0x42ce57 MOV	%RDI,0xe0(%RSP)

0x42ce5f MOV	%RBX,0xe8(%RSP)

0x42ce67 MOVSXD	%EAX,%RBX

0x42ce6a NOPW	(%RAX,%RAX,1)

(278) 0x42ce70 CMP	%EDX,%ESI

(278) 0x42ce72 CMOVBE	%ESI,%EDX

(278) 0x42ce75 LEA	(%RCX,%RDX,1),%EAX

(278) 0x42ce78 MOV	%EDX,0x4(%RSP)

(278) 0x42ce7c MOV	%EAX,0x54(%RSP)

(278) 0x42ce80 CMP	%EAX,%ECX

(278) 0x42ce82 JAE	42d1c1

(278) 0x42ce88 MOV	0xb0(%RSP),%RAX

(278) 0x42ce90 MOVAPD	%XMM4,%XMM5

(278) 0x42ce94 MULSD	%XMM3,%XMM5

(278) 0x42ce98 MOV	0x10(%RAX),%R12

(278) 0x42ce9c MOV	(%RAX),%RCX

(278) 0x42ce9f MOV	0xb8(%RSP),%RAX

(278) 0x42cea7 IMUL	%RBX,%RCX

(278) 0x42ceab MOV	%R12,0x90(%RSP)

(278) 0x42ceb3 MOV	0x10(%RAX),%R11

(278) 0x42ceb7 MOV	(%RAX),%RAX

(278) 0x42ceba MOV	%RAX,%RDI

(278) 0x42cebd MOV	%RCX,0x98(%RSP)

(278) 0x42cec5 IMUL	%RBX,%RDI

(278) 0x42cec9 MOV	%R11,0x80(%RSP)

(278) 0x42ced1 LEA	(%RAX,%RDI,1),%R13

(278) 0x42ced5 MOV	0xc0(%RSP),%RAX

(278) 0x42cedd MOV	%RDI,0x88(%RSP)

(278) 0x42cee5 MOV	%R13,0x78(%RSP)

(278) 0x42ceea MOV	0x10(%RAX),%RBP

(278) 0x42ceee MOV	(%RAX),%RAX

(278) 0x42cef1 MOV	%RAX,%RSI

(278) 0x42cef4 MOV	%RBP,0x68(%RSP)

(278) 0x42cef9 IMUL	%RBX,%RSI

(278) 0x42cefd ADD	%RSI,%RAX

(278) 0x42cf00 MOV	%RSI,0x70(%RSP)

(278) 0x42cf05 MOV	%RAX,0x48(%RSP)

(278) 0x42cf0a MOV	0xc8(%RSP),%RAX

(278) 0x42cf12 MOV	0x10(%RAX),%RDX

(278) 0x42cf16 MOV	(%RAX),%R8

(278) 0x42cf19 MOV	0xd0(%RSP),%RAX

(278) 0x42cf21 MOV	%RDX,0x40(%RSP)

(278) 0x42cf26 MOV	0xd8(%RSP),%RDX

(278) 0x42cf2e IMUL	%RBX,%R8

(278) 0x42cf32 MOV	0x10(%RAX),%R10

(278) 0x42cf36 MOV	(%RAX),%R9

(278) 0x42cf39 MOV	0x10(%RDX),%RAX

(278) 0x42cf3d IMUL	%RBX,%R9

(278) 0x42cf41 MOV	%R10,0x38(%RSP)

(278) 0x42cf46 MOV	%RAX,0x28(%RSP)

(278) 0x42cf4b MOV	(%RDX),%RAX

(278) 0x42cf4e MOV	%R8,0x60(%RSP)

(278) 0x42cf53 IMUL	%RBX,%RAX

(278) 0x42cf57 MOV	%R9,0x58(%RSP)

(278) 0x42cf5c MOV	%RAX,0x30(%RSP)

(278) 0x42cf61 MOV	0xe0(%RSP),%R14

(278) 0x42cf69 MOV	0xe8(%RSP),%R15

(278) 0x42cf71 MOV	0x10(%R14),%RDX

(278) 0x42cf75 MOV	(%R15),%R10

(278) 0x42cf78 MOV	%RDX,0x18(%RSP)

(278) 0x42cf7d MOV	(%R14),%RDX

(278) 0x42cf80 IMUL	%RBX,%R10

(278) 0x42cf84 MOV	0x10(%R15),%R14

(278) 0x42cf88 IMUL	%RBX,%RDX

(278) 0x42cf8c CMPL	$0x1,0x4(%RSP)

(278) 0x42cf91 MOV	%R14,0x10(%RSP)

(278) 0x42cf96 MOV	%R10,0x8(%RSP)

(278) 0x42cf9b MOV	%RDX,0x20(%RSP)

(278) 0x42cfa0 JE	42d0d8

(278) 0x42cfa6 MOVSXD	0x50(%RSP),%RAX

(278) 0x42cfab MOVAPD	%XMM5,%XMM2

(278) 0x42cfaf UNPCKLPD	%XMM2,%XMM2

(278) 0x42cfb3 LEA	(%RCX,%RAX,1),%RDX

(278) 0x42cfb7 MOV	0x8(%RSP),%RCX

(278) 0x42cfbc LEA	(%R12,%RDX,8),%R15

(278) 0x42cfc0 LEA	(%RDI,%RAX,1),%RDX

(278) 0x42cfc4 MOV	0x30(%RSP),%RDI

(278) 0x42cfc9 LEA	(%R11,%RDX,8),%R14

(278) 0x42cfcd LEA	(%R13,%RAX,1),%RDX

(278) 0x42cfd2 LEA	(%R11,%RDX,8),%R13

(278) 0x42cfd6 MOV	0x48(%RSP),%R11

(278) 0x42cfdb LEA	(%RSI,%RAX,1),%RDX

(278) 0x42cfdf MOV	0x18(%RSP),%RSI

(278) 0x42cfe4 LEA	(%RBP,%RDX,8),%R12

(278) 0x42cfe9 LEA	(%R11,%RAX,1),%RDX

(278) 0x42cfed LEA	(%RBP,%RDX,8),%RBP

(278) 0x42cff2 LEA	(%R8,%RAX,1),%RDX

(278) 0x42cff6 MOV	0x40(%RSP),%R8

(278) 0x42cffb LEA	(%R8,%RDX,8),%R11

(278) 0x42cfff LEA	(%R9,%RAX,1),%RDX

(278) 0x42d003 MOV	0x38(%RSP),%R9

(278) 0x42d008 LEA	(%R9,%RDX,8),%R10

(278) 0x42d00c LEA	(%RDI,%RAX,1),%RDX

(278) 0x42d010 MOV	0x28(%RSP),%RDI

(278) 0x42d015 SAL	$0x3,%RDX

(278) 0x42d019 LEA	(%RDI,%RDX,1),%R9

(278) 0x42d01d LEA	0x8(%RDI,%RDX,1),%R8

(278) 0x42d022 MOV	0x20(%RSP),%RDX

(278) 0x42d027 ADD	%RAX,%RDX

(278) 0x42d02a ADD	%RCX,%RAX

(278) 0x42d02d MOV	0x10(%RSP),%RCX

(278) 0x42d032 SAL	$0x3,%RDX

(278) 0x42d036 LEA	(%RSI,%RDX,1),%RDI

(278) 0x42d03a LEA	0x8(%RSI,%RDX,1),%RSI

(278) 0x42d03f MOV	0x4(%RSP),%EDX

(278) 0x42d043 LEA	(%RCX,%RAX,8),%RCX

(278) 0x42d047 XOR	%EAX,%EAX

(278) 0x42d049 SHR	$0x1,%EDX

(278) 0x42d04b SAL	$0x4,%RDX

(278) 0x42d04f NOP

  (279) 0x42d050 MOVUPD	(%R14,%RAX,1),%XMM6

  (279) 0x42d056 MOVUPD	(%R13,%RAX,1),%XMM0

  (279) 0x42d05d MOVUPD	(%R12,%RAX,1),%XMM7

  (279) 0x42d063 MOVUPD	(%R15,%RAX,1),%XMM1

  (279) 0x42d069 ADDPD	%XMM6,%XMM0

  (279) 0x42d06d MOVUPD	(%RBP,%RAX,1),%XMM6

  (279) 0x42d073 MULPD	%XMM2,%XMM1

  (279) 0x42d077 ADDPD	%XMM7,%XMM0

  (279) 0x42d07b ADDPD	%XMM6,%XMM0

  (279) 0x42d07f MULPD	%XMM1,%XMM0

  (279) 0x42d083 MOVUPS	%XMM0,(%R11,%RAX,1)

  (279) 0x42d088 MOVUPD	(%R9,%RAX,1),%XMM7

  (279) 0x42d08e MOVUPD	(%RDI,%RAX,1),%XMM6

  (279) 0x42d093 MOVUPD	(%R8,%RAX,1),%XMM0

  (279) 0x42d099 MOVUPD	(%R10,%RAX,1),%XMM1

  (279) 0x42d09f ADDPD	%XMM7,%XMM0

  (279) 0x42d0a3 MULPD	%XMM2,%XMM1

  (279) 0x42d0a7 MOVUPD	(%RSI,%RAX,1),%XMM7

  (279) 0x42d0ac ADDPD	%XMM6,%XMM0

  (279) 0x42d0b0 ADDPD	%XMM7,%XMM0

  (279) 0x42d0b4 MULPD	%XMM1,%XMM0

  (279) 0x42d0b8 MOVUPS	%XMM0,(%RCX,%RAX,1)

  (279) 0x42d0bc ADD	$0x10,%RAX

  (279) 0x42d0c0 CMP	%RAX,%RDX

  (279) 0x42d0c3 JNE	42d050

(278) 0x42d0c5 MOV	0x4(%RSP),%EAX

(278) 0x42d0c9 TEST	$0x1,%AL

(278) 0x42d0cb JE	42d1bd

(278) 0x42d0d1 AND	$-0x2,%EAX

(278) 0x42d0d4 ADD	%EAX,0x50(%RSP)

(278) 0x42d0d8 MOVSXD	0x50(%RSP),%RAX

(278) 0x42d0dd MOV	0x78(%RSP),%RCX

(278) 0x42d0e2 MOV	0x80(%RSP),%R10

(278) 0x42d0ea MOV	0x88(%RSP),%RSI

(278) 0x42d0f2 ADD	%RAX,%RCX

(278) 0x42d0f5 MOV	0x60(%RSP),%RDX

(278) 0x42d0fa MOV	0x30(%RSP),%RDI

(278) 0x42d0ff MOVSD	(%R10,%RCX,8),%XMM0

(278) 0x42d105 ADD	%RAX,%RSI

(278) 0x42d108 MOV	0x70(%RSP),%RCX

(278) 0x42d10d ADDSD	(%R10,%RSI,8),%XMM0

(278) 0x42d113 MOV	0x68(%RSP),%RSI

(278) 0x42d118 ADD	%RAX,%RDX

(278) 0x42d11b ADD	%RAX,%RCX

(278) 0x42d11e MOV	0x28(%RSP),%R15

(278) 0x42d123 MOV	0x18(%RSP),%R8

(278) 0x42d128 ADDSD	(%RSI,%RCX,8),%XMM0

(278) 0x42d12d MOV	0x48(%RSP),%RCX

(278) 0x42d132 ADD	%RAX,%RCX

(278) 0x42d135 ADDSD	(%RSI,%RCX,8),%XMM0

(278) 0x42d13a MOV	0x98(%RSP),%RCX

(278) 0x42d142 MOV	0x90(%RSP),%RSI

(278) 0x42d14a ADD	%RAX,%RCX

(278) 0x42d14d MOVSD	(%RSI,%RCX,8),%XMM2

(278) 0x42d152 MOV	0x40(%RSP),%RCX

(278) 0x42d157 MULSD	%XMM5,%XMM2

(278) 0x42d15b MULSD	%XMM2,%XMM0

(278) 0x42d15f MOVSD	%XMM0,(%RCX,%RDX,8)

(278) 0x42d164 LEA	0x1(%RAX),%EDX

(278) 0x42d167 MOV	0x8(%RSP),%RCX

(278) 0x42d16c MOVSXD	%EDX,%RDX

(278) 0x42d16f LEA	(%RDI,%RDX,1),%RSI

(278) 0x42d173 ADD	%RAX,%RDI

(278) 0x42d176 ADD	%RAX,%RCX

(278) 0x42d179 MOVSD	(%R15,%RSI,8),%XMM0

(278) 0x42d17f ADDSD	(%R15,%RDI,8),%XMM0

(278) 0x42d185 MOV	0x20(%RSP),%RDI

(278) 0x42d18a LEA	(%RDI,%RAX,1),%RSI

(278) 0x42d18e ADD	%RDI,%RDX

(278) 0x42d191 MOV	0x38(%RSP),%RDI

(278) 0x42d196 ADDSD	(%R8,%RSI,8),%XMM0

(278) 0x42d19c MOV	0x58(%RSP),%RSI

(278) 0x42d1a1 ADDSD	(%R8,%RDX,8),%XMM0

(278) 0x42d1a7 ADD	%RAX,%RSI

(278) 0x42d1aa MOV	0x10(%RSP),%RAX

(278) 0x42d1af MULSD	(%RDI,%RSI,8),%XMM5

(278) 0x42d1b4 MULSD	%XMM5,%XMM0

(278) 0x42d1b8 MOVSD	%XMM0,(%RAX,%RCX,8)

(278) 0x42d1bd MOV	0x54(%RSP),%ECX

(278) 0x42d1c1 ADD	$0x1,%RBX

(278) 0x42d1c5 CMP	%EBX,0xa0(%RSP)

(278) 0x42d1cc JLE	42d1f0

(278) 0x42d1ce MOV	0xac(%RSP),%ESI

(278) 0x42d1d5 MOV	0xa4(%RSP),%EAX

(278) 0x42d1dc MOV	0xa8(%RSP),%EDX

(278) 0x42d1e3 MOV	%EAX,0x50(%RSP)

(278) 0x42d1e7 SUB	%ECX,%ESI

(278) 0x42d1e9 JMP	42ce70

0x42d1ee XCHG	%AX,%AX

0x42d1f0 ADD	$0xf8,%RSP

0x42d1f7 POP	%RBX

0x42d1f8 POP	%RBP

0x42d1f9 POP	%R12

0x42d1fb POP	%R13

0x42d1fd POP	%R14

0x42d1ff POP	%R15

0x42d201 RET

0x42d202 ADD	$0x1,%ESI

0x42d205 XOR	%EDX,%EDX

0x42d207 JMP	42cdc5

0x42d20c NOPL	(%RAX)

Coverage (%)	Name	Source Location	Module
►96.64+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►3.10+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	flux_calc(global_variables&)		exec
○	hydro(global_variables&, paral[...]		exec
○	main		exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines
Module	exec

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.00 to 1.33 cycles (9.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 8% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 12.00 to 0.76 cycles (15.82x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 12.00 to 10.88 cycles (1.10x speedup).

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 10.63 cycles (1.13x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
omp_get_thread_num@plt: 1 occurrences►

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 104 bytes. The binary function is storing 84 bytes.

General properties

nb instructions	86
nb uops	87
loop length	338
used x86 registers	12
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	13

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.88 cycles
front end	10.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.50	5.50	5.50	5.50	5.50	5.50	7.75	7.75	7.75	7.75	0.00	0.00	0.00	0.00	0.00	0.00
cycles	5.50	5.50	5.50	5.50	5.50	5.50	7.75	7.75	7.75	7.75	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	10.88
Dispatch	7.75
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	7%
load	6%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	8%
load	10%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

3% of peak load performance is reached (8.67 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (7.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 42cd40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB $0xf8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0x50(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
LEA 0x1(%RAX),%EBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV 0x54(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x48(%RDI),%EDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD $0x3,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA 0x1(%RDI),%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV 0x4c(%RBX),%EDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %EAX,0xa0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %ECX,0xa4(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %EAX,%EBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 42d1f0 <_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x4b0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
LEA 0x3(%RDI),%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
SUB %EBP,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMP %R14D,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 42d1f0 <_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x4b0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %R14D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SUB %ECX,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %R15D,0xa8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CALL 404660 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404550 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R13D,%EAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
DIV %R12D	2	0	0	0	2	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JB 42d202 <_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x4c2>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
IMUL %ESI,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
ADD %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA (%RSI,%RCX,1),%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %EAX,0xac(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %EAX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JAE 42d1f0 <_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x4b0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV 0xa4(%RSP),%EDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOVSD (%RBX),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
DIVL 0xa8(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	10-17	6	scal (6.3%)
MOVSD 0x1857e(%RIP),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
ADD %EDX,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %R14D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
ADD %EBP,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %EDI,0x50(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
SUB %EDI,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV 0x8(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDI,0xb0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x18(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDI,0xb8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x28(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDI,0xc0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x38(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDI,0xc8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x10(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDI,0xd0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x20(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDI,0xd8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x30(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x40(%RBX),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDI,0xe0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %RBX,0xe8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOVSXD %EAX,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0xf8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
ADD $0x1,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
JMP 42cdc5 <_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x85>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines
Module	exec

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.00 to 1.33 cycles (9.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 10.63 cycles (1.13x speedup).

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
omp_get_thread_num@plt: 1 occurrences►

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 104 bytes. The binary function is storing 84 bytes.

General properties

nb instructions	86
nb uops	87
loop length	338
used x86 registers	12
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	13

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.88 cycles
front end	10.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.50	5.50	5.50	5.50	5.50	5.50	7.75	7.75	7.75	7.75	0.00	0.00	0.00	0.00	0.00	0.00
cycles	5.50	5.50	5.50	5.50	5.50	5.50	7.75	7.75	7.75	7.75	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	10.88
Dispatch	7.75
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	7%
load	6%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	8%
load	10%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

3% of peak load performance is reached (8.67 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (7.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 42cd40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB $0xf8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0x50(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
LEA 0x1(%RAX),%EBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV 0x54(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x48(%RDI),%EDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD $0x3,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA 0x1(%RDI),%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV 0x4c(%RBX),%EDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %EAX,0xa0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %ECX,0xa4(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %EAX,%EBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 42d1f0 <_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x4b0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
LEA 0x3(%RDI),%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
SUB %EBP,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMP %R14D,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 42d1f0 <_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x4b0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %R14D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SUB %ECX,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %R15D,0xa8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CALL 404660 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404550 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R13D,%EAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
DIV %R12D	2	0	0	0	2	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JB 42d202 <_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x4c2>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
IMUL %ESI,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
ADD %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA (%RSI,%RCX,1),%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %EAX,0xac(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %EAX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JAE 42d1f0 <_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x4b0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV 0xa4(%RSP),%EDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOVSD (%RBX),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
DIVL 0xa8(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	10-17	6	scal (6.3%)
MOVSD 0x1857e(%RIP),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
ADD %EDX,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %R14D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
ADD %EBP,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %EDI,0x50(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
SUB %EDI,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV 0x8(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDI,0xb0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x18(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDI,0xb8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x28(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDI,0xc0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x38(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDI,0xc8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x10(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDI,0xd0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x20(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDI,0xd8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x30(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x40(%RBX),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDI,0xe0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %RBX,0xe8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOVSXD %EAX,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0xf8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
ADD $0x1,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
JMP 42cdc5 <_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x85>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼flux_calc_kernel(int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	4.12	1.58
▼Loop 278 - - exec–	0.00	0.01
○Loop 279 - - exec	4.12	1.58

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Code clean check

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Execution units bottlenecks

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Expensive FP math instructions/calls

CALL instructions

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Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code