OV - exec - Function field_summary(global_variables&, parallel_&) [clone ._omp

	Function: field_summary(global_variables&, parallel_&) [clone ._omp_fn.0]	Module: exec	Source: :0-0	Coverage (incl. loops): 0.28% \| (excl. loops): 0.00%

  ***  This Panel is Intentionally Left Blank.  ***

It is due to a lack of debug symbols in the given object
(loop or function).

0x42c7c0 PUSH	%R15

0x42c7c2 PUSH	%R14

0x42c7c4 PUSH	%R13

0x42c7c6 PUSH	%R12

0x42c7c8 PUSH	%RBP

0x42c7c9 PUSH	%RBX

0x42c7ca MOV	%RDI,%RBX

0x42c7cd SUB	$0x68,%RSP

0x42c7d1 MOV	0x3c(%RDI),%R13D

0x42c7d5 MOV	0x38(%RDI),%EAX

0x42c7d8 MOV	0x34(%RDI),%R12D

0x42c7dc SUB	%R13D,%EAX

0x42c7df LEA	0x1(%RAX),%R15D

0x42c7e3 MOV	%R15D,(%RSP)

0x42c7e7 CALL	404660 <omp_get_num_threads@plt>

0x42c7ec MOV	%EAX,%EBP

0x42c7ee CALL	404550 <omp_get_thread_num@plt>

0x42c7f3 MOV	%EAX,%ECX

0x42c7f5 MOV	0x30(%RBX),%EAX

0x42c7f8 SUB	%R12D,%EAX

0x42c7fb ADD	$0x1,%EAX

0x42c7fe IMUL	%R15D,%EAX

0x42c802 CLTD

0x42c803 IDIV	%EBP

0x42c805 CMP	%EDX,%ECX

0x42c807 JL	42cad0

0x42c80d IMUL	%EAX,%ECX

0x42c810 LEA	(%RCX,%RDX,1),%R8D

0x42c814 ADD	%R8D,%EAX

0x42c817 MOV	%EAX,0x10(%RSP)

0x42c81b CMP	%EAX,%R8D

0x42c81e JGE	42ca78

0x42c824 MOV	(%RBX),%RAX

0x42c827 LEA	0x1(%R13),%ESI

0x42c82b PXOR	%XMM4,%XMM4

0x42c82f MOV	%RBX,0x58(%RSP)

0x42c834 MOV	%ESI,0x3c(%RSP)

0x42c838 MOVAPD	%XMM4,%XMM6

0x42c83c MOVAPD	%XMM4,%XMM3

0x42c840 MOVAPD	%XMM4,%XMM5

0x42c844 MOV	0x10(%RAX),%RCX

0x42c848 MOV	0x30(%RAX),%R13

0x42c84c MOVAPD	%XMM4,%XMM2

0x42c850 MOVAPD	%XMM4,%XMM7

0x42c854 LEA	0x1(%R12),%ESI

0x42c859 MOV	0xd8(%RAX),%RBP

0x42c860 MOV	(%RAX),%R12

0x42c863 MOV	%ESI,0x38(%RSP)

0x42c867 MOV	0x60(%RAX),%RSI

0x42c86b MOV	%RCX,0x30(%RSP)

0x42c870 MOV	0x290(%RAX),%RCX

0x42c877 MOV	%RSI,0x48(%RSP)

0x42c87c MOV	0x70(%RAX),%RSI

0x42c880 MOV	%RCX,0x28(%RSP)

0x42c885 MOV	0x2a0(%RAX),%RCX

0x42c88c MOV	%RSI,0x50(%RSP)

0x42c891 MOV	0x40(%RAX),%RSI

0x42c895 MOV	%RCX,0x40(%RSP)

0x42c89a MOV	0xe8(%RAX),%R10

0x42c8a1 MOV	0xa8(%RAX),%R11

0x42c8a8 MOV	0xb8(%RAX),%R9

0x42c8af MOV	%RSI,%RBX

0x42c8b2 MOVSD	0x18abe(%RIP),%XMM1

0x42c8ba MOVSD	0x180c5(%RIP),%XMM8

0x42c8c3 NOPW	%CS:(%RAX,%RAX,1)

0x42c8ce XCHG	%AX,%AX

(275) 0x42c8d0 MOV	%R8D,%EAX

(275) 0x42c8d3 MOV	0x38(%RSP),%ECX

(275) 0x42c8d7 MOV	0x3c(%RSP),%ESI

(275) 0x42c8db ADD	$0x1,%R8D

(275) 0x42c8df CLTD

(275) 0x42c8e0 IDIVL	(%RSP)

(275) 0x42c8e3 ADD	%ECX,%EAX

(275) 0x42c8e5 ADD	%ESI,%EDX

(275) 0x42c8e7 MOVSXD	%EAX,%RCX

(275) 0x42c8ea MOVSXD	%EDX,%RSI

(275) 0x42c8ed ADD	$0x1,%EDX

(275) 0x42c8f0 ADD	$0x1,%EAX

(275) 0x42c8f3 MOV	%RCX,%R14

(275) 0x42c8f6 MOVSXD	%EDX,%RDX

(275) 0x42c8f9 CLTQ

(275) 0x42c8fb IMUL	%R11,%R14

(275) 0x42c8ff LEA	(%RSI,%R14,1),%RDI

(275) 0x42c903 ADD	%RDX,%R14

(275) 0x42c906 MOVSD	(%R9,%RDI,8),%XMM0

(275) 0x42c90c MOV	%RBP,%RDI

(275) 0x42c90f IMUL	%RCX,%RDI

(275) 0x42c913 MULSD	%XMM0,%XMM0

(275) 0x42c917 LEA	(%RSI,%RDI,1),%R15

(275) 0x42c91b ADD	%RDX,%RDI

(275) 0x42c91e MOVSD	(%R10,%R15,8),%XMM9

(275) 0x42c924 MOVSD	(%R10,%RDI,8),%XMM10

(275) 0x42c92a MOV	%R11,%RDI

(275) 0x42c92d IMUL	%RAX,%RDI

(275) 0x42c931 MULSD	%XMM9,%XMM9

(275) 0x42c936 IMUL	%RBP,%RAX

(275) 0x42c93a MULSD	%XMM10,%XMM10

(275) 0x42c93f ADDSD	%XMM0,%XMM9

(275) 0x42c944 MOVSD	(%R9,%R14,8),%XMM0

(275) 0x42c94a LEA	(%RSI,%RDI,1),%R14

(275) 0x42c94e ADD	%RDX,%RDI

(275) 0x42c951 ADD	%RAX,%RDX

(275) 0x42c954 MULSD	%XMM0,%XMM0

(275) 0x42c958 MOVSD	(%R10,%RDX,8),%XMM12

(275) 0x42c95e MOV	0x40(%RSP),%RDX

(275) 0x42c963 MULSD	%XMM1,%XMM9

(275) 0x42c968 MULSD	%XMM12,%XMM12

(275) 0x42c96d ADDSD	%XMM10,%XMM0

(275) 0x42c972 ADDSD	%XMM7,%XMM9

(275) 0x42c977 MULSD	%XMM1,%XMM0

(275) 0x42c97b ADDSD	%XMM9,%XMM0

(275) 0x42c980 MOVSD	(%R9,%R14,8),%XMM9

(275) 0x42c986 LEA	(%RSI,%RAX,1),%R14

(275) 0x42c98a MOV	0x28(%RSP),%RAX

(275) 0x42c98f MOVSD	(%R10,%R14,8),%XMM10

(275) 0x42c995 MULSD	%XMM9,%XMM9

(275) 0x42c99a IMUL	%RCX,%RAX

(275) 0x42c99e MULSD	%XMM10,%XMM10

(275) 0x42c9a3 ADD	%RSI,%RAX

(275) 0x42c9a6 ADDSD	%XMM10,%XMM9

(275) 0x42c9ab MOVSD	(%RDX,%RAX,8),%XMM10

(275) 0x42c9b1 MOV	%R12,%RAX

(275) 0x42c9b4 MOV	0x30(%RSP),%RDX

(275) 0x42c9b9 IMUL	%RCX,%RAX

(275) 0x42c9bd ADDSD	%XMM10,%XMM4

(275) 0x42c9c2 MULSD	%XMM1,%XMM9

(275) 0x42c9c7 ADD	%RSI,%RAX

(275) 0x42c9ca MOVSD	(%RDX,%RAX,8),%XMM11

(275) 0x42c9d0 MOV	%R13,%RAX

(275) 0x42c9d3 IMUL	%RCX,%RAX

(275) 0x42c9d7 MULSD	%XMM10,%XMM11

(275) 0x42c9dc ADDSD	%XMM0,%XMM9

(275) 0x42c9e1 MOVSD	(%R9,%RDI,8),%XMM0

(275) 0x42c9e7 ADD	%RSI,%RAX

(275) 0x42c9ea MULSD	%XMM0,%XMM0

(275) 0x42c9ee MOVSD	(%RBX,%RAX,8),%XMM13

(275) 0x42c9f4 MOV	0x48(%RSP),%RAX

(275) 0x42c9f9 MULSD	%XMM11,%XMM13

(275) 0x42c9fe IMUL	%RAX,%RCX

(275) 0x42ca02 ADDSD	%XMM11,%XMM6

(275) 0x42ca07 MOV	0x50(%RSP),%RAX

(275) 0x42ca0c MULSD	%XMM8,%XMM11

(275) 0x42ca11 ADDSD	%XMM12,%XMM0

(275) 0x42ca16 ADD	%RSI,%RCX

(275) 0x42ca19 MULSD	(%RAX,%RCX,8),%XMM10

(275) 0x42ca1f ADDSD	%XMM13,%XMM3

(275) 0x42ca24 MULSD	%XMM1,%XMM0

(275) 0x42ca28 ADDSD	%XMM10,%XMM2

(275) 0x42ca2d ADDSD	%XMM9,%XMM0

(275) 0x42ca32 MULSD	%XMM11,%XMM0

(275) 0x42ca37 ADDSD	%XMM0,%XMM5

(275) 0x42ca3b CMP	%R8D,0x10(%RSP)

(275) 0x42ca40 JNE	42c8d0

0x42ca46 PXOR	%XMM0,%XMM0

0x42ca4a UNPCKLPD	%XMM6,%XMM4

0x42ca4e UNPCKLPD	%XMM5,%XMM3

0x42ca52 MOV	0x58(%RSP),%RBX

0x42ca57 ADDSD	%XMM7,%XMM2

0x42ca5b ADDPD	%XMM0,%XMM4

0x42ca5f ADDPD	%XMM0,%XMM3

0x42ca63 MOVQ	%XMM2,%RBP

0x42ca68 MOVAPS	%XMM4,0x10(%RSP)

0x42ca6d MOVAPS	%XMM3,(%RSP)

0x42ca71 JMP	42ca87

0x42ca73 NOPL	(%RAX,%RAX,1)

0x42ca78 PXOR	%XMM6,%XMM6

0x42ca7c XOR	%EBP,%EBP

0x42ca7e MOVAPS	%XMM6,(%RSP)

0x42ca82 MOVAPS	%XMM6,0x10(%RSP)

0x42ca87 CALL	4041d0 <GOMP_atomic_start@plt>

0x42ca8c MOVUPD	0x18(%RBX),%XMM0

0x42ca91 MOVUPD	0x8(%RBX),%XMM1

0x42ca96 MOVQ	%RBP,%XMM2

0x42ca9b ADDPD	(%RSP),%XMM0

0x42caa0 ADDSD	0x28(%RBX),%XMM2

0x42caa5 ADDPD	0x10(%RSP),%XMM1

0x42caab MOVSD	%XMM2,0x28(%RBX)

0x42cab0 MOVUPS	%XMM1,0x8(%RBX)

0x42cab4 MOVUPS	%XMM0,0x18(%RBX)

0x42cab8 ADD	$0x68,%RSP

0x42cabc POP	%RBX

0x42cabd POP	%RBP

0x42cabe POP	%R12

0x42cac0 POP	%R13

0x42cac2 POP	%R14

0x42cac4 POP	%R15

0x42cac6 JMP	404260

0x42cacb NOPL	(%RAX,%RAX,1)

0x42cad0 ADD	$0x1,%EAX

0x42cad3 XOR	%EDX,%EDX

0x42cad5 JMP	42c80d

0x42cada NOPW	(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►96.93+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►2.46+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	field_summary(global_variables[...]		exec
○	hydro(global_variables&, paral[...]		exec
○	main		exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines
Module	exec

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 13.00 to 5.00 cycles (2.60x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 16% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 13.00 to 1.44 cycles (9.04x speedup).

Details

38% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

28% of SSE/AVX loads are used in vector version.
35% of SSE/AVX stores are used in vector version.
66% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
47% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

GOMP_atomic_start@plt: 1 occurrences►
omp_get_num_threads@plt: 1 occurrences►
omp_get_thread_num@plt: 1 occurrences►

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
MOVQ: 1 occurrences►

Vector unaligned load/store instructions

Detected 4 suboptimal vector unaligned load/store instructions.

Details

MOVUPD: 2 occurrences►
MOVUPS: 2 occurrences►

Workaround

Pass to your compiler a micro-architecture specialization option:
- Please look into your compiler manual for march=native or equivalent
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries
2. inform your compiler that your arrays are vector aligned: read your compiler manual.

Conversion instructions

Detected expensive conversion instructions.

Details

CLTD: 1 occurrences►

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 4 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 10 FP arithmetical operations:

10: addition or subtraction

The binary function is loading 216 bytes (27 double precision FP elements). The binary function is storing 168 bytes (21 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.

General properties

nb instructions	105
nb uops	104
loop length	426
used x86 registers	16
used mmx registers	0
used xmm registers	9
used ymm registers	0
used zmm registers	0
nb stack references	10

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	13.00 cycles
front end	13.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	4.17	4.17	4.17	4.17	4.17	4.17	11.25	11.25	11.25	11.25	1.50	1.50	3.00	3.00	4.00	4.00
cycles	4.17	4.17	4.17	4.17	4.17	4.17	11.25	11.25	11.25	11.25	1.50	1.50	3.00	3.00	4.00	4.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

6.00

Cycles summary

Front-end	13.00
Dispatch	11.25
DIV/SQRT	6.00
Overall L1	13.00

Vectorization ratios

INT

all	10%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	27%

all	70%
load	57%
store	85%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	66%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	71%

INT+FP

all	38%
load	28%
store	35%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	66%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	47%

Vector efficiency ratios

INT

all	11%
load	12%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	21%
load	19%
store	23%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	20%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	21%

INT+FP

all	16%
load	16%
store	15%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	20%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	16%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 13.00 cycles. At this rate:

6% of peak load performance is reached (16.62 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
10% of peak store performance is reached (12.92 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 13.00 to 11.25 cycles (1.16x speedup).

ASM code

In the binary file, the address of the function is: 42c7c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB $0x68,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x3c(%RDI),%R13D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x38(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x34(%RDI),%R12D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
SUB %R13D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x1(%RAX),%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R15D,(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
CALL 404660 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%EBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404550 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x30(%RBX),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
SUB %R12D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x1,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %R15D,%EAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
CLTD																				scal (6.3%)
IDIV %EBP	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-14	6	scal (6.3%)
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JL 42cad0 <_Z13field_summaryR16global_variablesR9parallel_._omp_fn.0+0x310>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %EAX,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
LEA (%RCX,%RDX,1),%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %R8D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EAX,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
CMP %EAX,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 42ca78 <_Z13field_summaryR16global_variablesR9parallel_._omp_fn.0+0x2b8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV (%RBX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA 0x1(%R13),%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
PXOR %XMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
MOV %RBX,0x58(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %ESI,0x3c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOVAPD %XMM4,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOVAPD %XMM4,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOVAPD %XMM4,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV 0x10(%RAX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x30(%RAX),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOVAPD %XMM4,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOVAPD %XMM4,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
LEA 0x1(%R12),%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV 0xd8(%RAX),%RBP	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV (%RAX),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %ESI,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV 0x60(%RAX),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV %RCX,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x290(%RAX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RSI,0x48(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x70(%RAX),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV %RCX,0x28(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x2a0(%RAX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RSI,0x50(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x40(%RAX),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV %RCX,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0xe8(%RAX),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0xa8(%RAX),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0xb8(%RAX),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV %RSI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVSD 0x18abe(%RIP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVSD 0x180c5(%RIP),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
PXOR %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
UNPCKLPD %XMM6,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
UNPCKLPD %XMM5,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
MOV 0x58(%RSP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
ADDSD %XMM7,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
ADDPD %XMM0,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
ADDPD %XMM0,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
MOVQ %XMM2,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVAPS %XMM4,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	2	vect (25.0%)
MOVAPS %XMM3,(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	2	vect (25.0%)
JMP 42ca87 <_Z13field_summaryR16global_variablesR9parallel_._omp_fn.0+0x2c7>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
PXOR %XMM6,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
XOR %EBP,%EBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOVAPS %XMM6,(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	2	vect (25.0%)
MOVAPS %XMM6,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	2	vect (25.0%)
CALL 4041d0 <GOMP_atomic_start@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOVUPD 0x18(%RBX),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MOVUPD 0x8(%RBX),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MOVQ %RBP,%XMM2	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (12.5%)
ADDPD (%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
ADDSD 0x28(%RBX),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
ADDPD 0x10(%RSP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
MOVSD %XMM2,0x28(%RBX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVUPS %XMM1,0x8(%RBX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
MOVUPS %XMM0,0x18(%RBX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
ADD $0x68,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
JMP 404260 <GOMP_atomic_end@plt>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0x1,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 42c80d <_Z13field_summaryR16global_variablesR9parallel_._omp_fn.0+0x4d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines
Module	exec

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 13.00 to 5.00 cycles (2.60x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

38% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

28% of SSE/AVX loads are used in vector version.
35% of SSE/AVX stores are used in vector version.
66% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
47% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

GOMP_atomic_start@plt: 1 occurrences►
omp_get_num_threads@plt: 1 occurrences►
omp_get_thread_num@plt: 1 occurrences►

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
MOVQ: 1 occurrences►

Vector unaligned load/store instructions

Detected 4 suboptimal vector unaligned load/store instructions.

Details

MOVUPD: 2 occurrences►
MOVUPS: 2 occurrences►

Workaround

Pass to your compiler a micro-architecture specialization option:
- Please look into your compiler manual for march=native or equivalent
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries
2. inform your compiler that your arrays are vector aligned: read your compiler manual.

Conversion instructions

Detected expensive conversion instructions.

Details

CLTD: 1 occurrences►

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function is composed of 10 FP arithmetical operations:

10: addition or subtraction

The binary function is loading 216 bytes (27 double precision FP elements). The binary function is storing 168 bytes (21 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.

General properties

nb instructions	105
nb uops	104
loop length	426
used x86 registers	16
used mmx registers	0
used xmm registers	9
used ymm registers	0
used zmm registers	0
nb stack references	10

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	13.00 cycles
front end	13.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	4.17	4.17	4.17	4.17	4.17	4.17	11.25	11.25	11.25	11.25	1.50	1.50	3.00	3.00	4.00	4.00
cycles	4.17	4.17	4.17	4.17	4.17	4.17	11.25	11.25	11.25	11.25	1.50	1.50	3.00	3.00	4.00	4.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

6.00

Cycles summary

Front-end	13.00
Dispatch	11.25
DIV/SQRT	6.00
Overall L1	13.00

Vectorization ratios

INT

all	10%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	27%

all	70%
load	57%
store	85%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	66%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	71%

INT+FP

all	38%
load	28%
store	35%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	66%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	47%

Vector efficiency ratios

INT

all	11%
load	12%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	21%
load	19%
store	23%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	20%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	21%

INT+FP

all	16%
load	16%
store	15%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	20%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	16%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 13.00 cycles. At this rate:

6% of peak load performance is reached (16.62 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
10% of peak store performance is reached (12.92 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 42c7c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB $0x68,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x3c(%RDI),%R13D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x38(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x34(%RDI),%R12D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
SUB %R13D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x1(%RAX),%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R15D,(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
CALL 404660 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%EBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404550 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x30(%RBX),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
SUB %R12D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x1,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %R15D,%EAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
CLTD																				scal (6.3%)
IDIV %EBP	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-14	6	scal (6.3%)
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JL 42cad0 <_Z13field_summaryR16global_variablesR9parallel_._omp_fn.0+0x310>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %EAX,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
LEA (%RCX,%RDX,1),%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %R8D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EAX,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
CMP %EAX,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 42ca78 <_Z13field_summaryR16global_variablesR9parallel_._omp_fn.0+0x2b8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV (%RBX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA 0x1(%R13),%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
PXOR %XMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
MOV %RBX,0x58(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %ESI,0x3c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOVAPD %XMM4,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOVAPD %XMM4,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOVAPD %XMM4,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV 0x10(%RAX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x30(%RAX),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOVAPD %XMM4,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOVAPD %XMM4,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
LEA 0x1(%R12),%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV 0xd8(%RAX),%RBP	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV (%RAX),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %ESI,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV 0x60(%RAX),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV %RCX,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x290(%RAX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RSI,0x48(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x70(%RAX),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV %RCX,0x28(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x2a0(%RAX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RSI,0x50(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x40(%RAX),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV %RCX,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0xe8(%RAX),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0xa8(%RAX),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0xb8(%RAX),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV %RSI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVSD 0x18abe(%RIP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVSD 0x180c5(%RIP),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
PXOR %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
UNPCKLPD %XMM6,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
UNPCKLPD %XMM5,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
MOV 0x58(%RSP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
ADDSD %XMM7,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
ADDPD %XMM0,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
ADDPD %XMM0,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
MOVQ %XMM2,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVAPS %XMM4,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	2	vect (25.0%)
MOVAPS %XMM3,(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	2	vect (25.0%)
JMP 42ca87 <_Z13field_summaryR16global_variablesR9parallel_._omp_fn.0+0x2c7>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
PXOR %XMM6,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
XOR %EBP,%EBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOVAPS %XMM6,(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	2	vect (25.0%)
MOVAPS %XMM6,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	2	vect (25.0%)
CALL 4041d0 <GOMP_atomic_start@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOVUPD 0x18(%RBX),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MOVUPD 0x8(%RBX),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MOVQ %RBP,%XMM2	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (12.5%)
ADDPD (%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
ADDSD 0x28(%RBX),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
ADDPD 0x10(%RSP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
MOVSD %XMM2,0x28(%RBX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVUPS %XMM1,0x8(%RBX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
MOVUPS %XMM0,0x18(%RBX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
ADD $0x68,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
JMP 404260 <GOMP_atomic_end@plt>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0x1,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 42c80d <_Z13field_summaryR16global_variablesR9parallel_._omp_fn.0+0x4d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼field_summary(global_variables&, parallel_&) [clone ._omp_fn.0]–	0.28	0.11
○Loop 275 - - exec	0.28	0.11

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Vector unaligned load/store instructions

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Type of elements and instruction set

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