OV - exec - Function calc_dt_kernel(int, int, int, int, double, double, double, double, double, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, double&, int&, double&, double&, int&, int&, int&) [clone ._omp

	Function: calc_dt_kernel(int, int, int, int, double, double, double, double, double, clover::Buffer2 ...	Module: exec	Source: :0-0	Coverage (incl. loops): 4.20% \| (excl. loops): 0.00%

  ***  This Panel is Intentionally Left Blank.  ***

It is due to a lack of debug symbols in the given object
(loop or function).

0x42a6c0 PUSH	%R15

0x42a6c2 MOV	%RDI,%R15

0x42a6c5 PUSH	%R14

0x42a6c7 PUSH	%R13

0x42a6c9 PUSH	%R12

0x42a6cb PUSH	%RBP

0x42a6cc PUSH	%RBX

0x42a6cd SUB	$0x98,%RSP

0x42a6d4 MOV	0x80(%RDI),%EAX

0x42a6da LEA	0x1(%RAX),%R13D

0x42a6de MOV	0x84(%RDI),%EAX

0x42a6e4 LEA	0x2(%RAX),%R8D

0x42a6e8 MOV	0x78(%RDI),%EAX

0x42a6eb LEA	0x1(%RAX),%ESI

0x42a6ee MOV	0x7c(%RDI),%EAX

0x42a6f1 CMP	%R8D,%R13D

0x42a6f4 JGE	42ac15

0x42a6fa MOV	%R8D,%EBX

0x42a6fd LEA	0x2(%RAX),%R12D

0x42a701 MOV	%R8D,0x10(%RSP)

0x42a706 SUB	%R13D,%EBX

0x42a709 CMP	%R12D,%ESI

0x42a70c JGE	42ac15

0x42a712 MOV	%R12D,%R14D

0x42a715 MOV	%ESI,0x8(%RSP)

0x42a719 SUB	%ESI,%R14D

0x42a71c MOV	%R14D,0x68(%RSP)

0x42a721 CALL	404660 <omp_get_num_threads@plt>

0x42a726 MOV	%EAX,%EBP

0x42a728 CALL	404550 <omp_get_thread_num@plt>

0x42a72d XOR	%EDX,%EDX

0x42a72f MOV	0x8(%RSP),%ESI

0x42a733 MOV	0x10(%RSP),%R8D

0x42a738 MOV	%EAX,%EDI

0x42a73a MOV	%R14D,%EAX

0x42a73d IMUL	%EBX,%EAX

0x42a740 DIV	%EBP

0x42a742 CMP	%EDX,%EDI

0x42a744 MOV	%EAX,%ECX

0x42a746 JB	42ac01

0x42a74c IMUL	%ECX,%EDI

0x42a74f MOVSD	0x1acf1(%RIP),%XMM0

0x42a757 ADD	%EDX,%EDI

0x42a759 LEA	(%RCX,%RDI,1),%R9D

0x42a75d CMP	%R9D,%EDI

0x42a760 JAE	42abcf

0x42a766 MOV	%EDI,%EAX

0x42a768 XOR	%EDX,%EDX

0x42a76a MOVSD	0x18(%R15),%XMM6

0x42a770 MOV	%R8D,0x6c(%RSP)

0x42a775 DIVL	0x68(%RSP)

0x42a779 MOV	%ESI,0x80(%RSP)

0x42a780 MOVSD	%XMM6,0x58(%RSP)

0x42a786 MOVSD	0x10(%R15),%XMM6

0x42a78c MOV	%R9D,0x84(%RSP)

0x42a794 MOVSD	%XMM6,0x70(%RSP)

0x42a79a MOVSD	0x8(%R15),%XMM6

0x42a7a0 MOVSD	%XMM0,0x88(%RSP)

0x42a7a9 MOVSD	%XMM6,0x78(%RSP)

0x42a7af MOVSD	(%R15),%XMM6

0x42a7b4 MOVSD	%XMM0,0x10(%RSP)

0x42a7ba MOVSD	%XMM6,0x50(%RSP)

0x42a7c0 ADD	%R13D,%EAX

0x42a7c3 LEA	(%RDX,%RSI,1),%EBX

0x42a7c6 MOV	%R12D,%EDX

0x42a7c9 MOVSXD	%EAX,%R12

0x42a7cc SUB	%EBX,%EDX

0x42a7ce MOV	%R12,%R13

0x42a7d1 NOPW	%CS:(%RAX,%RAX,1)

0x42a7dc NOPL	(%RAX)

(257) 0x42a7e0 CMP	%EDX,%ECX

(257) 0x42a7e2 CMOVA	%EDX,%ECX

(257) 0x42a7e5 LEA	(%RDI,%RCX,1),%ESI

(257) 0x42a7e8 CMP	%ESI,%EDI

(257) 0x42a7ea JAE	42ab97

(257) 0x42a7f0 MOVSD	0x78(%RSP),%XMM5

(257) 0x42a7f6 MOVSXD	%EBX,%RBX

(257) 0x42a7f9 LEA	-0x1(%RCX),%R14D

(257) 0x42a7fd MOV	%ESI,0x64(%RSP)

(257) 0x42a801 MOVSD	0x70(%RSP),%XMM7

(257) 0x42a807 LEA	0x1(%RBX),%RBP

(257) 0x42a80b LEA	(,%R13,8),%R12

(257) 0x42a813 MOVAPD	%XMM5,%XMM6

(257) 0x42a817 MOV	%RBP,%RAX

(257) 0x42a81a ADD	%RBP,%R14

(257) 0x42a81d MOV	%R13,%RBP

(257) 0x42a820 ADDSD	%XMM5,%XMM6

(257) 0x42a824 MOV	%RAX,%R13

(257) 0x42a827 MOVSD	%XMM6,0x48(%RSP)

(257) 0x42a82d MOVAPD	%XMM7,%XMM6

(257) 0x42a831 ADDSD	%XMM7,%XMM6

(257) 0x42a835 MOVSD	%XMM6,0x40(%RSP)

(257) 0x42a83b JMP	42a890

0x42a83d NOPL	(%RAX)

  (258) 0x42a840 MOVSD	0x1a400(%RIP),%XMM1

  (258) 0x42a848 MOVAPD	%XMM4,%XMM0

  (258) 0x42a84c CALL	4041a0 <fmin@plt>

  (258) 0x42a851 MOVAPD	%XMM0,%XMM1

  (258) 0x42a855 MOVSD	0x38(%RSP),%XMM0

  (258) 0x42a85b CALL	4041a0 <fmin@plt>

  (258) 0x42a860 MOVAPD	%XMM0,%XMM1

  (258) 0x42a864 MOVSD	0x30(%RSP),%XMM0

  (258) 0x42a86a CALL	4041a0 <fmin@plt>

  (258) 0x42a86f MOVSD	0x10(%RSP),%XMM1

  (258) 0x42a875 CALL	4041a0 <fmin@plt>

  (258) 0x42a87a MOVSD	%XMM0,0x10(%RSP)

  (258) 0x42a880 CMP	%R13,%R14

  (258) 0x42a883 JE	42ab8e

  (258) 0x42a889 MOV	%R13,%RBX

  (258) 0x42a88c ADD	$0x1,%R13

  (258) 0x42a890 MOV	0x30(%R15),%RDX

  (258) 0x42a894 MOV	0x58(%R15),%RCX

  (258) 0x42a898 PXOR	%XMM7,%XMM7

  (258) 0x42a89c MOV	0x50(%R15),%RSI

  (258) 0x42a8a0 MOV	0x8(%RDX),%RDX

  (258) 0x42a8a4 MOVSD	(%RDX,%RBX,8),%XMM5

  (258) 0x42a8a9 MOV	0x38(%R15),%RDX

  (258) 0x42a8ad MOV	0x8(%RDX),%RDX

  (258) 0x42a8b1 MOVSD	%XMM5,0x8(%RSP)

  (258) 0x42a8b7 MOVSD	(%RDX,%R12,1),%XMM6

  (258) 0x42a8bd MOV	(%RCX),%RDX

  (258) 0x42a8c0 MOV	0x10(%RCX),%RCX

  (258) 0x42a8c4 IMUL	%RBP,%RDX

  (258) 0x42a8c8 MOVSD	%XMM6,0x18(%RSP)

  (258) 0x42a8ce ADD	%RBX,%RDX

  (258) 0x42a8d1 MOVSD	(%RCX,%RDX,8),%XMM0

  (258) 0x42a8d6 MOV	(%RSI),%RDX

  (258) 0x42a8d9 MOV	0x48(%R15),%RCX

  (258) 0x42a8dd MOV	0x10(%RSI),%RSI

  (258) 0x42a8e1 IMUL	%RBP,%RDX

  (258) 0x42a8e5 MOVAPD	%XMM0,%XMM1

  (258) 0x42a8e9 MULSD	%XMM0,%XMM1

  (258) 0x42a8ed ADD	%RBX,%RDX

  (258) 0x42a8f0 MOVSD	(%RSI,%RDX,8),%XMM0

  (258) 0x42a8f5 MOV	(%RCX),%RDX

  (258) 0x42a8f8 MOV	0x10(%RCX),%RCX

  (258) 0x42a8fc IMUL	%RBP,%RDX

  (258) 0x42a900 ADDSD	%XMM0,%XMM0

  (258) 0x42a904 ADD	%RBX,%RDX

  (258) 0x42a907 DIVSD	(%RCX,%RDX,8),%XMM0

  (258) 0x42a90c ADDSD	%XMM1,%XMM0

  (258) 0x42a910 UCOMISD	%XMM0,%XMM7

  (258) 0x42a914 JA	42ac0b

  (258) 0x42a91a SQRTSD	%XMM0,%XMM0

  (258) 0x42a91e MOVSD	0x19c82(%RIP),%XMM1

  (258) 0x42a926 CALL	4043d0 <fmax@plt>

  (258) 0x42a92b MOVSD	0x18(%RSP),%XMM1

  (258) 0x42a931 MOVSD	%XMM0,0x20(%RSP)

  (258) 0x42a937 MOVSD	0x8(%RSP),%XMM0

  (258) 0x42a93d CALL	4041a0 <fmin@plt>

  (258) 0x42a942 MOV	0x60(%R15),%RDX

  (258) 0x42a946 MOV	0x20(%R15),%RDI

  (258) 0x42a94a MOVSD	0x19c56(%RIP),%XMM5

  (258) 0x42a952 MULSD	0x50(%RSP),%XMM0

  (258) 0x42a958 MOV	0x10(%RDX),%R8

  (258) 0x42a95c MOV	(%RDX),%RDX

  (258) 0x42a95f MOV	(%RDI),%RAX

  (258) 0x42a962 MOV	0x10(%RDI),%RSI

  (258) 0x42a966 MOV	%RDX,%RCX

  (258) 0x42a969 IMUL	%RBP,%RCX

  (258) 0x42a96d IMUL	%RBP,%RAX

  (258) 0x42a971 MOVAPD	%XMM0,%XMM6

  (258) 0x42a975 DIVSD	0x20(%RSP),%XMM6

  (258) 0x42a97b MOVSD	%XMM6,0x30(%RSP)

  (258) 0x42a981 LEA	(%RCX,%RBX,1),%R10

  (258) 0x42a985 ADD	%RCX,%RDX

  (258) 0x42a988 ADD	%R13,%RCX

  (258) 0x42a98b MOVSD	(%R8,%RCX,8),%XMM2

  (258) 0x42a991 LEA	(%RDX,%RBX,1),%R9

  (258) 0x42a995 MOV	0x40(%R15),%RCX

  (258) 0x42a999 ADD	%R13,%RDX

  (258) 0x42a99c ADDSD	(%R8,%RDX,8),%XMM2

  (258) 0x42a9a2 LEA	(%RAX,%R13,1),%RDX

  (258) 0x42a9a6 MOVSD	(%R8,%R10,8),%XMM4

  (258) 0x42a9ac MULSD	(%RSI,%RDX,8),%XMM2

  (258) 0x42a9b1 MOV	(%RCX),%RDX

  (258) 0x42a9b4 MOV	0x10(%RCX),%RCX

  (258) 0x42a9b8 ADDSD	(%R8,%R9,8),%XMM4

  (258) 0x42a9be LEA	(%RAX,%RBX,1),%R9

  (258) 0x42a9c2 IMUL	%RBP,%RDX

  (258) 0x42a9c6 MULSD	(%RSI,%R9,8),%XMM4

  (258) 0x42a9cc ADD	%RBX,%RDX

  (258) 0x42a9cf MOVAPD	%XMM2,%XMM7

  (258) 0x42a9d3 ANDPD	0x1a215(%RIP),%XMM7

  (258) 0x42a9db MOVSD	%XMM2,0x18(%RSP)

  (258) 0x42a9e1 MOVSD	(%RCX,%RDX,8),%XMM3

  (258) 0x42a9e6 MOVAPD	%XMM4,%XMM1

  (258) 0x42a9ea ANDPD	0x1a1fe(%RIP),%XMM1

  (258) 0x42a9f2 MOVAPD	%XMM7,%XMM0

  (258) 0x42a9f6 MOVSD	%XMM4,0x28(%RSP)

  (258) 0x42a9fc MULSD	%XMM3,%XMM5

  (258) 0x42aa00 MOVSD	%XMM3,0x20(%RSP)

  (258) 0x42aa06 MOVSD	%XMM5,0x8(%RSP)

  (258) 0x42aa0c CALL	4043d0 <fmax@plt>

  (258) 0x42aa11 MOVAPD	%XMM0,%XMM1

  (258) 0x42aa15 MOVSD	0x8(%RSP),%XMM0

  (258) 0x42aa1b CALL	4043d0 <fmax@plt>

  (258) 0x42aa20 MOVSD	0x20(%RSP),%XMM3

  (258) 0x42aa26 MOVSD	0x48(%RSP),%XMM1

  (258) 0x42aa2c PXOR	%XMM5,%XMM5

  (258) 0x42aa30 MULSD	%XMM3,%XMM1

  (258) 0x42aa34 DIVSD	%XMM0,%XMM1

  (258) 0x42aa38 MOVSD	%XMM1,0x38(%RSP)

  (258) 0x42aa3e MOV	0x68(%R15),%RDX

  (258) 0x42aa42 MOV	0x28(%R15),%RCX

  (258) 0x42aa46 MOVSD	0x18(%RSP),%XMM2

  (258) 0x42aa4c MOVSD	0x28(%RSP),%XMM4

  (258) 0x42aa52 MOV	0x10(%RDX),%RSI

  (258) 0x42aa56 MOV	0x10(%RCX),%R8

  (258) 0x42aa5a MOV	(%RDX),%RDX

  (258) 0x42aa5d MOV	(%RCX),%RCX

  (258) 0x42aa60 ADDSD	%XMM5,%XMM2

  (258) 0x42aa64 MOV	%RDX,%RDI

  (258) 0x42aa67 MOV	%RCX,%R9

  (258) 0x42aa6a IMUL	%RBP,%RDI

  (258) 0x42aa6e SUBSD	%XMM4,%XMM2

  (258) 0x42aa72 IMUL	%RBP,%R9

  (258) 0x42aa76 ADD	%RDI,%RDX

  (258) 0x42aa79 LEA	(%RDI,%RBX,1),%R11

  (258) 0x42aa7d LEA	(%RDI,%R13,1),%R10

  (258) 0x42aa81 ADD	%R9,%RCX

  (258) 0x42aa84 LEA	(%RDX,%RBX,1),%RDI

  (258) 0x42aa88 ADD	%R13,%RDX

  (258) 0x42aa8b MOVSD	(%RSI,%R11,8),%XMM1

  (258) 0x42aa91 ADD	%RBX,%RCX

  (258) 0x42aa94 MOVSD	(%RSI,%RDI,8),%XMM0

  (258) 0x42aa99 ADDSD	(%RSI,%RDX,8),%XMM0

  (258) 0x42aa9e MULSD	(%R8,%RCX,8),%XMM0

  (258) 0x42aaa4 ADDSD	(%RSI,%R10,8),%XMM1

  (258) 0x42aaaa LEA	(%R9,%RBX,1),%R10

  (258) 0x42aaae MULSD	(%R8,%R10,8),%XMM1

  (258) 0x42aab4 ADDSD	%XMM0,%XMM2

  (258) 0x42aab8 ANDPD	0x1a130(%RIP),%XMM0

  (258) 0x42aac0 SUBSD	%XMM1,%XMM2

  (258) 0x42aac4 ANDPD	0x1a124(%RIP),%XMM1

  (258) 0x42aacc MOVSD	%XMM2,0x18(%RSP)

  (258) 0x42aad2 CALL	4043d0 <fmax@plt>

  (258) 0x42aad7 MOVAPD	%XMM0,%XMM1

  (258) 0x42aadb MOVSD	0x8(%RSP),%XMM0

  (258) 0x42aae1 CALL	4043d0 <fmax@plt>

  (258) 0x42aae6 MOVSD	0x20(%RSP),%XMM3

  (258) 0x42aaec MOVSD	0x40(%RSP),%XMM4

  (258) 0x42aaf2 MOVSD	0x18(%RSP),%XMM2

  (258) 0x42aaf8 MOVSD	0x1a950(%RIP),%XMM7

  (258) 0x42ab00 MULSD	%XMM3,%XMM4

  (258) 0x42ab04 ADDSD	%XMM3,%XMM3

  (258) 0x42ab08 DIVSD	%XMM3,%XMM2

  (258) 0x42ab0c DIVSD	%XMM0,%XMM4

  (258) 0x42ab10 COMISD	%XMM2,%XMM7

  (258) 0x42ab14 JBE	42a840

  (258) 0x42ab1a MOVSD	0x19a7e(%RIP),%XMM0

  (258) 0x42ab22 MOVSD	0x1a11e(%RIP),%XMM1

  (258) 0x42ab2a MOVSD	%XMM4,0x8(%RSP)

  (258) 0x42ab30 DIVSD	%XMM2,%XMM0

  (258) 0x42ab34 MULSD	0x58(%RSP),%XMM0

  (258) 0x42ab3a CALL	4041a0 <fmin@plt>

  (258) 0x42ab3f MOVSD	0x8(%RSP),%XMM4

  (258) 0x42ab45 MOVAPD	%XMM0,%XMM1

  (258) 0x42ab49 MOVAPD	%XMM4,%XMM0

  (258) 0x42ab4d CALL	4041a0 <fmin@plt>

  (258) 0x42ab52 MOVAPD	%XMM0,%XMM1

  (258) 0x42ab56 MOVSD	0x38(%RSP),%XMM0

  (258) 0x42ab5c CALL	4041a0 <fmin@plt>

  (258) 0x42ab61 MOVAPD	%XMM0,%XMM1

  (258) 0x42ab65 MOVSD	0x30(%RSP),%XMM0

  (258) 0x42ab6b CALL	4041a0 <fmin@plt>

  (258) 0x42ab70 MOVAPD	%XMM0,%XMM1

  (258) 0x42ab74 MOVSD	0x10(%RSP),%XMM0

  (258) 0x42ab7a CALL	4041a0 <fmin@plt>

  (258) 0x42ab7f MOVSD	%XMM0,0x10(%RSP)

  (258) 0x42ab85 CMP	%R13,%R14

  (258) 0x42ab88 JNE	42a889

(257) 0x42ab8e MOV	0x64(%RSP),%ESI

(257) 0x42ab92 MOV	%RBP,%R13

(257) 0x42ab95 MOV	%ESI,%EDI

(257) 0x42ab97 ADD	$0x1,%R13

(257) 0x42ab9b CMP	%R13D,0x6c(%RSP)

(257) 0x42aba0 JLE	42abc0

(257) 0x42aba2 MOV	0x84(%RSP),%ECX

(257) 0x42aba9 MOV	0x68(%RSP),%EDX

(257) 0x42abad MOV	0x80(%RSP),%EBX

(257) 0x42abb4 SUB	%EDI,%ECX

(257) 0x42abb6 JMP	42a7e0

0x42abbb NOPL	(%RAX,%RAX,1)

0x42abc0 MOVSD	0x10(%RSP),%XMM0

0x42abc6 MINSD	0x88(%RSP),%XMM0

0x42abcf MOV	0x70(%R15),%RDX

0x42abd3 LEA	0x70(%R15),%RCX

(256) 0x42abd7 MOVQ	%RDX,%XMM6

(256) 0x42abdc MOV	%RDX,%RAX

(256) 0x42abdf MINSD	%XMM0,%XMM6

(256) 0x42abe3 MOVQ	%XMM6,%RSI

(256) 0x42abe8 LOCK CMPXCHG	%RSI,(%RCX)

(256) 0x42abed JNE	42ac1f

0x42abef ADD	$0x98,%RSP

0x42abf6 POP	%RBX

0x42abf7 POP	%RBP

0x42abf8 POP	%R12

0x42abfa POP	%R13

0x42abfc POP	%R14

0x42abfe POP	%R15

0x42ac00 RET

0x42ac01 ADD	$0x1,%ECX

0x42ac04 XOR	%EDX,%EDX

0x42ac06 JMP	42a74c

  (258) 0x42ac0b CALL	4042a0 <sqrt@plt>

  (258) 0x42ac10 JMP	42a91e

0x42ac15 MOVSD	0x1a82b(%RIP),%XMM0

0x42ac1d JMP	42abcf

(256) 0x42ac1f MOV	%RAX,%RDX

(256) 0x42ac22 JMP	42abd7

0x42ac24 NOPW	%CS:(%RAX,%RAX,1)

0x42ac2f NOP

Coverage (%)	Name	Source Location	Module
►97.04+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►2.87+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	calc_dt_kernel(int, int, int, [...]		exec
○	calc_dt(global_variables&, int[...]		exec
○	timestep(global_variables&, pa[...]		exec
○	hydro(global_variables&, paral[...]		exec
○	main		exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines
Module	exec

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.00 to 3.50 cycles (3.43x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 9% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 12.00 to 0.80 cycles (14.96x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 12.00 to 11.13 cycles (1.08x speedup).

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact.
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 10.88 cycles (1.10x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
omp_get_thread_num@plt: 1 occurrences►

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 100 bytes (12 double precision FP elements). The binary function is storing 72 bytes (9 double precision FP elements).

General properties

nb instructions	91
nb uops	89
loop length	369
used x86 registers	14
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	11

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	11.13 cycles
front end	11.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.83	5.83	5.83	5.83	5.83	5.83	7.50	7.50	7.50	7.50	0.00	0.00	0.50	0.50	3.00	3.00
cycles	5.83	5.83	5.83	5.83	5.83	5.83	7.50	7.50	7.50	7.50	0.00	0.00	0.50	0.50	3.00	3.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	11.13
Dispatch	7.50
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	6%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	9%
load	11%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

3% of peak load performance is reached (8.33 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (6.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 42a6c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x98,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x80(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
LEA 0x1(%RAX),%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV 0x84(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
LEA 0x2(%RAX),%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV 0x78(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
LEA 0x1(%RAX),%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV 0x7c(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
CMP %R8D,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 42ac15 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x555>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R8D,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
LEA 0x2(%RAX),%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R8D,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
SUB %R13D,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CMP %R12D,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 42ac15 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x555>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R12D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV %ESI,0x8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
SUB %ESI,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %R14D,0x68(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
CALL 404660 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
MOV %EAX,%EBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404550 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x8(%RSP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x10(%RSP),%R8D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
MOV %EAX,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R14D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %EBX,%EAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
DIV %EBP	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	10-17	6	scal (6.3%)
CMP %EDX,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JB 42ac01 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x541>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %ECX,%EDI	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
MOVSD 0x1acf1(%RIP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
ADD %EDX,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RCX,%RDI,1),%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %R9D,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JAE 42abcf <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x50f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %EDI,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOVSD 0x18(%R15),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MOV %R8D,0x6c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
DIVL 0x68(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	0	0	0	0	10-17	6	scal (6.3%)
MOV %ESI,0x80(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOVSD %XMM6,0x58(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVSD 0x10(%R15),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MOV %R9D,0x84(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOVSD %XMM6,0x70(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVSD 0x8(%R15),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MOVSD %XMM0,0x88(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVSD %XMM6,0x78(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVSD (%R15),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MOVSD %XMM0,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVSD %XMM6,0x50(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
ADD %R13D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RDX,%RSI,1),%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R12D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVSXD %EAX,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SUB %EBX,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R12,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOVSD 0x10(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MINSD 0x88(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	2	0.50	scal (12.5%)
MOV 0x70(%R15),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
LEA 0x70(%R15),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD $0x98,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD $0x1,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 42a74c <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x8c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
MOVSD 0x1a82b(%RIP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
JMP 42abcf <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x50f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines
Module	exec

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.00 to 3.50 cycles (3.43x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact.
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 10.88 cycles (1.10x speedup).

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
omp_get_thread_num@plt: 1 occurrences►

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

General properties

nb instructions	91
nb uops	89
loop length	369
used x86 registers	14
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	11

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	11.13 cycles
front end	11.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.83	5.83	5.83	5.83	5.83	5.83	7.50	7.50	7.50	7.50	0.00	0.00	0.50	0.50	3.00	3.00
cycles	5.83	5.83	5.83	5.83	5.83	5.83	7.50	7.50	7.50	7.50	0.00	0.00	0.50	0.50	3.00	3.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	11.13
Dispatch	7.50
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	6%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	9%
load	11%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

3% of peak load performance is reached (8.33 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (6.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 42a6c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x98,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x80(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
LEA 0x1(%RAX),%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV 0x84(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
LEA 0x2(%RAX),%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV 0x78(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
LEA 0x1(%RAX),%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV 0x7c(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
CMP %R8D,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 42ac15 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x555>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R8D,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
LEA 0x2(%RAX),%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R8D,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
SUB %R13D,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CMP %R12D,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 42ac15 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x555>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R12D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV %ESI,0x8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
SUB %ESI,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %R14D,0x68(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
CALL 404660 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
MOV %EAX,%EBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404550 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x8(%RSP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x10(%RSP),%R8D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
MOV %EAX,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R14D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %EBX,%EAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
DIV %EBP	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	10-17	6	scal (6.3%)
CMP %EDX,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JB 42ac01 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x541>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %ECX,%EDI	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
MOVSD 0x1acf1(%RIP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
ADD %EDX,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RCX,%RDI,1),%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %R9D,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JAE 42abcf <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x50f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %EDI,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOVSD 0x18(%R15),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MOV %R8D,0x6c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
DIVL 0x68(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	0	0	0	0	10-17	6	scal (6.3%)
MOV %ESI,0x80(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOVSD %XMM6,0x58(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVSD 0x10(%R15),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MOV %R9D,0x84(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOVSD %XMM6,0x70(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVSD 0x8(%R15),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MOVSD %XMM0,0x88(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVSD %XMM6,0x78(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVSD (%R15),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MOVSD %XMM0,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVSD %XMM6,0x50(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
ADD %R13D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RDX,%RSI,1),%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R12D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVSXD %EAX,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SUB %EBX,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R12,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOVSD 0x10(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MINSD 0x88(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	2	0.50	scal (12.5%)
MOV 0x70(%R15),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
LEA 0x70(%R15),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD $0x98,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD $0x1,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 42a74c <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x8c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
MOVSD 0x1a82b(%RIP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
JMP 42abcf <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x50f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼calc_dt_kernel(int, int, int, int, double, double, double, double, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D–	4.20	1.61
▼Loop 257 - - exec–	0.00	0.00
○Loop 258 - - exec	4.20	1.61
○Loop 256 - - exec	0.00	0.00

Report Configuration

Code clean check

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Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

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Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code