OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone ._omp

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: :0-0	Coverage (incl. loops): 4.27% \| (excl. loops): 0.00%

  ***  This Panel is Intentionally Left Blank.  ***

It is due to a lack of debug symbols in the given object
(loop or function).

0x4284e0 PUSH	%R15

0x4284e2 PUSH	%R14

0x4284e4 PUSH	%R13

0x4284e6 PUSH	%R12

0x4284e8 PUSH	%RBP

0x4284e9 MOV	%RDI,%RBP

0x4284ec PUSH	%RBX

0x4284ed SUB	$0xb8,%RSP

0x4284f4 MOV	0x34(%RDI),%EAX

0x4284f7 MOV	0x30(%RDI),%R14D

0x4284fb MOV	0x28(%RDI),%EDI

0x4284fe MOV	0x2c(%RBP),%ECX

0x428501 ADD	$0x3,%EAX

0x428504 ADD	$0x1,%EDI

0x428507 MOV	%EAX,0x88(%RSP)

0x42850e MOV	%EDI,0x8c(%RSP)

0x428515 CMP	%EAX,%R14D

0x428518 JGE	428860

0x42851e MOV	%EAX,%R12D

0x428521 LEA	0x3(%RCX),%R13D

0x428525 SUB	%R14D,%R12D

0x428528 CMP	%R13D,%EDI

0x42852b JGE	428860

0x428531 MOV	%R13D,%R15D

0x428534 SUB	%EDI,%R15D

0x428537 MOV	%R15D,0x90(%RSP)

0x42853f CALL	404660 <omp_get_num_threads@plt>

0x428544 MOV	%EAX,%EBX

0x428546 CALL	404550 <omp_get_thread_num@plt>

0x42854b XOR	%EDX,%EDX

0x42854d MOV	%EAX,%ECX

0x42854f MOV	%R15D,%EAX

0x428552 IMUL	%R12D,%EAX

0x428556 DIV	%EBX

0x428558 MOV	%EAX,%EDI

0x42855a CMP	%EDX,%ECX

0x42855c JB	4288e4

0x428562 IMUL	%EDI,%ECX

0x428565 ADD	%EDX,%ECX

0x428567 LEA	(%RDI,%RCX,1),%EAX

0x42856a MOV	%EAX,0x94(%RSP)

0x428571 CMP	%EAX,%ECX

0x428573 JAE	428860

0x428579 MOV	%ECX,%EAX

0x42857b XOR	%EDX,%EDX

0x42857d MOV	0x10(%RBP),%R8

0x428581 MOV	0x8c(%RSP),%ESI

0x428588 MOV	0x18(%RBP),%R11

0x42858c MOVQ	0x1c65c(%RIP),%XMM4

0x428594 PXOR	%XMM2,%XMM2

0x428598 DIVL	0x90(%RSP)

0x42859f MOV	%R8,0x98(%RSP)

0x4285a7 MOV	0x20(%RBP),%R8

0x4285ab MOVSD	0x1cc7d(%RIP),%XMM3

0x4285b3 MOV	%R8,0xa0(%RSP)

0x4285bb MOV	(%RBP),%R8

0x4285bf MOV	%R8,0xa8(%RSP)

0x4285c7 LEA	(%RDX,%RSI,1),%EBX

0x4285ca LEA	(%RAX,%R14,1),%EDX

0x4285ce MOV	0x8(%RBP),%RSI

0x4285d2 MOV	%R13D,%EAX

0x4285d5 LEA	-0x1(%RDX),%EBP

0x4285d8 MOVSXD	%EDX,%RDX

0x4285db SUB	%EBX,%EAX

0x4285dd LEA	0x1(%RDX),%R9

0x4285e1 MOV	%EBP,%R12D

0x4285e4 MOV	%ECX,%EDX

0x4285e6 MOV	%R11,%RCX

0x4285e9 MOV	%RSI,%R11

0x4285ec NOPL	(%RAX)

(241) 0x4285f0 CMP	%EAX,%EDI

(241) 0x4285f2 CMOVBE	%EDI,%EAX

(241) 0x4285f5 LEA	0x2(%R12),%EDI

(241) 0x4285fa MOV	%EDI,0x6c(%RSP)

(241) 0x4285fe LEA	(%RDX,%RAX,1),%ESI

(241) 0x428601 CMP	%ESI,%EDX

(241) 0x428603 JAE	4288e0

(241) 0x428609 MOVSXD	%EBX,%RBX

(241) 0x42860c LEA	-0x1(%R9),%R10

(241) 0x428610 SUB	$0x1,%EAX

(241) 0x428613 MOV	%ESI,0x74(%RSP)

(241) 0x428617 MOV	0x98(%RSP),%RDI

(241) 0x42861f LEA	0x1(%RBX),%R14

(241) 0x428623 MOV	%R11,0x78(%RSP)

(241) 0x428628 ADD	%R14,%RAX

(241) 0x42862b MOV	%RCX,0x80(%RSP)

(241) 0x428633 MOV	0x10(%RDI),%RDX

(241) 0x428637 MOV	(%RDI),%RDI

(241) 0x42863a MOV	%RAX,0x40(%RSP)

(241) 0x42863f MOV	0x10(%R11),%RAX

(241) 0x428643 MOV	%R10,0x58(%RSP)

(241) 0x428648 MOV	%RDX,0x30(%RSP)

(241) 0x42864d MOV	(%R11),%RDX

(241) 0x428650 MOV	%RDI,0x38(%RSP)

(241) 0x428655 MOV	0xa0(%RSP),%RDI

(241) 0x42865d IMUL	%R10,%RDX

(241) 0x428661 MOV	%R9,(%RSP)

(241) 0x428665 MOV	0x8(%RDI),%R8

(241) 0x428669 MOV	0xa8(%RSP),%RDI

(241) 0x428671 LEA	(%RAX,%RDX,8),%RAX

(241) 0x428675 MOV	(%RCX),%RDX

(241) 0x428678 MOV	(%RDI),%R15

(241) 0x42867b MOV	%R8,0x60(%RSP)

(241) 0x428680 MOV	%RAX,0x50(%RSP)

(241) 0x428685 MOV	0x10(%RCX),%RAX

(241) 0x428689 LEA	-0x8(%R8,%R9,8),%R13

(241) 0x42868e IMUL	%R10,%RDX

(241) 0x428692 MOV	0x10(%RDI),%RBP

(241) 0x428696 MOV	%R15,%RDI

(241) 0x428699 MOV	%RBP,%R15

(241) 0x42869c MOV	%RDI,%RBP

(241) 0x42869f LEA	(%RAX,%RDX,8),%RAX

(241) 0x4286a3 MOV	%RAX,0x48(%RSP)

(241) 0x4286a8 LEA	0x3(%R12),%EAX

(241) 0x4286ad MOV	%EAX,0x70(%RSP)

(241) 0x4286b1 MOV	%R14,%RAX

(241) 0x4286b4 MOV	%R12D,%R14D

(241) 0x4286b7 MOV	%RAX,%R12

(241) 0x4286ba JMP	4287d3

0x4286bf NOP

  (242) 0x4286c0 MOVAPD	%XMM0,%XMM8

  (242) 0x4286c5 CMPSD	$0x2,%XMM2,%XMM0

  (242) 0x4286ca MOVSD	0x1bece(%RIP),%XMM1

  (242) 0x4286d2 ANDPD	%XMM4,%XMM9

  (242) 0x4286d7 ANDPD	%XMM4,%XMM8

  (242) 0x4286dc MOVAPD	%XMM7,%XMM4

  (242) 0x4286e0 MOVSD	(%R13),%XMM10

  (242) 0x4286e6 MOV	0x60(%RSP),%RAX

  (242) 0x4286eb ADDSD	%XMM3,%XMM4

  (242) 0x4286ef MOVSD	%XMM6,0x28(%RSP)

  (242) 0x4286f5 ANDPD	%XMM0,%XMM1

  (242) 0x4286f9 ANDNPD	%XMM3,%XMM0

  (242) 0x4286fd MOVSD	0x1cc7b(%RIP),%XMM3

  (242) 0x428705 MOVSD	%XMM5,0x20(%RSP)

  (242) 0x42870b ORPD	%XMM1,%XMM0

  (242) 0x42870f MOVSD	%XMM7,0x18(%RSP)

  (242) 0x428715 SUBSD	%XMM7,%XMM3

  (242) 0x428719 MOVSD	%XMM0,0x8(%RSP)

  (242) 0x42871f MOVAPD	%XMM4,%XMM0

  (242) 0x428723 MULSD	%XMM9,%XMM0

  (242) 0x428728 MOVSD	%XMM8,0x10(%RSP)

  (242) 0x42872f DIVSD	(%RAX,%R9,8),%XMM0

  (242) 0x428735 MOVAPD	%XMM3,%XMM1

  (242) 0x428739 MULSD	%XMM8,%XMM1

  (242) 0x42873e DIVSD	%XMM10,%XMM1

  (242) 0x428743 ADDSD	%XMM0,%XMM1

  (242) 0x428747 MOVAPD	%XMM9,%XMM0

  (242) 0x42874c MULSD	%XMM10,%XMM1

  (242) 0x428751 DIVSD	0x1cc37(%RIP),%XMM1

  (242) 0x428759 CALL	4041a0 <fmin@plt>

  (242) 0x42875e MOVSD	0x10(%RSP),%XMM8

  (242) 0x428765 MOVAPD	%XMM0,%XMM1

  (242) 0x428769 MOVAPD	%XMM8,%XMM0

  (242) 0x42876e CALL	4041a0 <fmin@plt>

  (242) 0x428773 MOVSD	0x8(%RSP),%XMM1

  (242) 0x428779 MOVSD	0x18(%RSP),%XMM7

  (242) 0x42877f PXOR	%XMM2,%XMM2

  (242) 0x428783 MOVSD	0x1caa5(%RIP),%XMM3

  (242) 0x42878b MOVQ	0x1c45d(%RIP),%XMM4

  (242) 0x428793 MULSD	%XMM0,%XMM1

  (242) 0x428797 MOVSD	0x20(%RSP),%XMM5

  (242) 0x42879d MOVSD	0x28(%RSP),%XMM6

  (242) 0x4287a3 MOVAPD	%XMM3,%XMM0

  (242) 0x4287a7 MOV	0x48(%RSP),%RAX

  (242) 0x4287ac SUBSD	%XMM7,%XMM0

  (242) 0x4287b0 MULSD	%XMM1,%XMM0

  (242) 0x4287b4 ADDSD	%XMM6,%XMM0

  (242) 0x4287b8 MULSD	%XMM5,%XMM0

  (242) 0x4287bc MOVSD	%XMM0,(%RAX,%RBX,8)

  (242) 0x4287c1 MOV	%R12,%RBX

  (242) 0x4287c4 CMP	%R12,0x40(%RSP)

  (242) 0x4287c9 JE	428890

  (242) 0x4287cf ADD	$0x1,%R12

  (242) 0x4287d3 MOV	0x50(%RSP),%RAX

  (242) 0x4287d8 MOVSD	(%RAX,%RBX,8),%XMM5

  (242) 0x4287dd COMISD	%XMM5,%XMM2

  (242) 0x4287e1 JA	428878

  (242) 0x4287e7 MOV	(%RSP),%RCX

  (242) 0x4287eb MOV	0x58(%RSP),%RDX

  (242) 0x4287f0 MOVSXD	%R14D,%RAX

  (242) 0x4287f3 MOVSXD	%R14D,%R9

  (242) 0x4287f6 MOV	0x38(%RSP),%RSI

  (242) 0x4287fb IMUL	%RBP,%RCX

  (242) 0x4287ff MOV	0x30(%RSP),%RDI

  (242) 0x428804 MOVAPD	%XMM5,%XMM7

  (242) 0x428808 IMUL	%RBP,%RAX

  (242) 0x42880c ANDPD	%XMM4,%XMM7

  (242) 0x428810 IMUL	%RDX,%RSI

  (242) 0x428814 IMUL	%RBP,%RDX

  (242) 0x428818 ADD	%RBX,%RCX

  (242) 0x42881b ADD	%RBX,%RAX

  (242) 0x42881e MOVSD	(%R15,%RCX,8),%XMM0

  (242) 0x428824 ADD	%RBX,%RSI

  (242) 0x428827 ADD	%RBX,%RDX

  (242) 0x42882a DIVSD	(%RDI,%RSI,8),%XMM7

  (242) 0x42882f MOVSD	(%R15,%RDX,8),%XMM6

  (242) 0x428835 MOVAPD	%XMM6,%XMM9

  (242) 0x42883a SUBSD	(%R15,%RAX,8),%XMM9

  (242) 0x428840 SUBSD	%XMM6,%XMM0

  (242) 0x428844 MOVAPD	%XMM9,%XMM1

  (242) 0x428849 MULSD	%XMM0,%XMM1

  (242) 0x42884d COMISD	%XMM2,%XMM1

  (242) 0x428851 JA	4286c0

  (242) 0x428857 PXOR	%XMM1,%XMM1

  (242) 0x42885b JMP	4287a3

0x428860 ADD	$0xb8,%RSP

0x428867 POP	%RBX

0x428868 POP	%RBP

0x428869 POP	%R12

0x42886b POP	%R13

0x42886d POP	%R14

0x42886f POP	%R15

0x428871 RET

0x428872 NOPW	(%RAX,%RAX,1)

  (242) 0x428878 MOVSXD	0x70(%RSP),%RAX

  (242) 0x42887d MOV	0x58(%RSP),%RCX

  (242) 0x428882 MOV	(%RSP),%RDX

  (242) 0x428886 MOVSXD	0x6c(%RSP),%R9

  (242) 0x42888b JMP	4287f6

(241) 0x428890 MOV	0x74(%RSP),%ESI

(241) 0x428894 MOV	0x78(%RSP),%R11

(241) 0x428899 MOV	%R14D,%R12D

(241) 0x42889c MOV	0x80(%RSP),%RCX

(241) 0x4288a4 MOV	(%RSP),%R9

(241) 0x4288a8 MOV	0x6c(%RSP),%EDI

(241) 0x4288ac ADD	$0x1,%R12D

(241) 0x4288b0 ADD	$0x1,%R9

(241) 0x4288b4 CMP	%EDI,0x88(%RSP)

(241) 0x4288bb JLE	428860

(241) 0x4288bd MOV	0x94(%RSP),%EDI

(241) 0x4288c4 MOV	0x90(%RSP),%EAX

(241) 0x4288cb MOV	%ESI,%EDX

(241) 0x4288cd MOV	0x8c(%RSP),%EBX

(241) 0x4288d4 SUB	%ESI,%EDI

(241) 0x4288d6 JMP	4285f0

0x4288db NOPL	(%RAX,%RAX,1)

(241) 0x4288e0 MOV	%EDX,%ESI

(241) 0x4288e2 JMP	4288a8

0x4288e4 ADD	$0x1,%EDI

0x4288e7 XOR	%EDX,%EDX

0x4288e9 JMP	428562

0x4288ee XCHG	%AX,%AX

Coverage (%)	Name	Source Location	Module
►96.77+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines
Module	exec

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.00 to 1.50 cycles (8.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 9% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 12.00 to 0.75 cycles (16.00x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 12.00 to 10.50 cycles (1.14x speedup).

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 10.25 cycles (1.17x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
omp_get_thread_num@plt: 1 occurrences►

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 80 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	85
nb uops	84
loop length	314
used x86 registers	15
used mmx registers	0
used xmm registers	3
used ymm registers	0
used zmm registers	0
nb stack references	13

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.50 cycles
front end	10.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.67	5.67	5.67	5.67	5.67	5.67	5.50	5.50	5.50	5.50	0.00	0.00	0.00	0.00	0.00	0.00
cycles	5.67	5.67	5.67	5.67	5.67	5.67	5.50	5.50	5.50	5.50	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	10.50
Dispatch	5.67
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

INT

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	10%

Vector efficiency ratios

INT

all	9%
load	11%
store	8%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	9%
load	11%
store	8%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

2% of peak load performance is reached (6.67 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.33 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4284e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0xb8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0x34(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x30(%RDI),%R14D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x28(%RDI),%EDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x2c(%RBP),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD $0x3,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD $0x1,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %EAX,0x88(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %EDI,0x8c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %EAX,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 428860 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.10+0x380>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
LEA 0x3(%RCX),%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
SUB %R14D,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMP %R13D,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 428860 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.10+0x380>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %R13D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SUB %EDI,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %R15D,0x90(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CALL 404660 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV %EAX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404550 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R12D,%EAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
DIV %EBX	2	0	0	0	2	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV %EAX,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JB 4288e4 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.10+0x404>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
IMUL %EDI,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
ADD %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA (%RDI,%RCX,1),%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %EAX,0x94(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %EAX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JAE 428860 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.10+0x380>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x10(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV 0x8c(%RSP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x18(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOVQ 0x1c65c(%RIP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
PXOR %XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
DIVL 0x90(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	10-17	6	scal (6.3%)
MOV %R8,0x98(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x20(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOVSD 0x1cc7d(%RIP),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
MOV %R8,0xa0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV (%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV %R8,0xa8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
LEA (%RDX,%RSI,1),%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA (%RAX,%R14,1),%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV 0x8(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %R13D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x1(%RDX),%EBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOVSXD %EDX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
SUB %EBX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA 0x1(%RDX),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %EBP,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R11,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RSI,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0xb8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0x1,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 428562 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.10+0x82>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines
Module	exec

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.00 to 1.50 cycles (8.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 10.25 cycles (1.17x speedup).

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
omp_get_thread_num@plt: 1 occurrences►

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 80 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	85
nb uops	84
loop length	314
used x86 registers	15
used mmx registers	0
used xmm registers	3
used ymm registers	0
used zmm registers	0
nb stack references	13

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.50 cycles
front end	10.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.67	5.67	5.67	5.67	5.67	5.67	5.50	5.50	5.50	5.50	0.00	0.00	0.00	0.00	0.00	0.00
cycles	5.67	5.67	5.67	5.67	5.67	5.67	5.50	5.50	5.50	5.50	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	10.50
Dispatch	5.67
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

INT

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	10%

Vector efficiency ratios

INT

all	9%
load	11%
store	8%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	9%
load	11%
store	8%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

2% of peak load performance is reached (6.67 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.33 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4284e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0xb8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0x34(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x30(%RDI),%R14D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x28(%RDI),%EDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x2c(%RBP),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD $0x3,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD $0x1,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %EAX,0x88(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %EDI,0x8c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %EAX,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 428860 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.10+0x380>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
LEA 0x3(%RCX),%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
SUB %R14D,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMP %R13D,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 428860 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.10+0x380>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %R13D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SUB %EDI,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %R15D,0x90(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CALL 404660 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV %EAX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404550 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R12D,%EAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
DIV %EBX	2	0	0	0	2	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV %EAX,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JB 4288e4 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.10+0x404>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
IMUL %EDI,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
ADD %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA (%RDI,%RCX,1),%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %EAX,0x94(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %EAX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JAE 428860 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.10+0x380>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x10(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV 0x8c(%RSP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x18(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOVQ 0x1c65c(%RIP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
PXOR %XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
DIVL 0x90(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	10-17	6	scal (6.3%)
MOV %R8,0x98(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x20(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOVSD 0x1cc7d(%RIP),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
MOV %R8,0xa0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV (%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV %R8,0xa8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
LEA (%RDX,%RSI,1),%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA (%RAX,%R14,1),%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV 0x8(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %R13D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x1(%RDX),%EBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOVSXD %EDX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
SUB %EBX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA 0x1(%RDX),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %EBP,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R11,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RSI,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0xb8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0x1,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 428562 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.10+0x82>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	4.27	1.64
▼Loop 241 - - exec–	0.01	0.01
○Loop 242 - - exec	4.26	1.63

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Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code