OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone ._omp

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: :0-0	Coverage (incl. loops): 4.22% \| (excl. loops): 0.00%

  ***  This Panel is Intentionally Left Blank.  ***

It is due to a lack of debug symbols in the given object
(loop or function).

0x428120 PUSH	%R15

0x428122 PUSH	%R14

0x428124 PUSH	%R13

0x428126 MOV	%RDI,%R13

0x428129 PUSH	%R12

0x42812b PUSH	%RBP

0x42812c PUSH	%RBX

0x42812d SUB	$0x98,%RSP

0x428134 MOV	0x30(%R13),%EAX

0x428138 MOV	0x28(%RDI),%EDI

0x42813b MOV	0x2c(%R13),%EBX

0x42813f LEA	0x1(%RAX),%R12D

0x428143 MOV	0x34(%R13),%EAX

0x428147 MOV	%EDI,0x74(%RSP)

0x42814b ADD	$0x3,%EAX

0x42814e MOV	%EAX,0x70(%RSP)

0x428152 CMP	%EAX,%R12D

0x428155 JGE	428450

0x42815b LEA	0x3(%RBX),%R14D

0x42815f MOV	%EAX,%EBX

0x428161 SUB	%R12D,%EBX

0x428164 CMP	%R14D,%EDI

0x428167 JGE	428450

0x42816d MOV	%R14D,%R15D

0x428170 SUB	%EDI,%R15D

0x428173 MOV	%R15D,0x88(%RSP)

0x42817b CALL	404660 <omp_get_num_threads@plt>

0x428180 MOV	%EAX,%EBP

0x428182 CALL	404550 <omp_get_thread_num@plt>

0x428187 XOR	%EDX,%EDX

0x428189 MOV	%EAX,%ECX

0x42818b MOV	%R15D,%EAX

0x42818e IMUL	%EBX,%EAX

0x428191 DIV	%EBP

0x428193 MOV	%EAX,%ESI

0x428195 CMP	%EDX,%ECX

0x428197 JB	4284d3

0x42819d IMUL	%ESI,%ECX

0x4281a0 LEA	(%RCX,%RDX,1),%EDI

0x4281a3 LEA	(%RSI,%RDI,1),%ECX

0x4281a6 CMP	%ECX,%EDI

0x4281a8 JAE	428450

0x4281ae XOR	%EDX,%EDX

0x4281b0 MOV	%EDI,%EAX

0x4281b2 MOV	0x8(%R13),%R8

0x4281b6 MOV	0x10(%R13),%R10

0x4281ba DIVL	0x88(%RSP)

0x4281c1 MOV	%ECX,0x8c(%RSP)

0x4281c8 MOVQ	0x1ca20(%RIP),%XMM4

0x4281d0 MOVSD	0x1d058(%RIP),%XMM3

0x4281d8 PXOR	%XMM2,%XMM2

0x4281dc MOV	%R10,%RCX

0x4281df MOV	%EAX,%R9D

0x4281e2 MOV	0x74(%RSP),%EAX

0x4281e6 ADD	%R12D,%R9D

0x4281e9 LEA	(%RDX,%RAX,1),%EBP

0x4281ec MOV	0x20(%R13),%RAX

0x4281f0 MOV	%R14D,%EDX

0x4281f3 MOVSXD	%R9D,%R11

0x4281f6 SUB	%EBP,%EDX

0x4281f8 MOV	%RAX,0x78(%RSP)

0x4281fd MOV	(%R13),%RAX

0x428201 CMP	%EDX,%ESI

0x428203 CMOVBE	%ESI,%EDX

0x428206 MOV	%RAX,0x80(%RSP)

0x42820e MOV	0x18(%R13),%RAX

0x428212 LEA	(%RDI,%RDX,1),%R9D

0x428216 MOV	%RAX,%RBX

0x428219 MOV	%R8,%RAX

0x42821c MOV	%RBX,%R8

0x42821f CMP	%R9D,%EDI

0x428222 JAE	4284ce

0x428228 NOPL	(%RAX,%RAX,1)

  (238) 0x428230 MOV	(%RCX),%RDI

  (238) 0x428233 LEA	0x1(%RBP),%EBX

  (238) 0x428236 SUB	$0x1,%EDX

  (238) 0x428239 MOVSXD	%EBP,%RBP

  (238) 0x42823c MOV	0x80(%RSP),%RSI

  (238) 0x428244 MOVSXD	%EBX,%RBX

  (238) 0x428247 MOV	%RAX,0x50(%RSP)

  (238) 0x42824c IMUL	%R11,%RDI

  (238) 0x428250 MOV	%R9D,0x4c(%RSP)

  (238) 0x428255 MOV	0x10(%RCX),%R15

  (238) 0x428259 MOV	0x10(%RSI),%R12

  (238) 0x42825d MOV	(%RSI),%R13

  (238) 0x428260 MOV	%RCX,0x58(%RSP)

  (238) 0x428265 MOV	%R8,0x60(%RSP)

  (238) 0x42826a MOV	%RDI,0x30(%RSP)

  (238) 0x42826f MOV	0x78(%RSP),%RDI

  (238) 0x428274 IMUL	%R11,%R13

  (238) 0x428278 MOV	%R11,0x68(%RSP)

  (238) 0x42827d MOV	0x8(%RDI),%R14

  (238) 0x428281 LEA	0x2(%RBP,%RDX,1),%RDI

  (238) 0x428286 MOV	(%RAX),%RBP

  (238) 0x428289 MOV	0x10(%RAX),%RDX

  (238) 0x42828d MOV	%RBX,%RAX

  (238) 0x428290 MOV	%RDI,0x38(%RSP)

  (238) 0x428295 IMUL	%R11,%RBP

  (238) 0x428299 MOV	%R14,%RBX

  (238) 0x42829c MOV	%R12,%R14

  (238) 0x42829f LEA	(%RDX,%RBP,8),%RSI

  (238) 0x4282a3 MOV	(%R8),%RBP

  (238) 0x4282a6 MOV	0x10(%R8),%RDX

  (238) 0x4282aa MOV	%RSI,0x40(%RSP)

  (238) 0x4282af IMUL	%R11,%RBP

  (238) 0x4282b3 LEA	(%RDX,%RBP,8),%RBP

  (238) 0x4282b7 MOV	%RBP,%R12

  (238) 0x4282ba MOV	%R13,%RBP

  (238) 0x4282bd MOV	%RAX,%R13

  (238) 0x4282c0 JMP	4283d1

0x4282c5 NOPL	(%RAX)

    (239) 0x4282c8 MOVAPD	%XMM0,%XMM8

    (239) 0x4282cd CMPSD	$0x2,%XMM2,%XMM0

    (239) 0x4282d2 MOVSD	0x1c2c6(%RIP),%XMM1

    (239) 0x4282da ANDPD	%XMM4,%XMM9

    (239) 0x4282df ANDPD	%XMM4,%XMM8

    (239) 0x4282e4 MOVAPD	%XMM7,%XMM4

    (239) 0x4282e8 MOVSD	-0x8(%RBX,%R13,8),%XMM10

    (239) 0x4282ef MOVSD	%XMM6,0x28(%RSP)

    (239) 0x4282f5 ADDSD	%XMM3,%XMM4

    (239) 0x4282f9 MOVSD	%XMM5,0x20(%RSP)

    (239) 0x4282ff ANDPD	%XMM0,%XMM1

    (239) 0x428303 ANDNPD	%XMM3,%XMM0

    (239) 0x428307 MOVSD	0x1d071(%RIP),%XMM3

    (239) 0x42830f MOVSD	%XMM7,0x18(%RSP)

    (239) 0x428315 ORPD	%XMM1,%XMM0

    (239) 0x428319 MOVSD	%XMM8,0x10(%RSP)

    (239) 0x428320 SUBSD	%XMM7,%XMM3

    (239) 0x428324 MOVSD	%XMM0,0x8(%RSP)

    (239) 0x42832a MOVAPD	%XMM4,%XMM0

    (239) 0x42832e MULSD	%XMM9,%XMM0

    (239) 0x428333 DIVSD	(%RBX,%R9,8),%XMM0

    (239) 0x428339 MOVAPD	%XMM3,%XMM1

    (239) 0x42833d MULSD	%XMM8,%XMM1

    (239) 0x428342 DIVSD	%XMM10,%XMM1

    (239) 0x428347 ADDSD	%XMM0,%XMM1

    (239) 0x42834b MOVAPD	%XMM9,%XMM0

    (239) 0x428350 MULSD	%XMM10,%XMM1

    (239) 0x428355 DIVSD	0x1d033(%RIP),%XMM1

    (239) 0x42835d CALL	4041a0 <fmin@plt>

    (239) 0x428362 MOVSD	0x10(%RSP),%XMM8

    (239) 0x428369 MOVAPD	%XMM0,%XMM1

    (239) 0x42836d MOVAPD	%XMM8,%XMM0

    (239) 0x428372 CALL	4041a0 <fmin@plt>

    (239) 0x428377 MOVSD	0x8(%RSP),%XMM1

    (239) 0x42837d MOVSD	0x18(%RSP),%XMM7

    (239) 0x428383 PXOR	%XMM2,%XMM2

    (239) 0x428387 MOVSD	0x1cea1(%RIP),%XMM3

    (239) 0x42838f MOVQ	0x1c859(%RIP),%XMM4

    (239) 0x428397 MULSD	%XMM0,%XMM1

    (239) 0x42839b MOVSD	0x20(%RSP),%XMM5

    (239) 0x4283a1 MOVSD	0x28(%RSP),%XMM6

    (239) 0x4283a7 MOVAPD	%XMM3,%XMM0

    (239) 0x4283ab SUBSD	%XMM7,%XMM0

    (239) 0x4283af MULSD	%XMM1,%XMM0

    (239) 0x4283b3 ADDSD	%XMM6,%XMM0

    (239) 0x4283b7 MULSD	%XMM5,%XMM0

    (239) 0x4283bb MOVSD	%XMM0,-0x8(%R12,%R13,8)

    (239) 0x4283c2 ADD	$0x1,%R13

    (239) 0x4283c6 CMP	%R13,0x38(%RSP)

    (239) 0x4283cb JE	428480

    (239) 0x4283d1 MOV	0x40(%RSP),%RAX

    (239) 0x4283d6 LEA	-0x1(%R13),%RCX

    (239) 0x4283da MOVSD	-0x8(%RAX,%R13,8),%XMM5

    (239) 0x4283e1 COMISD	%XMM5,%XMM2

    (239) 0x4283e5 JA	428468

    (239) 0x4283eb LEA	-0x2(%R13),%EDX

    (239) 0x4283ef MOV	%R13,%R10

    (239) 0x4283f2 MOVSXD	%EDX,%R9

    (239) 0x4283f5 MOV	0x30(%RSP),%RAX

    (239) 0x4283fa ADD	%RBP,%R10

    (239) 0x4283fd MOVSXD	%EDX,%RDX

    (239) 0x428400 MOVAPD	%XMM5,%XMM7

    (239) 0x428404 ADD	%RBP,%RDX

    (239) 0x428407 MOVSD	(%R14,%R10,8),%XMM0

    (239) 0x42840d ANDPD	%XMM4,%XMM7

    (239) 0x428411 LEA	(%RAX,%RCX,1),%R11

    (239) 0x428415 ADD	%RBP,%RCX

    (239) 0x428418 MOVSD	(%R14,%RCX,8),%XMM6

    (239) 0x42841e DIVSD	(%R15,%R11,8),%XMM7

    (239) 0x428424 MOVAPD	%XMM6,%XMM9

    (239) 0x428429 SUBSD	(%R14,%RDX,8),%XMM9

    (239) 0x42842f SUBSD	%XMM6,%XMM0

    (239) 0x428433 MOVAPD	%XMM9,%XMM1

    (239) 0x428438 MULSD	%XMM0,%XMM1

    (239) 0x42843c COMISD	%XMM2,%XMM1

    (239) 0x428440 JA	4282c8

    (239) 0x428446 PXOR	%XMM1,%XMM1

    (239) 0x42844a JMP	4283a7

0x42844f NOP

0x428450 ADD	$0x98,%RSP

0x428457 POP	%RBX

0x428458 POP	%RBP

0x428459 POP	%R12

0x42845b POP	%R13

0x42845d POP	%R14

0x42845f POP	%R15

0x428461 RET

0x428462 NOPW	(%RAX,%RAX,1)

    (239) 0x428468 MOV	%RCX,%R10

    (239) 0x42846b MOVSXD	%R13D,%R9

    (239) 0x42846e LEA	0x1(%R13),%EDX

    (239) 0x428472 MOV	%R13,%RCX

    (239) 0x428475 JMP	4283f5

0x42847a NOPW	(%RAX,%RAX,1)

  (238) 0x428480 MOV	0x4c(%RSP),%R9D

  (238) 0x428485 MOV	0x50(%RSP),%RAX

  (238) 0x42848a MOV	0x58(%RSP),%RCX

  (238) 0x42848f MOV	0x60(%RSP),%R8

  (238) 0x428494 MOV	0x68(%RSP),%R11

  (238) 0x428499 ADD	$0x1,%R11

  (238) 0x42849d CMP	%R11D,0x70(%RSP)

  (238) 0x4284a2 JLE	428450

  (238) 0x4284a4 MOV	0x8c(%RSP),%ESI

  (238) 0x4284ab MOV	0x88(%RSP),%EDX

  (238) 0x4284b2 MOV	%R9D,%EDI

  (238) 0x4284b5 MOV	0x74(%RSP),%EBP

  (238) 0x4284b9 SUB	%R9D,%ESI

  (238) 0x4284bc CMP	%EDX,%ESI

  (238) 0x4284be CMOVBE	%ESI,%EDX

  (238) 0x4284c1 LEA	(%RDI,%RDX,1),%R9D

  (238) 0x4284c5 CMP	%R9D,%EDI

  (238) 0x4284c8 JB	428230

(240) 0x4284ce MOV	%EDI,%R9D

(240) 0x4284d1 JMP	428499

0x4284d3 ADD	$0x1,%ESI

0x4284d6 XOR	%EDX,%EDX

0x4284d8 JMP	42819d

0x4284dd NOPL	(%RAX)

Coverage (%)	Name	Source Location	Module
►96.82+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines
Module	exec

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.00 to 1.67 cycles (7.20x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 8% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 12.00 to 0.75 cycles (16.00x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 12.00 to 11.00 cycles (1.09x speedup).

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 10.75 cycles (1.12x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
omp_get_thread_num@plt: 1 occurrences►

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVBE: 1 occurrences►
DIV: 2 occurrences►

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 80 bytes. The binary function is storing 32 bytes.

General properties

nb instructions	89
nb uops	88
loop length	319
used x86 registers	16
used mmx registers	0
used xmm registers	3
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	11.00 cycles
front end	11.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	6.33	6.33	6.33	6.33	6.33	6.33	5.25	5.25	5.25	5.25	0.00	0.00	0.00	0.00	0.00	0.00
cycles	6.33	6.33	6.33	6.33	6.33	6.33	5.25	5.25	5.25	5.25	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	11.00
Dispatch	6.33
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

INT

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	8%

Vector efficiency ratios

INT

all	8%
load	10%
store	8%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	8%
load	11%
store	8%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

2% of peak load performance is reached (6.67 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (2.67 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 428120

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x98,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0x30(%R13),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x28(%RDI),%EDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x2c(%R13),%EBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
LEA 0x1(%RAX),%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV 0x34(%R13),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %EDI,0x74(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
ADD $0x3,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %EAX,0x70(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %EAX,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 428450 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.6+0x330>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
LEA 0x3(%RBX),%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %EAX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %R12D,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
CMP %R14D,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 428450 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.6+0x330>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %R14D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SUB %EDI,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %R15D,0x88(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CALL 404660 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV %EAX,%EBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404550 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %EBX,%EAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
DIV %EBP	2	0	0	0	2	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JB 4284d3 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.6+0x3b3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
IMUL %ESI,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
LEA (%RCX,%RDX,1),%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA (%RSI,%RDI,1),%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
CMP %ECX,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JAE 428450 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.6+0x330>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EDI,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x8(%R13),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV 0x10(%R13),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
DIVL 0x88(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	10-17	6	scal (6.3%)
MOV %ECX,0x8c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVQ 0x1ca20(%RIP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOVSD 0x1d058(%RIP),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
PXOR %XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
MOV %R10,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %EAX,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV 0x74(%RSP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %R12D,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
LEA (%RDX,%RAX,1),%EBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV 0x20(%R13),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %R14D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVSXD %R9D,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
SUB %EBP,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %RAX,0x78(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV (%R13),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP %EDX,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMOVBE %ESI,%EDX	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	1	0.33	N/A
MOV %RAX,0x80(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x18(%R13),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
LEA (%RDI,%RDX,1),%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RBX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
CMP %R9D,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JAE 4284ce <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.6+0x3ae>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0x98,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0x1,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 42819d <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.6+0x7d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines
Module	exec

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.00 to 1.67 cycles (7.20x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 10.75 cycles (1.12x speedup).

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
omp_get_thread_num@plt: 1 occurrences►

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVBE: 1 occurrences►
DIV: 2 occurrences►

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 80 bytes. The binary function is storing 32 bytes.

General properties

nb instructions	89
nb uops	88
loop length	319
used x86 registers	16
used mmx registers	0
used xmm registers	3
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	11.00 cycles
front end	11.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	6.33	6.33	6.33	6.33	6.33	6.33	5.25	5.25	5.25	5.25	0.00	0.00	0.00	0.00	0.00	0.00
cycles	6.33	6.33	6.33	6.33	6.33	6.33	5.25	5.25	5.25	5.25	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	11.00
Dispatch	6.33
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

INT

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	8%

Vector efficiency ratios

INT

all	8%
load	10%
store	8%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	8%
load	11%
store	8%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

2% of peak load performance is reached (6.67 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (2.67 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 428120

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x98,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0x30(%R13),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x28(%RDI),%EDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x2c(%R13),%EBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
LEA 0x1(%RAX),%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV 0x34(%R13),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %EDI,0x74(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
ADD $0x3,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %EAX,0x70(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %EAX,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 428450 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.6+0x330>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
LEA 0x3(%RBX),%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %EAX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %R12D,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
CMP %R14D,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 428450 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.6+0x330>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %R14D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SUB %EDI,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %R15D,0x88(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CALL 404660 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV %EAX,%EBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404550 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %EBX,%EAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
DIV %EBP	2	0	0	0	2	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JB 4284d3 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.6+0x3b3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
IMUL %ESI,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
LEA (%RCX,%RDX,1),%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA (%RSI,%RDI,1),%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
CMP %ECX,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JAE 428450 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.6+0x330>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EDI,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x8(%R13),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV 0x10(%R13),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
DIVL 0x88(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	10-17	6	scal (6.3%)
MOV %ECX,0x8c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVQ 0x1ca20(%RIP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOVSD 0x1d058(%RIP),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
PXOR %XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
MOV %R10,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %EAX,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV 0x74(%RSP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD %R12D,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
LEA (%RDX,%RAX,1),%EBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV 0x20(%R13),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %R14D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVSXD %R9D,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
SUB %EBP,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %RAX,0x78(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV (%R13),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP %EDX,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMOVBE %ESI,%EDX	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	1	0.33	N/A
MOV %RAX,0x80(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x18(%R13),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
LEA (%RDI,%RDX,1),%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RBX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
CMP %R9D,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JAE 4284ce <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.6+0x3ae>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0x98,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0x1,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 42819d <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.6+0x7d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	4.22	1.62
▼Loop 240 - - exec–	0.00	0.00
▼Loop 238 - - exec–	0.01	0.01
○Loop 239 - - exec	4.21	1.61

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Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code