OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone ._omp

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: :0-0	Coverage (incl. loops): 2.99% \| (excl. loops): 0.00%

  ***  This Panel is Intentionally Left Blank.  ***

It is due to a lack of debug symbols in the given object
(loop or function).

0x427820 PUSH	%R15

0x427822 PUSH	%R14

0x427824 PUSH	%R13

0x427826 PUSH	%R12

0x427828 PUSH	%RBP

0x427829 PUSH	%RBX

0x42782a MOV	%RDI,%RBX

0x42782d SUB	$0xb8,%RSP

0x427834 MOV	0x34(%RDI),%EAX

0x427837 MOV	0x28(%RDI),%ECX

0x42783a MOV	0x30(%RDI),%EBP

0x42783d ADD	$0x4,%EAX

0x427840 LEA	0x1(%RCX),%EDI

0x427843 MOV	0x2c(%RBX),%ECX

0x427846 MOV	%EAX,0x78(%RSP)

0x42784a MOV	%EDI,0x7c(%RSP)

0x42784e CMP	%EAX,%EBP

0x427850 JGE	427c20

0x427856 MOV	%EAX,%R13D

0x427859 LEA	0x3(%RCX),%R14D

0x42785d SUB	%EBP,%R13D

0x427860 CMP	%R14D,%EDI

0x427863 JGE	427c20

0x427869 MOV	%R14D,%R15D

0x42786c SUB	%EDI,%R15D

0x42786f MOV	%R15D,0x80(%RSP)

0x427877 CALL	404660 <omp_get_num_threads@plt>

0x42787c MOV	%EAX,%R12D

0x42787f CALL	404550 <omp_get_thread_num@plt>

0x427884 XOR	%EDX,%EDX

0x427886 MOV	%EAX,%ECX

0x427888 MOV	%R15D,%EAX

0x42788b IMUL	%R13D,%EAX

0x42788f DIV	%R12D

0x427892 MOV	%EAX,%ESI

0x427894 CMP	%EDX,%ECX

0x427896 JB	427c32

0x42789c IMUL	%ESI,%ECX

0x42789f ADD	%EDX,%ECX

0x4278a1 LEA	(%RSI,%RCX,1),%EAX

0x4278a4 MOV	%EAX,0x84(%RSP)

0x4278ab CMP	%EAX,%ECX

0x4278ad JAE	427c20

0x4278b3 MOV	%ECX,%EAX

0x4278b5 XOR	%EDX,%EDX

0x4278b7 MOV	0x7c(%RSP),%EDI

0x4278bb MOVSD	0x1dab5(%RIP),%XMM3

0x4278c3 DIVL	0x80(%RSP)

0x4278ca MOVAPD	%XMM3,%XMM2

0x4278ce UNPCKLPD	%XMM2,%XMM2

0x4278d2 ADD	%EDX,%EDI

0x4278d4 MOV	%R14D,%EDX

0x4278d7 ADD	%EBP,%EAX

0x4278d9 MOV	%EDI,0x40(%RSP)

0x4278dd SUB	%EDI,%EDX

0x4278df MOV	(%RBX),%RDI

0x4278e2 MOVSXD	%EAX,%R14

0x4278e5 MOV	%RDI,0x88(%RSP)

0x4278ed MOV	0x20(%RBX),%RDI

0x4278f1 MOV	%RDI,0x90(%RSP)

0x4278f9 MOV	0x10(%RBX),%RDI

0x4278fd MOV	%RDI,0x98(%RSP)

0x427905 MOV	0x8(%RBX),%RDI

0x427909 MOV	0x18(%RBX),%RBX

0x42790d MOV	%RDI,0xa0(%RSP)

0x427915 MOV	%RBX,0xa8(%RSP)

0x42791d NOPL	(%RAX)

(232) 0x427920 CMP	%EDX,%ESI

(232) 0x427922 CMOVBE	%ESI,%EDX

(232) 0x427925 LEA	(%RCX,%RDX,1),%EAX

(232) 0x427928 MOV	%EDX,0x4(%RSP)

(232) 0x42792c MOV	%EAX,0x44(%RSP)

(232) 0x427930 CMP	%EAX,%ECX

(232) 0x427932 JAE	427bee

(232) 0x427938 MOV	0x88(%RSP),%RSI

(232) 0x427940 LEA	-0x1(%R14),%EAX

(232) 0x427944 MOV	0xa0(%RSP),%R15

(232) 0x42794c CLTQ

(232) 0x42794e MOV	0xa8(%RSP),%R8

(232) 0x427956 MOV	(%RSI),%RCX

(232) 0x427959 MOV	0x10(%RSI),%RBX

(232) 0x42795d MOV	%RAX,%RDI

(232) 0x427960 MOV	0x90(%RSP),%RSI

(232) 0x427968 IMUL	%RCX,%RDI

(232) 0x42796c MOV	%RBX,0x68(%RSP)

(232) 0x427971 MOV	(%RSI),%RDX

(232) 0x427974 MOV	0x10(%RSI),%R9

(232) 0x427978 MOV	%RAX,%RSI

(232) 0x42797b IMUL	%R14,%RCX

(232) 0x42797f IMUL	%RDX,%RSI

(232) 0x427983 MOV	%RDI,0x70(%RSP)

(232) 0x427988 IMUL	%R14,%RDX

(232) 0x42798c MOV	%R9,0x58(%RSP)

(232) 0x427991 MOV	%RCX,0x50(%RSP)

(232) 0x427996 MOV	%RSI,0x60(%RSP)

(232) 0x42799b MOV	%RDX,0x48(%RSP)

(232) 0x4279a0 MOV	%RDX,%R10

(232) 0x4279a3 MOV	0x98(%RSP),%RDX

(232) 0x4279ab MOV	0x10(%RDX),%R11

(232) 0x4279af MOV	(%RDX),%RDX

(232) 0x4279b2 IMUL	%R14,%RDX

(232) 0x4279b6 MOV	%R11,0x30(%RSP)

(232) 0x4279bb MOV	0x10(%R15),%R11

(232) 0x4279bf MOV	%R11,0x8(%RSP)

(232) 0x4279c4 MOV	%RDX,0x38(%RSP)

(232) 0x4279c9 MOV	(%R15),%RDX

(232) 0x4279cc MOV	0x10(%R8),%R15

(232) 0x4279d0 MOV	%RDX,%R11

(232) 0x4279d3 IMUL	%RDX,%RAX

(232) 0x4279d7 MOV	%R15,0x20(%RSP)

(232) 0x4279dc MOV	(%R8),%R15

(232) 0x4279df IMUL	%R14,%R11

(232) 0x4279e3 IMUL	%R14,%R15

(232) 0x4279e7 CMPL	$0x1,0x4(%RSP)

(232) 0x4279ec MOV	%RAX,0x28(%RSP)

(232) 0x4279f1 MOV	%R11,0x10(%RSP)

(232) 0x4279f6 MOV	%R15,0x18(%RSP)

(232) 0x4279fb JE	427b27

(232) 0x427a01 MOVSXD	0x40(%RSP),%RAX

(232) 0x427a06 MOV	%RBX,%R8

(232) 0x427a09 LEA	(%R10,%RAX,1),%RDX

(232) 0x427a0d ADD	%RAX,%RSI

(232) 0x427a10 ADD	%RAX,%RDI

(232) 0x427a13 ADD	%RAX,%RCX

(232) 0x427a16 SAL	$0x3,%RSI

(232) 0x427a1a SAL	$0x3,%RDX

(232) 0x427a1e SAL	$0x3,%RDI

(232) 0x427a22 SAL	$0x3,%RCX

(232) 0x427a26 LEA	(%R9,%RSI,1),%R13

(232) 0x427a2a LEA	(%R9,%RDX,1),%RBP

(232) 0x427a2e LEA	-0x8(%R9,%RSI,1),%R11

(232) 0x427a33 LEA	-0x8(%R9,%RDX,1),%R9

(232) 0x427a38 MOV	0x38(%RSP),%RDX

(232) 0x427a3d MOV	0x10(%RSP),%RSI

(232) 0x427a42 LEA	(%RBX,%RDI,1),%R15

(232) 0x427a46 LEA	(%RBX,%RCX,1),%R12

(232) 0x427a4a LEA	-0x8(%RBX,%RDI,1),%RBX

(232) 0x427a4f MOV	0x30(%RSP),%RDI

(232) 0x427a54 ADD	%RAX,%RDX

(232) 0x427a57 LEA	-0x8(%R8,%RCX,1),%R10

(232) 0x427a5c MOV	0x8(%RSP),%RCX

(232) 0x427a61 LEA	(%RDI,%RDX,8),%R8

(232) 0x427a65 MOV	0x28(%RSP),%RDI

(232) 0x427a6a LEA	(%RDI,%RAX,1),%RDX

(232) 0x427a6e LEA	(%RCX,%RDX,8),%RDI

(232) 0x427a72 LEA	(%RSI,%RAX,1),%RDX

(232) 0x427a76 LEA	(%RCX,%RDX,8),%RSI

(232) 0x427a7a MOV	0x18(%RSP),%RCX

(232) 0x427a7f MOV	0x4(%RSP),%EDX

(232) 0x427a83 ADD	%RCX,%RAX

(232) 0x427a86 MOV	0x20(%RSP),%RCX

(232) 0x427a8b SHR	$0x1,%EDX

(232) 0x427a8d SAL	$0x4,%RDX

(232) 0x427a91 LEA	(%RCX,%RAX,8),%RCX

(232) 0x427a95 XOR	%EAX,%EAX

(232) 0x427a97 NOPW	(%RAX,%RAX,1)

  (233) 0x427aa0 MOVUPD	(%R12,%RAX,1),%XMM4

  (233) 0x427aa6 MOVUPD	(%R15,%RAX,1),%XMM5

  (233) 0x427aac MOVUPD	(%RBP,%RAX,1),%XMM0

  (233) 0x427ab2 MOVUPD	(%R13,%RAX,1),%XMM1

  (233) 0x427ab9 MOVUPD	(%RBX,%RAX,1),%XMM6

  (233) 0x427abe MOVUPD	(%R10,%RAX,1),%XMM7

  (233) 0x427ac4 MULPD	%XMM5,%XMM1

  (233) 0x427ac8 MULPD	%XMM4,%XMM0

  (233) 0x427acc ADDPD	%XMM1,%XMM0

  (233) 0x427ad0 MOVUPD	(%R11,%RAX,1),%XMM1

  (233) 0x427ad6 MULPD	%XMM6,%XMM1

  (233) 0x427ada ADDPD	%XMM1,%XMM0

  (233) 0x427ade MOVUPD	(%R9,%RAX,1),%XMM1

  (233) 0x427ae4 MULPD	%XMM7,%XMM1

  (233) 0x427ae8 ADDPD	%XMM1,%XMM0

  (233) 0x427aec MULPD	%XMM2,%XMM0

  (233) 0x427af0 MOVUPS	%XMM0,(%R8,%RAX,1)

  (233) 0x427af5 MOVUPD	(%RDI,%RAX,1),%XMM4

  (233) 0x427afa MOVUPD	(%RSI,%RAX,1),%XMM5

  (233) 0x427aff SUBPD	%XMM4,%XMM0

  (233) 0x427b03 ADDPD	%XMM5,%XMM0

  (233) 0x427b07 MOVUPS	%XMM0,(%RCX,%RAX,1)

  (233) 0x427b0b ADD	$0x10,%RAX

  (233) 0x427b0f CMP	%RAX,%RDX

  (233) 0x427b12 JNE	427aa0

(232) 0x427b14 MOV	0x4(%RSP),%EAX

(232) 0x427b18 TEST	$0x1,%AL

(232) 0x427b1a JE	427bea

(232) 0x427b20 AND	$-0x2,%EAX

(232) 0x427b23 ADD	%EAX,0x40(%RSP)

(232) 0x427b27 MOVSXD	0x40(%RSP),%RAX

(232) 0x427b2c MOV	0x48(%RSP),%R10

(232) 0x427b31 MOV	0x50(%RSP),%R11

(232) 0x427b36 MOV	0x58(%RSP),%RBX

(232) 0x427b3b MOV	0x68(%RSP),%RDI

(232) 0x427b40 MOV	0x60(%RSP),%R15

(232) 0x427b45 LEA	(%R10,%RAX,1),%RSI

(232) 0x427b49 LEA	-0x1(%RAX),%EDX

(232) 0x427b4c MOV	0x70(%RSP),%R8

(232) 0x427b51 LEA	(%R11,%RAX,1),%RCX

(232) 0x427b55 MOVSD	(%RBX,%RSI,8),%XMM0

(232) 0x427b5a MOVSXD	%EDX,%RDX

(232) 0x427b5d MULSD	(%RDI,%RCX,8),%XMM0

(232) 0x427b62 LEA	(%R15,%RAX,1),%RSI

(232) 0x427b66 LEA	(%R8,%RAX,1),%RCX

(232) 0x427b6a MOVSD	(%RBX,%RSI,8),%XMM1

(232) 0x427b6f LEA	(%R8,%RDX,1),%RSI

(232) 0x427b73 MULSD	(%RDI,%RCX,8),%XMM1

(232) 0x427b78 LEA	(%R15,%RDX,1),%RCX

(232) 0x427b7c ADDSD	%XMM1,%XMM0

(232) 0x427b80 MOVSD	(%RBX,%RCX,8),%XMM1

(232) 0x427b85 MULSD	(%RDI,%RSI,8),%XMM1

(232) 0x427b8a LEA	(%R10,%RDX,1),%RCX

(232) 0x427b8e ADD	%R11,%RDX

(232) 0x427b91 ADDSD	%XMM1,%XMM0

(232) 0x427b95 MOVSD	(%RBX,%RCX,8),%XMM1

(232) 0x427b9a MULSD	(%RDI,%RDX,8),%XMM1

(232) 0x427b9f MOV	0x38(%RSP),%RDX

(232) 0x427ba4 MOV	0x30(%RSP),%RDI

(232) 0x427ba9 MOV	0x28(%RSP),%RCX

(232) 0x427bae MOV	0x10(%RSP),%RBX

(232) 0x427bb3 ADD	%RAX,%RDX

(232) 0x427bb6 ADD	%RAX,%RCX

(232) 0x427bb9 ADD	%RAX,%RBX

(232) 0x427bbc ADDSD	%XMM1,%XMM0

(232) 0x427bc0 MULSD	%XMM3,%XMM0

(232) 0x427bc4 MOVSD	%XMM0,(%RDI,%RDX,8)

(232) 0x427bc9 MOV	0x8(%RSP),%RDI

(232) 0x427bce MOV	0x18(%RSP),%RDX

(232) 0x427bd3 SUBSD	(%RDI,%RCX,8),%XMM0

(232) 0x427bd8 ADDSD	(%RDI,%RBX,8),%XMM0

(232) 0x427bdd ADD	%RAX,%RDX

(232) 0x427be0 MOV	0x20(%RSP),%RAX

(232) 0x427be5 MOVSD	%XMM0,(%RAX,%RDX,8)

(232) 0x427bea MOV	0x44(%RSP),%ECX

(232) 0x427bee ADD	$0x1,%R14

(232) 0x427bf2 CMP	%R14D,0x78(%RSP)

(232) 0x427bf7 JLE	427c20

(232) 0x427bf9 MOV	0x84(%RSP),%ESI

(232) 0x427c00 MOV	0x7c(%RSP),%EAX

(232) 0x427c04 MOV	0x80(%RSP),%EDX

(232) 0x427c0b MOV	%EAX,0x40(%RSP)

(232) 0x427c0f SUB	%ECX,%ESI

(232) 0x427c11 JMP	427920

0x427c16 NOPW	%CS:(%RAX,%RAX,1)

0x427c20 ADD	$0xb8,%RSP

0x427c27 POP	%RBX

0x427c28 POP	%RBP

0x427c29 POP	%R12

0x427c2b POP	%R13

0x427c2d POP	%R14

0x427c2f POP	%R15

0x427c31 RET

0x427c32 ADD	$0x1,%ESI

0x427c35 XOR	%EDX,%EDX

0x427c37 JMP	42789c

0x427c3c NOPL	(%RAX)

Coverage (%)	Name	Source Location	Module
►96.81+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►1.60+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	advec_mom_kernel(int, int, int[...]		exec
○	advec_mom_driver(global_variab[...]		exec
○	advection(global_variables&)		exec
○	hydro(global_variables&, paral[...]		exec
○	main		exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec
►1.53+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	advec_mom_kernel(int, int, int[...]		exec
○	advec_mom_driver(global_variab[...]		exec
○	advection(global_variables&)		exec
○	hydro(global_variables&, paral[...]		exec
○	main		exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines
Module	exec

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.00 to 1.33 cycles (9.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 8% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 12.00 to 0.75 cycles (16.00x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 12.00 to 10.13 cycles (1.19x speedup).

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 9.88 cycles (1.22x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
omp_get_thread_num@plt: 1 occurrences►

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 72 bytes. The binary function is storing 60 bytes.

General properties

nb instructions	80
nb uops	81
loop length	298
used x86 registers	12
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	10

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.13 cycles
front end	10.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.33	5.33	5.33	5.33	5.33	5.33	6.00	6.00	6.00	6.00	0.25	0.25	0.25	0.25	0.00	0.00
cycles	5.33	5.33	5.33	5.33	5.33	5.33	6.00	6.00	6.00	6.00	0.25	0.25	0.25	0.25	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	10.13
Dispatch	6.00
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	33%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	7%

Vector efficiency ratios

INT

all	7%
load	6%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	16%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

INT+FP

all	8%
load	8%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

2% of peak load performance is reached (6.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (5.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 427820

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	Latency	Recip. throughput	Vectorization
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB $0xb8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x34(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x28(%RDI),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x30(%RDI),%EBP	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
ADD $0x4,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x1(%RCX),%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV 0x2c(%RBX),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %EAX,0x78(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOV %EDI,0x7c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
CMP %EAX,%EBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 427c20 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.9+0x400>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
LEA 0x3(%RCX),%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB %EBP,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CMP %R14D,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 427c20 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.9+0x400>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R14D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SUB %EDI,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %R15D,0x80(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
CALL 404660 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404550 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R13D,%EAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
DIV %R12D	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JB 427c32 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.9+0x412>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %ESI,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADD %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RSI,%RCX,1),%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %EAX,0x84(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
CMP %EAX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JAE 427c20 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.9+0x400>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV 0x7c(%RSP),%EDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVSD 0x1dab5(%RIP),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
DIVL 0x80(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	0	0	0	0	10-17	6	scal (6.3%)
MOVAPD %XMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
UNPCKLPD %XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
ADD %EDX,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R14D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
ADD %EBP,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EDI,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
SUB %EDI,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV (%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVSXD %EAX,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %RDI,0x88(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x20(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RDI,0x90(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x10(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RDI,0x98(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x8(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x18(%RBX),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RDI,0xa0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %RBX,0xa8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0xb8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD $0x1,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
JMP 42789c <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.9+0x7c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines
Module	exec

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.00 to 1.33 cycles (9.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 9.88 cycles (1.22x speedup).

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
omp_get_thread_num@plt: 1 occurrences►

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 72 bytes. The binary function is storing 60 bytes.

General properties

nb instructions	80
nb uops	81
loop length	298
used x86 registers	12
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	10

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.13 cycles
front end	10.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.33	5.33	5.33	5.33	5.33	5.33	6.00	6.00	6.00	6.00	0.25	0.25	0.25	0.25	0.00	0.00
cycles	5.33	5.33	5.33	5.33	5.33	5.33	6.00	6.00	6.00	6.00	0.25	0.25	0.25	0.25	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	10.13
Dispatch	6.00
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	33%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	7%

Vector efficiency ratios

INT

all	7%
load	6%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	16%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

INT+FP

all	8%
load	8%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

2% of peak load performance is reached (6.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (5.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 427820

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	Latency	Recip. throughput	Vectorization
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB $0xb8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x34(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x28(%RDI),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x30(%RDI),%EBP	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
ADD $0x4,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x1(%RCX),%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV 0x2c(%RBX),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %EAX,0x78(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOV %EDI,0x7c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
CMP %EAX,%EBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 427c20 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.9+0x400>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
LEA 0x3(%RCX),%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB %EBP,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CMP %R14D,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 427c20 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.9+0x400>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R14D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SUB %EDI,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %R15D,0x80(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
CALL 404660 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404550 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R13D,%EAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
DIV %R12D	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JB 427c32 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.9+0x412>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %ESI,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADD %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RSI,%RCX,1),%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %EAX,0x84(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
CMP %EAX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JAE 427c20 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.9+0x400>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV 0x7c(%RSP),%EDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVSD 0x1dab5(%RIP),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
DIVL 0x80(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	0	0	0	0	10-17	6	scal (6.3%)
MOVAPD %XMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
UNPCKLPD %XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
ADD %EDX,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R14D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
ADD %EBP,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EDI,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
SUB %EDI,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV (%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVSXD %EAX,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %RDI,0x88(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x20(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RDI,0x90(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x10(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RDI,0x98(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x8(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x18(%RBX),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RDI,0xa0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %RBX,0xa8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0xb8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD $0x1,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
JMP 42789c <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.9+0x7c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	2.99	1.15
▼Loop 232 - - exec–	0.01	0.01
○Loop 233 - - exec	2.98	1.14

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ASM code

Code clean check

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Vectorization

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Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code