OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone ._omp

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: :0-0	Coverage (incl. loops): 2.99% \| (excl. loops): 0.00%

  ***  This Panel is Intentionally Left Blank.  ***

It is due to a lack of debug symbols in the given object
(loop or function).

0x426f50 PUSH	%R15

0x426f52 PUSH	%R14

0x426f54 PUSH	%R13

0x426f56 PUSH	%R12

0x426f58 PUSH	%RBP

0x426f59 PUSH	%RBX

0x426f5a MOV	%RDI,%RBX

0x426f5d SUB	$0xb8,%RSP

0x426f64 MOV	0x30(%RBX),%EAX

0x426f67 MOV	0x28(%RDI),%EDI

0x426f6a MOV	0x2c(%RBX),%ESI

0x426f6d LEA	0x1(%RAX),%EBP

0x426f70 MOV	0x34(%RBX),%EAX

0x426f73 MOV	%EDI,0x7c(%RSP)

0x426f77 ADD	$0x3,%EAX

0x426f7a MOV	%EAX,0x78(%RSP)

0x426f7e CMP	%EAX,%EBP

0x426f80 JGE	427338

0x426f86 MOV	%EAX,%R13D

0x426f89 LEA	0x4(%RSI),%R14D

0x426f8d SUB	%EBP,%R13D

0x426f90 CMP	%R14D,%EDI

0x426f93 JGE	427338

0x426f99 MOV	%R14D,%R15D

0x426f9c SUB	%EDI,%R15D

0x426f9f MOV	%R15D,0x80(%RSP)

0x426fa7 CALL	404660 <omp_get_num_threads@plt>

0x426fac MOV	%EAX,%R12D

0x426faf CALL	404550 <omp_get_thread_num@plt>

0x426fb4 XOR	%EDX,%EDX

0x426fb6 MOV	%EAX,%ECX

0x426fb8 MOV	%R15D,%EAX

0x426fbb IMUL	%R13D,%EAX

0x426fbf DIV	%R12D

0x426fc2 MOV	%EAX,%ESI

0x426fc4 CMP	%EDX,%ECX

0x426fc6 JB	42734a

0x426fcc IMUL	%ESI,%ECX

0x426fcf ADD	%EDX,%ECX

0x426fd1 LEA	(%RSI,%RCX,1),%EAX

0x426fd4 MOV	%EAX,0x84(%RSP)

0x426fdb CMP	%EAX,%ECX

0x426fdd JAE	427338

0x426fe3 MOV	%ECX,%EAX

0x426fe5 XOR	%EDX,%EDX

0x426fe7 MOV	0x7c(%RSP),%EDI

0x426feb MOVSD	0x1e385(%RIP),%XMM3

0x426ff3 DIVL	0x80(%RSP)

0x426ffa MOVAPD	%XMM3,%XMM2

0x426ffe UNPCKLPD	%XMM2,%XMM2

0x427002 ADD	%EDX,%EDI

0x427004 MOV	%R14D,%EDX

0x427007 ADD	%EBP,%EAX

0x427009 MOV	%EDI,0x40(%RSP)

0x42700d SUB	%EDI,%EDX

0x42700f MOV	(%RBX),%RDI

0x427012 MOVSXD	%EAX,%R14

0x427015 MOV	%RDI,0x88(%RSP)

0x42701d MOV	0x20(%RBX),%RDI

0x427021 MOV	%RDI,0x90(%RSP)

0x427029 MOV	0x10(%RBX),%RDI

0x42702d MOV	%RDI,0x98(%RSP)

0x427035 MOV	0x8(%RBX),%RDI

0x427039 MOV	0x18(%RBX),%RBX

0x42703d MOV	%RDI,0xa0(%RSP)

0x427045 MOV	%RBX,0xa8(%RSP)

0x42704d NOPL	(%RAX)

(226) 0x427050 CMP	%EDX,%ESI

(226) 0x427052 CMOVBE	%ESI,%EDX

(226) 0x427055 LEA	(%RCX,%RDX,1),%EAX

(226) 0x427058 MOV	%EDX,0xc(%RSP)

(226) 0x42705c MOV	%EAX,0x44(%RSP)

(226) 0x427060 CMP	%EAX,%ECX

(226) 0x427062 JAE	42730a

(226) 0x427068 MOV	0x88(%RSP),%RAX

(226) 0x427070 LEA	-0x1(%R14),%ECX

(226) 0x427074 MOV	0xa0(%RSP),%R10

(226) 0x42707c MOVSXD	%ECX,%RCX

(226) 0x42707f MOV	0xa8(%RSP),%R11

(226) 0x427087 MOV	(%RAX),%RDX

(226) 0x42708a MOV	0x10(%RAX),%RBX

(226) 0x42708e MOV	%RCX,%RSI

(226) 0x427091 MOV	%RCX,%RDI

(226) 0x427094 MOV	0x90(%RSP),%RAX

(226) 0x42709c MOV	0x10(%R11),%R8

(226) 0x4270a0 IMUL	%RDX,%RDI

(226) 0x4270a4 MOV	%RDX,%RCX

(226) 0x4270a7 MOV	(%R11),%R11

(226) 0x4270aa MOV	%RBX,0x68(%RSP)

(226) 0x4270af MOV	0x10(%RAX),%R9

(226) 0x4270b3 MOV	(%RAX),%RAX

(226) 0x4270b6 IMUL	%R14,%RCX

(226) 0x4270ba MOV	%R8,0x20(%RSP)

(226) 0x4270bf IMUL	%R14,%R11

(226) 0x4270c3 IMUL	%RAX,%RSI

(226) 0x4270c7 MOV	%RDI,0x70(%RSP)

(226) 0x4270cc IMUL	%R14,%RAX

(226) 0x4270d0 MOV	%R9,0x58(%RSP)

(226) 0x4270d5 MOV	%RCX,0x50(%RSP)

(226) 0x4270da MOV	%RSI,0x60(%RSP)

(226) 0x4270df MOV	%RAX,0x48(%RSP)

(226) 0x4270e4 MOV	%RAX,%RDX

(226) 0x4270e7 MOV	0x98(%RSP),%RAX

(226) 0x4270ef MOV	%R11,0x18(%RSP)

(226) 0x4270f4 MOV	0x10(%RAX),%R15

(226) 0x4270f8 MOV	(%RAX),%RAX

(226) 0x4270fb MOV	%R15,0x30(%RSP)

(226) 0x427100 MOV	0x10(%R10),%R15

(226) 0x427104 IMUL	%R14,%RAX

(226) 0x427108 MOV	(%R10),%R10

(226) 0x42710b MOV	%R15,0x10(%RSP)

(226) 0x427110 IMUL	%R14,%R10

(226) 0x427114 CMPL	$0x1,0xc(%RSP)

(226) 0x427119 MOV	%RAX,0x38(%RSP)

(226) 0x42711e MOV	%R10,0x28(%RSP)

(226) 0x427123 JE	427247

(226) 0x427129 MOVSXD	0x40(%RSP),%RAX

(226) 0x42712e MOV	%RBX,%R8

(226) 0x427131 ADD	%RAX,%RDI

(226) 0x427134 ADD	%RAX,%RCX

(226) 0x427137 ADD	%RAX,%RSI

(226) 0x42713a ADD	%RAX,%RDX

(226) 0x42713d SAL	$0x3,%RDI

(226) 0x427141 SAL	$0x3,%RCX

(226) 0x427145 LEA	(%RBX,%RDI,1),%R15

(226) 0x427149 LEA	(%RBX,%RCX,1),%R12

(226) 0x42714d SAL	$0x3,%RSI

(226) 0x427151 SAL	$0x3,%RDX

(226) 0x427155 LEA	-0x8(%RBX,%RDI,1),%RBX

(226) 0x42715a MOV	0x38(%RSP),%RDI

(226) 0x42715f LEA	(%R9,%RSI,1),%R13

(226) 0x427163 LEA	(%R9,%RDX,1),%RBP

(226) 0x427167 LEA	-0x8(%R9,%RSI,1),%R11

(226) 0x42716c MOV	0x30(%RSP),%RSI

(226) 0x427171 LEA	-0x8(%R9,%RDX,1),%R9

(226) 0x427176 LEA	(%RDI,%RAX,1),%RDX

(226) 0x42717a MOV	0x28(%RSP),%RDI

(226) 0x42717f LEA	-0x8(%R8,%RCX,1),%R10

(226) 0x427184 MOV	0x10(%RSP),%RCX

(226) 0x427189 LEA	(%RSI,%RDX,8),%R8

(226) 0x42718d MOV	0x18(%RSP),%RSI

(226) 0x427192 LEA	(%RDI,%RAX,1),%RDX

(226) 0x427196 SAL	$0x3,%RDX

(226) 0x42719a ADD	%RSI,%RAX

(226) 0x42719d MOV	0x20(%RSP),%RSI

(226) 0x4271a2 LEA	-0x8(%RCX,%RDX,1),%RDI

(226) 0x4271a7 ADD	%RCX,%RDX

(226) 0x4271aa MOV	0xc(%RSP),%ECX

(226) 0x4271ae LEA	(%RSI,%RAX,8),%RSI

(226) 0x4271b2 XOR	%EAX,%EAX

(226) 0x4271b4 SHR	$0x1,%ECX

(226) 0x4271b6 SAL	$0x4,%RCX

(226) 0x4271ba NOPW	(%RAX,%RAX,1)

  (227) 0x4271c0 MOVUPD	(%R12,%RAX,1),%XMM4

  (227) 0x4271c6 MOVUPD	(%R15,%RAX,1),%XMM5

  (227) 0x4271cc MOVUPD	(%RBP,%RAX,1),%XMM0

  (227) 0x4271d2 MOVUPD	(%R13,%RAX,1),%XMM1

  (227) 0x4271d9 MOVUPD	(%RBX,%RAX,1),%XMM6

  (227) 0x4271de MOVUPD	(%R10,%RAX,1),%XMM7

  (227) 0x4271e4 MULPD	%XMM5,%XMM1

  (227) 0x4271e8 MULPD	%XMM4,%XMM0

  (227) 0x4271ec ADDPD	%XMM1,%XMM0

  (227) 0x4271f0 MOVUPD	(%R11,%RAX,1),%XMM1

  (227) 0x4271f6 MULPD	%XMM6,%XMM1

  (227) 0x4271fa ADDPD	%XMM1,%XMM0

  (227) 0x4271fe MOVUPD	(%R9,%RAX,1),%XMM1

  (227) 0x427204 MULPD	%XMM7,%XMM1

  (227) 0x427208 ADDPD	%XMM1,%XMM0

  (227) 0x42720c MULPD	%XMM2,%XMM0

  (227) 0x427210 MOVUPS	%XMM0,(%R8,%RAX,1)

  (227) 0x427215 MOVUPD	(%RDI,%RAX,1),%XMM4

  (227) 0x42721a MOVUPD	(%RDX,%RAX,1),%XMM5

  (227) 0x42721f SUBPD	%XMM4,%XMM0

  (227) 0x427223 ADDPD	%XMM5,%XMM0

  (227) 0x427227 MOVUPS	%XMM0,(%RSI,%RAX,1)

  (227) 0x42722b ADD	$0x10,%RAX

  (227) 0x42722f CMP	%RAX,%RCX

  (227) 0x427232 JNE	4271c0

(226) 0x427234 MOV	0xc(%RSP),%EAX

(226) 0x427238 TEST	$0x1,%AL

(226) 0x42723a JE	427306

(226) 0x427240 AND	$-0x2,%EAX

(226) 0x427243 ADD	%EAX,0x40(%RSP)

(226) 0x427247 MOVSXD	0x40(%RSP),%RAX

(226) 0x42724c MOV	0x48(%RSP),%R15

(226) 0x427251 MOV	0x50(%RSP),%R10

(226) 0x427256 MOV	0x68(%RSP),%RDI

(226) 0x42725b MOV	0x58(%RSP),%RBX

(226) 0x427260 MOV	0x60(%RSP),%R11

(226) 0x427265 LEA	(%R15,%RAX,1),%RSI

(226) 0x427269 LEA	-0x1(%RAX),%EDX

(226) 0x42726c MOV	0x70(%RSP),%R8

(226) 0x427271 LEA	(%R10,%RAX,1),%RCX

(226) 0x427275 MOVSXD	%EDX,%RDX

(226) 0x427278 MOVSD	(%RBX,%RSI,8),%XMM0

(226) 0x42727d LEA	(%R11,%RAX,1),%RSI

(226) 0x427281 MULSD	(%RDI,%RCX,8),%XMM0

(226) 0x427286 LEA	(%R8,%RAX,1),%RCX

(226) 0x42728a MOVSD	(%RBX,%RSI,8),%XMM1

(226) 0x42728f LEA	(%R8,%RDX,1),%RSI

(226) 0x427293 MULSD	(%RDI,%RCX,8),%XMM1

(226) 0x427298 LEA	(%R11,%RDX,1),%RCX

(226) 0x42729c ADDSD	%XMM1,%XMM0

(226) 0x4272a0 MOVSD	(%RBX,%RCX,8),%XMM1

(226) 0x4272a5 MULSD	(%RDI,%RSI,8),%XMM1

(226) 0x4272aa LEA	(%R15,%RDX,1),%RCX

(226) 0x4272ae LEA	(%R10,%RDX,1),%RSI

(226) 0x4272b2 ADDSD	%XMM1,%XMM0

(226) 0x4272b6 MOVSD	(%RBX,%RCX,8),%XMM1

(226) 0x4272bb MULSD	(%RDI,%RSI,8),%XMM1

(226) 0x4272c0 MOV	0x38(%RSP),%RCX

(226) 0x4272c5 MOV	0x30(%RSP),%RDI

(226) 0x4272ca MOV	0x10(%RSP),%RSI

(226) 0x4272cf ADD	%RAX,%RCX

(226) 0x4272d2 ADDSD	%XMM1,%XMM0

(226) 0x4272d6 MULSD	%XMM3,%XMM0

(226) 0x4272da MOVSD	%XMM0,(%RDI,%RCX,8)

(226) 0x4272df MOV	0x28(%RSP),%RDI

(226) 0x4272e4 MOV	0x18(%RSP),%RCX

(226) 0x4272e9 ADD	%RDI,%RDX

(226) 0x4272ec ADD	%RAX,%RCX

(226) 0x4272ef ADD	%RDI,%RAX

(226) 0x4272f2 SUBSD	(%RSI,%RDX,8),%XMM0

(226) 0x4272f7 ADDSD	(%RSI,%RAX,8),%XMM0

(226) 0x4272fc MOV	0x20(%RSP),%RAX

(226) 0x427301 MOVSD	%XMM0,(%RAX,%RCX,8)

(226) 0x427306 MOV	0x44(%RSP),%ECX

(226) 0x42730a ADD	$0x1,%R14

(226) 0x42730e CMP	%R14D,0x78(%RSP)

(226) 0x427313 JLE	427338

(226) 0x427315 MOV	0x84(%RSP),%ESI

(226) 0x42731c MOV	0x7c(%RSP),%EAX

(226) 0x427320 MOV	0x80(%RSP),%EDX

(226) 0x427327 MOV	%EAX,0x40(%RSP)

(226) 0x42732b SUB	%ECX,%ESI

(226) 0x42732d JMP	427050

0x427332 NOPW	(%RAX,%RAX,1)

0x427338 ADD	$0xb8,%RSP

0x42733f POP	%RBX

0x427340 POP	%RBP

0x427341 POP	%R12

0x427343 POP	%R13

0x427345 POP	%R14

0x427347 POP	%R15

0x427349 RET

0x42734a ADD	$0x1,%ESI

0x42734d XOR	%EDX,%EDX

0x42734f JMP	426fcc

0x427354 NOPW	%CS:(%RAX,%RAX,1)

0x42735f NOP

Coverage (%)	Name	Source Location	Module
►96.89+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►1.54+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	advec_mom_kernel(int, int, int[...]		exec
○	advec_mom_driver(global_variab[...]		exec
○	advection(global_variables&)		exec
○	hydro(global_variables&, paral[...]		exec
○	main		exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec
►1.54+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	advec_mom_kernel(int, int, int[...]		exec
○	advec_mom_driver(global_variab[...]		exec
○	advection(global_variables&)		exec
○	hydro(global_variables&, paral[...]		exec
○	main		exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines
Module	exec

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.00 to 1.38 cycles (8.73x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 8% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 12.00 to 0.75 cycles (16.00x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 12.00 to 10.13 cycles (1.19x speedup).

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 9.88 cycles (1.22x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
omp_get_thread_num@plt: 1 occurrences►

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 72 bytes. The binary function is storing 60 bytes.

General properties

nb instructions	81
nb uops	81
loop length	302
used x86 registers	12
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	10

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.13 cycles
front end	10.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.33	5.33	5.33	5.33	5.33	5.33	6.00	6.00	6.00	6.00	0.25	0.25	0.25	0.25	0.00	0.00
cycles	5.33	5.33	5.33	5.33	5.33	5.33	6.00	6.00	6.00	6.00	0.25	0.25	0.25	0.25	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	10.13
Dispatch	6.00
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	33%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	7%

Vector efficiency ratios

INT

all	7%
load	6%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	16%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

INT+FP

all	8%
load	9%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

2% of peak load performance is reached (6.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (5.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 426f50

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	Latency	Recip. throughput	Vectorization
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB $0xb8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x30(%RBX),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x28(%RDI),%EDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x2c(%RBX),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
LEA 0x1(%RAX),%EBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV 0x34(%RBX),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %EDI,0x7c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
ADD $0x3,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EAX,0x78(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
CMP %EAX,%EBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 427338 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x3e8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
LEA 0x4(%RSI),%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB %EBP,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CMP %R14D,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 427338 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x3e8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R14D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SUB %EDI,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %R15D,0x80(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
CALL 404660 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404550 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R13D,%EAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
DIV %R12D	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JB 42734a <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x3fa>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %ESI,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADD %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RSI,%RCX,1),%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %EAX,0x84(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
CMP %EAX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JAE 427338 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x3e8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV 0x7c(%RSP),%EDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVSD 0x1e385(%RIP),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
DIVL 0x80(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	0	0	0	0	10-17	6	scal (6.3%)
MOVAPD %XMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
UNPCKLPD %XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
ADD %EDX,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R14D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
ADD %EBP,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EDI,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
SUB %EDI,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV (%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVSXD %EAX,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %RDI,0x88(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x20(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RDI,0x90(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x10(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RDI,0x98(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x8(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x18(%RBX),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RDI,0xa0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %RBX,0xa8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0xb8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD $0x1,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
JMP 426fcc <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x7c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines
Module	exec

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.00 to 1.38 cycles (8.73x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 9.88 cycles (1.22x speedup).

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
omp_get_thread_num@plt: 1 occurrences►

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 72 bytes. The binary function is storing 60 bytes.

General properties

nb instructions	81
nb uops	81
loop length	302
used x86 registers	12
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	10

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.13 cycles
front end	10.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.33	5.33	5.33	5.33	5.33	5.33	6.00	6.00	6.00	6.00	0.25	0.25	0.25	0.25	0.00	0.00
cycles	5.33	5.33	5.33	5.33	5.33	5.33	6.00	6.00	6.00	6.00	0.25	0.25	0.25	0.25	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	10.13
Dispatch	6.00
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	33%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	7%

Vector efficiency ratios

INT

all	7%
load	6%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	16%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

INT+FP

all	8%
load	9%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

2% of peak load performance is reached (6.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (5.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 426f50

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	Latency	Recip. throughput	Vectorization
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB $0xb8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x30(%RBX),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x28(%RDI),%EDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x2c(%RBX),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
LEA 0x1(%RAX),%EBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV 0x34(%RBX),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %EDI,0x7c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
ADD $0x3,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EAX,0x78(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
CMP %EAX,%EBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 427338 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x3e8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
LEA 0x4(%RSI),%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB %EBP,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CMP %R14D,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 427338 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x3e8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R14D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SUB %EDI,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %R15D,0x80(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
CALL 404660 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404550 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R13D,%EAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
DIV %R12D	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JB 42734a <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x3fa>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %ESI,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADD %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RSI,%RCX,1),%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %EAX,0x84(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
CMP %EAX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JAE 427338 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x3e8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV 0x7c(%RSP),%EDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVSD 0x1e385(%RIP),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
DIVL 0x80(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	0	0	0	0	10-17	6	scal (6.3%)
MOVAPD %XMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
UNPCKLPD %XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
ADD %EDX,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R14D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
ADD %EBP,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EDI,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
SUB %EDI,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV (%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVSXD %EAX,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %RDI,0x88(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x20(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RDI,0x90(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x10(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RDI,0x98(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x8(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x18(%RBX),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RDI,0xa0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %RBX,0xa8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0xb8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD $0x1,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
JMP 426fcc <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x7c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	2.99	1.15
▼Loop 226 - - exec–	0.01	0.01
○Loop 227 - - exec	2.98	1.14

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Code clean check

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Vectorization

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Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

CALL instructions

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Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code