OV - exec - Loop 222

	Loop Id: 222	Module: exec	Source: :0-0	Coverage: 0.05%

0x42d4a0 INC	%RAX

0x42d4a3 MOVQ	%RAX,%XMM0

0x42d4a8 PSHUFD	$0x44,%XMM0,%XMM0

0x42d4ad PXOR	0x3e21b(%RIP),%XMM0

0x42d4b5 MOVDQA	0x360(%RSP),%XMM4

0x42d4be MOVDQA	%XMM4,%XMM1

0x42d4c2 PCMPGTD	%XMM0,%XMM1

0x42d4c6 PSHUFD	$-0x60,%XMM1,%XMM3

0x42d4cb PCMPEQD	%XMM0,%XMM4

0x42d4cf PSHUFD	$-0xb,%XMM4,%XMM4

0x42d4d4 PAND	%XMM3,%XMM4

0x42d4d8 PSHUFD	$-0xb,%XMM1,%XMM1

0x42d4dd POR	%XMM4,%XMM1

0x42d4e1 MOVDQA	0x350(%RSP),%XMM6

0x42d4ea MOVDQA	%XMM6,%XMM3

0x42d4ee PCMPGTD	%XMM0,%XMM3

0x42d4f2 PSHUFD	$-0x60,%XMM3,%XMM4

0x42d4f7 PCMPEQD	%XMM6,%XMM0

0x42d4fb PSHUFD	$-0xb,%XMM0,%XMM6

0x42d500 PAND	%XMM4,%XMM6

0x42d504 PSHUFD	$-0xb,%XMM3,%XMM0

0x42d509 POR	%XMM6,%XMM0

0x42d50d PACKSSDW	%XMM1,%XMM0

0x42d511 MOVAPD	0xd0(%RSP),%XMM4

0x42d51a MOVAPD	0x390(%RSP),%XMM6

0x42d523 PSHUFD	$-0x6,%XMM8,%XMM1

0x42d529 PSLLD	$0x1f,%XMM1

0x42d52e PSRAD	$0x1f,%XMM1

0x42d533 MOVAPD	%XMM5,%XMM3

0x42d537 ANDPD	%XMM1,%XMM3

0x42d53b ANDNPD	%XMM6,%XMM1

0x42d53f MOVAPD	%XMM1,%XMM6

0x42d543 ORPD	%XMM3,%XMM6

0x42d547 PSHUFD	$0x50,%XMM8,%XMM1

0x42d54d PSLLD	$0x1f,%XMM1

0x42d552 PSRAD	$0x1f,%XMM1

0x42d557 MOVAPD	%XMM2,%XMM3

0x42d55b ANDPD	%XMM1,%XMM3

0x42d55f ANDNPD	%XMM4,%XMM1

0x42d563 MOVAPD	%XMM1,%XMM4

0x42d567 ORPD	%XMM3,%XMM4

0x42d56b PAND	%XMM0,%XMM8

0x42d570 MOVDQA	%XMM8,%XMM0

0x42d575 PSLLD	$0x1f,%XMM0

0x42d57a MOVMSKPS	%XMM0,%ECX

0x42d57d MOVAPD	%XMM2,%XMM7

0x42d581 MOVAPD	%XMM5,%XMM11

0x42d586 TEST	%ECX,%ECX

0x42d588 JE	42cbf0

0x42d58e MOVDQA	%XMM8,%XMM0

0x42d593 PSLLD	$0x1f,%XMM0

0x42d598 MOVMSKPS	%XMM0,%ECX

0x42d59b TEST	%ECX,%ECX

0x42d59d JE	42d950

0x42d5a3 MOVAPS	%XMM6,0x390(%RSP)

0x42d5ab MOVAPS	%XMM4,0xd0(%RSP)

0x42d5b3 MOVQ	%RAX,%XMM0

0x42d5b8 PSHUFD	$0x44,%XMM0,%XMM4

0x42d5bd MOVDQA	0x340(%RSP),%XMM0

0x42d5c6 PMULUDQ	%XMM4,%XMM0

0x42d5ca MOVDQA	%XMM4,%XMM1

0x42d5ce PSRLQ	$0x20,%XMM1

0x42d5d3 MOVDQA	0x160(%RSP),%XMM3

0x42d5dc MOVDQA	%XMM3,%XMM2

0x42d5e0 PMULUDQ	%XMM1,%XMM2

0x42d5e4 PADDQ	%XMM0,%XMM2

0x42d5e8 PSLLQ	$0x20,%XMM2

0x42d5ed PMULUDQ	%XMM4,%XMM3

0x42d5f1 PADDQ	%XMM2,%XMM3

0x42d5f5 MOVDQA	0x330(%RSP),%XMM0

0x42d5fe PADDQ	%XMM3,%XMM0

0x42d602 MOVDQA	%XMM0,0x3e0(%RSP)

0x42d60b PADDQ	0x320(%RSP),%XMM3

0x42d614 MOVDQA	%XMM3,0x3f0(%RSP)

0x42d61d MOVDQA	0x310(%RSP),%XMM0

0x42d626 PMULUDQ	%XMM4,%XMM0

0x42d62a MOVDQA	0x150(%RSP),%XMM2

0x42d633 PMULUDQ	%XMM2,%XMM1

0x42d637 PADDQ	%XMM0,%XMM1

0x42d63b PSLLQ	$0x20,%XMM1

0x42d640 PMULUDQ	%XMM2,%XMM4

0x42d644 PADDQ	%XMM1,%XMM4

0x42d648 MOVDQA	0x380(%RSP),%XMM0

0x42d651 PADDQ	%XMM4,%XMM0

0x42d655 MOVDQA	%XMM0,0x3d0(%RSP)

0x42d65e PADDQ	0x370(%RSP),%XMM4

0x42d667 MOVDQA	%XMM4,0xe0(%RSP)

0x42d670 MOV	$0x1,%ECX

0x42d675 MOVDQA	0x3db12(%RIP),%XMM15

0x42d67e MOVDQA	%XMM8,0xf0(%RSP)

0x42d688 JMP	42d7c8

  (223) 0x42d690 MOVDQA	0x170(%RSP),%XMM10

  (223) 0x42d69a PAND	%XMM14,%XMM6

  (223) 0x42d69f PANDN	%XMM13,%XMM14

  (223) 0x42d6a4 MOVDQA	%XMM14,%XMM13

  (223) 0x42d6a9 POR	%XMM6,%XMM13

  (223) 0x42d6ae PAND	%XMM1,%XMM0

  (223) 0x42d6b2 PANDN	%XMM12,%XMM1

  (223) 0x42d6b7 MOVDQA	%XMM1,%XMM12

  (223) 0x42d6bc POR	%XMM0,%XMM12

  (223) 0x42d6c1 MOVDQA	%XMM12,%XMM0

  (223) 0x42d6c6 MULPD	%XMM12,%XMM0

  (223) 0x42d6cb ADDPD	%XMM9,%XMM0

  (223) 0x42d6d0 MOVDQA	%XMM13,%XMM1

  (223) 0x42d6d5 MULPD	%XMM13,%XMM1

  (223) 0x42d6da ADDPD	%XMM3,%XMM1

  (223) 0x42d6de MOVAPD	0x3dd3a(%RIP),%XMM3

  (223) 0x42d6e6 MULPD	%XMM3,%XMM0

  (223) 0x42d6ea ADDPD	%XMM0,%XMM11

  (223) 0x42d6ef MULPD	%XMM3,%XMM1

  (223) 0x42d6f3 ADDPD	%XMM1,%XMM7

  (223) 0x42d6f7 MOVQ	%RCX,%XMM0

  (223) 0x42d6fc PSHUFD	$0x44,%XMM0,%XMM1

  (223) 0x42d701 PXOR	0x3dfc7(%RIP),%XMM1

  (223) 0x42d709 MOVDQA	0x3c0(%RSP),%XMM4

  (223) 0x42d712 MOVDQA	%XMM4,%XMM3

  (223) 0x42d716 PCMPGTD	%XMM1,%XMM3

  (223) 0x42d71a MOVDQA	0x3b0(%RSP),%XMM6

  (223) 0x42d723 MOVDQA	%XMM6,%XMM0

  (223) 0x42d727 PCMPGTD	%XMM1,%XMM0

  (223) 0x42d72b PCMPEQD	%XMM1,%XMM4

  (223) 0x42d72f PCMPEQD	%XMM6,%XMM1

  (223) 0x42d733 SHUFPS	$-0x23,%XMM4,%XMM1

  (223) 0x42d737 MOVDQA	%XMM0,%XMM4

  (223) 0x42d73b SHUFPS	$-0x78,%XMM3,%XMM4

  (223) 0x42d73f ANDPS	%XMM4,%XMM1

  (223) 0x42d742 SHUFPS	$-0x23,%XMM3,%XMM0

  (223) 0x42d746 ORPS	%XMM1,%XMM0

  (223) 0x42d749 PSHUFD	$-0x6,%XMM15,%XMM1

  (223) 0x42d74f PSLLD	$0x1f,%XMM1

  (223) 0x42d754 PSRAD	$0x1f,%XMM1

  (223) 0x42d759 MOVAPD	%XMM11,%XMM3

  (223) 0x42d75e ANDPD	%XMM1,%XMM3

  (223) 0x42d762 ANDNPD	%XMM5,%XMM1

  (223) 0x42d766 MOVAPD	%XMM1,%XMM5

  (223) 0x42d76a ORPD	%XMM3,%XMM5

  (223) 0x42d76e PSHUFD	$0x50,%XMM15,%XMM1

  (223) 0x42d774 PSLLD	$0x1f,%XMM1

  (223) 0x42d779 PSRAD	$0x1f,%XMM1

  (223) 0x42d77e MOVAPD	%XMM7,%XMM3

  (223) 0x42d782 ANDPD	%XMM1,%XMM3

  (223) 0x42d786 ANDNPD	%XMM2,%XMM1

  (223) 0x42d78a MOVAPD	%XMM1,%XMM2

  (223) 0x42d78e ORPD	%XMM3,%XMM2

  (223) 0x42d792 PAND	%XMM0,%XMM15

  (223) 0x42d797 MOVDQA	0xf0(%RSP),%XMM8

  (223) 0x42d7a1 MOVDQA	%XMM8,%XMM0

  (223) 0x42d7a6 PAND	%XMM15,%XMM0

  (223) 0x42d7ab PSLLD	$0x1f,%XMM0

  (223) 0x42d7b0 MOVMSKPS	%XMM0,%EDX

  (223) 0x42d7b3 INC	%RCX

  (223) 0x42d7b6 TEST	%EDX,%EDX

  (223) 0x42d7b8 MOVDQA	0x3a0(%RSP),%XMM14

  (223) 0x42d7c2 JE	42d4a0

  (223) 0x42d7c8 LEA	-0x1(%RCX),%RDX

  (223) 0x42d7cc MOVDQA	%XMM8,%XMM1

  (223) 0x42d7d1 PAND	%XMM15,%XMM1

  (223) 0x42d7d6 MOVQ	%RDX,%XMM0

  (223) 0x42d7db PSHUFD	$0x44,%XMM0,%XMM8

  (223) 0x42d7e1 MOVDQA	0x3f0(%RSP),%XMM0

  (223) 0x42d7ea PADDQ	%XMM8,%XMM0

  (223) 0x42d7ef PSLLQ	$0x3,%XMM0

  (223) 0x42d7f4 PADDQ	%XMM10,%XMM0

  (223) 0x42d7f9 MOVDQA	%XMM1,%XMM3

  (223) 0x42d7fd PSLLD	$0x1f,%XMM3

  (223) 0x42d802 MOVMSKPS	%XMM3,%EDX

  (223) 0x42d805 TEST	$0x1,%DL

  (223) 0x42d808 JE	42d813

  (223) 0x42d80a MOVQ	%XMM0,%RDI

  (223) 0x42d80f MOVSD	(%RDI),%XMM3

  (223) 0x42d813 TEST	$0x2,%DL

  (223) 0x42d816 JE	42d825

  (223) 0x42d818 PSHUFD	$-0x12,%XMM0,%XMM0

  (223) 0x42d81d MOVQ	%XMM0,%RDI

  (223) 0x42d822 MOVHPS	(%RDI),%XMM3

  (223) 0x42d825 MOVDQA	0x3e0(%RSP),%XMM0

  (223) 0x42d82e PADDQ	%XMM8,%XMM0

  (223) 0x42d833 PSLLQ	$0x3,%XMM0

  (223) 0x42d838 PADDQ	%XMM10,%XMM0

  (223) 0x42d83d TEST	$0x4,%DL

  (223) 0x42d840 JE	42d860

  (223) 0x42d842 MOVQ	%XMM0,%RDI

  (223) 0x42d847 MOVLPS	(%RDI),%XMM9

  (223) 0x42d84b TEST	$0x8,%DL

  (223) 0x42d84e JNE	42d865

  (223) 0x42d850 JMP	42d873

  (223) 0x42d860 TEST	$0x8,%DL

  (223) 0x42d863 JE	42d873

  (223) 0x42d865 PSHUFD	$-0x12,%XMM0,%XMM0

  (223) 0x42d86a MOVQ	%XMM0,%RDI

  (223) 0x42d86f MOVHPS	(%RDI),%XMM9

  (223) 0x42d873 MOVDQA	0xe0(%RSP),%XMM0

  (223) 0x42d87c PADDQ	%XMM8,%XMM0

  (223) 0x42d881 PSLLQ	$0x3,%XMM0

  (223) 0x42d886 PADDQ	%XMM14,%XMM0

  (223) 0x42d88b TEST	$0x1,%DL

  (223) 0x42d88e JE	42d899

  (223) 0x42d890 MOVQ	%XMM0,%RDI

  (223) 0x42d895 MOVSD	(%RDI),%XMM6

  (223) 0x42d899 TEST	$0x2,%DL

  (223) 0x42d89c JE	42d8ab

  (223) 0x42d89e PSHUFD	$-0x12,%XMM0,%XMM0

  (223) 0x42d8a3 MOVQ	%XMM0,%RDI

  (223) 0x42d8a8 MOVHPS	(%RDI),%XMM6

  (223) 0x42d8ab PADDQ	0x3d0(%RSP),%XMM8

  (223) 0x42d8b5 PSLLQ	$0x3,%XMM8

  (223) 0x42d8bb PADDQ	%XMM14,%XMM8

  (223) 0x42d8c0 TEST	$0x4,%DL

  (223) 0x42d8c3 JE	42d8d0

  (223) 0x42d8c5 MOVQ	%XMM8,%RDI

  (223) 0x42d8ca MOVLPS	(%RDI),%XMM0

  (223) 0x42d8cd JMP	42d8d0

  (223) 0x42d8d0 PSHUFD	$0x50,%XMM1,%XMM14

  (223) 0x42d8d6 PSLLD	$0x1f,%XMM14

  (223) 0x42d8dc PSRAD	$0x1f,%XMM14

  (223) 0x42d8e2 MOVDQA	%XMM14,%XMM10

  (223) 0x42d8e7 PANDN	0x30(%RSP),%XMM10

  (223) 0x42d8ee PAND	%XMM14,%XMM3

  (223) 0x42d8f3 POR	%XMM10,%XMM3

  (223) 0x42d8f8 PSHUFD	$-0x6,%XMM1,%XMM1

  (223) 0x42d8fd PSLLD	$0x1f,%XMM1

  (223) 0x42d902 PSRAD	$0x1f,%XMM1

  (223) 0x42d907 MOVDQA	%XMM1,%XMM4

  (223) 0x42d90b PANDN	0x60(%RSP),%XMM4

  (223) 0x42d911 PAND	%XMM1,%XMM9

  (223) 0x42d916 POR	%XMM4,%XMM9

  (223) 0x42d91b MOVDQA	%XMM9,0x60(%RSP)

  (223) 0x42d922 MULPD	%XMM9,%XMM9

  (223) 0x42d927 MOVDQA	%XMM3,0x30(%RSP)

  (223) 0x42d92d MULPD	%XMM3,%XMM3

  (223) 0x42d931 TEST	$0x8,%DL

  (223) 0x42d934 JE	42d690

  (223) 0x42d93a PSHUFD	$-0x12,%XMM8,%XMM8

  (223) 0x42d940 MOVQ	%XMM8,%RDX

  (223) 0x42d945 MOVHPS	(%RDX),%XMM0

  (223) 0x42d948 JMP	42d690

0x42d950 PXOR	%XMM2,%XMM2

0x42d954 PXOR	%XMM5,%XMM5

0x42d958 XOR	%EAX,%EAX

0x42d95a PXOR	%XMM0,%XMM0

0x42d95e JMP	42d523

  ***  This Panel is Intentionally Left Blank.  ***

It is due to a lack of debug symbols in the given object
(loop or function).

Coverage (%)	Name	Module
►50.52+	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_launch_thread	libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]	libiomp5.so
○	start_thread	libc.so.6
○	__GI___clone3	libc.so.6
►34.46+	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_launch_thread	libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]	libiomp5.so
►8.16+	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_launch_thread	libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]	libiomp5.so
○	start_thread	libc.so.6
►3.47+	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_fork_call	libiomp5.so
○	__kmpc_fork_call	libiomp5.so
○	field_summary(global_variables[...]	exec
○	hydro(global_variables&, paral[...]	exec
○	main	exec
○	__libc_start_call_main	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	exec
►2.34+	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_launch_thread	libiomp5.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.52
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.06
Bottlenecks	P10, P11, P12, P13,
Function	field_summary(global_variables&, parallel_&) [clone .extracted]
Source
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	13.00
CQA cycles if no scalar integer	13.00
CQA cycles if FP arith vectorized	13.00
CQA cycles if fully vectorized	2.88
Front-end cycles	12.25
P0 cycles	1.33
P1 cycles	1.33
P2 cycles	1.33
P3 cycles	1.33
P4 cycles	1.33
P5 cycles	1.33
P6 cycles	5.25
P7 cycles	5.25
P8 cycles	5.25
P9 cycles	5.25
P10 cycles	13.00
P11 cycles	13.00
P12 cycles	13.00
P13 cycles	13.00
P14 cycles	4.50
P15 cycles	4.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	96.00
Nb uops	98.00
Nb loads	14.00
Nb stores	7.00
Nb stack references	17.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	25.85
Bytes prefetched	0.00
Bytes loaded	224.00
Bytes stored	112.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	94.44
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	88.89
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	92.98
Vector-efficiency ratio all	23.33
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	23.61
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	23.90

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.52
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.06
Bottlenecks	P10, P11, P12, P13,
Function	field_summary(global_variables&, parallel_&) [clone .extracted]
Source
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	13.00
CQA cycles if no scalar integer	13.00
CQA cycles if FP arith vectorized	13.00
CQA cycles if fully vectorized	2.88
Front-end cycles	12.25
P0 cycles	1.33
P1 cycles	1.33
P2 cycles	1.33
P3 cycles	1.33
P4 cycles	1.33
P5 cycles	1.33
P6 cycles	5.25
P7 cycles	5.25
P8 cycles	5.25
P9 cycles	5.25
P10 cycles	13.00
P11 cycles	13.00
P12 cycles	13.00
P13 cycles	13.00
P14 cycles	4.50
P15 cycles	4.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	96.00
Nb uops	98.00
Nb loads	14.00
Nb stores	7.00
Nb stack references	17.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	25.85
Bytes prefetched	0.00
Bytes loaded	224.00
Bytes stored	112.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	94.44
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	88.89
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	92.98
Vector-efficiency ratio all	23.33
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	23.61
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	23.90

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	field_summary(global_variables&, parallel_&) [clone .extracted]
Source file and lines
Module	exec

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 257 paths individually, rerun with max-paths=257
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 257 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. Only 23% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 13.00 to 2.87 cycles (4.52x speedup).

Details

94% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

88% of SSE/AVX addition or subtraction instructions are used in vector version.
92% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Pass to your compiler a micro-architecture specialization option:
- Please look into your compiler manual for march=native or equivalent
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries
2. inform your compiler that your arrays are vector aligned: read your compiler manual.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

MOVQ: 2 occurrences►

Conversion instructions

Detected expensive conversion instructions.

Details

PACKSSDW: 1 occurrences►

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 224 bytes. The binary loop is storing 112 bytes.

General properties

nb instructions	96
nb uops	98
loop length	512
used x86 registers	3
used mmx registers	0
used xmm registers	11
used ymm registers	0
used zmm registers	0
nb stack references	17

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.25 cycles
front end	12.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.33	1.33	1.33	1.33	1.33	1.33	5.25	5.25	5.25	5.25	13.00	13.00	13.00	13.00	4.50	4.50
cycles	1.33	1.33	1.33	1.33	1.33	1.33	5.25	5.25	5.25	5.25	13.00	13.00	13.00	13.00	4.50	4.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	12.25
Dispatch	13.00
Overall L1	13.00

Vectorization ratios

INT

all	93%
load	100%
store	100%
mul	100%
add-sub	88%
fma	NA (no fma vectorizable/vectorized instructions)
other	90%

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	94%
load	100%
store	100%
mul	100%
add-sub	88%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	92%

Vector efficiency ratios

INT

all	22%
load	25%
store	25%
mul	12%
add-sub	23%
fma	NA (no fma vectorizable/vectorized instructions)
other	23%

all	25%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	23%
load	25%
store	25%
mul	12%
add-sub	23%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	23%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 13.00 cycles. At this rate:

6% of peak load performance is reached (17.23 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (8.62 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 42d58e

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOVQ %RAX,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
PXOR 0x3e21b(%RIP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (25.0%)
MOVDQA 0x360(%RSP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MOVDQA %XMM4,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
PCMPGTD %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
PSHUFD $-0x60,%XMM1,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
PCMPEQD %XMM0,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
PSHUFD $-0xb,%XMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
PAND %XMM3,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
PSHUFD $-0xb,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
POR %XMM4,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVDQA 0x350(%RSP),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MOVDQA %XMM6,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
PCMPGTD %XMM0,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
PSHUFD $-0x60,%XMM3,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
PCMPEQD %XMM6,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
PSHUFD $-0xb,%XMM0,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
PAND %XMM4,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
PSHUFD $-0xb,%XMM3,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
POR %XMM6,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
PACKSSDW %XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	vect (25.0%)
MOVAPD 0xd0(%RSP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MOVAPD 0x390(%RSP),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
PSHUFD $-0x6,%XMM8,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
PSLLD $0x1f,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	vect (25.0%)
PSRAD $0x1f,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	vect (25.0%)
MOVAPD %XMM5,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
ANDPD %XMM1,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
ANDNPD %XMM6,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVAPD %XMM1,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
ORPD %XMM3,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
PSHUFD $0x50,%XMM8,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
PSLLD $0x1f,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	vect (25.0%)
PSRAD $0x1f,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	vect (25.0%)
MOVAPD %XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
ANDPD %XMM1,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
ANDNPD %XMM4,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVAPD %XMM1,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
ORPD %XMM3,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
PAND %XMM0,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVDQA %XMM8,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
PSLLD $0x1f,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	vect (25.0%)
MOVMSKPS %XMM0,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (25.0%)
MOVAPD %XMM2,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOVAPD %XMM5,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
TEST %ECX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 42cbf0 <_Z13field_summaryR16global_variablesR9parallel_.extracted+0x320>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOVDQA %XMM8,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
PSLLD $0x1f,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	vect (25.0%)
MOVMSKPS %XMM0,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (25.0%)
TEST %ECX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 42d950 <_Z13field_summaryR16global_variablesR9parallel_.extracted+0x1080>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOVAPS %XMM6,0x390(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	2	vect (25.0%)
MOVAPS %XMM4,0xd0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	2	vect (25.0%)
MOVQ %RAX,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVDQA 0x340(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
PMULUDQ %XMM4,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (12.5%)
MOVDQA %XMM4,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
PSRLQ $0x20,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	vect (25.0%)
MOVDQA 0x160(%RSP),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MOVDQA %XMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
PMULUDQ %XMM1,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (12.5%)
PADDQ %XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
PSLLQ $0x20,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	vect (25.0%)
PMULUDQ %XMM4,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (12.5%)
PADDQ %XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVDQA 0x330(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
PADDQ %XMM3,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVDQA %XMM0,0x3e0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
PADDQ 0x320(%RSP),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM3,0x3f0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
MOVDQA 0x310(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
PMULUDQ %XMM4,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (12.5%)
MOVDQA 0x150(%RSP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
PMULUDQ %XMM2,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (12.5%)
PADDQ %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
PSLLQ $0x20,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	vect (25.0%)
PMULUDQ %XMM2,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (12.5%)
PADDQ %XMM1,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVDQA 0x380(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
PADDQ %XMM4,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVDQA %XMM0,0x3d0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
PADDQ 0x370(%RSP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM4,0xe0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
MOV $0x1,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVDQA 0x3db12(%RIP),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MOVDQA %XMM8,0xf0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
JMP 42d7c8 <_Z13field_summaryR16global_variablesR9parallel_.extracted+0xef8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
PXOR %XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
PXOR %XMM5,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
PXOR %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
JMP 42d523 <_Z13field_summaryR16global_variablesR9parallel_.extracted+0xc53>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A

Function	field_summary(global_variables&, parallel_&) [clone .extracted]
Source file and lines
Module	exec

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 257 paths individually, rerun with max-paths=257
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

gain
potential
hint
expert

Vectorization

Details

94% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

88% of SSE/AVX addition or subtraction instructions are used in vector version.
92% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Pass to your compiler a micro-architecture specialization option:
- Please look into your compiler manual for march=native or equivalent
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries
2. inform your compiler that your arrays are vector aligned: read your compiler manual.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

MOVQ: 2 occurrences►

Conversion instructions

Detected expensive conversion instructions.

Details

PACKSSDW: 1 occurrences►

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 224 bytes. The binary loop is storing 112 bytes.

General properties

nb instructions	96
nb uops	98
loop length	512
used x86 registers	3
used mmx registers	0
used xmm registers	11
used ymm registers	0
used zmm registers	0
nb stack references	17

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.25 cycles
front end	12.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.33	1.33	1.33	1.33	1.33	1.33	5.25	5.25	5.25	5.25	13.00	13.00	13.00	13.00	4.50	4.50
cycles	1.33	1.33	1.33	1.33	1.33	1.33	5.25	5.25	5.25	5.25	13.00	13.00	13.00	13.00	4.50	4.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	12.25
Dispatch	13.00
Overall L1	13.00

Vectorization ratios

INT

all	93%
load	100%
store	100%
mul	100%
add-sub	88%
fma	NA (no fma vectorizable/vectorized instructions)
other	90%

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	94%
load	100%
store	100%
mul	100%
add-sub	88%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	92%

Vector efficiency ratios

INT

all	22%
load	25%
store	25%
mul	12%
add-sub	23%
fma	NA (no fma vectorizable/vectorized instructions)
other	23%

all	25%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	23%
load	25%
store	25%
mul	12%
add-sub	23%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	23%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 13.00 cycles. At this rate:

6% of peak load performance is reached (17.23 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (8.62 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 42d58e

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOVQ %RAX,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
PXOR 0x3e21b(%RIP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (25.0%)
MOVDQA 0x360(%RSP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MOVDQA %XMM4,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
PCMPGTD %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
PSHUFD $-0x60,%XMM1,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
PCMPEQD %XMM0,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
PSHUFD $-0xb,%XMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
PAND %XMM3,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
PSHUFD $-0xb,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
POR %XMM4,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVDQA 0x350(%RSP),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MOVDQA %XMM6,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
PCMPGTD %XMM0,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
PSHUFD $-0x60,%XMM3,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
PCMPEQD %XMM6,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
PSHUFD $-0xb,%XMM0,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
PAND %XMM4,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
PSHUFD $-0xb,%XMM3,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
POR %XMM6,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
PACKSSDW %XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	vect (25.0%)
MOVAPD 0xd0(%RSP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MOVAPD 0x390(%RSP),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
PSHUFD $-0x6,%XMM8,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
PSLLD $0x1f,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	vect (25.0%)
PSRAD $0x1f,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	vect (25.0%)
MOVAPD %XMM5,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
ANDPD %XMM1,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
ANDNPD %XMM6,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVAPD %XMM1,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
ORPD %XMM3,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
PSHUFD $0x50,%XMM8,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
PSLLD $0x1f,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	vect (25.0%)
PSRAD $0x1f,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	vect (25.0%)
MOVAPD %XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
ANDPD %XMM1,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
ANDNPD %XMM4,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVAPD %XMM1,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
ORPD %XMM3,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
PAND %XMM0,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVDQA %XMM8,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
PSLLD $0x1f,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	vect (25.0%)
MOVMSKPS %XMM0,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (25.0%)
MOVAPD %XMM2,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOVAPD %XMM5,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
TEST %ECX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 42cbf0 <_Z13field_summaryR16global_variablesR9parallel_.extracted+0x320>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOVDQA %XMM8,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
PSLLD $0x1f,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	vect (25.0%)
MOVMSKPS %XMM0,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (25.0%)
TEST %ECX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 42d950 <_Z13field_summaryR16global_variablesR9parallel_.extracted+0x1080>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOVAPS %XMM6,0x390(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	2	vect (25.0%)
MOVAPS %XMM4,0xd0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	2	vect (25.0%)
MOVQ %RAX,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVDQA 0x340(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
PMULUDQ %XMM4,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (12.5%)
MOVDQA %XMM4,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
PSRLQ $0x20,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	vect (25.0%)
MOVDQA 0x160(%RSP),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MOVDQA %XMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
PMULUDQ %XMM1,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (12.5%)
PADDQ %XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
PSLLQ $0x20,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	vect (25.0%)
PMULUDQ %XMM4,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (12.5%)
PADDQ %XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVDQA 0x330(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
PADDQ %XMM3,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVDQA %XMM0,0x3e0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
PADDQ 0x320(%RSP),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM3,0x3f0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
MOVDQA 0x310(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
PMULUDQ %XMM4,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (12.5%)
MOVDQA 0x150(%RSP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
PMULUDQ %XMM2,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (12.5%)
PADDQ %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
PSLLQ $0x20,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	vect (25.0%)
PMULUDQ %XMM2,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (12.5%)
PADDQ %XMM1,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVDQA 0x380(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
PADDQ %XMM4,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVDQA %XMM0,0x3d0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
PADDQ 0x370(%RSP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM4,0xe0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
MOV $0x1,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVDQA 0x3db12(%RIP),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MOVDQA %XMM8,0xf0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
JMP 42d7c8 <_Z13field_summaryR16global_variablesR9parallel_.extracted+0xef8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
PXOR %XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
PXOR %XMM5,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
PXOR %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
JMP 42d523 <_Z13field_summaryR16global_variablesR9parallel_.extracted+0xc53>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code