OV - exec - Loop 173

	Loop Id: 173	Module: exec	Source: :0-0	Coverage: 1.34%

0x4236f0 MOVQ	%XMM7,%RSI

0x4236f5 MOVQ	%XMM9,%R14

0x4236fa XOR	%EDX,%EDX

0x4236fc MOV	%RSI,%RAX

0x4236ff DIV	%R14

0x423702 PSHUFD	$-0x12,%XMM7,%XMM1

0x423707 MOVQ	%RAX,%XMM3

0x42370c MOVQ	%XMM1,%RDI

0x423711 MOVDQA	0x40(%RSP),%XMM1    [8]

0x423717 MOVQ	%XMM1,%RBX

0x42371c XOR	%EDX,%EDX

0x42371e MOV	%RDI,%RAX

0x423721 DIV	%RBX

0x423724 MOVQ	%RAX,%XMM1

0x423729 PUNPCKLQDQ	%XMM1,%XMM3

0x42372d PSHUFD	$-0x18,%XMM3,%XMM12

0x423733 MOV	%RSI,%RAX

0x423736 CQTO

0x423738 PADDD	0x70(%RSP),%XMM12    [8]

0x42373f IDIV	%R14

0x423742 MOVQ	%RDX,%XMM1

0x423747 MOV	%RDI,%RAX

0x42374a CQTO

0x42374c IDIV	%RBX

0x42374f MOVQ	%RDX,%XMM3

0x423754 PUNPCKLQDQ	%XMM3,%XMM1

0x423758 PSHUFD	$-0x18,%XMM1,%XMM1

0x42375d PXOR	%XMM6,%XMM6

0x423761 PADDD	0x60(%RSP),%XMM1    [8]

0x423767 PXOR	%XMM10,%XMM10

0x42376c PCMPGTD	%XMM12,%XMM10

0x423771 MOVDQA	%XMM12,%XMM14

0x423776 MOVDQA	%XMM1,%XMM15

0x42377b PUNPCKLDQ	%XMM10,%XMM14

0x423780 MOVDQA	%XMM0,%XMM11

0x423785 PMULUDQ	%XMM14,%XMM11

0x42378a PADDD	%XMM8,%XMM15

0x42378f PUNPCKLDQ	0x47008(%RIP),%XMM10    [7]

0x423798 MOVDQA	%XMM2,%XMM3

0x42379c PMULUDQ	%XMM10,%XMM3

0x4237a1 PCMPGTD	%XMM15,%XMM6

0x4237a6 PADDQ	%XMM11,%XMM3

0x4237ab MOVDQA	%XMM2,%XMM11

0x4237b0 PMULUDQ	%XMM14,%XMM11

0x4237b5 PUNPCKLDQ	%XMM6,%XMM15

0x4237ba PXOR	%XMM6,%XMM6

0x4237be PCMPGTD	%XMM1,%XMM6

0x4237c2 PUNPCKLDQ	%XMM6,%XMM1

0x4237c6 PSLLQ	$0x20,%XMM3

0x4237cb PSUBD	%XMM8,%XMM12

0x4237d0 PXOR	%XMM6,%XMM6

0x4237d4 PCMPGTD	%XMM12,%XMM6

0x4237d9 PADDQ	%XMM11,%XMM3

0x4237de PUNPCKLDQ	%XMM6,%XMM12

0x4237e3 MOVDQA	%XMM2,%XMM11

0x4237e8 PMULUDQ	%XMM12,%XMM11

0x4237ed PMULUDQ	%XMM0,%XMM12

0x4237f2 PSHUFD	$-0x2c,%XMM6,%XMM6

0x4237f7 PMULUDQ	%XMM2,%XMM6

0x4237fb PADDQ	%XMM12,%XMM6

0x423800 PSLLQ	$0x20,%XMM6

0x423805 PADDQ	%XMM11,%XMM6

0x42380a MOVDQA	%XMM3,%XMM11

0x42380f PADDQ	%XMM1,%XMM3

0x423813 PSLLQ	$0x3,%XMM3

0x423818 PADDQ	%XMM4,%XMM3

0x42381c MOVQ	%XMM3,%RAX

0x423821 PSHUFD	$-0x12,%XMM3,%XMM3

0x423826 MOVQ	%XMM3,%RDX

0x42382b PADDQ	%XMM15,%XMM11

0x423830 PSLLQ	$0x3,%XMM11

0x423836 PADDQ	%XMM4,%XMM11

0x42383b MOVQ	%XMM11,%RSI

0x423840 PSHUFD	$-0x12,%XMM11,%XMM3

0x423846 PADDQ	%XMM6,%XMM15

0x42384b PSLLQ	$0x3,%XMM15

0x423851 MOVQ	%XMM3,%RDI

0x423856 PADDQ	%XMM4,%XMM15

0x42385b MOVQ	%XMM15,%RBX

0x423860 PSHUFD	$-0x12,%XMM15,%XMM3

0x423866 MOVSD	(%RAX),%XMM11    [4]

0x42386b MOVQ	%XMM3,%RAX

0x423870 PADDQ	%XMM1,%XMM6

0x423874 PSLLQ	$0x3,%XMM6

0x423879 MOVSD	(%RSI),%XMM3    [6]

0x42387d PADDQ	%XMM4,%XMM6

0x423881 MOVQ	%XMM6,%RSI

0x423886 MOVHPD	(%RDX),%XMM11    [12]

0x42388b PSHUFD	$-0x12,%XMM6,%XMM6

0x423890 MOVQ	%XMM6,%RDX

0x423895 MOVHPD	(%RDI),%XMM3    [1]

0x423899 MOVSD	(%RBX),%XMM6    [9]

0x42389d MOVHPD	(%RAX),%XMM6    [3]

0x4238a1 ADDPD	%XMM3,%XMM11

0x4238a6 MOVSD	(%RSI),%XMM3    [5]

0x4238aa MOVHPD	(%RDX),%XMM3    [11]

0x4238ae ADDPD	%XMM6,%XMM3

0x4238b2 ADDPD	%XMM11,%XMM3

0x4238b7 MOVDQA	%XMM5,%XMM6

0x4238bb PMULUDQ	%XMM14,%XMM6

0x4238c0 PMULUDQ	%XMM13,%XMM14

0x4238c5 PMULUDQ	%XMM5,%XMM10

0x4238ca PADDQ	%XMM14,%XMM10

0x4238cf PADDQ	%XMM1,%XMM6

0x4238d3 PSLLQ	$0x20,%XMM10

0x4238d9 PADDQ	%XMM10,%XMM6

0x4238de PSLLQ	$0x3,%XMM6

0x4238e3 PADDQ	0x50(%RSP),%XMM6    [8]

0x4238e9 MOVQ	%XMM6,%RAX

0x4238ee PSHUFD	$-0x12,%XMM6,%XMM1

0x4238f3 MOVQ	%XMM1,%RDX

0x4238f8 MULPD	0x47b20(%RIP),%XMM3    [7]

0x423900 MOVLPD	%XMM3,(%RAX)    [2]

0x423904 MOVHPD	%XMM3,(%RDX)    [10]

0x423908 PADDQ	0x47b20(%RIP),%XMM7    [7]

0x423910 ADD	$0x2,%RBP

0x423914 CMP	%R12,%RBP

0x423917 JB	4236f0

  ***  This Panel is Intentionally Left Blank.  ***

It is due to a lack of debug symbols in the given object
(loop or function).

Coverage (%)	Name	Module
►48.06+	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_launch_thread	libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]	libiomp5.so
○	start_thread	libc.so.6
○	__GI___clone3	libc.so.6
►41.13+	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_launch_thread	libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]	libiomp5.so
►5.27+	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_launch_thread	libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]	libiomp5.so
○	start_thread	libc.so.6
►2.38+	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_launch_thread	libiomp5.so
►1.50+	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_fork_call	libiomp5.so
○	__kmpc_fork_call	libiomp5.so
○	advec_mom_kernel(int, int, int[...]	exec
○	advec_mom_driver(global_variab[...]	exec
○	advection(global_variables&)	exec
○	hydro(global_variables&, paral[...]	exec
○	main	exec
○	__libc_start_call_main	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	exec
►1.46+	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_fork_call	libiomp5.so
○	__kmpc_fork_call	libiomp5.so
○	advec_mom_kernel(int, int, int[...]	exec
○	advec_mom_driver(global_variab[...]	exec
○	advection(global_variables&)	exec
○	hydro(global_variables&, paral[...]	exec
○	main	exec
○	__libc_start_call_main	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.58 - 2.70
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	7.66 - 8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.58 - 2.70
Bottlenecks	P10, P11,
Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone .extracted.23]
Source
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	28.00 - 48.00
CQA cycles if no scalar integer	17.75
CQA cycles if FP arith vectorized	28.00 - 48.00
CQA cycles if fully vectorized	3.66 - 6.00
Front-end cycles	15.50
P0 cycles	0.33
P1 cycles	0.33
P2 cycles	0.33
P3 cycles	8.00
P4 cycles	0.67
P5 cycles	0.33
P6 cycles	4.25
P7 cycles	4.25
P8 cycles	4.25
P9 cycles	4.25
P10 cycles	17.75
P11 cycles	17.75
P12 cycles	17.75
P13 cycles	17.75
P14 cycles	8.00
P15 cycles	8.00
DIV/SQRT cycles	28.00 - 48.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	118.00
Nb uops	124.00
Nb loads	15.00
Nb stores	2.00
Nb stack references	4.00
FLOP/cycle	0.29 - 0.17
Nb FLOP add-sub	6.00
Nb FLOP mul	2.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.00 - 6.86
Bytes prefetched	0.00
Bytes loaded	176.00
Bytes stored	16.00
Stride 0	2.00
Stride 1	0.00
Stride n	0.00
Stride unknown	10.00
Stride indirect	0.00
Vectorization ratio all	66.97
Vectorization ratio load	46.67
Vectorization ratio store	0.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	63.33
Vector-efficiency ratio all	19.27
Vector-efficiency ratio load	17.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	13.75
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	19.38

Metric	Value
CQA speedup if no scalar integer	1.58 - 2.70
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	7.66 - 8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.58 - 2.70
Bottlenecks	P10, P11,
Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone .extracted.23]
Source
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	28.00 - 48.00
CQA cycles if no scalar integer	17.75
CQA cycles if FP arith vectorized	28.00 - 48.00
CQA cycles if fully vectorized	3.66 - 6.00
Front-end cycles	15.50
P0 cycles	0.33
P1 cycles	0.33
P2 cycles	0.33
P3 cycles	8.00
P4 cycles	0.67
P5 cycles	0.33
P6 cycles	4.25
P7 cycles	4.25
P8 cycles	4.25
P9 cycles	4.25
P10 cycles	17.75
P11 cycles	17.75
P12 cycles	17.75
P13 cycles	17.75
P14 cycles	8.00
P15 cycles	8.00
DIV/SQRT cycles	28.00 - 48.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	118.00
Nb uops	124.00
Nb loads	15.00
Nb stores	2.00
Nb stack references	4.00
FLOP/cycle	0.29 - 0.17
Nb FLOP add-sub	6.00
Nb FLOP mul	2.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.00 - 6.86
Bytes prefetched	0.00
Bytes loaded	176.00
Bytes stored	16.00
Stride 0	2.00
Stride 1	0.00
Stride n	0.00
Stride unknown	10.00
Stride indirect	0.00
Vectorization ratio all	66.97
Vectorization ratio load	46.67
Vectorization ratio store	0.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	63.33
Vector-efficiency ratio all	19.27
Vector-efficiency ratio load	17.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	13.75
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	19.38

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone .extracted.23]
Source file and lines
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 48.00 to 17.75 cycles (2.70x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is partially vectorized. Only 19% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 48.00 to 6.00 cycles (8.00x speedup).

Details

66% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

46% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
63% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 48.00 to 17.75 cycles (2.70x speedup).

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact.
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 48.00 to 18.75 cycles (2.56x speedup).

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- Please look into your compiler manual for march=native or equivalent
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
IDIV: 2 occurrences►
MOVHPD: 1 occurrences►
MOVQ: 4 occurrences►

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 10 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vector unaligned load/store instructions

Detected 5 suboptimal vector unaligned load/store instructions.

Details

MOVHPD: 5 occurrences►

Workaround

Pass to your compiler a micro-architecture specialization option:
- Please look into your compiler manual for march=native or equivalent
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries
2. inform your compiler that your arrays are vector aligned: read your compiler manual.

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 2 occurrences►

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

4 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 8 FP arithmetical operations:

6: addition or subtraction
2: multiply

The binary loop is loading 176 bytes (22 double precision FP elements). The binary loop is storing 16 bytes (2 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

General properties

nb instructions	118
nb uops	124
loop length	557
used x86 registers	9
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	4
ADD-SUB / MUL ratio	3.00

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	15.50 cycles
front end	15.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.33	0.33	0.33	8.00	0.67	0.33	4.25	4.25	4.25	4.25	17.75	17.75	17.75	17.75	8.00	8.00
cycles	0.33	0.33	0.33	8.00	0.67	0.33	4.25	4.25	4.25	4.25	17.75	17.75	17.75	17.75	8.00	8.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	28.00-48.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	15.50
Dispatch	17.75
DIV/SQRT	28.00-48.00
Data deps.	1.00
Overall L1	28.00-48.00

Vectorization ratios

INT

all	72%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	59%

all	28%
load	11%
store	0%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	66%
load	46%
store	0%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	63%

Vector efficiency ratios

INT

all	19%
load	22%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	18%

all	16%
load	13%
store	12%
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	19%
load	17%
store	12%
mul	13%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	19%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 48.00 cycles. At this rate:

1% of peak load performance is reached (3.67 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.33 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4236f0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
MOVQ %XMM7,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVQ %XMM9,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %RSI,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %R14	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	10-22	7-12	scal (12.5%)
PSHUFD $-0x12,%XMM7,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVQ %RAX,%XMM3	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (12.5%)
MOVQ %XMM1,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVDQA 0x40(%RSP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MOVQ %XMM1,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %RDI,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %RBX	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	10-22	7-12	scal (12.5%)
MOVQ %RAX,%XMM1	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (12.5%)
PUNPCKLQDQ %XMM1,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
PSHUFD $-0x18,%XMM3,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOV %RSI,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CQTO																				scal (12.5%)
PADDD 0x70(%RSP),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (25.0%)
IDIV %R14	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12	scal (12.5%)
MOVQ %RDX,%XMM1	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (12.5%)
MOV %RDI,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CQTO																				scal (12.5%)
IDIV %RBX	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12	scal (12.5%)
MOVQ %RDX,%XMM3	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (12.5%)
PUNPCKLQDQ %XMM3,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
PSHUFD $-0x18,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
PXOR %XMM6,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
PADDD 0x60(%RSP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (25.0%)
PXOR %XMM10,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
PCMPGTD %XMM12,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVDQA %XMM12,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOVDQA %XMM1,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
PUNPCKLDQ %XMM10,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (12.5%)
MOVDQA %XMM0,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
PMULUDQ %XMM14,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (12.5%)
PADDD %XMM8,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
PUNPCKLDQ 0x47008(%RIP),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (12.5%)
MOVDQA %XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
PMULUDQ %XMM10,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (12.5%)
PCMPGTD %XMM15,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
PADDQ %XMM11,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVDQA %XMM2,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
PMULUDQ %XMM14,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (12.5%)
PUNPCKLDQ %XMM6,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (12.5%)
PXOR %XMM6,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
PCMPGTD %XMM1,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
PUNPCKLDQ %XMM6,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (12.5%)
PSLLQ $0x20,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	vect (25.0%)
PSUBD %XMM8,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
PXOR %XMM6,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
PCMPGTD %XMM12,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
PADDQ %XMM11,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
PUNPCKLDQ %XMM6,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (12.5%)
MOVDQA %XMM2,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
PMULUDQ %XMM12,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (12.5%)
PMULUDQ %XMM0,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (12.5%)
PSHUFD $-0x2c,%XMM6,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
PMULUDQ %XMM2,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (12.5%)
PADDQ %XMM12,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
PSLLQ $0x20,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	vect (25.0%)
PADDQ %XMM11,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVDQA %XMM3,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
PADDQ %XMM1,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
PSLLQ $0x3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	vect (25.0%)
PADDQ %XMM4,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVQ %XMM3,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
PSHUFD $-0x12,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVQ %XMM3,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
PADDQ %XMM15,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
PSLLQ $0x3,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	vect (25.0%)
PADDQ %XMM4,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVQ %XMM11,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
PSHUFD $-0x12,%XMM11,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
PADDQ %XMM6,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
PSLLQ $0x3,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	vect (25.0%)
MOVQ %XMM3,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
PADDQ %XMM4,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVQ %XMM15,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
PSHUFD $-0x12,%XMM15,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVSD (%RAX),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVQ %XMM3,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
PADDQ %XMM1,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
PSLLQ $0x3,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	vect (25.0%)
MOVSD (%RSI),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
PADDQ %XMM4,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVQ %XMM6,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVHPD (%RDX),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
PSHUFD $-0x12,%XMM6,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVQ %XMM6,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVHPD (%RDI),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
MOVSD (%RBX),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVHPD (%RAX),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
ADDPD %XMM3,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
MOVSD (%RSI),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVHPD (%RDX),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
ADDPD %XMM6,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
ADDPD %XMM11,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
MOVDQA %XMM5,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
PMULUDQ %XMM14,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (12.5%)
PMULUDQ %XMM13,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (12.5%)
PMULUDQ %XMM5,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (12.5%)
PADDQ %XMM14,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
PADDQ %XMM1,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
PSLLQ $0x20,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	vect (25.0%)
PADDQ %XMM10,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
PSLLQ $0x3,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	vect (25.0%)
PADDQ 0x50(%RSP),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (25.0%)
MOVQ %XMM6,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
PSHUFD $-0x12,%XMM6,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVQ %XMM1,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MULPD 0x47b20(%RIP),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
MOVLPD %XMM3,(%RAX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVHPD %XMM3,(%RDX)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	scal (12.5%)
PADDQ 0x47b20(%RIP),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (25.0%)
ADD $0x2,%RBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R12,%RBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JB 4236f0 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.23+0x170>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone .extracted.23]
Source file and lines
Module	exec

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

66% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

46% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
63% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact.
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 48.00 to 18.75 cycles (2.56x speedup).

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- Please look into your compiler manual for march=native or equivalent
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
IDIV: 2 occurrences►
MOVHPD: 1 occurrences►
MOVQ: 4 occurrences►

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 10 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vector unaligned load/store instructions

Detected 5 suboptimal vector unaligned load/store instructions.

Details

MOVHPD: 5 occurrences►

Workaround

Pass to your compiler a micro-architecture specialization option:
- Please look into your compiler manual for march=native or equivalent
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries
2. inform your compiler that your arrays are vector aligned: read your compiler manual.

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 2 occurrences►

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

4 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 8 FP arithmetical operations:

6: addition or subtraction
2: multiply

The binary loop is loading 176 bytes (22 double precision FP elements). The binary loop is storing 16 bytes (2 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

General properties

nb instructions	118
nb uops	124
loop length	557
used x86 registers	9
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	4
ADD-SUB / MUL ratio	3.00

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	15.50 cycles
front end	15.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.33	0.33	0.33	8.00	0.67	0.33	4.25	4.25	4.25	4.25	17.75	17.75	17.75	17.75	8.00	8.00
cycles	0.33	0.33	0.33	8.00	0.67	0.33	4.25	4.25	4.25	4.25	17.75	17.75	17.75	17.75	8.00	8.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	28.00-48.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	15.50
Dispatch	17.75
DIV/SQRT	28.00-48.00
Data deps.	1.00
Overall L1	28.00-48.00

Vectorization ratios

INT

all	72%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	59%

all	28%
load	11%
store	0%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	66%
load	46%
store	0%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	63%

Vector efficiency ratios

INT

all	19%
load	22%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	18%

all	16%
load	13%
store	12%
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	19%
load	17%
store	12%
mul	13%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	19%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 48.00 cycles. At this rate:

1% of peak load performance is reached (3.67 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.33 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4236f0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
MOVQ %XMM7,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVQ %XMM9,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %RSI,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %R14	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	10-22	7-12	scal (12.5%)
PSHUFD $-0x12,%XMM7,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVQ %RAX,%XMM3	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (12.5%)
MOVQ %XMM1,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVDQA 0x40(%RSP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MOVQ %XMM1,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %RDI,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %RBX	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	10-22	7-12	scal (12.5%)
MOVQ %RAX,%XMM1	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (12.5%)
PUNPCKLQDQ %XMM1,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
PSHUFD $-0x18,%XMM3,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOV %RSI,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CQTO																				scal (12.5%)
PADDD 0x70(%RSP),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (25.0%)
IDIV %R14	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12	scal (12.5%)
MOVQ %RDX,%XMM1	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (12.5%)
MOV %RDI,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CQTO																				scal (12.5%)
IDIV %RBX	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12	scal (12.5%)
MOVQ %RDX,%XMM3	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (12.5%)
PUNPCKLQDQ %XMM3,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
PSHUFD $-0x18,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
PXOR %XMM6,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
PADDD 0x60(%RSP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (25.0%)
PXOR %XMM10,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
PCMPGTD %XMM12,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVDQA %XMM12,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOVDQA %XMM1,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
PUNPCKLDQ %XMM10,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (12.5%)
MOVDQA %XMM0,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
PMULUDQ %XMM14,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (12.5%)
PADDD %XMM8,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
PUNPCKLDQ 0x47008(%RIP),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (12.5%)
MOVDQA %XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
PMULUDQ %XMM10,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (12.5%)
PCMPGTD %XMM15,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
PADDQ %XMM11,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVDQA %XMM2,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
PMULUDQ %XMM14,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (12.5%)
PUNPCKLDQ %XMM6,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (12.5%)
PXOR %XMM6,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
PCMPGTD %XMM1,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
PUNPCKLDQ %XMM6,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (12.5%)
PSLLQ $0x20,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	vect (25.0%)
PSUBD %XMM8,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
PXOR %XMM6,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
PCMPGTD %XMM12,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
PADDQ %XMM11,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
PUNPCKLDQ %XMM6,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (12.5%)
MOVDQA %XMM2,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
PMULUDQ %XMM12,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (12.5%)
PMULUDQ %XMM0,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (12.5%)
PSHUFD $-0x2c,%XMM6,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
PMULUDQ %XMM2,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (12.5%)
PADDQ %XMM12,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
PSLLQ $0x20,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	vect (25.0%)
PADDQ %XMM11,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVDQA %XMM3,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
PADDQ %XMM1,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
PSLLQ $0x3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	vect (25.0%)
PADDQ %XMM4,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVQ %XMM3,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
PSHUFD $-0x12,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVQ %XMM3,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
PADDQ %XMM15,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
PSLLQ $0x3,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	vect (25.0%)
PADDQ %XMM4,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVQ %XMM11,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
PSHUFD $-0x12,%XMM11,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
PADDQ %XMM6,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
PSLLQ $0x3,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	vect (25.0%)
MOVQ %XMM3,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
PADDQ %XMM4,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVQ %XMM15,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
PSHUFD $-0x12,%XMM15,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVSD (%RAX),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVQ %XMM3,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
PADDQ %XMM1,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
PSLLQ $0x3,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	vect (25.0%)
MOVSD (%RSI),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
PADDQ %XMM4,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVQ %XMM6,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVHPD (%RDX),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
PSHUFD $-0x12,%XMM6,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVQ %XMM6,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVHPD (%RDI),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
MOVSD (%RBX),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVHPD (%RAX),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
ADDPD %XMM3,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
MOVSD (%RSI),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVHPD (%RDX),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
ADDPD %XMM6,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
ADDPD %XMM11,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
MOVDQA %XMM5,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
PMULUDQ %XMM14,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (12.5%)
PMULUDQ %XMM13,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (12.5%)
PMULUDQ %XMM5,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (12.5%)
PADDQ %XMM14,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
PADDQ %XMM1,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
PSLLQ $0x20,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	vect (25.0%)
PADDQ %XMM10,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
PSLLQ $0x3,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	vect (25.0%)
PADDQ 0x50(%RSP),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (25.0%)
MOVQ %XMM6,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
PSHUFD $-0x12,%XMM6,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVQ %XMM1,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MULPD 0x47b20(%RIP),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
MOVLPD %XMM3,(%RAX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVHPD %XMM3,(%RDX)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	scal (12.5%)
PADDQ 0x47b20(%RIP),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (25.0%)
ADD $0x2,%RBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R12,%RBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JB 4236f0 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.23+0x170>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Report Configuration

Code clean check

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Vectorization

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Execution units bottlenecks

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Expensive FP math instructions/calls

FMA

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Complex instructions

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Slow data structures access

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Vector unaligned load/store instructions

Details

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Conversion instructions

Details

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Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code