OV - exec - Function __svml_idiv4

	Function: __svml_idiv4_e9	Module: exec	Source: :0-0	Coverage (incl. loops): 0.03% \| (excl. loops): 0.03%

  ***  This Panel is Intentionally Left Blank.  ***

It is due to a lack of debug symbols in the given object
(loop or function).

0x459220 ENDBR64

0x459224 VPXOR	%XMM2,%XMM2,%XMM2

0x459228 VPCMPEQD	%XMM2,%XMM1,%XMM2

0x45922c VTESTPS	%XMM2,%XMM2

0x459231 JE	45923a

0x459233 MOV	$0,%EAX

0x459238 DIV	%AL

0x45923a VCVTDQ2PS	%XMM1,%XMM2

0x45923e VRCPPS	%XMM2,%XMM2

0x459242 VCVTPS2PD	%XMM2,%YMM2

0x459246 VCVTDQ2PD	%XMM1,%YMM1

0x45924a VMULPD	%YMM2,%YMM1,%YMM3

0x45924e VBROADCASTSD	0x12269(%RIP),%YMM4

0x459257 VSUBPD	%YMM3,%YMM4,%YMM3

0x45925b VMULPD	%YMM2,%YMM3,%YMM2

0x45925f VCVTDQ2PD	%XMM0,%YMM0

0x459263 VMULPD	%YMM0,%YMM2,%YMM0

0x459267 VMULPD	%YMM1,%YMM2,%YMM1

0x45926b VBROADCASTSD	0x1300c(%RIP),%YMM2

0x459274 VSUBPD	%YMM1,%YMM2,%YMM1

0x459278 VMULPD	%YMM1,%YMM0,%YMM0

0x45927c VCVTTPD2DQ	%YMM0,%XMM0

0x459280 VZEROUPPER

0x459283 RET

0x459284 NOPW	%CS:(%RAX,%RAX,1)

0x45928e XCHG	%AX,%AX

Coverage (%)	Name	Module
►48.43+	__svml_idiv4	exec
○	field_summary(global_variables[...]	exec
○	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_launch_thread	libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]	libiomp5.so
○	start_thread	libc.so.6
○	__GI___clone3	libc.so.6
►38.26+	__svml_idiv4	exec
○	field_summary(global_variables[...]	exec
○	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_launch_thread	libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]	libiomp5.so
►6.10+	__svml_idiv4	exec
○	field_summary(global_variables[...]	exec
○	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_launch_thread	libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]	libiomp5.so
○	start_thread	libc.so.6
►3.14+	__svml_idiv4	exec
○	field_summary(global_variables[...]	exec
○	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_launch_thread	libiomp5.so
►2.96+	__svml_idiv4	exec
○	field_summary(global_variables[...]	exec
○	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_fork_call	libiomp5.so
○	__kmpc_fork_call	libiomp5.so
○	field_summary(global_variables[...]	exec
○	hydro(global_variables&, paral[...]	exec
○	main	exec
○	__libc_start_call_main	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.03% of application time for run icx_0

Source file and lines
Module	exec

The structure of this function is probably <if then [else] end>.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside function: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the function)
turning them into conditional moves, MIN or MAX

gain
potential
hint
expert

Vectorization

Your function is partially vectorized. Only 33% of vector register length is used (average across all SSE/AVX instructions).

Details

87% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
78% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- Please look into your compiler manual for march=native or equivalent
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 0 occurrences
VCVTDQ2PD: 0 occurrences
VCVTPS2PD: 0 occurrences
VCVTTPD2DQ: 0 occurrences
VTESTPS: 0 occurrences

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTDQ2PD (INT32 to FP64, SIMD): 0 occurrences
VCVTDQ2PS (INT32 to FP32, SIMD): 0 occurrences
VCVTPS2PD (FP32 to FP64, SIMD): 0 occurrences
VCVTTPD2DQ (FP64 to INT32, SIMD): 0 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements. Use double instead of single precision only when/where needed by numerical stability and avoid mixing precision.

Type of elements and instruction set

2 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in vector mode (four at a time). 7 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 32 FP arithmetical operations:

8: addition or subtraction
20: multiply
4: fast reciprocal

The binary function is loading 16 bytes (2 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 2.00 FP operations per loaded or stored byte.

General properties

nb instructions	23
nb uops	27.50
loop length	96.50
used x86 registers	0.50
used mmx registers	0
used xmm registers	3
used ymm registers	5
used zmm registers	0
nb stack references	0
ADD-SUB / MUL ratio	0.40

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	3.44 cycles
front end	3.44 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.17	0.17	0.17	1.33	0.83	0.83	0.50	0.50	0.50	0.50	4.75	4.75	4.75	4.75	0.50	0.50
cycles	0.17	0.17	0.17	1.33	0.83	0.83	0.50	0.50	0.50	0.50	4.75	4.75	4.75	4.75	0.50	0.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

2.00

Cycles summary

Front-end	3.44
Dispatch	4.75
DIV/SQRT	2.00
Overall L1	4.75

Vectorization ratios

INT

all	92%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	92%

all	84%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	60%

INT+FP

all	87%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	78%

Vector efficiency ratios

INT

all	23%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	23%

all	38%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	25%
other	25%

INT+FP

all	33%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	25%
other	24%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.75 cycles. At this rate:

1% of peak load performance is reached (3.37 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

The code analyzed by CQA in that panel excludes loops and represents 0.03% of application time for run icx_0

Source file and lines
Module	exec

hoisting them (moving them outside the function)
turning them into conditional moves, MIN or MAX

gain
potential
hint
expert

Vectorization

Your function is partially vectorized. Only 32% of vector register length is used (average across all SSE/AVX instructions).

Details

85% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
75% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Performance is limited by:

execution of FP add operations (the FP add unit is a bottleneck)
execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck)

Workaround

Reduce the number of FP add instructions
Reduce the number of FP multiply/FMA instructions

512-bits vectorization

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- Please look into your compiler manual for march=native or equivalent
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 1 occurrences►
VCVTDQ2PD: 2 occurrences►
VCVTPS2PD: 1 occurrences►
VCVTTPD2DQ: 1 occurrences►
VTESTPS: 1 occurrences►

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTDQ2PD (INT32 to FP64, SIMD): 2 occurrences►
VCVTDQ2PS (INT32 to FP32, SIMD): 1 occurrences►
VCVTPS2PD (FP32 to FP64, SIMD): 1 occurrences►
VCVTTPD2DQ (FP64 to INT32, SIMD): 1 occurrences►

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function is composed of 32 FP arithmetical operations:

8: addition or subtraction
20: multiply
4: fast reciprocal

The binary function is loading 16 bytes (2 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 2.00 FP operations per loaded or stored byte.

General properties

nb instructions	24
nb uops	29
loop length	100
used x86 registers	1
used mmx registers	0
used xmm registers	3
used ymm registers	5
used zmm registers	0
nb stack references	0
ADD-SUB / MUL ratio	0.40

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.63 cycles
front end	3.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.33	0.33	0.33	2.00	1.00	1.00	0.50	0.50	0.50	0.50	4.75	4.75	4.75	4.75	0.50	0.50
cycles	0.33	0.33	0.33	2.00	1.00	1.00	0.50	0.50	0.50	0.50	4.75	4.75	4.75	4.75	0.50	0.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

4.00

Cycles summary

Front-end	3.63
Dispatch	4.75
DIV/SQRT	4.00
Overall L1	4.75

Vectorization ratios

INT

all	85%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	85%

all	84%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	60%

INT+FP

all	85%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	75%

Vector efficiency ratios

INT

all	22%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	22%

all	38%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	25%
other	25%

INT+FP

all	32%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	25%
other	23%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.75 cycles. At this rate:

1% of peak load performance is reached (3.37 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 459220

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
ENDBR64																				N/A
VPXOR %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
VPCMPEQD %XMM2,%XMM1,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VTESTPS %XMM2,%XMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	7	0.50	vect (25.0%)
JE 45923a <__svml_idiv4_e9+0x1a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV $0,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
DIV %AL	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	10-14	4	N/A
VCVTDQ2PS %XMM1,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VRCPPS %XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (25.0%)
VCVTPS2PD %XMM2,%YMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	1	0.50	0	0	4	0.67	vect (25.0%)
VCVTDQ2PD %XMM1,%YMM1	2	0	0	0	0	0	0	0	0	0	0	0	0.50	1	0.50	0	0	4	0.67	vect (25.0%)
VMULPD %YMM2,%YMM1,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VBROADCASTSD 0x12269(%RIP),%YMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VSUBPD %YMM3,%YMM4,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMULPD %YMM2,%YMM3,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VCVTDQ2PD %XMM0,%YMM0	2	0	0	0	0	0	0	0	0	0	0	0	0.50	1	0.50	0	0	4	0.67	vect (25.0%)
VMULPD %YMM0,%YMM2,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMULPD %YMM1,%YMM2,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VBROADCASTSD 0x1300c(%RIP),%YMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VSUBPD %YMM1,%YMM2,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMULPD %YMM1,%YMM0,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VCVTTPD2DQ %YMM0,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0	0.50	1	0.50	0	0	6	0.67	vect (50.0%)
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.03% of application time for run icx_0

Source file and lines
Module	exec

hoisting them (moving them outside the function)
turning them into conditional moves, MIN or MAX

gain
potential
hint
expert

Vectorization

Your function is partially vectorized. Only 34% of vector register length is used (average across all SSE/AVX instructions).

Details

89% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
81% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Performance is limited by:

execution of FP add operations (the FP add unit is a bottleneck)
execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 4.75 to 3.25 cycles (1.46x speedup).

Workaround

Reduce the number of FP add instructions
Reduce the number of FP multiply/FMA instructions

512-bits vectorization

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- Please look into your compiler manual for march=native or equivalent
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTDQ2PD: 2 occurrences►
VCVTPS2PD: 1 occurrences►
VCVTTPD2DQ: 1 occurrences►
VTESTPS: 1 occurrences►

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTDQ2PD (INT32 to FP64, SIMD): 2 occurrences►
VCVTDQ2PS (INT32 to FP32, SIMD): 1 occurrences►
VCVTPS2PD (FP32 to FP64, SIMD): 1 occurrences►
VCVTTPD2DQ (FP64 to INT32, SIMD): 1 occurrences►

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function is composed of 32 FP arithmetical operations:

8: addition or subtraction
20: multiply
4: fast reciprocal

The binary function is loading 16 bytes (2 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 2.00 FP operations per loaded or stored byte.

General properties

nb instructions	22
nb uops	26
loop length	93
used x86 registers	0
used mmx registers	0
used xmm registers	3
used ymm registers	5
used zmm registers	0
nb stack references	0
ADD-SUB / MUL ratio	0.40

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.25 cycles
front end	3.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.00	0.00	0.00	0.67	0.67	0.67	0.50	0.50	0.50	0.50	4.75	4.75	4.75	4.75	0.50	0.50
cycles	0.00	0.00	0.00	0.67	0.67	0.67	0.50	0.50	0.50	0.50	4.75	4.75	4.75	4.75	0.50	0.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.25
Dispatch	4.75
Overall L1	4.75

Vectorization ratios

INT

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	84%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	60%

INT+FP

all	89%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	81%

Vector efficiency ratios

INT

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	38%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	25%
other	25%

INT+FP

all	34%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	25%
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.75 cycles. At this rate:

1% of peak load performance is reached (3.37 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 459220

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
ENDBR64																				N/A
VPXOR %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
VPCMPEQD %XMM2,%XMM1,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VTESTPS %XMM2,%XMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	7	0.50	vect (25.0%)
JE 45923a <__svml_idiv4_e9+0x1a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VCVTDQ2PS %XMM1,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VRCPPS %XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (25.0%)
VCVTPS2PD %XMM2,%YMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	1	0.50	0	0	4	0.67	vect (25.0%)
VCVTDQ2PD %XMM1,%YMM1	2	0	0	0	0	0	0	0	0	0	0	0	0.50	1	0.50	0	0	4	0.67	vect (25.0%)
VMULPD %YMM2,%YMM1,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VBROADCASTSD 0x12269(%RIP),%YMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VSUBPD %YMM3,%YMM4,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMULPD %YMM2,%YMM3,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VCVTDQ2PD %XMM0,%YMM0	2	0	0	0	0	0	0	0	0	0	0	0	0.50	1	0.50	0	0	4	0.67	vect (25.0%)
VMULPD %YMM0,%YMM2,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMULPD %YMM1,%YMM2,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VBROADCASTSD 0x1300c(%RIP),%YMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VSUBPD %YMM1,%YMM2,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMULPD %YMM1,%YMM0,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VCVTTPD2DQ %YMM0,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0	0.50	1	0.50	0	0	6	0.67	vect (50.0%)
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
○__svml_idiv4_e9	0.03	0.01

Report Configuration

Vectorization

Details

Workaround

512-bits vectorization

FMA

Workaround

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

512-bits vectorization

FMA

Workaround

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

512-bits vectorization

FMA

Workaround

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code