OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone .extracted.51]

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: :0-0	Coverage (incl. loops): 1.29% \| (excl. loops): 0.00%

  ***  This Panel is Intentionally Left Blank.  ***

It is due to a lack of debug symbols in the given object
(loop or function).

0x425180 PUSH	%RBP

0x425181 PUSH	%R15

0x425183 PUSH	%R14

0x425185 PUSH	%R13

0x425187 PUSH	%R12

0x425189 PUSH	%RBX

0x42518a SUB	$0x88,%RSP

0x425191 MOV	%R8,0x8(%RSP)

0x425196 MOV	0xd0(%RSP),%RAX

0x42519e MOV	0xc0(%RSP),%R13

0x4251a6 MOVL	$0,0x4(%RSP)

0x4251ae TEST	%RAX,%RAX

0x4251b1 JS	425554

0x4251b7 MOV	%R9,%R14

0x4251ba MOV	%RCX,%R15

0x4251bd MOV	%RDX,%R12

0x4251c0 MOV	(%RDI),%ESI

0x4251c2 MOVQ	$0,0x18(%RSP)

0x4251cb MOV	%RAX,0x10(%RSP)

0x4251d0 MOVQ	$0x1,0x38(%RSP)

0x4251d9 SUB	$0x8,%RSP

0x4251dd LEA	0x40(%RSP),%RAX

0x4251e2 LEA	0xc(%RSP),%RCX

0x4251e7 LEA	0x20(%RSP),%R8

0x4251ec LEA	0x18(%RSP),%R9

0x4251f1 MOV	$0x47c9d0,%EDI

0x4251f6 MOV	%ESI,0x8(%RSP)

0x4251fa MOV	$0x22,%EDX

0x4251ff PUSH	$0x1

0x425201 PUSH	$0x1

0x425203 PUSH	%RAX

0x425204 CALL	4031e0 <__kmpc_for_static_init_8@plt>

0x425209 ADD	$0x20,%RSP

0x42520d MOV	0x18(%RSP),%RCX

0x425212 MOV	0x10(%RSP),%R9

0x425217 CMP	%R9,%RCX

0x42521a JA	425536

0x425220 SUB	%R14D,%R13D

0x425223 MOV	(%R12),%R10

0x425227 MOV	0x10(%R12),%R11

0x42522c MOV	(%R15),%R12

0x42522f MOV	0x10(%R15),%R15

0x425233 INC	%R9

0x425236 MOV	%R9,%RAX

0x425239 SUB	%RCX,%RAX

0x42523c MOV	$-0x2,%EBP

0x425241 AND	%RAX,%RBP

0x425244 JE	4255e4

0x42524a MOV	%RAX,0x20(%RSP)

0x42524f MOVD	%R13D,%XMM0

0x425254 PSHUFD	$0x44,%XMM0,%XMM1

0x425259 MOVD	0x8(%RSP),%XMM0

0x42525f PSHUFD	$0x50,%XMM0,%XMM0

0x425264 MOVDQA	%XMM0,0x70(%RSP)

0x42526a MOV	%R14,0x30(%RSP)

0x42526f MOVD	%R14D,%XMM0

0x425274 PSHUFD	$0x50,%XMM0,%XMM0

0x425279 MOVDQA	%XMM0,0x60(%RSP)

0x42527f MOVQ	%R10,%XMM0

0x425284 PSHUFD	$0x44,%XMM0,%XMM2

0x425289 MOVQ	%R11,%XMM0

0x42528e PSHUFD	$0x44,%XMM0,%XMM4

0x425293 MOV	%R12,0x28(%RSP)

0x425298 MOVQ	%R12,%XMM0

0x42529d PSHUFD	$0x44,%XMM0,%XMM5

0x4252a2 MOVQ	%R15,%XMM0

0x4252a7 PSHUFD	$0x44,%XMM0,%XMM0

0x4252ac MOVDQA	%XMM0,0x50(%RSP)

0x4252b2 MOVQ	%RCX,%XMM0

0x4252b7 PSHUFD	$0x44,%XMM0,%XMM7

0x4252bc PADDQ	0x4614c(%RIP),%XMM7

0x4252c4 XOR	%R14D,%R14D

0x4252c7 MOVDQA	%XMM1,%XMM10

0x4252cc PSHUFD	$-0x12,%XMM1,%XMM0

0x4252d1 MOVDQA	%XMM0,0x40(%RSP)

0x4252d7 MOVDQA	%XMM2,%XMM6

0x4252db PSRLQ	$0x20,%XMM6

0x4252e0 MOVDQA	%XMM5,%XMM13

0x4252e5 PSRLQ	$0x20,%XMM13

0x4252eb PCMPEQD	%XMM8,%XMM8

(181) 0x4252f0 MOVQ	%XMM7,%RSI

(181) 0x4252f5 MOVQ	%XMM10,%RBX

(181) 0x4252fa MOV	%RSI,%RAX

(181) 0x4252fd XOR	%EDX,%EDX

(181) 0x4252ff DIV	%RBX

(181) 0x425302 MOV	%RAX,%RDI

(181) 0x425305 PSHUFD	$-0x12,%XMM7,%XMM1

(181) 0x42530a MOVQ	%XMM1,%R8

(181) 0x42530f MOVDQA	0x40(%RSP),%XMM0

(181) 0x425315 MOVQ	%XMM0,%R12

(181) 0x42531a MOV	%R8,%RAX

(181) 0x42531d XOR	%EDX,%EDX

(181) 0x42531f DIV	%R12

(181) 0x425322 MOVQ	%RDI,%XMM1

(181) 0x425327 MOVQ	%RAX,%XMM3

(181) 0x42532c PUNPCKLQDQ	%XMM3,%XMM1

(181) 0x425330 PSHUFD	$-0x18,%XMM1,%XMM15

(181) 0x425336 PADDD	0x70(%RSP),%XMM15

(181) 0x42533d MOV	%RSI,%RAX

(181) 0x425340 CQTO

(181) 0x425342 IDIV	%RBX

(181) 0x425345 MOV	%RDX,%RSI

(181) 0x425348 MOV	%R8,%RAX

(181) 0x42534b CQTO

(181) 0x42534d MOVQ	%RSI,%XMM1

(181) 0x425352 IDIV	%R12

(181) 0x425355 MOVQ	%RDX,%XMM3

(181) 0x42535a PUNPCKLQDQ	%XMM3,%XMM1

(181) 0x42535e PSHUFD	$-0x18,%XMM1,%XMM9

(181) 0x425364 PXOR	%XMM14,%XMM14

(181) 0x425369 MOVDQA	%XMM15,%XMM11

(181) 0x42536e PADDD	0x60(%RSP),%XMM9

(181) 0x425375 PADDD	%XMM8,%XMM11

(181) 0x42537a PXOR	%XMM1,%XMM1

(181) 0x42537e PCMPGTD	%XMM11,%XMM1

(181) 0x425383 PCMPGTD	%XMM9,%XMM14

(181) 0x425388 PUNPCKLDQ	%XMM1,%XMM11

(181) 0x42538d MOVDQA	%XMM2,%XMM3

(181) 0x425391 PMULUDQ	%XMM11,%XMM3

(181) 0x425396 MOVDQA	%XMM9,%XMM12

(181) 0x42539b PMULUDQ	%XMM6,%XMM11

(181) 0x4253a0 PSHUFD	$-0x2c,%XMM1,%XMM1

(181) 0x4253a5 PMULUDQ	%XMM2,%XMM1

(181) 0x4253a9 PUNPCKLDQ	%XMM14,%XMM12

(181) 0x4253ae PXOR	%XMM14,%XMM14

(181) 0x4253b3 PCMPGTD	%XMM15,%XMM14

(181) 0x4253b8 PUNPCKLDQ	%XMM14,%XMM15

(181) 0x4253bd PADDQ	%XMM11,%XMM1

(181) 0x4253c2 MOVDQA	%XMM6,%XMM0

(181) 0x4253c6 PUNPCKLDQ	0x453d1(%RIP),%XMM14

(181) 0x4253cf MOVDQA	%XMM2,%XMM11

(181) 0x4253d4 PMULUDQ	%XMM15,%XMM0

(181) 0x4253d9 PMULUDQ	%XMM14,%XMM11

(181) 0x4253de PADDQ	%XMM0,%XMM11

(181) 0x4253e3 MOVDQA	%XMM2,%XMM0

(181) 0x4253e7 PMULUDQ	%XMM15,%XMM0

(181) 0x4253ec PSLLQ	$0x20,%XMM11

(181) 0x4253f2 PADDQ	%XMM0,%XMM11

(181) 0x4253f7 PSLLQ	$0x20,%XMM1

(181) 0x4253fc PADDQ	%XMM3,%XMM1

(181) 0x425400 MOVDQA	%XMM1,%XMM0

(181) 0x425404 PADDQ	%XMM12,%XMM0

(181) 0x425409 PSLLQ	$0x3,%XMM0

(181) 0x42540e PADDQ	%XMM4,%XMM0

(181) 0x425412 MOVQ	%XMM0,%RAX

(181) 0x425417 PSHUFD	$-0x12,%XMM0,%XMM0

(181) 0x42541c PSUBD	%XMM8,%XMM9

(181) 0x425421 MOVQ	%XMM0,%RDX

(181) 0x425426 PXOR	%XMM0,%XMM0

(181) 0x42542a PCMPGTD	%XMM9,%XMM0

(181) 0x42542f PUNPCKLDQ	%XMM0,%XMM9

(181) 0x425434 PADDQ	%XMM9,%XMM1

(181) 0x425439 PADDQ	%XMM11,%XMM9

(181) 0x42543e PADDQ	%XMM12,%XMM11

(181) 0x425443 PSLLQ	$0x3,%XMM11

(181) 0x425449 PADDQ	%XMM4,%XMM11

(181) 0x42544e MOVQ	%XMM11,%RSI

(181) 0x425453 PSLLQ	$0x3,%XMM1

(181) 0x425458 PSHUFD	$-0x12,%XMM11,%XMM0

(181) 0x42545e PADDQ	%XMM4,%XMM1

(181) 0x425462 MOVQ	%XMM1,%RDI

(181) 0x425467 PSHUFD	$-0x12,%XMM1,%XMM1

(181) 0x42546c MOVQ	%XMM0,%R8

(181) 0x425471 MOVQ	%XMM1,%RBX

(181) 0x425476 MOVSD	(%RDI),%XMM0

(181) 0x42547a PSLLQ	$0x3,%XMM9

(181) 0x425480 MOVSD	(%RAX),%XMM1

(181) 0x425484 PADDQ	%XMM4,%XMM9

(181) 0x425489 MOVQ	%XMM9,%RAX

(181) 0x42548e MOVHPD	(%RBX),%XMM0

(181) 0x425492 PSHUFD	$-0x12,%XMM9,%XMM3

(181) 0x425498 MOVQ	%XMM3,%RDI

(181) 0x42549d MOVHPD	(%RDX),%XMM1

(181) 0x4254a1 MOVSD	(%RAX),%XMM3

(181) 0x4254a5 MOVHPD	(%RDI),%XMM3

(181) 0x4254a9 ADDPD	%XMM0,%XMM3

(181) 0x4254ad MOVSD	(%RSI),%XMM0

(181) 0x4254b1 MOVHPD	(%R8),%XMM0

(181) 0x4254b6 ADDPD	%XMM1,%XMM0

(181) 0x4254ba ADDPD	%XMM0,%XMM3

(181) 0x4254be MOVDQA	%XMM5,%XMM0

(181) 0x4254c2 PMULUDQ	%XMM15,%XMM0

(181) 0x4254c7 PMULUDQ	%XMM13,%XMM15

(181) 0x4254cc PMULUDQ	%XMM5,%XMM14

(181) 0x4254d1 PADDQ	%XMM15,%XMM14

(181) 0x4254d6 PADDQ	%XMM12,%XMM0

(181) 0x4254db PSLLQ	$0x20,%XMM14

(181) 0x4254e1 PADDQ	%XMM14,%XMM0

(181) 0x4254e6 PSLLQ	$0x3,%XMM0

(181) 0x4254eb PADDQ	0x50(%RSP),%XMM0

(181) 0x4254f1 MOVQ	%XMM0,%RAX

(181) 0x4254f6 PSHUFD	$-0x12,%XMM0,%XMM0

(181) 0x4254fb MOVQ	%XMM0,%RDX

(181) 0x425500 MULPD	0x45f18(%RIP),%XMM3

(181) 0x425508 MOVLPD	%XMM3,(%RAX)

(181) 0x42550c MOVHPD	%XMM3,(%RDX)

(181) 0x425510 PADDQ	0x45f18(%RIP),%XMM7

(181) 0x425518 ADD	$0x2,%R14

(181) 0x42551c CMP	%RBP,%R14

(181) 0x42551f JB	4252f0

0x425525 CMP	%RBP,0x20(%RSP)

0x42552a MOV	0x30(%RSP),%R14

0x42552f MOV	0x28(%RSP),%R12

0x425534 JNE	425566

0x425536 MOV	$0x47c9f0,%EDI

0x42553b MOV	(%RSP),%ESI

0x42553e ADD	$0x88,%RSP

0x425545 POP	%RBX

0x425546 POP	%R12

0x425548 POP	%R13

0x42554a POP	%R14

0x42554c POP	%R15

0x42554e POP	%RBP

0x42554f JMP	403050

0x425554 ADD	$0x88,%RSP

0x42555b POP	%RBX

0x42555c POP	%R12

0x42555e POP	%R13

0x425560 POP	%R14

0x425562 POP	%R15

0x425564 POP	%RBP

0x425565 RET

0x425566 ADD	%RBP,%RCX

0x425569 JMP	4255e4

0x42556b NOPL	(%RAX,%RAX,1)

(180) 0x425570 MOV	%RCX,%RAX

(180) 0x425573 CQTO

(180) 0x425575 IDIV	%R13

(180) 0x425578 ADD	0x8(%RSP),%ESI

(180) 0x42557c ADD	%R14D,%EDX

(180) 0x42557f MOVSXD	%EDX,%RAX

(180) 0x425582 LEA	-0x1(%RSI),%EDX

(180) 0x425585 MOVSXD	%EDX,%RDX

(180) 0x425588 IMUL	%R10,%RDX

(180) 0x42558c LEA	(%RDX,%RAX,1),%RDI

(180) 0x425590 MOVSXD	%ESI,%RSI

(180) 0x425593 MOV	%R10,%R8

(180) 0x425596 IMUL	%RSI,%R8

(180) 0x42559a LEA	(%R8,%RAX,1),%RBX

(180) 0x42559e MOVSD	(%R11,%RBX,8),%XMM0

(180) 0x4255a4 ADDSD	(%R11,%RDI,8),%XMM0

(180) 0x4255aa ADD	%RAX,%RDX

(180) 0x4255ad INC	%RDX

(180) 0x4255b0 ADDSD	(%R11,%RDX,8),%XMM0

(180) 0x4255b6 LEA	(%R8,%RAX,1),%RDX

(180) 0x4255ba INC	%RDX

(180) 0x4255bd ADDSD	(%R11,%RDX,8),%XMM0

(180) 0x4255c3 MULSD	0x45e35(%RIP),%XMM0

(180) 0x4255cb IMUL	%R12,%RSI

(180) 0x4255cf ADD	%RAX,%RSI

(180) 0x4255d2 MOVSD	%XMM0,(%R15,%RSI,8)

(180) 0x4255d8 INC	%RCX

(180) 0x4255db CMP	%RCX,%R9

(180) 0x4255de JE	425536

(180) 0x4255e4 MOV	%RCX,%RDI

(180) 0x4255e7 SHR	$0x20,%RDI

(180) 0x4255eb JE	425610

(180) 0x4255ed MOV	%RCX,%RAX

(180) 0x4255f0 XOR	%EDX,%EDX

(180) 0x4255f2 DIV	%R13

(180) 0x4255f5 MOV	%RAX,%RSI

(180) 0x4255f8 TEST	%RDI,%RDI

(180) 0x4255fb JNE	425570

(180) 0x425601 JMP	425622

0x425603 NOPW	%CS:(%RAX,%RAX,1)

(180) 0x425610 MOV	%ECX,%EAX

(180) 0x425612 XOR	%EDX,%EDX

(180) 0x425614 DIV	%R13D

(180) 0x425617 MOV	%EAX,%ESI

(180) 0x425619 TEST	%RDI,%RDI

(180) 0x42561c JNE	425570

(180) 0x425622 MOV	%ECX,%EAX

(180) 0x425624 XOR	%EDX,%EDX

(180) 0x425626 DIV	%R13D

(180) 0x425629 JMP	425578

0x42562e XCHG	%AX,%AX

Coverage (%)	Name	Module
►48.57+	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_launch_thread	libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]	libiomp5.so
○	start_thread	libc.so.6
○	__GI___clone3	libc.so.6
►40.78+	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_launch_thread	libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]	libiomp5.so
►5.27+	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_launch_thread	libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]	libiomp5.so
○	start_thread	libc.so.6
►2.31+	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_launch_thread	libiomp5.so
►1.56+	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_fork_call	libiomp5.so
○	__kmpc_fork_call	libiomp5.so
○	advec_mom_kernel(int, int, int[...]	exec
○	advec_mom_driver(global_variab[...]	exec
○	advection(global_variables&)	exec
○	hydro(global_variables&, paral[...]	exec
○	main	exec
○	__libc_start_call_main	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	exec
►1.50+	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_fork_call	libiomp5.so
○	__kmpc_fork_call	libiomp5.so
○	advec_mom_kernel(int, int, int[...]	exec
○	advec_mom_driver(global_variab[...]	exec
○	advection(global_variables&)	exec
○	hydro(global_variables&, paral[...]	exec
○	main	exec
○	__libc_start_call_main	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_0

Source file and lines
Module	exec

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 14.00 to 5.63 cycles (2.49x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 15% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 14.00 to 1.41 cycles (9.95x speedup).

Details

38% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

10% of SSE/AVX loads are used in vector version.
30% of SSE/AVX stores are used in vector version.
33% of SSE/AVX addition or subtraction instructions are used in vector version.
53% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__kmpc_for_static_init_8@plt: 1 occurrences►

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

MOVD: 2 occurrences►
MOVQ: 5 occurrences►

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 116 bytes. The binary function is storing 128 bytes.

General properties

nb instructions	107
nb uops	112
loop length	458
used x86 registers	16
used mmx registers	0
used xmm registers	10
used ymm registers	0
used zmm registers	0
nb stack references	16

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	14.00 cycles
front end	14.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	4.83	4.83	4.83	4.83	4.83	4.83	7.25	7.25	7.25	7.25	5.00	5.00	5.00	5.00	2.00	2.00
cycles	4.83	4.83	4.83	4.83	4.83	4.83	7.25	7.25	7.25	7.25	5.00	5.00	5.00	5.00	2.00	2.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	14.00
Dispatch	7.25
Overall L1	14.00

Vectorization ratios

all	38%
load	10%
store	30%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	33%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	53%

Vector efficiency ratios

all	15%
load	11%
store	14%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	14%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 14.00 cycles. At this rate:

3% of peak load performance is reached (8.29 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (9.14 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 14.00 to 7.25 cycles (1.93x speedup).

ASM code

In the binary file, the address of the function is: 425180

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x88,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R8,0x8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0xd0(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xc0(%RSP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOVL $0,0x4(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
TEST %RAX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JS 425554 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.51+0x3d4>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R9,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RCX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
MOVQ $0,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV %RAX,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOVQ $0x1,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x40(%RSP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0xc(%RSP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x20(%RSP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x18(%RSP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x47c9d0,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %ESI,0x8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 4031e0 <__kmpc_for_static_init_8@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x18(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RSP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
CMP %R9,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JA 425536 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.51+0x3b6>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
SUB %R14D,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV (%R12),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%R12),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV (%R15),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%R15),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
INC %R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R9,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RCX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $-0x2,%EBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND %RAX,%RBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 4255e4 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.51+0x464>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RAX,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOVD %R13D,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (6.3%)
PSHUFD $0x44,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVD 0x8(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	scal (6.3%)
PSHUFD $0x50,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVDQA %XMM0,0x70(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
MOV %R14,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOVD %R14D,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (6.3%)
PSHUFD $0x50,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVDQA %XMM0,0x60(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
MOVQ %R10,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVQ %R11,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOV %R12,0x28(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOVQ %R12,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVQ %R15,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVDQA %XMM0,0x50(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
MOVQ %RCX,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
PADDQ 0x4614c(%RIP),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (25.0%)
XOR %R14D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOVDQA %XMM1,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
PSHUFD $-0x12,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVDQA %XMM0,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
MOVDQA %XMM2,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
PSRLQ $0x20,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM5,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
PSRLQ $0x20,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	vect (25.0%)
PCMPEQD %XMM8,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
CMP %RBP,0x20(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOV 0x30(%RSP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x28(%RSP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JNE 425566 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.51+0x3e6>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV $0x47c9f0,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RSP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
ADD $0x88,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
JMP 403050 <__kmpc_for_static_fini@plt>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
ADD $0x88,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD %RBP,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 4255e4 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.51+0x464>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_0

Source file and lines
Module	exec

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 14.00 to 5.63 cycles (2.49x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

38% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

10% of SSE/AVX loads are used in vector version.
30% of SSE/AVX stores are used in vector version.
33% of SSE/AVX addition or subtraction instructions are used in vector version.
53% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

__kmpc_for_static_init_8@plt: 1 occurrences►

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

MOVD: 2 occurrences►
MOVQ: 5 occurrences►

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 116 bytes. The binary function is storing 128 bytes.

General properties

nb instructions	107
nb uops	112
loop length	458
used x86 registers	16
used mmx registers	0
used xmm registers	10
used ymm registers	0
used zmm registers	0
nb stack references	16

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	14.00 cycles
front end	14.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	4.83	4.83	4.83	4.83	4.83	4.83	7.25	7.25	7.25	7.25	5.00	5.00	5.00	5.00	2.00	2.00
cycles	4.83	4.83	4.83	4.83	4.83	4.83	7.25	7.25	7.25	7.25	5.00	5.00	5.00	5.00	2.00	2.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	14.00
Dispatch	7.25
Overall L1	14.00

Vectorization ratios

all	38%
load	10%
store	30%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	33%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	53%

Vector efficiency ratios

all	15%
load	11%
store	14%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	14%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 14.00 cycles. At this rate:

3% of peak load performance is reached (8.29 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (9.14 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 425180

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x88,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R8,0x8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0xd0(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xc0(%RSP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOVL $0,0x4(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
TEST %RAX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JS 425554 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.51+0x3d4>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R9,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RCX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
MOVQ $0,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV %RAX,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOVQ $0x1,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x40(%RSP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0xc(%RSP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x20(%RSP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x18(%RSP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x47c9d0,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %ESI,0x8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 4031e0 <__kmpc_for_static_init_8@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x18(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RSP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
CMP %R9,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JA 425536 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.51+0x3b6>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
SUB %R14D,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV (%R12),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%R12),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV (%R15),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%R15),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
INC %R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R9,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RCX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $-0x2,%EBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND %RAX,%RBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 4255e4 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.51+0x464>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RAX,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOVD %R13D,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (6.3%)
PSHUFD $0x44,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVD 0x8(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	scal (6.3%)
PSHUFD $0x50,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVDQA %XMM0,0x70(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
MOV %R14,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOVD %R14D,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (6.3%)
PSHUFD $0x50,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVDQA %XMM0,0x60(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
MOVQ %R10,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVQ %R11,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOV %R12,0x28(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOVQ %R12,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVQ %R15,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVDQA %XMM0,0x50(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
MOVQ %RCX,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
PADDQ 0x4614c(%RIP),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (25.0%)
XOR %R14D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOVDQA %XMM1,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
PSHUFD $-0x12,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVDQA %XMM0,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
MOVDQA %XMM2,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
PSRLQ $0x20,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM5,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
PSRLQ $0x20,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	vect (25.0%)
PCMPEQD %XMM8,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
CMP %RBP,0x20(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOV 0x30(%RSP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x28(%RSP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JNE 425566 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.51+0x3e6>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV $0x47c9f0,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RSP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
ADD $0x88,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
JMP 403050 <__kmpc_for_static_fini@plt>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
ADD $0x88,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD %RBP,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 4255e4 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.51+0x464>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	1.29	0.53
○Loop 181 - - exec	1.29	0.53
○Loop 180 - - exec	0.00	0.00

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Matching between your function (in the source code) and the binary function

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Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code