OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone .extracted.37]

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: :0-0	Coverage (incl. loops): 5.32% \| (excl. loops): 0.00%

  ***  This Panel is Intentionally Left Blank.  ***

It is due to a lack of debug symbols in the given object
(loop or function).

0x423fb0 PUSH	%RBP

0x423fb1 PUSH	%R15

0x423fb3 PUSH	%R14

0x423fb5 PUSH	%R13

0x423fb7 PUSH	%R12

0x423fb9 PUSH	%RBX

0x423fba SUB	$0x148,%RSP

0x423fc1 MOV	%RCX,%R13

0x423fc4 MOV	%RDX,%R15

0x423fc7 MOV	0x1a8(%RSP),%RAX

0x423fcf MOV	0x198(%RSP),%RBP

0x423fd7 MOV	0x190(%RSP),%RDX

0x423fdf MOV	0x188(%RSP),%RCX

0x423fe7 MOV	%RCX,0x10(%RSP)

0x423fec MOV	0x180(%RSP),%RCX

0x423ff4 MOV	%RCX,0x18(%RSP)

0x423ff9 MOVL	$0,0xc(%RSP)

0x424001 TEST	%RAX,%RAX

0x424004 JS	42469d

0x42400a MOV	%R9,%R14

0x42400d MOV	%R8,%R12

0x424010 MOV	%RDX,(%RSP)

0x424014 MOV	(%RDI),%ESI

0x424016 MOVQ	$0,0x28(%RSP)

0x42401f MOV	%RAX,0x20(%RSP)

0x424024 MOVQ	$0x1,0x58(%RSP)

0x42402d SUB	$0x8,%RSP

0x424031 LEA	0x60(%RSP),%RAX

0x424036 LEA	0x14(%RSP),%RCX

0x42403b LEA	0x30(%RSP),%R8

0x424040 LEA	0x28(%RSP),%R9

0x424045 MOV	$0x47c910,%EDI

0x42404a MOV	%ESI,0x10(%RSP)

0x42404e MOV	$0x22,%EDX

0x424053 PUSH	$0x1

0x424055 PUSH	$0x1

0x424057 PUSH	%RAX

0x424058 CALL	4031e0 <__kmpc_for_static_init_8@plt>

0x42405d ADD	$0x20,%RSP

0x424061 MOV	0x28(%RSP),%RCX

0x424066 MOV	0x20(%RSP),%RAX

0x42406b CMP	%RAX,%RCX

0x42406e JA	4246b6

0x424074 MOV	%RAX,%RDX

0x424077 MOV	(%RSP),%R10

0x42407b SUB	%R10D,%EBP

0x42407e MOV	(%R13),%RAX

0x424082 MOV	0x10(%R13),%R11

0x424086 MOV	(%R12),%R13

0x42408a MOV	0x10(%R12),%R8

0x42408f MOV	(%R15),%RSI

0x424092 MOV	0x10(%R15),%R15

0x424096 MOV	(%R14),%RDI

0x424099 MOV	0x10(%R14),%R9

0x42409d INC	%RDX

0x4240a0 MOV	%RDX,0x50(%RSP)

0x4240a5 SUB	%RCX,%RDX

0x4240a8 MOV	$-0x2,%EBX

0x4240ad AND	%RDX,%RBX

0x4240b0 MOV	%RSI,0x48(%RSP)

0x4240b5 MOV	%RDI,0x40(%RSP)

0x4240ba MOV	%R9,0x38(%RSP)

0x4240bf JE	4246d5

0x4240c5 MOV	%RDX,0x30(%RSP)

0x4240ca MOVD	%EBP,%XMM0

0x4240ce PSHUFD	$0x44,%XMM0,%XMM1

0x4240d3 MOVQ	0x10(%RSP),%XMM0

0x4240d9 PSHUFD	$0x44,%XMM0,%XMM0

0x4240de MOVDQA	%XMM0,0x120(%RSP)

0x4240e7 MOVD	%R10D,%XMM0

0x4240ec PSHUFD	$0x50,%XMM0,%XMM0

0x4240f1 MOVDQA	%XMM0,0x110(%RSP)

0x4240fa MOVQ	%RAX,%XMM0

0x4240ff PSHUFD	$0x44,%XMM0,%XMM2

0x424104 MOVQ	%R11,%XMM0

0x424109 PSHUFD	$0x44,%XMM0,%XMM0

0x42410e MOVDQA	%XMM0,0xf0(%RSP)

0x424117 MOVQ	%R13,%XMM0

0x42411c PSHUFD	$0x44,%XMM0,%XMM0

0x424121 MOVDQA	%XMM0,0xe0(%RSP)

0x42412a MOVQ	%R8,%XMM0

0x42412f PSHUFD	$0x44,%XMM0,%XMM0

0x424134 MOVDQA	%XMM0,0xd0(%RSP)

0x42413d MOVQ	%RSI,%XMM0

0x424142 PSHUFD	$0x44,%XMM0,%XMM0

0x424147 MOVDQA	%XMM0,0xc0(%RSP)

0x424150 MOVQ	%R15,%XMM0

0x424155 PSHUFD	$0x44,%XMM0,%XMM0

0x42415a MOVDQA	%XMM0,0xb0(%RSP)

0x424163 MOVQ	%RDI,%XMM0

0x424168 PSHUFD	$0x44,%XMM0,%XMM0

0x42416d MOVDQA	%XMM0,0xa0(%RSP)

0x424176 MOVQ	%R9,%XMM0

0x42417b PSHUFD	$0x44,%XMM0,%XMM0

0x424180 MOVDQA	%XMM0,0x90(%RSP)

0x424189 MOVQ	%RCX,%XMM0

0x42418e PSHUFD	$0x44,%XMM0,%XMM9

0x424194 PADDQ	0x47273(%RIP),%XMM9

0x42419d XOR	%R10D,%R10D

0x4241a0 MOVDQA	%XMM1,0x130(%RSP)

0x4241a9 PSHUFD	$-0x12,%XMM1,%XMM0

0x4241ae MOVDQA	%XMM0,0x80(%RSP)

0x4241b7 MOVDQA	%XMM2,0x100(%RSP)

0x4241c0 PSRLQ	$0x20,%XMM2

0x4241c5 MOVDQA	%XMM2,0x70(%RSP)

0x4241cb MOV	%RAX,%R14

0x4241ce JMP	4242ba

0x4241d3 NOPW	%CS:(%RAX,%RAX,1)

(177) 0x4241e0 MOVDQA	0x60(%RSP),%XMM9

(177) 0x4241e7 DIVPD	%XMM7,%XMM14

(177) 0x4241ec ADDPD	%XMM8,%XMM14

(177) 0x4241f1 XORPD	%XMM7,%XMM7

(177) 0x4241f5 CMPPD	$0x1,%XMM3,%XMM7

(177) 0x4241fa MULPD	0x4729e(%RIP),%XMM6

(177) 0x424202 MULPD	%XMM14,%XMM6

(177) 0x424207 MINPD	%XMM4,%XMM0

(177) 0x42420b MINPD	%XMM6,%XMM0

(177) 0x42420f MOVAPD	%XMM0,%XMM3

(177) 0x424213 XORPD	0x47295(%RIP),%XMM3

(177) 0x42421b ANDPD	%XMM7,%XMM0

(177) 0x42421f ANDNPD	%XMM3,%XMM7

(177) 0x424223 ORPD	%XMM0,%XMM7

(177) 0x424227 ANDPD	%XMM7,%XMM13

(177) 0x42422c MOVAPD	0x4724c(%RIP),%XMM0

(177) 0x424234 SUBPD	%XMM5,%XMM0

(177) 0x424238 MULPD	%XMM13,%XMM0

(177) 0x42423d ADDPD	%XMM12,%XMM0

(177) 0x424242 MULPD	%XMM10,%XMM0

(177) 0x424247 MOVDQA	0xa0(%RSP),%XMM5

(177) 0x424250 MOVDQA	%XMM5,%XMM3

(177) 0x424254 PSRLQ	$0x20,%XMM3

(177) 0x424259 PMULUDQ	%XMM2,%XMM3

(177) 0x42425d MOVDQA	%XMM5,%XMM4

(177) 0x424261 PMULUDQ	%XMM2,%XMM4

(177) 0x424265 PSRLQ	$0x20,%XMM2

(177) 0x42426a PMULUDQ	%XMM5,%XMM2

(177) 0x42426e PADDQ	%XMM3,%XMM2

(177) 0x424272 PADDQ	%XMM1,%XMM4

(177) 0x424276 PSLLQ	$0x20,%XMM2

(177) 0x42427b PADDQ	%XMM2,%XMM4

(177) 0x42427f PSLLQ	$0x3,%XMM4

(177) 0x424284 PADDQ	0x90(%RSP),%XMM4

(177) 0x42428d MOVQ	%XMM4,%RAX

(177) 0x424292 PSHUFD	$-0x12,%XMM4,%XMM1

(177) 0x424297 MOVQ	%XMM1,%RDX

(177) 0x42429c MOVLPD	%XMM0,(%RAX)

(177) 0x4242a0 MOVHPD	%XMM0,(%RDX)

(177) 0x4242a4 PADDQ	0x47183(%RIP),%XMM9

(177) 0x4242ad ADD	$0x2,%R10

(177) 0x4242b1 CMP	%RBX,%R10

(177) 0x4242b4 JAE	4246af

(177) 0x4242ba MOV	%R8,%R12

(177) 0x4242bd MOV	%R13,%R8

(177) 0x4242c0 MOV	%R11,%R13

(177) 0x4242c3 MOV	%R14,%R11

(177) 0x4242c6 MOVQ	%XMM9,%RSI

(177) 0x4242cb MOVDQA	0x130(%RSP),%XMM0

(177) 0x4242d4 MOVQ	%XMM0,%R9

(177) 0x4242d9 MOV	%RSI,%RAX

(177) 0x4242dc XOR	%EDX,%EDX

(177) 0x4242de DIV	%R9

(177) 0x4242e1 MOVQ	%RAX,%XMM6

(177) 0x4242e6 MOVDQA	%XMM9,0x60(%RSP)

(177) 0x4242ed PSHUFD	$-0x12,%XMM9,%XMM0

(177) 0x4242f3 MOVQ	%XMM0,%RDI

(177) 0x4242f8 MOVDQA	0x80(%RSP),%XMM0

(177) 0x424301 MOVQ	%XMM0,%R14

(177) 0x424306 MOV	%RDI,%RAX

(177) 0x424309 XOR	%EDX,%EDX

(177) 0x42430b DIV	%R14

(177) 0x42430e MOVQ	%RAX,%XMM0

(177) 0x424313 PUNPCKLQDQ	%XMM0,%XMM6

(177) 0x424317 PADDQ	0x120(%RSP),%XMM6

(177) 0x424320 MOV	%RSI,%RAX

(177) 0x424323 CQTO

(177) 0x424325 IDIV	%R9

(177) 0x424328 MOVQ	%RDX,%XMM0

(177) 0x42432d MOV	%RDI,%RAX

(177) 0x424330 CQTO

(177) 0x424332 IDIV	%R14

(177) 0x424335 MOVQ	%RDX,%XMM1

(177) 0x42433a PUNPCKLQDQ	%XMM1,%XMM0

(177) 0x42433e PSHUFD	$-0x18,%XMM0,%XMM0

(177) 0x424343 PADDD	0x110(%RSP),%XMM0

(177) 0x42434c PXOR	%XMM2,%XMM2

(177) 0x424350 PCMPGTD	%XMM0,%XMM2

(177) 0x424354 MOVDQA	%XMM0,%XMM1

(177) 0x424358 PUNPCKLDQ	%XMM2,%XMM1

(177) 0x42435c PSHUFD	$-0x18,%XMM6,%XMM2

(177) 0x424361 PSLLQ	$0x20,%XMM6

(177) 0x424366 PSRAD	$0x1f,%XMM6

(177) 0x42436b PSHUFD	$-0x13,%XMM6,%XMM3

(177) 0x424370 PUNPCKLDQ	%XMM3,%XMM2

(177) 0x424374 MOVDQA	0x100(%RSP),%XMM5

(177) 0x42437d MOVDQA	%XMM5,%XMM3

(177) 0x424381 PMULUDQ	%XMM2,%XMM3

(177) 0x424385 MOVDQA	0x70(%RSP),%XMM4

(177) 0x42438b PMULUDQ	%XMM2,%XMM4

(177) 0x42438f PSRLQ	$0x20,%XMM6

(177) 0x424394 PMULUDQ	%XMM6,%XMM5

(177) 0x424398 PADDQ	%XMM4,%XMM5

(177) 0x42439c PSLLQ	$0x20,%XMM5

(177) 0x4243a1 PADDQ	%XMM1,%XMM3

(177) 0x4243a5 PADDQ	%XMM5,%XMM3

(177) 0x4243a9 PSLLQ	$0x3,%XMM3

(177) 0x4243ae PADDQ	0xf0(%RSP),%XMM3

(177) 0x4243b7 MOVQ	%XMM3,%RAX

(177) 0x4243bc PSHUFD	$-0x12,%XMM3,%XMM3

(177) 0x4243c1 MOVQ	%XMM3,%RDX

(177) 0x4243c6 MOVSD	(%RAX),%XMM10

(177) 0x4243cb MOVHPD	(%RDX),%XMM10

(177) 0x4243d0 MOVAPD	%XMM10,%XMM4

(177) 0x4243d5 CMPPD	$0x1,0x463c2(%RIP),%XMM4

(177) 0x4243de MOVDQA	%XMM0,%XMM5

(177) 0x4243e2 PCMPEQD	%XMM3,%XMM3

(177) 0x4243e6 PSUBD	%XMM3,%XMM5

(177) 0x4243ea MOVDQA	%XMM0,%XMM14

(177) 0x4243ef PADDD	%XMM3,%XMM14

(177) 0x4243f4 PXOR	%XMM3,%XMM3

(177) 0x4243f8 PCMPGTD	%XMM5,%XMM3

(177) 0x4243fc MOVDQA	%XMM5,%XMM15

(177) 0x424401 PUNPCKLDQ	%XMM3,%XMM15

(177) 0x424406 PADDD	0x47132(%RIP),%XMM0

(177) 0x42440e MOVAPD	%XMM4,%XMM7

(177) 0x424412 ANDNPD	%XMM15,%XMM7

(177) 0x424417 MOVDQA	%XMM1,%XMM3

(177) 0x42441b PAND	%XMM4,%XMM3

(177) 0x42441f POR	%XMM7,%XMM3

(177) 0x424423 MOVDQA	%XMM4,%XMM7

(177) 0x424427 PANDN	%XMM1,%XMM7

(177) 0x42442b PAND	%XMM4,%XMM15

(177) 0x424430 POR	%XMM7,%XMM15

(177) 0x424435 MOVDQA	0xc0(%RSP),%XMM13

(177) 0x42443f MOVDQA	%XMM13,%XMM7

(177) 0x424444 PMULUDQ	%XMM2,%XMM7

(177) 0x424448 MOVDQA	%XMM13,%XMM8

(177) 0x42444d PSRLQ	$0x20,%XMM8

(177) 0x424453 PMULUDQ	%XMM2,%XMM8

(177) 0x424458 PMULUDQ	%XMM6,%XMM13

(177) 0x42445d PADDQ	%XMM8,%XMM13

(177) 0x424462 PSLLQ	$0x20,%XMM13

(177) 0x424468 PADDQ	%XMM7,%XMM13

(177) 0x42446d MOVDQA	%XMM13,%XMM7

(177) 0x424472 PADDQ	%XMM15,%XMM7

(177) 0x424477 PSLLQ	$0x3,%XMM7

(177) 0x42447c MOVDQA	0xb0(%RSP),%XMM9

(177) 0x424486 PADDQ	%XMM9,%XMM7

(177) 0x42448b MOVQ	%XMM7,%RAX

(177) 0x424490 PSHUFD	$-0x12,%XMM7,%XMM7

(177) 0x424495 MOVQ	%XMM7,%RDX

(177) 0x42449a PXOR	%XMM7,%XMM7

(177) 0x42449e PCMPGTD	%XMM14,%XMM7

(177) 0x4244a3 MOVDQA	%XMM14,%XMM8

(177) 0x4244a8 PUNPCKLDQ	%XMM7,%XMM8

(177) 0x4244ad MOVDQA	%XMM4,%XMM7

(177) 0x4244b1 PANDN	%XMM8,%XMM7

(177) 0x4244b6 PXOR	%XMM8,%XMM8

(177) 0x4244bb PCMPGTD	%XMM0,%XMM8

(177) 0x4244c0 PUNPCKLDQ	%XMM8,%XMM0

(177) 0x4244c5 MOVSD	(%RAX),%XMM12

(177) 0x4244ca MOVHPD	(%RDX),%XMM12

(177) 0x4244cf PAND	%XMM4,%XMM0

(177) 0x4244d3 POR	%XMM7,%XMM0

(177) 0x4244d7 PADDQ	%XMM13,%XMM0

(177) 0x4244dc PSLLQ	$0x3,%XMM0

(177) 0x4244e1 PADDQ	%XMM9,%XMM0

(177) 0x4244e6 MOVQ	%XMM0,%RAX

(177) 0x4244eb PSHUFD	$-0x12,%XMM0,%XMM0

(177) 0x4244f0 MOVQ	%XMM0,%RDX

(177) 0x4244f5 MOVSD	(%RAX),%XMM7

(177) 0x4244f9 MOVHPD	(%RDX),%XMM7

(177) 0x4244fd MOVAPD	%XMM12,%XMM0

(177) 0x424502 PADDQ	%XMM3,%XMM13

(177) 0x424507 PSLLQ	$0x3,%XMM13

(177) 0x42450d PADDQ	%XMM9,%XMM13

(177) 0x424512 MOVQ	%XMM13,%RAX

(177) 0x424517 PSHUFD	$-0x12,%XMM13,%XMM3

(177) 0x42451d MOVQ	%XMM3,%RDX

(177) 0x424522 MOVSD	(%RAX),%XMM3

(177) 0x424526 MOVHPD	(%RDX),%XMM3

(177) 0x42452a SUBPD	%XMM7,%XMM0

(177) 0x42452e SUBPD	%XMM12,%XMM3

(177) 0x424533 MOVAPD	%XMM3,%XMM7

(177) 0x424537 MULPD	%XMM0,%XMM7

(177) 0x42453b PXOR	%XMM13,%XMM13

(177) 0x424540 CMPPD	$0x1,%XMM7,%XMM13

(177) 0x424546 MOVMSKPD	%XMM13,%EAX

(177) 0x42454b TEST	%EAX,%EAX

(177) 0x42454d JE	424559

(177) 0x42454f MOV	0x18(%RSP),%RDX

(177) 0x424554 MOVQ	0x8(%RDX),%XMM7

(177) 0x424559 MOVDQA	0xe0(%RSP),%XMM8

(177) 0x424563 MOVDQA	%XMM8,%XMM11

(177) 0x424568 PMULUDQ	%XMM2,%XMM11

(177) 0x42456d MOVDQA	%XMM8,%XMM9

(177) 0x424572 PSRLQ	$0x20,%XMM9

(177) 0x424578 PMULUDQ	%XMM2,%XMM9

(177) 0x42457d PMULUDQ	%XMM8,%XMM6

(177) 0x424582 PADDQ	%XMM9,%XMM6

(177) 0x424587 PSLLQ	$0x20,%XMM6

(177) 0x42458c PADDQ	%XMM11,%XMM6

(177) 0x424591 PADDQ	%XMM15,%XMM6

(177) 0x424596 PSLLQ	$0x3,%XMM6

(177) 0x42459b PADDQ	0xd0(%RSP),%XMM6

(177) 0x4245a4 MOVQ	%XMM6,%RDX

(177) 0x4245a9 PSHUFD	$-0x12,%XMM6,%XMM6

(177) 0x4245ae MOVQ	%XMM6,%RSI

(177) 0x4245b3 MOVSD	(%RDX),%XMM8

(177) 0x4245b8 MOVHPD	(%RSI),%XMM8

(177) 0x4245bd PSHUFD	$0x44,%XMM7,%XMM15

(177) 0x4245c3 MOVDQA	%XMM1,%XMM7

(177) 0x4245c7 PSLLQ	$0x3,%XMM7

(177) 0x4245cc PADDQ	%XMM15,%XMM7

(177) 0x4245d1 TEST	$0x1,%AL

(177) 0x4245d3 JE	4245de

(177) 0x4245d5 MOVQ	%XMM7,%RDX

(177) 0x4245da MOVSD	(%RDX),%XMM6

(177) 0x4245de TEST	$0x2,%AL

(177) 0x4245e0 MOV	%R11,%R14

(177) 0x4245e3 MOVAPD	0x464e4(%RIP),%XMM9

(177) 0x4245ec JE	4245fc

(177) 0x4245ee PSHUFD	$-0x12,%XMM7,%XMM7

(177) 0x4245f3 MOVQ	%XMM7,%RDX

(177) 0x4245f8 MOVHPD	(%RDX),%XMM6

(177) 0x4245fc MOV	%R13,%R11

(177) 0x4245ff MOV	%R8,%R13

(177) 0x424602 MOV	%R12,%R8

(177) 0x424605 SHUFPS	$-0x18,%XMM4,%XMM4

(177) 0x424609 PAND	%XMM4,%XMM5

(177) 0x42460d PANDN	%XMM14,%XMM4

(177) 0x424612 POR	%XMM5,%XMM4

(177) 0x424616 MOVAPD	%XMM10,%XMM5

(177) 0x42461b ANDPD	%XMM9,%XMM5

(177) 0x424620 DIVPD	%XMM8,%XMM5

(177) 0x424625 MOVAPD	%XMM5,%XMM14

(177) 0x42462a ADDPD	0x46e4d(%RIP),%XMM14

(177) 0x424633 PXOR	%XMM7,%XMM7

(177) 0x424637 PCMPGTD	%XMM4,%XMM7

(177) 0x42463b PUNPCKLDQ	%XMM7,%XMM4

(177) 0x42463f PSLLQ	$0x3,%XMM4

(177) 0x424644 PADDQ	%XMM4,%XMM15

(177) 0x424649 TEST	$0x1,%AL

(177) 0x42464b JE	424656

(177) 0x42464d MOVQ	%XMM15,%RDX

(177) 0x424652 MOVSD	(%RDX),%XMM7

(177) 0x424656 ANDPD	%XMM9,%XMM0

(177) 0x42465b MOVAPD	%XMM3,%XMM4

(177) 0x42465f ANDPD	%XMM9,%XMM4

(177) 0x424664 MOVAPD	0x46e23(%RIP),%XMM8

(177) 0x42466d SUBPD	%XMM5,%XMM8

(177) 0x424672 MULPD	%XMM4,%XMM8

(177) 0x424677 DIVPD	%XMM6,%XMM8

(177) 0x42467c MULPD	%XMM0,%XMM14

(177) 0x424681 TEST	$0x2,%AL

(177) 0x424683 JE	4241e0

(177) 0x424689 PSHUFD	$-0x12,%XMM15,%XMM9

(177) 0x42468f MOVQ	%XMM9,%RAX

(177) 0x424694 MOVHPD	(%RAX),%XMM7

(177) 0x424698 JMP	4241e0

0x42469d ADD	$0x148,%RSP

0x4246a4 POP	%RBX

0x4246a5 POP	%R12

0x4246a7 POP	%R13

0x4246a9 POP	%R14

0x4246ab POP	%R15

0x4246ad POP	%RBP

0x4246ae RET

0x4246af CMP	%RBX,0x30(%RSP)

0x4246b4 JNE	4246da

0x4246b6 MOV	$0x47c930,%EDI

0x4246bb MOV	0x8(%RSP),%ESI

0x4246bf ADD	$0x148,%RSP

0x4246c6 POP	%RBX

0x4246c7 POP	%R12

0x4246c9 POP	%R13

0x4246cb POP	%R14

0x4246cd POP	%R15

0x4246cf POP	%RBP

0x4246d0 JMP	403050

0x4246d5 MOV	%RAX,%R14

0x4246d8 JMP	4246dd

0x4246da ADD	%RBX,%RCX

0x4246dd PXOR	%XMM0,%XMM0

0x4246e1 MOVAPD	0x463e7(%RIP),%XMM1

0x4246e9 MOVSD	0x46dcf(%RIP),%XMM2

0x4246f1 MOVSD	0x4637f(%RIP),%XMM3

0x4246f9 MOVSD	0x46dc7(%RIP),%XMM4

0x424701 MOVAPD	0x46da7(%RIP),%XMM5

0x424709 JMP	42474b

0x42470b NOPL	(%RAX,%RAX,1)

(176) 0x424710 MOVAPD	%XMM3,%XMM9

(176) 0x424715 SUBSD	%XMM7,%XMM9

(176) 0x42471a MULSD	%XMM11,%XMM9

(176) 0x42471f ADDSD	%XMM8,%XMM9

(176) 0x424724 MULSD	%XMM6,%XMM9

(176) 0x424729 IMUL	0x40(%RSP),%RSI

(176) 0x42472f ADD	%RAX,%RSI

(176) 0x424732 MOV	0x38(%RSP),%RAX

(176) 0x424737 MOVSD	%XMM9,(%RAX,%RSI,8)

(176) 0x42473d INC	%RCX

(176) 0x424740 CMP	%RCX,0x50(%RSP)

(176) 0x424745 JE	4246b6

(176) 0x42474b MOV	%RCX,%RDI

(176) 0x42474e SHR	$0x20,%RDI

(176) 0x424752 JE	424780

(176) 0x424754 MOV	%RCX,%RAX

(176) 0x424757 XOR	%EDX,%EDX

(176) 0x424759 DIV	%RBP

(176) 0x42475c MOV	%RAX,%RSI

(176) 0x42475f MOV	(%RSP),%R10

(176) 0x424763 TEST	%RDI,%RDI

(176) 0x424766 JE	424791

(176) 0x424768 MOV	%RCX,%RAX

(176) 0x42476b CQTO

(176) 0x42476d IDIV	%RBP

(176) 0x424770 JMP	424797

0x424772 NOPW	%CS:(%RAX,%RAX,1)

(176) 0x424780 MOV	%ECX,%EAX

(176) 0x424782 XOR	%EDX,%EDX

(176) 0x424784 DIV	%EBP

(176) 0x424786 MOV	%EAX,%ESI

(176) 0x424788 MOV	(%RSP),%R10

(176) 0x42478c TEST	%RDI,%RDI

(176) 0x42478f JNE	424768

(176) 0x424791 MOV	%ECX,%EAX

(176) 0x424793 XOR	%EDX,%EDX

(176) 0x424795 DIV	%EBP

(176) 0x424797 ADD	0x10(%RSP),%RSI

(176) 0x42479c LEA	(%RDX,%R10,1),%EDI

(176) 0x4247a0 MOVSXD	%EDI,%RAX

(176) 0x4247a3 MOVSXD	%ESI,%RSI

(176) 0x4247a6 MOV	%R14,%R9

(176) 0x4247a9 IMUL	%RSI,%R9

(176) 0x4247ad ADD	%RAX,%R9

(176) 0x4247b0 MOVSD	(%R11,%R9,8),%XMM6

(176) 0x4247b6 UCOMISD	%XMM6,%XMM0

(176) 0x4247ba LEA	0x1(%RDX,%R10,1),%EDX

(176) 0x4247bf MOVSXD	%EDX,%R10

(176) 0x4247c2 JBE	4247d0

(176) 0x4247c4 ADD	$0x2,%EDI

(176) 0x4247c7 MOV	%RAX,%R12

(176) 0x4247ca JMP	4247da

0x4247cc NOPL	(%RAX)

(176) 0x4247d0 DEC	%EDI

(176) 0x4247d2 MOV	%R10,%R12

(176) 0x4247d5 MOV	%RAX,%R10

(176) 0x4247d8 MOV	%EDI,%EDX

(176) 0x4247da MOVAPD	%XMM6,%XMM7

(176) 0x4247de ANDPD	%XMM1,%XMM7

(176) 0x4247e2 MOV	%R13,%R9

(176) 0x4247e5 IMUL	%RSI,%R9

(176) 0x4247e9 ADD	%R10,%R9

(176) 0x4247ec DIVSD	(%R8,%R9,8),%XMM7

(176) 0x4247f2 MOV	0x48(%RSP),%R9

(176) 0x4247f7 IMUL	%RSI,%R9

(176) 0x4247fb ADD	%R9,%R10

(176) 0x4247fe MOVSXD	%EDI,%RDI

(176) 0x424801 ADD	%R9,%RDI

(176) 0x424804 ADD	%R12,%R9

(176) 0x424807 MOVSD	(%R15,%R10,8),%XMM8

(176) 0x42480d MOVAPD	%XMM8,%XMM9

(176) 0x424812 MOVHPD	(%R15,%R9,8),%XMM9

(176) 0x424818 MOVSD	(%R15,%RDI,8),%XMM10

(176) 0x42481e UNPCKLPD	%XMM8,%XMM10

(176) 0x424823 SUBPD	%XMM10,%XMM9

(176) 0x424828 MOVAPD	%XMM9,%XMM10

(176) 0x42482d UNPCKHPD	%XMM9,%XMM10

(176) 0x424832 MOVAPD	%XMM10,%XMM12

(176) 0x424837 MULSD	%XMM9,%XMM12

(176) 0x42483c PXOR	%XMM11,%XMM11

(176) 0x424841 UCOMISD	%XMM11,%XMM12

(176) 0x424846 JBE	424710

(176) 0x42484c MOV	0x18(%RSP),%RDI

(176) 0x424851 MOV	0x8(%RDI),%RDI

(176) 0x424855 ANDPD	%XMM1,%XMM9

(176) 0x42485a MOVAPD	%XMM2,%XMM11

(176) 0x42485f SUBSD	%XMM7,%XMM11

(176) 0x424864 MOVAPD	%XMM7,%XMM12

(176) 0x424869 ADDSD	%XMM3,%XMM12

(176) 0x42486e UNPCKLPD	%XMM11,%XMM12

(176) 0x424873 MOVSXD	%EDX,%RDX

(176) 0x424876 MOVSD	(%RDI,%RAX,8),%XMM11

(176) 0x42487c MULPD	%XMM9,%XMM12

(176) 0x424881 MOVSD	(%RDI,%RDX,8),%XMM13

(176) 0x424887 UNPCKLPD	%XMM11,%XMM13

(176) 0x42488c DIVPD	%XMM13,%XMM12

(176) 0x424891 MOVAPD	%XMM12,%XMM13

(176) 0x424896 UNPCKHPD	%XMM12,%XMM13

(176) 0x42489b ADDSD	%XMM12,%XMM13

(176) 0x4248a0 MULSD	%XMM4,%XMM11

(176) 0x4248a5 MULSD	%XMM13,%XMM11

(176) 0x4248aa PSHUFD	$-0x12,%XMM9,%XMM12

(176) 0x4248b0 MINSD	%XMM9,%XMM12

(176) 0x4248b5 MINSD	%XMM11,%XMM12

(176) 0x4248ba XORPD	%XMM11,%XMM11

(176) 0x4248bf CMPSD	$0x1,%XMM10,%XMM11

(176) 0x4248c5 MOVAPD	%XMM11,%XMM9

(176) 0x4248ca ANDPD	%XMM12,%XMM9

(176) 0x4248cf XORPD	%XMM5,%XMM12

(176) 0x4248d4 ANDNPD	%XMM12,%XMM11

(176) 0x4248d9 ORPD	%XMM9,%XMM11

(176) 0x4248de JMP	424710

0x4248e3 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Module
►48.18+	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_launch_thread	libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]	libiomp5.so
○	start_thread	libc.so.6
○	__GI___clone3	libc.so.6
►41.05+	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_launch_thread	libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]	libiomp5.so
►5.37+	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_launch_thread	libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]	libiomp5.so
○	start_thread	libc.so.6
►2.31+	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_launch_thread	libiomp5.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_0

Source file and lines
Module	exec

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 18.63 to 8.63 cycles (2.16x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 16% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 18.63 to 2.11 cycles (8.84x speedup).

Details

40% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

17% of SSE/AVX loads are used in vector version.
50% of SSE/AVX stores are used in vector version.
25% of SSE/AVX addition or subtraction instructions are used in vector version.
46% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__kmpc_for_static_init_8@plt: 1 occurrences►

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

MOVD: 2 occurrences►
MOVQ: 9 occurrences►

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 224 bytes. The binary function is storing 304 bytes.

General properties

nb instructions	142
nb uops	149
loop length	706
used x86 registers	16
used mmx registers	0
used xmm registers	7
used ymm registers	0
used zmm registers	0
nb stack references	33

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	18.63 cycles
front end	18.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.17	5.17	5.17	5.17	5.17	5.17	13.25	13.25	13.25	13.25	6.50	6.50	6.50	6.50	6.50	6.50
cycles	5.17	5.17	5.17	5.17	5.17	5.17	13.25	13.25	13.25	13.25	6.50	6.50	6.50	6.50	6.50	6.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	18.63
Dispatch	13.25
Overall L1	18.63

Vectorization ratios

INT

all	40%
load	8%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	46%

all	40%
load	40%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	40%
load	17%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	46%

Vector efficiency ratios

INT

all	16%
load	12%
store	17%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	14%
fma	NA (no fma vectorizable/vectorized instructions)
other	17%

all	17%
load	17%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	16%
load	13%
store	17%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	14%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	17%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 18.63 cycles. At this rate:

4% of peak load performance is reached (12.03 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (16.32 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 18.63 to 13.25 cycles (1.41x speedup).

ASM code

In the binary file, the address of the function is: 423fb0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x148,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x1a8(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x198(%RSP),%RBP	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x190(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x188(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RCX,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x180(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RCX,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOVL $0,0xc(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
TEST %RAX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JS 42469d <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.37+0x6ed>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R9,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R8,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDX,(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
MOVQ $0,0x28(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV %RAX,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOVQ $0x1,0x58(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x60(%RSP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x14(%RSP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x30(%RSP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x28(%RSP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x47c910,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %ESI,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 4031e0 <__kmpc_for_static_init_8@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x28(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x20(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CMP %RAX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JA 4246b6 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.37+0x706>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RAX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV (%RSP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
SUB %R10D,%EBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV (%R13),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%R13),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV (%R12),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%R12),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV (%R15),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%R15),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%R14),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%R14),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
INC %RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RDX,0x50(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
SUB %RCX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV $-0x2,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND %RDX,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSI,0x48(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDI,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R9,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
JE 4246d5 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.37+0x725>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RDX,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOVD %EBP,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (6.3%)
PSHUFD $0x44,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVQ 0x10(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVDQA %XMM0,0x120(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
MOVD %R10D,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (6.3%)
PSHUFD $0x50,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVDQA %XMM0,0x110(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
MOVQ %RAX,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVQ %R11,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVDQA %XMM0,0xf0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
MOVQ %R13,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVDQA %XMM0,0xe0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
MOVQ %R8,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVDQA %XMM0,0xd0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
MOVQ %RSI,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVDQA %XMM0,0xc0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
MOVQ %R15,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVDQA %XMM0,0xb0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
MOVQ %RDI,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVDQA %XMM0,0xa0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
MOVQ %R9,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVDQA %XMM0,0x90(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
MOVQ %RCX,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
PADDQ 0x47273(%RIP),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (25.0%)
XOR %R10D,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOVDQA %XMM1,0x130(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
PSHUFD $-0x12,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVDQA %XMM0,0x80(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
MOVDQA %XMM2,0x100(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
PSRLQ $0x20,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM2,0x70(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
MOV %RAX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 4242ba <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.37+0x30a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0x148,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP %RBX,0x30(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JNE 4246da <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.37+0x72a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV $0x47c930,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x8(%RSP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
ADD $0x148,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
JMP 403050 <__kmpc_for_static_fini@plt>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV %RAX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 4246dd <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.37+0x72d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
ADD %RBX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PXOR %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
MOVAPD 0x463e7(%RIP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MOVSD 0x46dcf(%RIP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVSD 0x4637f(%RIP),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVSD 0x46dc7(%RIP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVAPD 0x46da7(%RIP),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
JMP 42474b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.37+0x79b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_0

Source file and lines
Module	exec

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 18.63 to 8.63 cycles (2.16x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

40% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

17% of SSE/AVX loads are used in vector version.
50% of SSE/AVX stores are used in vector version.
25% of SSE/AVX addition or subtraction instructions are used in vector version.
46% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

__kmpc_for_static_init_8@plt: 1 occurrences►

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

MOVD: 2 occurrences►
MOVQ: 9 occurrences►

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 224 bytes. The binary function is storing 304 bytes.

General properties

nb instructions	142
nb uops	149
loop length	706
used x86 registers	16
used mmx registers	0
used xmm registers	7
used ymm registers	0
used zmm registers	0
nb stack references	33

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	18.63 cycles
front end	18.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.17	5.17	5.17	5.17	5.17	5.17	13.25	13.25	13.25	13.25	6.50	6.50	6.50	6.50	6.50	6.50
cycles	5.17	5.17	5.17	5.17	5.17	5.17	13.25	13.25	13.25	13.25	6.50	6.50	6.50	6.50	6.50	6.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	18.63
Dispatch	13.25
Overall L1	18.63

Vectorization ratios

INT

all	40%
load	8%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	46%

all	40%
load	40%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	40%
load	17%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	46%

Vector efficiency ratios

INT

all	16%
load	12%
store	17%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	14%
fma	NA (no fma vectorizable/vectorized instructions)
other	17%

all	17%
load	17%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	16%
load	13%
store	17%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	14%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	17%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 18.63 cycles. At this rate:

4% of peak load performance is reached (12.03 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (16.32 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 423fb0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x148,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x1a8(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x198(%RSP),%RBP	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x190(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x188(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RCX,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x180(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RCX,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOVL $0,0xc(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
TEST %RAX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JS 42469d <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.37+0x6ed>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R9,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R8,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDX,(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
MOVQ $0,0x28(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV %RAX,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOVQ $0x1,0x58(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x60(%RSP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x14(%RSP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x30(%RSP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x28(%RSP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x47c910,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %ESI,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 4031e0 <__kmpc_for_static_init_8@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x28(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x20(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CMP %RAX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JA 4246b6 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.37+0x706>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RAX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV (%RSP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
SUB %R10D,%EBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV (%R13),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%R13),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV (%R12),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%R12),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV (%R15),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%R15),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%R14),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%R14),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
INC %RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RDX,0x50(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
SUB %RCX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV $-0x2,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND %RDX,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSI,0x48(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDI,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R9,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
JE 4246d5 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.37+0x725>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RDX,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOVD %EBP,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (6.3%)
PSHUFD $0x44,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVQ 0x10(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVDQA %XMM0,0x120(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
MOVD %R10D,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (6.3%)
PSHUFD $0x50,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVDQA %XMM0,0x110(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
MOVQ %RAX,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVQ %R11,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVDQA %XMM0,0xf0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
MOVQ %R13,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVDQA %XMM0,0xe0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
MOVQ %R8,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVDQA %XMM0,0xd0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
MOVQ %RSI,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVDQA %XMM0,0xc0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
MOVQ %R15,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVDQA %XMM0,0xb0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
MOVQ %RDI,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVDQA %XMM0,0xa0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
MOVQ %R9,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVDQA %XMM0,0x90(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
MOVQ %RCX,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
PADDQ 0x47273(%RIP),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (25.0%)
XOR %R10D,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOVDQA %XMM1,0x130(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
PSHUFD $-0x12,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVDQA %XMM0,0x80(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
MOVDQA %XMM2,0x100(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
PSRLQ $0x20,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM2,0x70(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
MOV %RAX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 4242ba <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.37+0x30a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0x148,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP %RBX,0x30(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JNE 4246da <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.37+0x72a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV $0x47c930,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x8(%RSP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
ADD $0x148,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
JMP 403050 <__kmpc_for_static_fini@plt>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV %RAX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 4246dd <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.37+0x72d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
ADD %RBX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PXOR %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
MOVAPD 0x463e7(%RIP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MOVSD 0x46dcf(%RIP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVSD 0x4637f(%RIP),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVSD 0x46dc7(%RIP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOVAPD 0x46da7(%RIP),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
JMP 42474b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.37+0x79b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	5.32	2.18
○Loop 177 - - exec	5.32	2.18
○Loop 176 - - exec	0.00	0.00

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Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code