OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone .extracted.23]

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: :0-0	Coverage (incl. loops): 1.35% \| (excl. loops): 0.00%

  ***  This Panel is Intentionally Left Blank.  ***

It is due to a lack of debug symbols in the given object
(loop or function).

0x423580 PUSH	%RBP

0x423581 PUSH	%R15

0x423583 PUSH	%R14

0x423585 PUSH	%R13

0x423587 PUSH	%R12

0x423589 PUSH	%RBX

0x42358a SUB	$0x88,%RSP

0x423591 MOV	0xd0(%RSP),%RAX

0x423599 MOV	0xc0(%RSP),%R13

0x4235a1 MOVL	$0,0xc(%RSP)

0x4235a9 TEST	%RAX,%RAX

0x4235ac JS	42394f

0x4235b2 MOV	%R9,%RBX

0x4235b5 MOV	%R8,%R14

0x4235b8 MOV	%RCX,%R15

0x4235bb MOV	%RDX,%R12

0x4235be MOV	(%RDI),%EBP

0x4235c0 MOVQ	$0,0x18(%RSP)

0x4235c9 MOV	%RAX,0x10(%RSP)

0x4235ce MOVQ	$0x1,0x38(%RSP)

0x4235d7 SUB	$0x8,%RSP

0x4235db LEA	0x40(%RSP),%RAX

0x4235e0 LEA	0x14(%RSP),%RCX

0x4235e5 LEA	0x20(%RSP),%R8

0x4235ea LEA	0x18(%RSP),%R9

0x4235ef MOV	$0x47c850,%EDI

0x4235f4 MOV	%EBP,%ESI

0x4235f6 MOV	$0x22,%EDX

0x4235fb PUSH	$0x1

0x4235fd PUSH	$0x1

0x4235ff PUSH	%RAX

0x423600 CALL	4031e0 <__kmpc_for_static_init_8@plt>

0x423605 ADD	$0x20,%RSP

0x423609 MOV	0x18(%RSP),%RCX

0x42360e MOV	0x10(%RSP),%R8

0x423613 CMP	%R8,%RCX

0x423616 JA	423932

0x42361c SUB	%EBX,%R13D

0x42361f MOV	(%R12),%R9

0x423623 MOV	0x10(%R12),%R10

0x423628 MOV	(%R15),%R11

0x42362b MOV	0x10(%R15),%R15

0x42362f INC	%R8

0x423632 MOV	%R8,%RAX

0x423635 SUB	%RCX,%RAX

0x423638 MOV	$-0x2,%R12D

0x42363e AND	%RAX,%R12

0x423641 JE	4239e1

0x423647 MOV	%RAX,0x20(%RSP)

0x42364c MOV	%EBP,0x8(%RSP)

0x423650 MOVD	%R13D,%XMM0

0x423655 PSHUFD	$0x44,%XMM0,%XMM1

0x42365a MOV	%R14,0x28(%RSP)

0x42365f MOVD	%R14D,%XMM0

0x423664 PSHUFD	$0x50,%XMM0,%XMM0

0x423669 MOVDQA	%XMM0,0x70(%RSP)

0x42366f MOV	%RBX,0x30(%RSP)

0x423674 MOVD	%EBX,%XMM0

0x423678 PSHUFD	$0x50,%XMM0,%XMM0

0x42367d MOVDQA	%XMM0,0x60(%RSP)

0x423683 MOVQ	%R9,%XMM0

0x423688 PSHUFD	$0x44,%XMM0,%XMM2

0x42368d MOVQ	%R10,%XMM0

0x423692 PSHUFD	$0x44,%XMM0,%XMM4

0x423697 MOVQ	%R11,%XMM0

0x42369c PSHUFD	$0x44,%XMM0,%XMM5

0x4236a1 MOVQ	%R15,%XMM0

0x4236a6 PSHUFD	$0x44,%XMM0,%XMM0

0x4236ab MOVDQA	%XMM0,0x50(%RSP)

0x4236b1 MOVQ	%RCX,%XMM0

0x4236b6 PSHUFD	$0x44,%XMM0,%XMM7

0x4236bb PADDQ	0x47d4d(%RIP),%XMM7

0x4236c3 XOR	%EBP,%EBP

0x4236c5 MOVDQA	%XMM1,%XMM9

0x4236ca PSHUFD	$-0x12,%XMM1,%XMM0

0x4236cf MOVDQA	%XMM0,0x40(%RSP)

0x4236d5 MOVDQA	%XMM2,%XMM0

0x4236d9 PSRLQ	$0x20,%XMM0

0x4236de MOVDQA	%XMM5,%XMM13

0x4236e3 PSRLQ	$0x20,%XMM13

0x4236e9 PCMPEQD	%XMM8,%XMM8

0x4236ee XCHG	%AX,%AX

(173) 0x4236f0 MOVQ	%XMM7,%RSI

(173) 0x4236f5 MOVQ	%XMM9,%R14

(173) 0x4236fa XOR	%EDX,%EDX

(173) 0x4236fc MOV	%RSI,%RAX

(173) 0x4236ff DIV	%R14

(173) 0x423702 PSHUFD	$-0x12,%XMM7,%XMM1

(173) 0x423707 MOVQ	%RAX,%XMM3

(173) 0x42370c MOVQ	%XMM1,%RDI

(173) 0x423711 MOVDQA	0x40(%RSP),%XMM1

(173) 0x423717 MOVQ	%XMM1,%RBX

(173) 0x42371c XOR	%EDX,%EDX

(173) 0x42371e MOV	%RDI,%RAX

(173) 0x423721 DIV	%RBX

(173) 0x423724 MOVQ	%RAX,%XMM1

(173) 0x423729 PUNPCKLQDQ	%XMM1,%XMM3

(173) 0x42372d PSHUFD	$-0x18,%XMM3,%XMM12

(173) 0x423733 MOV	%RSI,%RAX

(173) 0x423736 CQTO

(173) 0x423738 PADDD	0x70(%RSP),%XMM12

(173) 0x42373f IDIV	%R14

(173) 0x423742 MOVQ	%RDX,%XMM1

(173) 0x423747 MOV	%RDI,%RAX

(173) 0x42374a CQTO

(173) 0x42374c IDIV	%RBX

(173) 0x42374f MOVQ	%RDX,%XMM3

(173) 0x423754 PUNPCKLQDQ	%XMM3,%XMM1

(173) 0x423758 PSHUFD	$-0x18,%XMM1,%XMM1

(173) 0x42375d PXOR	%XMM6,%XMM6

(173) 0x423761 PADDD	0x60(%RSP),%XMM1

(173) 0x423767 PXOR	%XMM10,%XMM10

(173) 0x42376c PCMPGTD	%XMM12,%XMM10

(173) 0x423771 MOVDQA	%XMM12,%XMM14

(173) 0x423776 MOVDQA	%XMM1,%XMM15

(173) 0x42377b PUNPCKLDQ	%XMM10,%XMM14

(173) 0x423780 MOVDQA	%XMM0,%XMM11

(173) 0x423785 PMULUDQ	%XMM14,%XMM11

(173) 0x42378a PADDD	%XMM8,%XMM15

(173) 0x42378f PUNPCKLDQ	0x47008(%RIP),%XMM10

(173) 0x423798 MOVDQA	%XMM2,%XMM3

(173) 0x42379c PMULUDQ	%XMM10,%XMM3

(173) 0x4237a1 PCMPGTD	%XMM15,%XMM6

(173) 0x4237a6 PADDQ	%XMM11,%XMM3

(173) 0x4237ab MOVDQA	%XMM2,%XMM11

(173) 0x4237b0 PMULUDQ	%XMM14,%XMM11

(173) 0x4237b5 PUNPCKLDQ	%XMM6,%XMM15

(173) 0x4237ba PXOR	%XMM6,%XMM6

(173) 0x4237be PCMPGTD	%XMM1,%XMM6

(173) 0x4237c2 PUNPCKLDQ	%XMM6,%XMM1

(173) 0x4237c6 PSLLQ	$0x20,%XMM3

(173) 0x4237cb PSUBD	%XMM8,%XMM12

(173) 0x4237d0 PXOR	%XMM6,%XMM6

(173) 0x4237d4 PCMPGTD	%XMM12,%XMM6

(173) 0x4237d9 PADDQ	%XMM11,%XMM3

(173) 0x4237de PUNPCKLDQ	%XMM6,%XMM12

(173) 0x4237e3 MOVDQA	%XMM2,%XMM11

(173) 0x4237e8 PMULUDQ	%XMM12,%XMM11

(173) 0x4237ed PMULUDQ	%XMM0,%XMM12

(173) 0x4237f2 PSHUFD	$-0x2c,%XMM6,%XMM6

(173) 0x4237f7 PMULUDQ	%XMM2,%XMM6

(173) 0x4237fb PADDQ	%XMM12,%XMM6

(173) 0x423800 PSLLQ	$0x20,%XMM6

(173) 0x423805 PADDQ	%XMM11,%XMM6

(173) 0x42380a MOVDQA	%XMM3,%XMM11

(173) 0x42380f PADDQ	%XMM1,%XMM3

(173) 0x423813 PSLLQ	$0x3,%XMM3

(173) 0x423818 PADDQ	%XMM4,%XMM3

(173) 0x42381c MOVQ	%XMM3,%RAX

(173) 0x423821 PSHUFD	$-0x12,%XMM3,%XMM3

(173) 0x423826 MOVQ	%XMM3,%RDX

(173) 0x42382b PADDQ	%XMM15,%XMM11

(173) 0x423830 PSLLQ	$0x3,%XMM11

(173) 0x423836 PADDQ	%XMM4,%XMM11

(173) 0x42383b MOVQ	%XMM11,%RSI

(173) 0x423840 PSHUFD	$-0x12,%XMM11,%XMM3

(173) 0x423846 PADDQ	%XMM6,%XMM15

(173) 0x42384b PSLLQ	$0x3,%XMM15

(173) 0x423851 MOVQ	%XMM3,%RDI

(173) 0x423856 PADDQ	%XMM4,%XMM15

(173) 0x42385b MOVQ	%XMM15,%RBX

(173) 0x423860 PSHUFD	$-0x12,%XMM15,%XMM3

(173) 0x423866 MOVSD	(%RAX),%XMM11

(173) 0x42386b MOVQ	%XMM3,%RAX

(173) 0x423870 PADDQ	%XMM1,%XMM6

(173) 0x423874 PSLLQ	$0x3,%XMM6

(173) 0x423879 MOVSD	(%RSI),%XMM3

(173) 0x42387d PADDQ	%XMM4,%XMM6

(173) 0x423881 MOVQ	%XMM6,%RSI

(173) 0x423886 MOVHPD	(%RDX),%XMM11

(173) 0x42388b PSHUFD	$-0x12,%XMM6,%XMM6

(173) 0x423890 MOVQ	%XMM6,%RDX

(173) 0x423895 MOVHPD	(%RDI),%XMM3

(173) 0x423899 MOVSD	(%RBX),%XMM6

(173) 0x42389d MOVHPD	(%RAX),%XMM6

(173) 0x4238a1 ADDPD	%XMM3,%XMM11

(173) 0x4238a6 MOVSD	(%RSI),%XMM3

(173) 0x4238aa MOVHPD	(%RDX),%XMM3

(173) 0x4238ae ADDPD	%XMM6,%XMM3

(173) 0x4238b2 ADDPD	%XMM11,%XMM3

(173) 0x4238b7 MOVDQA	%XMM5,%XMM6

(173) 0x4238bb PMULUDQ	%XMM14,%XMM6

(173) 0x4238c0 PMULUDQ	%XMM13,%XMM14

(173) 0x4238c5 PMULUDQ	%XMM5,%XMM10

(173) 0x4238ca PADDQ	%XMM14,%XMM10

(173) 0x4238cf PADDQ	%XMM1,%XMM6

(173) 0x4238d3 PSLLQ	$0x20,%XMM10

(173) 0x4238d9 PADDQ	%XMM10,%XMM6

(173) 0x4238de PSLLQ	$0x3,%XMM6

(173) 0x4238e3 PADDQ	0x50(%RSP),%XMM6

(173) 0x4238e9 MOVQ	%XMM6,%RAX

(173) 0x4238ee PSHUFD	$-0x12,%XMM6,%XMM1

(173) 0x4238f3 MOVQ	%XMM1,%RDX

(173) 0x4238f8 MULPD	0x47b20(%RIP),%XMM3

(173) 0x423900 MOVLPD	%XMM3,(%RAX)

(173) 0x423904 MOVHPD	%XMM3,(%RDX)

(173) 0x423908 PADDQ	0x47b20(%RIP),%XMM7

(173) 0x423910 ADD	$0x2,%RBP

(173) 0x423914 CMP	%R12,%RBP

(173) 0x423917 JB	4236f0

0x42391d CMP	%R12,0x20(%RSP)

0x423922 MOV	0x30(%RSP),%RBX

0x423927 MOV	0x28(%RSP),%R14

0x42392c MOV	0x8(%RSP),%EBP

0x423930 JNE	423961

0x423932 MOV	$0x47c870,%EDI

0x423937 MOV	%EBP,%ESI

0x423939 ADD	$0x88,%RSP

0x423940 POP	%RBX

0x423941 POP	%R12

0x423943 POP	%R13

0x423945 POP	%R14

0x423947 POP	%R15

0x423949 POP	%RBP

0x42394a JMP	403050

0x42394f ADD	$0x88,%RSP

0x423956 POP	%RBX

0x423957 POP	%R12

0x423959 POP	%R13

0x42395b POP	%R14

0x42395d POP	%R15

0x42395f POP	%RBP

0x423960 RET

0x423961 ADD	%R12,%RCX

0x423964 JMP	4239e1

0x423966 NOPW	%CS:(%RAX,%RAX,1)

(172) 0x423970 MOV	%RCX,%RAX

(172) 0x423973 CQTO

(172) 0x423975 IDIV	%R13

(172) 0x423978 ADD	%R14D,%ESI

(172) 0x42397b ADD	%EBX,%EDX

(172) 0x42397d MOVSXD	%ESI,%RAX

(172) 0x423980 MOV	%R9,%RSI

(172) 0x423983 IMUL	%RAX,%RSI

(172) 0x423987 MOVSXD	%EDX,%RDX

(172) 0x42398a LEA	(%RSI,%RDX,1),%RDI

(172) 0x42398e DEC	%RDI

(172) 0x423991 ADD	%RDX,%RSI

(172) 0x423994 MOVSD	(%R10,%RSI,8),%XMM0

(172) 0x42399a ADDSD	(%R10,%RDI,8),%XMM0

(172) 0x4239a0 LEA	0x1(%RAX),%ESI

(172) 0x4239a3 MOVSXD	%ESI,%RSI

(172) 0x4239a6 IMUL	%R9,%RSI

(172) 0x4239aa LEA	(%RSI,%RDX,1),%RDI

(172) 0x4239ae DEC	%RDI

(172) 0x4239b1 ADDSD	(%R10,%RDI,8),%XMM0

(172) 0x4239b7 ADD	%RDX,%RSI

(172) 0x4239ba ADDSD	(%R10,%RSI,8),%XMM0

(172) 0x4239c0 MULSD	0x47a38(%RIP),%XMM0

(172) 0x4239c8 IMUL	%R11,%RAX

(172) 0x4239cc ADD	%RDX,%RAX

(172) 0x4239cf MOVSD	%XMM0,(%R15,%RAX,8)

(172) 0x4239d5 INC	%RCX

(172) 0x4239d8 CMP	%RCX,%R8

(172) 0x4239db JE	423932

(172) 0x4239e1 MOV	%RCX,%RDI

(172) 0x4239e4 SHR	$0x20,%RDI

(172) 0x4239e8 JE	423a00

(172) 0x4239ea MOV	%RCX,%RAX

(172) 0x4239ed XOR	%EDX,%EDX

(172) 0x4239ef DIV	%R13

(172) 0x4239f2 MOV	%RAX,%RSI

(172) 0x4239f5 TEST	%RDI,%RDI

(172) 0x4239f8 JNE	423970

(172) 0x4239fe JMP	423a12

(172) 0x423a00 MOV	%ECX,%EAX

(172) 0x423a02 XOR	%EDX,%EDX

(172) 0x423a04 DIV	%R13D

(172) 0x423a07 MOV	%EAX,%ESI

(172) 0x423a09 TEST	%RDI,%RDI

(172) 0x423a0c JNE	423970

(172) 0x423a12 MOV	%ECX,%EAX

(172) 0x423a14 XOR	%EDX,%EDX

(172) 0x423a16 DIV	%R13D

(172) 0x423a19 JMP	423978

0x423a1e XCHG	%AX,%AX

Coverage (%)	Name	Module
►48.06+	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_launch_thread	libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]	libiomp5.so
○	start_thread	libc.so.6
○	__GI___clone3	libc.so.6
►41.13+	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_launch_thread	libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]	libiomp5.so
►5.27+	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_launch_thread	libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]	libiomp5.so
○	start_thread	libc.so.6
►2.38+	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_launch_thread	libiomp5.so
►1.50+	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_fork_call	libiomp5.so
○	__kmpc_fork_call	libiomp5.so
○	advec_mom_kernel(int, int, int[...]	exec
○	advec_mom_driver(global_variab[...]	exec
○	advection(global_variables&)	exec
○	hydro(global_variables&, paral[...]	exec
○	main	exec
○	__libc_start_call_main	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	exec
►1.46+	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_fork_call	libiomp5.so
○	__kmpc_fork_call	libiomp5.so
○	advec_mom_kernel(int, int, int[...]	exec
○	advec_mom_driver(global_variab[...]	exec
○	advection(global_variables&)	exec
○	hydro(global_variables&, paral[...]	exec
○	main	exec
○	__libc_start_call_main	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_0

Source file and lines
Module	exec

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 14.38 to 5.88 cycles (2.45x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 15% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 14.38 to 1.44 cycles (9.97x speedup).

Details

35% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

9% of SSE/AVX loads are used in vector version.
33% of SSE/AVX stores are used in vector version.
33% of SSE/AVX addition or subtraction instructions are used in vector version.
46% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__kmpc_for_static_init_8@plt: 1 occurrences►

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

MOVD: 3 occurrences►
MOVQ: 5 occurrences►

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 112 bytes. The binary function is storing 120 bytes.

General properties

nb instructions	109
nb uops	115
loop length	453
used x86 registers	16
used mmx registers	0
used xmm registers	9
used ymm registers	0
used zmm registers	0
nb stack references	15

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	14.38 cycles
front end	14.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	4.83	4.83	4.83	4.83	4.83	4.83	6.75	6.75	6.75	6.75	5.25	5.25	5.25	5.25	2.00	2.00
cycles	4.83	4.83	4.83	4.83	4.83	4.83	6.75	6.75	6.75	6.75	5.25	5.25	5.25	5.25	2.00	2.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	14.38
Dispatch	6.75
Overall L1	14.38

Vectorization ratios

all	35%
load	9%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	33%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	46%

Vector efficiency ratios

all	15%
load	12%
store	14%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	14%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 14.38 cycles. At this rate:

3% of peak load performance is reached (7.79 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (8.35 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 14.38 to 6.75 cycles (2.13x speedup).

ASM code

In the binary file, the address of the function is: 423580

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x88,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0xd0(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xc0(%RSP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOVL $0,0xc(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
TEST %RAX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JS 42394f <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.23+0x3cf>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R9,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %R8,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RCX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%RDI),%EBP	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
MOVQ $0,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV %RAX,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOVQ $0x1,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x40(%RSP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x14(%RSP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x20(%RSP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x18(%RSP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x47c850,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EBP,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 4031e0 <__kmpc_for_static_init_8@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x18(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RSP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
CMP %R8,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JA 423932 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.23+0x3b2>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
SUB %EBX,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV (%R12),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%R12),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV (%R15),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%R15),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
INC %R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RCX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $-0x2,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND %RAX,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 4239e1 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.23+0x461>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RAX,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %EBP,0x8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOVD %R13D,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (6.3%)
PSHUFD $0x44,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOV %R14,0x28(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOVD %R14D,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (6.3%)
PSHUFD $0x50,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVDQA %XMM0,0x70(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
MOV %RBX,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOVD %EBX,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (6.3%)
PSHUFD $0x50,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVDQA %XMM0,0x60(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
MOVQ %R9,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVQ %R10,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVQ %R11,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVQ %R15,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVDQA %XMM0,0x50(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
MOVQ %RCX,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
PADDQ 0x47d4d(%RIP),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (25.0%)
XOR %EBP,%EBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOVDQA %XMM1,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
PSHUFD $-0x12,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVDQA %XMM0,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
MOVDQA %XMM2,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
PSRLQ $0x20,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM5,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
PSRLQ $0x20,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	vect (25.0%)
PCMPEQD %XMM8,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
CMP %R12,0x20(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOV 0x30(%RSP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x28(%RSP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x8(%RSP),%EBP	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
JNE 423961 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.23+0x3e1>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV $0x47c870,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EBP,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
ADD $0x88,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
JMP 403050 <__kmpc_for_static_fini@plt>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
ADD $0x88,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD %R12,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 4239e1 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.23+0x461>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_0

Source file and lines
Module	exec

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 14.38 to 5.88 cycles (2.45x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

35% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

9% of SSE/AVX loads are used in vector version.
33% of SSE/AVX stores are used in vector version.
33% of SSE/AVX addition or subtraction instructions are used in vector version.
46% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

__kmpc_for_static_init_8@plt: 1 occurrences►

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

MOVD: 3 occurrences►
MOVQ: 5 occurrences►

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 112 bytes. The binary function is storing 120 bytes.

General properties

nb instructions	109
nb uops	115
loop length	453
used x86 registers	16
used mmx registers	0
used xmm registers	9
used ymm registers	0
used zmm registers	0
nb stack references	15

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	14.38 cycles
front end	14.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	4.83	4.83	4.83	4.83	4.83	4.83	6.75	6.75	6.75	6.75	5.25	5.25	5.25	5.25	2.00	2.00
cycles	4.83	4.83	4.83	4.83	4.83	4.83	6.75	6.75	6.75	6.75	5.25	5.25	5.25	5.25	2.00	2.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	14.38
Dispatch	6.75
Overall L1	14.38

Vectorization ratios

all	35%
load	9%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	33%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	46%

Vector efficiency ratios

all	15%
load	12%
store	14%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	14%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 14.38 cycles. At this rate:

3% of peak load performance is reached (7.79 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (8.35 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 423580

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x88,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0xd0(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xc0(%RSP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOVL $0,0xc(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
TEST %RAX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JS 42394f <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.23+0x3cf>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R9,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %R8,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RCX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%RDI),%EBP	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
MOVQ $0,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV %RAX,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOVQ $0x1,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x40(%RSP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x14(%RSP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x20(%RSP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x18(%RSP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x47c850,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EBP,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 4031e0 <__kmpc_for_static_init_8@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x18(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RSP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
CMP %R8,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JA 423932 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.23+0x3b2>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
SUB %EBX,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV (%R12),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%R12),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV (%R15),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%R15),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
INC %R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RCX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $-0x2,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND %RAX,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 4239e1 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.23+0x461>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RAX,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %EBP,0x8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOVD %R13D,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (6.3%)
PSHUFD $0x44,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOV %R14,0x28(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOVD %R14D,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (6.3%)
PSHUFD $0x50,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVDQA %XMM0,0x70(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
MOV %RBX,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOVD %EBX,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (6.3%)
PSHUFD $0x50,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVDQA %XMM0,0x60(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
MOVQ %R9,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVQ %R10,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVQ %R11,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVQ %R15,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVDQA %XMM0,0x50(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
MOVQ %RCX,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
PADDQ 0x47d4d(%RIP),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (25.0%)
XOR %EBP,%EBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOVDQA %XMM1,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
PSHUFD $-0x12,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVDQA %XMM0,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
MOVDQA %XMM2,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
PSRLQ $0x20,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	vect (25.0%)
MOVDQA %XMM5,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
PSRLQ $0x20,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	vect (25.0%)
PCMPEQD %XMM8,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
CMP %R12,0x20(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOV 0x30(%RSP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x28(%RSP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x8(%RSP),%EBP	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
JNE 423961 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.23+0x3e1>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV $0x47c870,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EBP,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
ADD $0x88,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
JMP 403050 <__kmpc_for_static_fini@plt>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
ADD $0x88,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD %R12,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 4239e1 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.23+0x461>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	1.35	0.55
○Loop 173 - - exec	1.34	0.55
○Loop 172 - - exec	0.00	0.00

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Matching between your function (in the source code) and the binary function

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ASM code

Code clean check

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Vectorization

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Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code