OV - exec - Function advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone .extracted.30]

	Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ...	Module: exec	Source: :0-0	Coverage (incl. loops): 3.14% \| (excl. loops): 0.00%

  ***  This Panel is Intentionally Left Blank.  ***

It is due to a lack of debug symbols in the given object
(loop or function).

0x41f4a0 PUSH	%RBP

0x41f4a1 PUSH	%R15

0x41f4a3 PUSH	%R14

0x41f4a5 PUSH	%R13

0x41f4a7 PUSH	%R12

0x41f4a9 PUSH	%RBX

0x41f4aa SUB	$0x148,%RSP

0x41f4b1 MOV	%RCX,%R15

0x41f4b4 MOV	0x1b0(%RSP),%RAX

0x41f4bc MOV	0x1a0(%RSP),%RBP

0x41f4c4 MOV	0x198(%RSP),%R10

0x41f4cc MOV	0x190(%RSP),%RCX

0x41f4d4 MOV	%RCX,0x50(%RSP)

0x41f4d9 MOV	0x188(%RSP),%RBX

0x41f4e1 MOV	0x180(%RSP),%R14

0x41f4e9 MOVL	$0,0x14(%RSP)

0x41f4f1 TEST	%RAX,%RAX

0x41f4f4 JS	41fb39

0x41f4fa MOV	%R8,%R12

0x41f4fd MOV	%RDX,%R13

0x41f500 MOV	%R9,0x8(%RSP)

0x41f505 MOV	(%RDI),%ESI

0x41f507 MOVQ	$0,0x60(%RSP)

0x41f510 MOV	%RAX,0x58(%RSP)

0x41f515 MOVQ	$0x1,0x88(%RSP)

0x41f521 SUB	$0x8,%RSP

0x41f525 LEA	0x90(%RSP),%RAX

0x41f52d LEA	0x1c(%RSP),%RCX

0x41f532 LEA	0x68(%RSP),%R8

0x41f537 LEA	0x60(%RSP),%R9

0x41f53c MOV	$0x47c5b0,%EDI

0x41f541 MOV	%ESI,0x18(%RSP)

0x41f545 MOV	$0x22,%EDX

0x41f54a PUSH	$0x1

0x41f54c PUSH	$0x1

0x41f54e PUSH	%RAX

0x41f54f MOV	%R10,0x38(%RSP)

0x41f554 CALL	4031e0 <__kmpc_for_static_init_8@plt>

0x41f559 MOV	0x38(%RSP),%R11

0x41f55e ADD	$0x20,%RSP

0x41f562 MOV	0x60(%RSP),%RCX

0x41f567 MOV	0x58(%RSP),%RDX

0x41f56c CMP	%RDX,%RCX

0x41f56f JA	41fb1a

0x41f575 MOV	%RDX,%RAX

0x41f578 SUB	%R11D,%EBP

0x41f57b MOV	(%R13),%RDX

0x41f57f MOV	0x10(%R13),%R9

0x41f583 MOV	(%R14),%RSI

0x41f586 MOV	0x10(%R14),%RDI

0x41f58a MOV	(%R12),%R8

0x41f58e MOV	0x10(%R12),%R12

0x41f593 MOV	(%R15),%R10

0x41f596 MOV	%R10,0x48(%RSP)

0x41f59b MOV	0x10(%R15),%R15

0x41f59f MOV	(%RBX),%R10

0x41f5a2 MOV	%R10,0x40(%RSP)

0x41f5a7 MOV	0x10(%RBX),%R13

0x41f5ab MOV	0x8(%RSP),%R10

0x41f5b0 MOV	(%R10),%RBX

0x41f5b3 MOV	0x10(%R10),%R14

0x41f5b7 INC	%RAX

0x41f5ba MOV	%RAX,0x8(%RSP)

0x41f5bf SUB	%RCX,%RAX

0x41f5c2 MOV	$-0x2,%R10D

0x41f5c8 AND	%RAX,%R10

0x41f5cb MOV	%RSI,0x38(%RSP)

0x41f5d0 MOV	%RDI,0x30(%RSP)

0x41f5d5 MOV	%R8,0x28(%RSP)

0x41f5da MOV	%R9,0x20(%RSP)

0x41f5df MOV	%RBX,0x80(%RSP)

0x41f5e7 JE	41fb4b

0x41f5ed MOV	%RAX,0x68(%RSP)

0x41f5f2 MOV	%RBP,0x78(%RSP)

0x41f5f7 MOVD	%EBP,%XMM0

0x41f5fb PSHUFD	$0x44,%XMM0,%XMM0

0x41f600 MOVDQA	%XMM0,0x130(%RSP)

0x41f609 MOVQ	0x50(%RSP),%XMM0

0x41f60f PSHUFD	$0x44,%XMM0,%XMM0

0x41f614 MOVDQA	%XMM0,0x120(%RSP)

0x41f61d MOVD	%R11D,%XMM0

0x41f622 PSHUFD	$0x50,%XMM0,%XMM0

0x41f627 MOVDQA	%XMM0,0x110(%RSP)

0x41f630 MOV	%RDX,0x70(%RSP)

0x41f635 MOVQ	%RDX,%XMM0

0x41f63a PSHUFD	$0x44,%XMM0,%XMM0

0x41f63f MOVDQA	%XMM0,0x100(%RSP)

0x41f648 MOVQ	%R9,%XMM0

0x41f64d PSHUFD	$0x44,%XMM0,%XMM0

0x41f652 MOVDQA	%XMM0,0xf0(%RSP)

0x41f65b MOVQ	%RSI,%XMM0

0x41f660 PSHUFD	$0x44,%XMM0,%XMM0

0x41f665 MOVDQA	%XMM0,0xc0(%RSP)

0x41f66e MOVQ	%RDI,%XMM0

0x41f673 PSHUFD	$0x44,%XMM0,%XMM0

0x41f678 MOVDQA	%XMM0,0xe0(%RSP)

0x41f681 MOVQ	%R8,%XMM0

0x41f686 PSHUFD	$0x44,%XMM0,%XMM7

0x41f68b MOVQ	%R12,%XMM0

0x41f690 PSHUFD	$0x44,%XMM0,%XMM0

0x41f695 MOVDQA	%XMM0,0xd0(%RSP)

0x41f69e MOVQ	0x48(%RSP),%XMM0

0x41f6a4 PSHUFD	$0x44,%XMM0,%XMM3

0x41f6a9 MOVQ	%R15,%XMM0

0x41f6ae PSHUFD	$0x44,%XMM0,%XMM0

0x41f6b3 MOVDQA	%XMM0,0xb0(%RSP)

0x41f6bc MOVQ	0x40(%RSP),%XMM0

0x41f6c2 PSHUFD	$0x44,%XMM0,%XMM11

0x41f6c8 MOVQ	%R13,%XMM0

0x41f6cd PSHUFD	$0x44,%XMM0,%XMM0

0x41f6d2 MOVDQA	%XMM0,0xa0(%RSP)

0x41f6db MOVQ	%RBX,%XMM0

0x41f6e0 PSHUFD	$0x44,%XMM0,%XMM13

0x41f6e6 MOVQ	%R14,%XMM0

0x41f6eb MOVQ	%RCX,%XMM1

0x41f6f0 PSHUFD	$0x44,%XMM1,%XMM14

0x41f6f6 PADDQ	0x4bd11(%RIP),%XMM14

0x41f6ff PSHUFD	$0x44,%XMM0,%XMM0

0x41f704 MOVDQA	%XMM0,0x90(%RSP)

0x41f70d XOR	%R11D,%R11D

(159) 0x41f710 MOVQ	%XMM14,%RSI

(159) 0x41f715 MOVDQA	0x130(%RSP),%XMM2

(159) 0x41f71e MOVQ	%XMM2,%R8

(159) 0x41f723 XOR	%EDX,%EDX

(159) 0x41f725 MOV	%RSI,%RAX

(159) 0x41f728 DIV	%R8

(159) 0x41f72b PSHUFD	$-0x12,%XMM14,%XMM0

(159) 0x41f731 MOVQ	%RAX,%XMM1

(159) 0x41f736 MOVQ	%XMM0,%RDI

(159) 0x41f73b PSHUFD	$-0x12,%XMM2,%XMM0

(159) 0x41f740 MOVQ	%XMM0,%RBX

(159) 0x41f745 MOV	%RDI,%RAX

(159) 0x41f748 XOR	%EDX,%EDX

(159) 0x41f74a DIV	%RBX

(159) 0x41f74d MOVQ	%RAX,%XMM0

(159) 0x41f752 PUNPCKLQDQ	%XMM0,%XMM1

(159) 0x41f756 MOV	%RSI,%RAX

(159) 0x41f759 CQTO

(159) 0x41f75b PADDQ	0x120(%RSP),%XMM1

(159) 0x41f764 IDIV	%R8

(159) 0x41f767 MOVQ	%RDX,%XMM0

(159) 0x41f76c MOV	%RDI,%RAX

(159) 0x41f76f CQTO

(159) 0x41f771 IDIV	%RBX

(159) 0x41f774 MOVQ	%RDX,%XMM2

(159) 0x41f779 PUNPCKLQDQ	%XMM2,%XMM0

(159) 0x41f77d PXOR	%XMM8,%XMM8

(159) 0x41f782 PSHUFD	$-0x18,%XMM1,%XMM6

(159) 0x41f787 PSHUFD	$-0x18,%XMM0,%XMM4

(159) 0x41f78c PSLLQ	$0x20,%XMM1

(159) 0x41f791 PSRAD	$0x1f,%XMM1

(159) 0x41f796 PSHUFD	$-0x13,%XMM1,%XMM0

(159) 0x41f79b PADDD	0x110(%RSP),%XMM4

(159) 0x41f7a4 PUNPCKLDQ	%XMM0,%XMM6

(159) 0x41f7a8 MOVDQA	0x100(%RSP),%XMM12

(159) 0x41f7b2 MOVDQA	%XMM12,%XMM0

(159) 0x41f7b7 PMULUDQ	%XMM6,%XMM0

(159) 0x41f7bb PCMPGTD	%XMM4,%XMM8

(159) 0x41f7c0 MOVDQA	%XMM12,%XMM10

(159) 0x41f7c5 PSRLQ	$0x20,%XMM10

(159) 0x41f7cb PMULUDQ	%XMM6,%XMM10

(159) 0x41f7d0 MOVDQA	%XMM4,%XMM2

(159) 0x41f7d4 PSRLQ	$0x20,%XMM1

(159) 0x41f7d9 PMULUDQ	%XMM1,%XMM12

(159) 0x41f7de PUNPCKLDQ	%XMM8,%XMM2

(159) 0x41f7e3 PADDQ	%XMM10,%XMM12

(159) 0x41f7e8 PADDQ	%XMM2,%XMM0

(159) 0x41f7ec MOVDQA	0xc0(%RSP),%XMM5

(159) 0x41f7f5 MOVDQA	%XMM5,%XMM8

(159) 0x41f7fa PSLLQ	$0x20,%XMM12

(159) 0x41f800 PMULUDQ	%XMM6,%XMM8

(159) 0x41f805 MOVDQA	%XMM5,%XMM10

(159) 0x41f80a PSRLQ	$0x20,%XMM10

(159) 0x41f810 PADDQ	%XMM12,%XMM0

(159) 0x41f815 PMULUDQ	%XMM6,%XMM10

(159) 0x41f81a MOVDQA	%XMM5,%XMM12

(159) 0x41f81f PMULUDQ	%XMM1,%XMM12

(159) 0x41f824 PSLLQ	$0x3,%XMM0

(159) 0x41f829 PADDQ	%XMM10,%XMM12

(159) 0x41f82e PSLLQ	$0x20,%XMM12

(159) 0x41f834 PADDQ	%XMM2,%XMM8

(159) 0x41f839 PADDQ	0xf0(%RSP),%XMM0

(159) 0x41f842 PADDQ	%XMM12,%XMM8

(159) 0x41f847 PSLLQ	$0x3,%XMM8

(159) 0x41f84d PADDQ	0xe0(%RSP),%XMM8

(159) 0x41f857 MOVQ	%XMM0,%RAX

(159) 0x41f85c MOVDQA	%XMM7,%XMM12

(159) 0x41f861 PMULUDQ	%XMM6,%XMM12

(159) 0x41f866 MOVDQA	%XMM7,%XMM10

(159) 0x41f86b PSHUFD	$-0x12,%XMM0,%XMM15

(159) 0x41f871 PSRLQ	$0x20,%XMM10

(159) 0x41f877 PMULUDQ	%XMM6,%XMM10

(159) 0x41f87c MOVDQA	%XMM7,%XMM0

(159) 0x41f880 MOVQ	%XMM8,%RSI

(159) 0x41f885 PMULUDQ	%XMM1,%XMM0

(159) 0x41f889 PADDQ	%XMM10,%XMM0

(159) 0x41f88e PSLLQ	$0x20,%XMM0

(159) 0x41f893 PSHUFD	$-0x12,%XMM8,%XMM10

(159) 0x41f899 PADDQ	%XMM12,%XMM0

(159) 0x41f89e MOVDQA	%XMM0,%XMM8

(159) 0x41f8a3 PADDQ	%XMM2,%XMM8

(159) 0x41f8a8 PSLLQ	$0x3,%XMM8

(159) 0x41f8ae PSUBD	0x4bbaa(%RIP),%XMM4

(159) 0x41f8b6 PXOR	%XMM12,%XMM12

(159) 0x41f8bb PCMPGTD	%XMM4,%XMM12

(159) 0x41f8c0 MOVQ	%XMM15,%RDX

(159) 0x41f8c5 PUNPCKLDQ	%XMM12,%XMM4

(159) 0x41f8ca MOVDQA	%XMM3,%XMM15

(159) 0x41f8cf PMULUDQ	%XMM6,%XMM15

(159) 0x41f8d4 MOVQ	%XMM10,%R9

(159) 0x41f8d9 MOVDQA	%XMM3,%XMM10

(159) 0x41f8de PSRLQ	$0x20,%XMM10

(159) 0x41f8e4 PMULUDQ	%XMM6,%XMM10

(159) 0x41f8e9 MOVDQA	0xd0(%RSP),%XMM5

(159) 0x41f8f2 PADDQ	%XMM5,%XMM8

(159) 0x41f8f7 MOVDQA	%XMM3,%XMM9

(159) 0x41f8fc PMULUDQ	%XMM1,%XMM9

(159) 0x41f901 PADDQ	%XMM10,%XMM9

(159) 0x41f906 MOVSD	(%RAX),%XMM12

(159) 0x41f90b PSLLQ	$0x20,%XMM9

(159) 0x41f911 PADDQ	%XMM2,%XMM15

(159) 0x41f916 PADDQ	%XMM9,%XMM15

(159) 0x41f91b MOVSD	(%RSI),%XMM10

(159) 0x41f920 PADDQ	%XMM4,%XMM0

(159) 0x41f924 PSLLQ	$0x3,%XMM0

(159) 0x41f929 PADDQ	%XMM5,%XMM0

(159) 0x41f92d MOVQ	%XMM8,%RBP

(159) 0x41f932 MOVQ	%XMM0,%R8

(159) 0x41f937 PSHUFD	$-0x12,%XMM0,%XMM0

(159) 0x41f93c PSLLQ	$0x3,%XMM15

(159) 0x41f942 PSHUFD	$-0x12,%XMM8,%XMM8

(159) 0x41f948 PADDQ	0xb0(%RSP),%XMM15

(159) 0x41f952 MOVQ	%XMM15,%RSI

(159) 0x41f957 PSHUFD	$-0x12,%XMM15,%XMM9

(159) 0x41f95d MOVQ	%XMM0,%RBX

(159) 0x41f962 MOVQ	%XMM9,%RDI

(159) 0x41f967 MOVDQA	%XMM11,%XMM9

(159) 0x41f96c MOVHPD	(%R9),%XMM10

(159) 0x41f971 PMULUDQ	%XMM6,%XMM9

(159) 0x41f976 MOVDQA	%XMM11,%XMM0

(159) 0x41f97b PSRLQ	$0x20,%XMM0

(159) 0x41f980 MOVQ	%XMM8,%R9

(159) 0x41f985 PMULUDQ	%XMM6,%XMM0

(159) 0x41f989 MOVDQA	%XMM11,%XMM8

(159) 0x41f98e MOVHPD	(%RDX),%XMM12

(159) 0x41f993 PMULUDQ	%XMM1,%XMM8

(159) 0x41f998 PADDQ	%XMM0,%XMM8

(159) 0x41f99d PSLLQ	$0x20,%XMM8

(159) 0x41f9a3 MOVSD	(%RBP),%XMM0

(159) 0x41f9a8 PADDQ	%XMM9,%XMM8

(159) 0x41f9ad MOVDQA	%XMM8,%XMM9

(159) 0x41f9b2 MOVHPD	(%R9),%XMM0

(159) 0x41f9b7 PADDQ	%XMM2,%XMM9

(159) 0x41f9bc PSLLQ	$0x3,%XMM9

(159) 0x41f9c2 MOVDQA	0xa0(%RSP),%XMM5

(159) 0x41f9cb PADDQ	%XMM5,%XMM9

(159) 0x41f9d0 MULPD	%XMM10,%XMM12

(159) 0x41f9d5 MOVQ	%XMM9,%R9

(159) 0x41f9da PSHUFD	$-0x12,%XMM9,%XMM9

(159) 0x41f9e0 MOVQ	%XMM9,%RBP

(159) 0x41f9e5 ADDPD	%XMM12,%XMM0

(159) 0x41f9ea MOVSD	(%RSI),%XMM9

(159) 0x41f9ef MOVHPD	(%RDI),%XMM9

(159) 0x41f9f4 MULPD	%XMM12,%XMM9

(159) 0x41f9f9 MOVSD	(%R8),%XMM12

(159) 0x41f9fe PADDQ	%XMM4,%XMM8

(159) 0x41fa03 MOVHPD	(%RBX),%XMM12

(159) 0x41fa08 PSLLQ	$0x3,%XMM8

(159) 0x41fa0e PADDQ	%XMM5,%XMM8

(159) 0x41fa13 MOVQ	%XMM8,%R8

(159) 0x41fa18 SUBPD	%XMM12,%XMM0

(159) 0x41fa1d PSHUFD	$-0x12,%XMM8,%XMM8

(159) 0x41fa23 MOVSD	(%R8),%XMM12

(159) 0x41fa28 MOVQ	%XMM8,%R8

(159) 0x41fa2d MOVSD	(%R9),%XMM8

(159) 0x41fa32 MOVHPD	(%R8),%XMM12

(159) 0x41fa37 MOVHPD	(%RBP),%XMM8

(159) 0x41fa3d ADDPD	%XMM9,%XMM8

(159) 0x41fa42 MOVDQA	%XMM13,%XMM9

(159) 0x41fa47 PMULUDQ	%XMM6,%XMM9

(159) 0x41fa4c SUBPD	%XMM12,%XMM8

(159) 0x41fa51 MOVDQA	%XMM13,%XMM12

(159) 0x41fa56 PSRLQ	$0x20,%XMM12

(159) 0x41fa5c PMULUDQ	%XMM6,%XMM12

(159) 0x41fa61 PMULUDQ	%XMM13,%XMM1

(159) 0x41fa66 PADDQ	%XMM12,%XMM1

(159) 0x41fa6b PSLLQ	$0x20,%XMM1

(159) 0x41fa70 PADDQ	%XMM9,%XMM1

(159) 0x41fa75 PADDQ	%XMM1,%XMM2

(159) 0x41fa79 PSLLQ	$0x3,%XMM2

(159) 0x41fa7e MOVDQA	0x90(%RSP),%XMM5

(159) 0x41fa87 PADDQ	%XMM5,%XMM2

(159) 0x41fa8b MOVQ	%XMM2,%R8

(159) 0x41fa90 PSHUFD	$-0x12,%XMM2,%XMM2

(159) 0x41fa95 MOVQ	%XMM2,%R9

(159) 0x41fa9a MOVSD	(%R8),%XMM2

(159) 0x41fa9f MOVHPD	(%R9),%XMM2

(159) 0x41faa4 ADDPD	%XMM10,%XMM2

(159) 0x41faa9 PADDQ	%XMM4,%XMM1

(159) 0x41faad PSLLQ	$0x3,%XMM1

(159) 0x41fab2 PADDQ	%XMM5,%XMM1

(159) 0x41fab6 MOVQ	%XMM1,%R8

(159) 0x41fabb PSHUFD	$-0x12,%XMM1,%XMM1

(159) 0x41fac0 MOVQ	%XMM1,%R9

(159) 0x41fac5 MOVSD	(%R8),%XMM1

(159) 0x41faca MOVHPD	(%R9),%XMM1

(159) 0x41facf SUBPD	%XMM1,%XMM2

(159) 0x41fad3 DIVPD	%XMM0,%XMM8

(159) 0x41fad8 DIVPD	%XMM2,%XMM0

(159) 0x41fadc MOVLPD	%XMM0,(%RAX)

(159) 0x41fae0 MOVHPD	%XMM0,(%RDX)

(159) 0x41fae4 MOVLPD	%XMM8,(%RSI)

(159) 0x41fae9 MOVHPD	%XMM8,(%RDI)

(159) 0x41faee PADDQ	0x4b939(%RIP),%XMM14

(159) 0x41faf7 ADD	$0x2,%R11

(159) 0x41fafb CMP	%R10,%R11

(159) 0x41fafe JB	41f710

0x41fb04 CMP	%R10,0x68(%RSP)

0x41fb09 MOV	0x78(%RSP),%RBP

0x41fb0e MOV	0x18(%RSP),%R11

0x41fb13 MOV	0x70(%RSP),%RBX

0x41fb18 JNE	41fb53

0x41fb1a MOV	$0x47c5d0,%EDI

0x41fb1f MOV	0x10(%RSP),%ESI

0x41fb23 ADD	$0x148,%RSP

0x41fb2a POP	%RBX

0x41fb2b POP	%R12

0x41fb2d POP	%R13

0x41fb2f POP	%R14

0x41fb31 POP	%R15

0x41fb33 POP	%RBP

0x41fb34 JMP	403050

0x41fb39 ADD	$0x148,%RSP

0x41fb40 POP	%RBX

0x41fb41 POP	%R12

0x41fb43 POP	%R13

0x41fb45 POP	%R14

0x41fb47 POP	%R15

0x41fb49 POP	%RBP

0x41fb4a RET

0x41fb4b MOV	%RDX,%RBX

0x41fb4e JMP	41fc2c

0x41fb53 ADD	%R10,%RCX

0x41fb56 JMP	41fc2c

0x41fb5b NOPL	(%RAX,%RAX,1)

(158) 0x41fb60 MOV	%RCX,%RAX

(158) 0x41fb63 CQTO

(158) 0x41fb65 IDIV	%RBP

(158) 0x41fb68 MOV	0x38(%RSP),%RDI

(158) 0x41fb6d ADD	%R11D,%EDX

(158) 0x41fb70 MOVSXD	%EDX,%RDX

(158) 0x41fb73 MOVSXD	%ESI,%RSI

(158) 0x41fb76 MOV	%RBX,%RAX

(158) 0x41fb79 IMUL	%RSI,%RAX

(158) 0x41fb7d ADD	%RDX,%RAX

(158) 0x41fb80 IMUL	%RSI,%RDI

(158) 0x41fb84 ADD	%RDX,%RDI

(158) 0x41fb87 MOVSD	(%R8,%RDI,8),%XMM1

(158) 0x41fb8d MOVSD	(%R10,%RAX,8),%XMM0

(158) 0x41fb93 MULSD	%XMM1,%XMM0

(158) 0x41fb97 MOV	%R9,%RDI

(158) 0x41fb9a IMUL	%RSI,%RDI

(158) 0x41fb9e LEA	(%RDI,%RDX,1),%R8

(158) 0x41fba2 MOVSD	(%R12,%R8,8),%XMM2

(158) 0x41fba8 ADDSD	%XMM0,%XMM2

(158) 0x41fbac ADD	%RDX,%RDI

(158) 0x41fbaf INC	%RDI

(158) 0x41fbb2 SUBSD	(%R12,%RDI,8),%XMM2

(158) 0x41fbb8 MOV	0x48(%RSP),%RDI

(158) 0x41fbbd IMUL	%RSI,%RDI

(158) 0x41fbc1 ADD	%RDX,%RDI

(158) 0x41fbc4 MULSD	(%R15,%RDI,8),%XMM0

(158) 0x41fbca MOV	0x40(%RSP),%R8

(158) 0x41fbcf IMUL	%RSI,%R8

(158) 0x41fbd3 LEA	(%R8,%RDX,1),%R9

(158) 0x41fbd7 ADDSD	(%R13,%R9,8),%XMM0

(158) 0x41fbde ADD	%RDX,%R8

(158) 0x41fbe1 INC	%R8

(158) 0x41fbe4 SUBSD	(%R13,%R8,8),%XMM0

(158) 0x41fbeb IMUL	0x80(%RSP),%RSI

(158) 0x41fbf4 LEA	(%RSI,%RDX,1),%R8

(158) 0x41fbf8 ADDSD	(%R14,%R8,8),%XMM1

(158) 0x41fbfe ADD	%RSI,%RDX

(158) 0x41fc01 INC	%RDX

(158) 0x41fc04 SUBSD	(%R14,%RDX,8),%XMM1

(158) 0x41fc0a DIVSD	%XMM2,%XMM0

(158) 0x41fc0e DIVSD	%XMM1,%XMM2

(158) 0x41fc12 MOVSD	%XMM2,(%R10,%RAX,8)

(158) 0x41fc18 MOVSD	%XMM0,(%R15,%RDI,8)

(158) 0x41fc1e INC	%RCX

(158) 0x41fc21 CMP	%RCX,0x8(%RSP)

(158) 0x41fc26 JE	41fb1a

(158) 0x41fc2c MOV	%RCX,%RDI

(158) 0x41fc2f SHR	$0x20,%RDI

(158) 0x41fc33 JE	41fc50

(158) 0x41fc35 MOV	%RCX,%RAX

(158) 0x41fc38 XOR	%EDX,%EDX

(158) 0x41fc3a DIV	%RBP

(158) 0x41fc3d MOV	%RAX,%RSI

(158) 0x41fc40 JMP	41fc58

0x41fc42 NOPW	%CS:(%RAX,%RAX,1)

(158) 0x41fc50 MOV	%ECX,%EAX

(158) 0x41fc52 XOR	%EDX,%EDX

(158) 0x41fc54 DIV	%EBP

(158) 0x41fc56 MOV	%EAX,%ESI

(158) 0x41fc58 MOV	0x30(%RSP),%R8

(158) 0x41fc5d MOV	0x28(%RSP),%R9

(158) 0x41fc62 MOV	0x20(%RSP),%R10

(158) 0x41fc67 ADD	0x50(%RSP),%RSI

(158) 0x41fc6c TEST	%RDI,%RDI

(158) 0x41fc6f JNE	41fb60

(158) 0x41fc75 MOV	%ECX,%EAX

(158) 0x41fc77 XOR	%EDX,%EDX

(158) 0x41fc79 DIV	%EBP

(158) 0x41fc7b JMP	41fb68

Coverage (%)	Name	Module
►48.22+	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_launch_thread	libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]	libiomp5.so
○	start_thread	libc.so.6
○	__GI___clone3	libc.so.6
►40.96+	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_launch_thread	libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]	libiomp5.so
►5.39+	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_launch_thread	libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]	libiomp5.so
○	start_thread	libc.so.6
►2.31+	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_launch_thread	libiomp5.so
►1.58+	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_fork_call	libiomp5.so
○	__kmpc_fork_call	libiomp5.so
○	advec_cell_kernel(int, int, in[...]	exec
○	advec_cell_driver(global_varia[...]	exec
○	advection(global_variables&)	exec
○	hydro(global_variables&, paral[...]	exec
○	main	exec
○	__libc_start_call_main	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	exec
►1.55+	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_fork_call	libiomp5.so
○	__kmpc_fork_call	libiomp5.so
○	advec_cell_kernel(int, int, in[...]	exec
○	advec_cell_driver(global_varia[...]	exec
○	advection(global_variables&)	exec
○	hydro(global_variables&, paral[...]	exec
○	main	exec
○	__libc_start_call_main	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_0

Source file and lines
Module	exec

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 20.13 to 8.75 cycles (2.30x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 16% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 20.13 to 2.22 cycles (9.06x speedup).

Details

35% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

6% of SSE/AVX loads are used in vector version.
36% of SSE/AVX stores are used in vector version.
50% of SSE/AVX addition or subtraction instructions are used in vector version.
47% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__kmpc_for_static_init_8@plt: 1 occurrences►

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

MOVD: 2 occurrences►
MOVQ: 11 occurrences►

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 256 bytes. The binary function is storing 320 bytes.

General properties

nb instructions	149
nb uops	161
loop length	730
used x86 registers	16
used mmx registers	0
used xmm registers	7
used ymm registers	0
used zmm registers	0
nb stack references	36

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	20.13 cycles
front end	20.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.00	5.00	5.00	5.00	5.00	5.00	15.75	15.75	15.75	15.75	7.50	7.50	7.50	7.50	5.50	5.50
cycles	5.00	5.00	5.00	5.00	5.00	5.00	15.75	15.75	15.75	15.75	7.50	7.50	7.50	7.50	5.50	5.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	20.13
Dispatch	15.75
Overall L1	20.13

Vectorization ratios

all	35%
load	6%
store	36%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	47%

Vector efficiency ratios

all	16%
load	12%
store	16%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	15%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	17%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.13 cycles. At this rate:

4% of peak load performance is reached (12.72 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (15.90 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 20.13 to 15.75 cycles (1.28x speedup).

ASM code

In the binary file, the address of the function is: 41f4a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x148,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x1b0(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x1a0(%RSP),%RBP	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x198(%RSP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x190(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RCX,0x50(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x188(%RSP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x180(%RSP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOVL $0,0x14(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
TEST %RAX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JS 41fb39 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.30+0x699>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R8,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R9,0x8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
MOVQ $0,0x60(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV %RAX,0x58(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOVQ $0x1,0x88(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x90(%RSP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x1c(%RSP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x68(%RSP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x60(%RSP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x47c5b0,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %ESI,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %R10,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
CALL 4031e0 <__kmpc_for_static_init_8@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV 0x38(%RSP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x60(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x58(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
CMP %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JA 41fb1a <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.30+0x67a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RDX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %R11D,%EBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV (%R13),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%R13),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV (%R14),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%R14),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%R12),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%R12),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%R15),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R10,0x48(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x10(%R15),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RBX),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R10,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x10(%RBX),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x8(%RSP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%R10),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%R10),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,0x8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
SUB %RCX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $-0x2,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND %RAX,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSI,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDI,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R8,0x28(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R9,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RBX,0x80(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
JE 41fb4b <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.30+0x6ab>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RAX,0x68(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RBP,0x78(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOVD %EBP,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (6.3%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVDQA %XMM0,0x130(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
MOVQ 0x50(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVDQA %XMM0,0x120(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
MOVD %R11D,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (6.3%)
PSHUFD $0x50,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVDQA %XMM0,0x110(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
MOV %RDX,0x70(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOVQ %RDX,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVDQA %XMM0,0x100(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
MOVQ %R9,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVDQA %XMM0,0xf0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
MOVQ %RSI,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVDQA %XMM0,0xc0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
MOVQ %RDI,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVDQA %XMM0,0xe0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
MOVQ %R8,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVQ %R12,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVDQA %XMM0,0xd0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
MOVQ 0x48(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVQ %R15,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVDQA %XMM0,0xb0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
MOVQ 0x40(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVQ %R13,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVDQA %XMM0,0xa0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
MOVQ %RBX,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVQ %R14,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (12.5%)
MOVQ %RCX,%XMM1	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (12.5%)
PSHUFD $0x44,%XMM1,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
PADDQ 0x4bd11(%RIP),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (25.0%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVDQA %XMM0,0x90(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
XOR %R11D,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
CMP %R10,0x68(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOV 0x78(%RSP),%RBP	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x18(%RSP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x70(%RSP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JNE 41fb53 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.30+0x6b3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV $0x47c5d0,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x10(%RSP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
ADD $0x148,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
JMP 403050 <__kmpc_for_static_fini@plt>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
ADD $0x148,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 41fc2c <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.30+0x78c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
ADD %R10,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 41fc2c <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.30+0x78c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_0

Source file and lines
Module	exec

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 20.13 to 8.75 cycles (2.30x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

35% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

6% of SSE/AVX loads are used in vector version.
36% of SSE/AVX stores are used in vector version.
50% of SSE/AVX addition or subtraction instructions are used in vector version.
47% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

__kmpc_for_static_init_8@plt: 1 occurrences►

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

MOVD: 2 occurrences►
MOVQ: 11 occurrences►

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 256 bytes. The binary function is storing 320 bytes.

General properties

nb instructions	149
nb uops	161
loop length	730
used x86 registers	16
used mmx registers	0
used xmm registers	7
used ymm registers	0
used zmm registers	0
nb stack references	36

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	20.13 cycles
front end	20.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.00	5.00	5.00	5.00	5.00	5.00	15.75	15.75	15.75	15.75	7.50	7.50	7.50	7.50	5.50	5.50
cycles	5.00	5.00	5.00	5.00	5.00	5.00	15.75	15.75	15.75	15.75	7.50	7.50	7.50	7.50	5.50	5.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	20.13
Dispatch	15.75
Overall L1	20.13

Vectorization ratios

all	35%
load	6%
store	36%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	47%

Vector efficiency ratios

all	16%
load	12%
store	16%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	15%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	17%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.13 cycles. At this rate:

4% of peak load performance is reached (12.72 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (15.90 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 41f4a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x148,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x1b0(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x1a0(%RSP),%RBP	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x198(%RSP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x190(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RCX,0x50(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x188(%RSP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x180(%RSP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOVL $0,0x14(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
TEST %RAX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JS 41fb39 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.30+0x699>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R8,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R9,0x8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
MOVQ $0,0x60(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV %RAX,0x58(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOVQ $0x1,0x88(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x90(%RSP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x1c(%RSP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x68(%RSP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x60(%RSP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x47c5b0,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %ESI,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %R10,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
CALL 4031e0 <__kmpc_for_static_init_8@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV 0x38(%RSP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x60(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x58(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
CMP %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JA 41fb1a <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.30+0x67a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RDX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %R11D,%EBP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV (%R13),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%R13),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV (%R14),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%R14),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%R12),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%R12),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%R15),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R10,0x48(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x10(%R15),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RBX),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R10,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x10(%RBX),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x8(%RSP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%R10),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%R10),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,0x8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
SUB %RCX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $-0x2,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND %RAX,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSI,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDI,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R8,0x28(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R9,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RBX,0x80(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
JE 41fb4b <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.30+0x6ab>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RAX,0x68(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RBP,0x78(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOVD %EBP,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (6.3%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVDQA %XMM0,0x130(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
MOVQ 0x50(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVDQA %XMM0,0x120(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
MOVD %R11D,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (6.3%)
PSHUFD $0x50,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVDQA %XMM0,0x110(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
MOV %RDX,0x70(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOVQ %RDX,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVDQA %XMM0,0x100(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
MOVQ %R9,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVDQA %XMM0,0xf0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
MOVQ %RSI,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVDQA %XMM0,0xc0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
MOVQ %RDI,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVDQA %XMM0,0xe0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
MOVQ %R8,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVQ %R12,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVDQA %XMM0,0xd0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
MOVQ 0x48(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVQ %R15,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVDQA %XMM0,0xb0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
MOVQ 0x40(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVQ %R13,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVDQA %XMM0,0xa0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
MOVQ %RBX,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (12.5%)
PSHUFD $0x44,%XMM0,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVQ %R14,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (12.5%)
MOVQ %RCX,%XMM1	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1	scal (12.5%)
PSHUFD $0x44,%XMM1,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
PADDQ 0x4bd11(%RIP),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (25.0%)
PSHUFD $0x44,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOVDQA %XMM0,0x90(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
XOR %R11D,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
CMP %R10,0x68(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOV 0x78(%RSP),%RBP	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x18(%RSP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x70(%RSP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JNE 41fb53 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.30+0x6b3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV $0x47c5d0,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x10(%RSP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
ADD $0x148,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
JMP 403050 <__kmpc_for_static_fini@plt>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
ADD $0x148,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 41fc2c <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.30+0x78c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
ADD %R10,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 41fc2c <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.30+0x78c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	3.14	1.29
○Loop 159 - - exec	3.14	1.29
○Loop 158 - - exec	0.00	0.00

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Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code