OV - exec - Function calc_dt_kernel(int, int, int, int, double, double, double, double, double, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, double&, int&, double&, double&, int&, int&, int&) [clone .omp

	Function: calc_dt_kernel(int, int, int, int, double, double, double, double, double, clover::Buffer2 ...	Module: exec	Source: calc_dt.cpp:49-75 [...]	Coverage (incl. loops): 3.04% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 46 - 69

--------------------------------------------------------------------------------

46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp: 49 - 75

--------------------------------------------------------------------------------

49: #pragma omp parallel for simd collapse(2) reduction(min : dt_min_val0)

50:   for (int j = (y_min + 1); j < (y_max + 2); j++) {

51:     for (int i = (x_min + 1); i < (x_max + 2); i++) {

52:       double dsx = celldx[i];

53:       double dsy = celldy[j];

54:       double cc = soundspeed(i, j) * soundspeed(i, j);

55:       cc = cc + 2.0 * viscosity_a(i, j) / density0(i, j);

56:       cc = std::fmax(std::sqrt(cc), g_small);

57:       double dtct = dtc_safe * std::fmin(dsx, dsy) / cc;

58:       double div = 0.0;

59:       double dv1 = (xvel0(i, j) + xvel0(i + 0, j + 1)) * xarea(i, j);

60:       double dv2 = (xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1)) * xarea(i + 1, j + 0);

61:       div = div + dv2 - dv1;

62:       double dtut = dtu_safe * 2.0 * volume(i, j) / std::fmax(std::fmax(std::fabs(dv1), std::fabs(dv2)), g_small * volume(i, j));

63:       dv1 = (yvel0(i, j) + yvel0(i + 1, j + 0)) * yarea(i, j);

64:       dv2 = (yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1)) * yarea(i + 0, j + 1);

65:       div = div + dv2 - dv1;

66:       double dtvt = dtv_safe * 2.0 * volume(i, j) / std::fmax(std::fmax(std::fabs(dv1), std::fabs(dv2)), g_small * volume(i, j));

67:       div = div / (2.0 * volume(i, j));

68:       double dtdivt;

69:       if (div < -g_small) {

70:         dtdivt = dtdiv_safe * (-1.0 / div);

71:       } else {

72:         dtdivt = g_big;

73:       }

74:       double mins = std::fmin(dtct, std::fmin(dtut, std::fmin(dtvt, std::fmin(dtdivt, g_big))));

75:       dt_min_val0 = std::fmin(mins, dt_min_val0);

0x23a6b0 PUSH	%RBP

0x23a6b1 MOV	%RSP,%RBP

0x23a6b4 PUSH	%R15

0x23a6b6 PUSH	%R14

0x23a6b8 PUSH	%R13

0x23a6ba PUSH	%R12

0x23a6bc PUSH	%RBX

0x23a6bd SUB	$0x68,%RSP

0x23a6c1 MOV	(%RDX),%R15D

0x23a6c4 MOV	(%RCX),%EBX

0x23a6c6 INC	%R15D

0x23a6c9 ADD	$0x2,%EBX

0x23a6cc SUB	%R15D,%EBX

0x23a6cf JLE	23abd5

0x23a6d5 MOV	(%R8),%R10D

0x23a6d8 MOV	(%R9),%R13D

0x23a6db INC	%R10D

0x23a6de ADD	$0x2,%R13D

0x23a6e2 CMP	%R10D,%R13D

0x23a6e5 JLE	23abd5

0x23a6eb SUB	%R10D,%R13D

0x23a6ee IMUL	%R13,%RBX

0x23a6f2 DEC	%RBX

0x23a6f5 MOVQ	$0,-0x48(%RBP)

0x23a6fd MOV	%RBX,-0x30(%RBP)

0x23a701 MOVQ	$0x1,-0x78(%RBP)

0x23a709 MOVL	$0,-0x40(%RBP)

0x23a710 MOV	(%RDI),%ESI

0x23a712 SUB	$0x8,%RSP

0x23a716 LEA	-0x78(%RBP),%RAX

0x23a71a LEA	0x24037(%RIP),%RDI

0x23a721 LEA	-0x40(%RBP),%RCX

0x23a725 LEA	-0x48(%RBP),%R8

0x23a729 LEA	-0x30(%RBP),%R9

0x23a72d MOV	%ESI,-0x3c(%RBP)

0x23a730 MOV	$0x22,%EDX

0x23a735 PUSH	$0x1

0x23a737 PUSH	$0x1

0x23a739 PUSH	%RAX

0x23a73a MOV	%R10D,%R12D

0x23a73d CALL	25ccf0 <@plt_start@+0x530>

0x23a742 ADD	$0x20,%RSP

0x23a746 MOV	-0x30(%RBP),%RAX

0x23a74a CMP	%RBX,%RAX

0x23a74d CMOVL	%RAX,%RBX

0x23a751 MOV	%RBX,-0x30(%RBP)

0x23a755 MOV	-0x48(%RBP),%R14

0x23a759 CMP	%RBX,%R14

0x23a75c JLE	23a801

0x23a762 MOVSD	-0x29683(%RIP),%XMM9

0x23a76b MOV	0x80(%RBP),%RBX

0x23a772 MOVSD	%XMM9,-0x38(%RBP)

0x23a778 LEA	0x23ff1(%RIP),%RDI

0x23a77f MOV	-0x3c(%RBP),%R14D

0x23a783 MOV	%R14D,%ESI

0x23a786 CALL	25cd00 <@plt_start@+0x540>

0x23a78b LEA	-0x38(%RBP),%RAX

0x23a78f MOV	%RAX,-0x70(%RBP)

0x23a793 SUB	$0x8,%RSP

0x23a797 LEA	0x27e92(%RIP),%RAX

0x23a79e LEA	0x23fe3(%RIP),%RDI

0x23a7a5 LEA	-0x11c(%RIP),%R9

0x23a7ac LEA	-0x70(%RBP),%R8

0x23a7b0 MOV	$0x8,%ECX

0x23a7b5 MOV	%R14D,%ESI

0x23a7b8 MOV	$0x1,%EDX

0x23a7bd PUSH	%RAX

0x23a7be CALL	25cd20 <@plt_start@+0x560>

0x23a7c3 ADD	$0x10,%RSP

0x23a7c7 CMP	$0x2,%EAX

0x23a7ca JE	23abb4

0x23a7d0 CMP	$0x1,%EAX

0x23a7d3 JNE	23abd5

0x23a7d9 MOVSD	(%RBX),%XMM0

0x23a7dd MINSD	-0x38(%RBP),%XMM0

0x23a7e2 MOVSD	%XMM0,(%RBX)

0x23a7e6 LEA	0x23f9b(%RIP),%RDI

0x23a7ed LEA	0x27e3c(%RIP),%RDX

0x23a7f4 MOV	%R14D,%ESI

0x23a7f7 CALL	25cd30 <@plt_start@+0x570>

0x23a7fc JMP	23abd5

0x23a801 MOV	0x78(%RBP),%R11

0x23a805 MOVSD	-0x29726(%RIP),%XMM9

0x23a80e XORPD	%XMM10,%XMM10

0x23a813 MOVSD	-0x296c4(%RIP),%XMM11

0x23a81c MOVAPD	-0x295a5(%RIP),%XMM12

0x23a825 MOVSD	-0x29766(%RIP),%XMM13

0x23a82e MOVSD	-0x2973f(%RIP),%XMM14

0x23a837 MOVSD	-0x29710(%RIP),%XMM15

0x23a840 MOV	%R12D,%R10D

0x23a843 MOV	%R13,-0x50(%RBP)

0x23a847 JMP	23ab02

0x23a84c NOPL	(%RAX)

(201) 0x23a850 MOV	%R14,-0x68(%RBP)

(201) 0x23a854 MOV	%R15D,%R13D

(201) 0x23a857 MOV	%R10D,%R15D

(201) 0x23a85a MOV	%R11,%R14

(201) 0x23a85d MOVSD	%XMM9,-0x60(%RBP)

(201) 0x23a863 MOVAPD	%XMM8,-0x90(%RBP)

(201) 0x23a86c MOVSD	%XMM6,-0x58(%RBP)

(201) 0x23a871 CALL	25cd40 <@plt_start@+0x580>

(201) 0x23a876 MOVSD	-0x58(%RBP),%XMM6

(201) 0x23a87b MOVAPD	-0x90(%RBP),%XMM8

(201) 0x23a884 MOVSD	-0x2975d(%RIP),%XMM15

(201) 0x23a88d MOVSD	-0x2979e(%RIP),%XMM14

(201) 0x23a896 MOVSD	-0x297d7(%RIP),%XMM13

(201) 0x23a89f MOVAPD	-0x29628(%RIP),%XMM12

(201) 0x23a8a8 MOVSD	-0x29759(%RIP),%XMM11

(201) 0x23a8b1 XORPD	%XMM10,%XMM10

(201) 0x23a8b6 MOVSD	-0x60(%RBP),%XMM9

(201) 0x23a8bc MOV	%R14,%R11

(201) 0x23a8bf MOV	%R15D,%R10D

(201) 0x23a8c2 MOV	%R13D,%R15D

(201) 0x23a8c5 MOV	-0x50(%RBP),%R13

(201) 0x23a8c9 MOV	-0x68(%RBP),%R14

(201) 0x23a8cd MOV	0x40(%RBP),%RAX

(201) 0x23a8d1 MOV	(%RAX),%RCX

(201) 0x23a8d4 MOV	0x10(%RAX),%RDX

(201) 0x23a8d8 MOV	%RCX,%RSI

(201) 0x23a8db IMUL	%R12,%RSI

(201) 0x23a8df LEA	(%RSI,%RBX,1),%RAX

(201) 0x23a8e3 MOVSD	(%RDX,%RAX,8),%XMM1

(201) 0x23a8e8 LEA	0x1(%R12),%EAX

(201) 0x23a8ed CLTQ

(201) 0x23a8ef IMUL	%RAX,%RCX

(201) 0x23a8f3 LEA	(%RCX,%RBX,1),%RDI

(201) 0x23a8f7 ADDSD	(%RDX,%RDI,8),%XMM1

(201) 0x23a8fc MOV	0x48(%RBP),%R8

(201) 0x23a900 MOV	0x10(%R8),%RDI

(201) 0x23a904 MOV	(%R8),%R8

(201) 0x23a907 IMUL	%R12,%R8

(201) 0x23a90b LEA	(%R8,%RBX,1),%R9

(201) 0x23a90f MULSD	(%RDI,%R9,8),%XMM1

(201) 0x23a915 ADD	%RBX,%RSI

(201) 0x23a918 INC	%RSI

(201) 0x23a91b MOVSD	(%RDX,%RSI,8),%XMM3

(201) 0x23a920 LEA	0x1(%RCX,%RBX,1),%RCX

(201) 0x23a925 ADDSD	(%RDX,%RCX,8),%XMM3

(201) 0x23a92a LEA	0x1(%R8,%RBX,1),%RCX

(201) 0x23a92f MULSD	(%RDI,%RCX,8),%XMM3

(201) 0x23a934 MOV	0x58(%RBP),%RDX

(201) 0x23a938 MOV	0x10(%RDX),%RCX

(201) 0x23a93c MOV	(%RDX),%RDX

(201) 0x23a93f IMUL	%R12,%RDX

(201) 0x23a943 ADD	%RBX,%RDX

(201) 0x23a946 MOVSD	(%RCX,%RDX,8),%XMM2

(201) 0x23a94b MOV	0x60(%RBP),%RDX

(201) 0x23a94f MOV	(%RDX),%RCX

(201) 0x23a952 MOV	0x10(%RDX),%RDX

(201) 0x23a956 MOV	%RCX,%RSI

(201) 0x23a959 IMUL	%R12,%RSI

(201) 0x23a95d LEA	(%RSI,%RBX,1),%RDI

(201) 0x23a961 MOVSD	(%RDX,%RDI,8),%XMM5

(201) 0x23a966 MOVAPD	%XMM6,%XMM4

(201) 0x23a96a CMPSD	$0x3,%XMM6,%XMM4

(201) 0x23a96f MOVAPD	%XMM4,%XMM7

(201) 0x23a973 ANDPD	%XMM8,%XMM7

(201) 0x23a978 MINSD	%XMM6,%XMM8

(201) 0x23a97d ADD	%RBX,%RSI

(201) 0x23a980 INC	%RSI

(201) 0x23a983 ADDSD	(%RDX,%RSI,8),%XMM5

(201) 0x23a988 IMUL	%RAX,%RCX

(201) 0x23a98c LEA	(%RCX,%RBX,1),%RSI

(201) 0x23a990 MOVSD	(%RDX,%RSI,8),%XMM6

(201) 0x23a995 ADD	%RBX,%RCX

(201) 0x23a998 INC	%RCX

(201) 0x23a99b ADDSD	(%RDX,%RCX,8),%XMM6

(201) 0x23a9a0 MOV	0x68(%RBP),%RDX

(201) 0x23a9a4 MOV	(%RDX),%RCX

(201) 0x23a9a7 MOV	0x10(%RDX),%RDX

(201) 0x23a9ab IMUL	%RCX,%R12

(201) 0x23a9af ADD	%RBX,%R12

(201) 0x23a9b2 MULSD	(%RDX,%R12,8),%XMM5

(201) 0x23a9b8 IMUL	%RAX,%RCX

(201) 0x23a9bc ADD	%RBX,%RCX

(201) 0x23a9bf MULSD	(%RDX,%RCX,8),%XMM6

(201) 0x23a9c4 ANDNPD	%XMM8,%XMM4

(201) 0x23a9c9 ORPD	%XMM7,%XMM4

(201) 0x23a9cd MOV	0x38(%RBP),%RAX

(201) 0x23a9d1 MULSD	(%RAX),%XMM4

(201) 0x23a9d5 MAXSD	%XMM11,%XMM0

(201) 0x23a9da DIVSD	%XMM0,%XMM4

(201) 0x23a9de MOVAPD	%XMM3,%XMM0

(201) 0x23a9e2 ADDSD	%XMM10,%XMM0

(201) 0x23a9e7 SUBSD	%XMM1,%XMM0

(201) 0x23a9eb ANDPD	%XMM12,%XMM1

(201) 0x23a9f0 ANDPD	%XMM12,%XMM3

(201) 0x23a9f5 MOVAPD	%XMM1,%XMM7

(201) 0x23a9f9 CMPSD	$0x3,%XMM1,%XMM7

(201) 0x23a9fe MOVAPD	%XMM7,%XMM8

(201) 0x23aa03 ANDPD	%XMM3,%XMM8

(201) 0x23aa08 MAXSD	%XMM1,%XMM3

(201) 0x23aa0c ANDNPD	%XMM3,%XMM7

(201) 0x23aa10 ORPD	%XMM8,%XMM7

(201) 0x23aa15 MOVAPD	%XMM2,%XMM3

(201) 0x23aa19 MULSD	%XMM11,%XMM3

(201) 0x23aa1e MOVAPD	%XMM3,%XMM1

(201) 0x23aa22 MAXSD	%XMM7,%XMM1

(201) 0x23aa26 CMPSD	$0x3,%XMM7,%XMM7

(201) 0x23aa2b MOVAPD	%XMM7,%XMM8

(201) 0x23aa30 ANDNPD	%XMM1,%XMM8

(201) 0x23aa35 MOV	0x50(%RBP),%RAX

(201) 0x23aa39 MOVSD	(%RAX),%XMM1

(201) 0x23aa3d ADDSD	%XMM1,%XMM1

(201) 0x23aa41 MULSD	%XMM2,%XMM1

(201) 0x23aa45 ANDPD	%XMM3,%XMM7

(201) 0x23aa49 ORPD	%XMM8,%XMM7

(201) 0x23aa4e DIVSD	%XMM7,%XMM1

(201) 0x23aa52 ADDSD	%XMM6,%XMM0

(201) 0x23aa56 SUBSD	%XMM5,%XMM0

(201) 0x23aa5a ANDPD	%XMM12,%XMM5

(201) 0x23aa5f ANDPD	%XMM12,%XMM6

(201) 0x23aa64 MOVAPD	%XMM5,%XMM7

(201) 0x23aa68 CMPSD	$0x3,%XMM5,%XMM7

(201) 0x23aa6d MOVAPD	%XMM7,%XMM8

(201) 0x23aa72 ANDPD	%XMM6,%XMM8

(201) 0x23aa77 MAXSD	%XMM5,%XMM6

(201) 0x23aa7b ANDNPD	%XMM6,%XMM7

(201) 0x23aa7f ORPD	%XMM8,%XMM7

(201) 0x23aa84 MOVAPD	%XMM3,%XMM5

(201) 0x23aa88 MAXSD	%XMM7,%XMM5

(201) 0x23aa8c CMPSD	$0x3,%XMM7,%XMM7

(201) 0x23aa91 MOVAPD	%XMM7,%XMM6

(201) 0x23aa95 ANDNPD	%XMM5,%XMM6

(201) 0x23aa99 ANDPD	%XMM3,%XMM7

(201) 0x23aa9d ORPD	%XMM6,%XMM7

(201) 0x23aaa1 MOV	0x70(%RBP),%RAX

(201) 0x23aaa5 MOVSD	(%RAX),%XMM3

(201) 0x23aaa9 ADDSD	%XMM3,%XMM3

(201) 0x23aaad MULSD	%XMM2,%XMM3

(201) 0x23aab1 DIVSD	%XMM7,%XMM3

(201) 0x23aab5 ADDSD	%XMM2,%XMM2

(201) 0x23aab9 DIVSD	%XMM2,%XMM0

(201) 0x23aabd MOVAPD	%XMM13,%XMM2

(201) 0x23aac2 DIVSD	%XMM0,%XMM2

(201) 0x23aac6 MULSD	(%R11),%XMM2

(201) 0x23aacb CMPSD	$0x1,%XMM14,%XMM0

(201) 0x23aad1 ANDPD	%XMM0,%XMM2

(201) 0x23aad5 ANDNPD	%XMM15,%XMM0

(201) 0x23aada ORPD	%XMM2,%XMM0

(201) 0x23aade MINSD	%XMM15,%XMM0

(201) 0x23aae3 MINSD	%XMM0,%XMM3

(201) 0x23aae7 MINSD	%XMM3,%XMM1

(201) 0x23aaeb MINSD	%XMM1,%XMM4

(201) 0x23aaef MINSD	%XMM4,%XMM9

(201) 0x23aaf4 CMP	-0x30(%RBP),%R14

(201) 0x23aaf8 LEA	0x1(%R14),%R14

(201) 0x23aafc JGE	23a76b

(201) 0x23ab02 MOV	%R14,%RAX

(201) 0x23ab05 SHR	$0x20,%RAX

(201) 0x23ab09 JE	23ab20

(201) 0x23ab0b MOV	%R14,%RAX

(201) 0x23ab0e CQTO

(201) 0x23ab10 IDIV	%R13

(201) 0x23ab13 JMP	23ab28

0x23ab15 NOPW	%CS:(%RAX,%RAX,1)

(201) 0x23ab20 MOV	%R14D,%EAX

(201) 0x23ab23 XOR	%EDX,%EDX

(201) 0x23ab25 DIV	%R13D

(201) 0x23ab28 ADD	%R15D,%EAX

(201) 0x23ab2b ADD	%R10D,%EDX

(201) 0x23ab2e MOVSXD	%EDX,%RBX

(201) 0x23ab31 MOV	0x10(%RBP),%RCX

(201) 0x23ab35 MOV	0x8(%RCX),%RCX

(201) 0x23ab39 MOVSD	(%RCX,%RBX,8),%XMM6

(201) 0x23ab3e MOVSXD	%EAX,%R12

(201) 0x23ab41 MOV	0x18(%RBP),%RAX

(201) 0x23ab45 MOV	0x8(%RAX),%RAX

(201) 0x23ab49 MOVSD	(%RAX,%R12,8),%XMM8

(201) 0x23ab4f MOV	0x20(%RBP),%RCX

(201) 0x23ab53 MOV	0x10(%RCX),%RAX

(201) 0x23ab57 MOV	(%RCX),%RCX

(201) 0x23ab5a IMUL	%R12,%RCX

(201) 0x23ab5e ADD	%RBX,%RCX

(201) 0x23ab61 MOVSD	(%RAX,%RCX,8),%XMM1

(201) 0x23ab66 MOV	0x28(%RBP),%RCX

(201) 0x23ab6a MOV	0x10(%RCX),%RAX

(201) 0x23ab6e MOV	(%RCX),%RCX

(201) 0x23ab71 IMUL	%R12,%RCX

(201) 0x23ab75 ADD	%RBX,%RCX

(201) 0x23ab78 MOVSD	(%RAX,%RCX,8),%XMM0

(201) 0x23ab7d ADDSD	%XMM0,%XMM0

(201) 0x23ab81 MOV	0x30(%RBP),%RCX

(201) 0x23ab85 MOV	0x10(%RCX),%RAX

(201) 0x23ab89 MOV	(%RCX),%RCX

(201) 0x23ab8c IMUL	%R12,%RCX

(201) 0x23ab90 ADD	%RBX,%RCX

(201) 0x23ab93 DIVSD	(%RAX,%RCX,8),%XMM0

(201) 0x23ab98 MULSD	%XMM1,%XMM1

(201) 0x23ab9c ADDSD	%XMM1,%XMM0

(201) 0x23aba0 UCOMISD	%XMM10,%XMM0

(201) 0x23aba5 JB	23a850

(201) 0x23abab SQRTSD	%XMM0,%XMM0

(201) 0x23abaf JMP	23a8cd

0x23abb4 MOV	(%RBX),%RAX

0x23abb7 MOVSD	-0x38(%RBP),%XMM0

0x23abbc NOPL	(%RAX)

(200) 0x23abc0 MOVQ	%RAX,%XMM1

(200) 0x23abc5 MINSD	%XMM0,%XMM1

(200) 0x23abc9 MOVQ	%XMM1,%RCX

(200) 0x23abce LOCK CMPXCHG	%RCX,(%RBX)

(200) 0x23abd3 JNE	23abc0

0x23abd5 ADD	$0x68,%RSP

0x23abd9 POP	%RBX

0x23abda POP	%R12

0x23abdc POP	%R13

0x23abde POP	%R14

0x23abe0 POP	%R15

0x23abe2 POP	%RBP

0x23abe3 RET

0x23abe4 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	calc_dt.cpp:49-75
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:49-75

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 13.38 to 3.00 cycles (4.46x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 9% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 13.38 to 1.01 cycles (13.25x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 4 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:49
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:49
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:49
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:49

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVL: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:50

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 152 bytes (19 double precision FP elements). The binary function is storing 72 bytes (9 double precision FP elements).

General properties

nb instructions	106
nb uops	107
loop length	466
used x86 registers	16
used mmx registers	0
used xmm registers	8
used ymm registers	0
used zmm registers	0
nb stack references	10

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	13.38 cycles
front end	13.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	8.17	8.17	8.17	8.17	8.17	8.17	8.75	8.75	8.75	8.75	0.00	0.00	0.50	0.50	1.00	1.00
cycles	8.17	8.17	8.17	8.17	8.17	8.17	8.75	8.75	8.75	8.75	0.00	0.00	0.50	0.50	1.00	1.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	13.38
Dispatch	8.75
Overall L1	13.38

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	15%
load	10%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	4%
load	5%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Vector efficiency ratios

INT

all	7%
load	8%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	14%
load	13%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

INT+FP

all	9%
load	11%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 13.38 cycles. At this rate:

4% of peak load performance is reached (11.36 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (5.38 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 13.38 to 8.75 cycles (1.53x speedup).

ASM code

In the binary file, the address of the function is: 23a6b0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x68,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RDX),%R15D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
MOV (%RCX),%EBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
INC %R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD $0x2,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %R15D,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
JLE 23abd5 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x525>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV (%R8),%R10D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
MOV (%R9),%R13D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
INC %R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD $0x2,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CMP %R10D,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 23abd5 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x525>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
SUB %R10D,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
IMUL %R13,%RBX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
DEC %RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVQ $0,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOV %RBX,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOVQ $0x1,-0x78(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOVL $0,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x78(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x24037(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x40(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x48(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x30(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %ESI,-0x3c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %R10D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 25ccf0 <@plt_start@+0x530>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x30(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
CMP %RBX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMOVL %RAX,%RBX	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %RBX,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV -0x48(%RBP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
CMP %RBX,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JLE 23a801 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x151>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOVSD -0x29683(%RIP),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x80(%RBP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVSD %XMM9,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
LEA 0x23ff1(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV -0x3c(%RBP),%R14D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 25cd00 <@plt_start@+0x540>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
LEA -0x38(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RAX,-0x70(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x27e92(%RIP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x23fe3(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x11c(%RIP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x70(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x8,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV $0x1,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 25cd20 <@plt_start@+0x560>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
ADD $0x10,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x2,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 23abb4 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x504>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x1,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JNE 23abd5 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x525>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOVSD (%RBX),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MINSD -0x38(%RBP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	2	0.50	scal (12.5%)
MOVSD %XMM0,(%RBX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
LEA 0x23f9b(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x27e3c(%RIP),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 25cd30 <@plt_start@+0x570>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
JMP 23abd5 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x525>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
MOV 0x78(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOVSD -0x29726(%RIP),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
XORPD %XMM10,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOVSD -0x296c4(%RIP),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MOVAPD -0x295a5(%RIP),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (25.0%)
MOVSD -0x29766(%RIP),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MOVSD -0x2973f(%RIP),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MOVSD -0x29710(%RIP),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MOV %R12D,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV %R13,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
JMP 23ab02 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x452>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV (%RBX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVSD -0x38(%RBP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0x68,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	calc_dt.cpp:49-75
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:49-75

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 13.38 to 3.00 cycles (4.46x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 4 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:49
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:49
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:49
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:49

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVL: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:50

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

General properties

nb instructions	106
nb uops	107
loop length	466
used x86 registers	16
used mmx registers	0
used xmm registers	8
used ymm registers	0
used zmm registers	0
nb stack references	10

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	13.38 cycles
front end	13.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	8.17	8.17	8.17	8.17	8.17	8.17	8.75	8.75	8.75	8.75	0.00	0.00	0.50	0.50	1.00	1.00
cycles	8.17	8.17	8.17	8.17	8.17	8.17	8.75	8.75	8.75	8.75	0.00	0.00	0.50	0.50	1.00	1.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	13.38
Dispatch	8.75
Overall L1	13.38

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	15%
load	10%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	4%
load	5%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Vector efficiency ratios

INT

all	7%
load	8%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	14%
load	13%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

INT+FP

all	9%
load	11%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 13.38 cycles. At this rate:

4% of peak load performance is reached (11.36 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (5.38 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 23a6b0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x68,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RDX),%R15D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
MOV (%RCX),%EBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
INC %R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD $0x2,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %R15D,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
JLE 23abd5 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x525>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV (%R8),%R10D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
MOV (%R9),%R13D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
INC %R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD $0x2,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CMP %R10D,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 23abd5 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x525>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
SUB %R10D,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
IMUL %R13,%RBX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
DEC %RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVQ $0,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOV %RBX,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOVQ $0x1,-0x78(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOVL $0,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x78(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x24037(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x40(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x48(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x30(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %ESI,-0x3c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %R10D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 25ccf0 <@plt_start@+0x530>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x30(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
CMP %RBX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMOVL %RAX,%RBX	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %RBX,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV -0x48(%RBP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
CMP %RBX,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JLE 23a801 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x151>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOVSD -0x29683(%RIP),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x80(%RBP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVSD %XMM9,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
LEA 0x23ff1(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV -0x3c(%RBP),%R14D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 25cd00 <@plt_start@+0x540>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
LEA -0x38(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RAX,-0x70(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x27e92(%RIP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x23fe3(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x11c(%RIP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x70(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x8,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV $0x1,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 25cd20 <@plt_start@+0x560>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
ADD $0x10,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x2,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 23abb4 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x504>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x1,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JNE 23abd5 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x525>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOVSD (%RBX),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MINSD -0x38(%RBP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	2	0.50	scal (12.5%)
MOVSD %XMM0,(%RBX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
LEA 0x23f9b(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x27e3c(%RIP),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 25cd30 <@plt_start@+0x570>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
JMP 23abd5 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x525>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
MOV 0x78(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOVSD -0x29726(%RIP),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
XORPD %XMM10,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOVSD -0x296c4(%RIP),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MOVAPD -0x295a5(%RIP),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (25.0%)
MOVSD -0x29766(%RIP),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MOVSD -0x2973f(%RIP),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MOVSD -0x29710(%RIP),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MOV %R12D,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV %R13,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
JMP 23ab02 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x452>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV (%RBX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVSD -0x38(%RBP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0x68,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼calc_dt_kernel(int, int, int, int, double, double, double, double, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D–	3.04	1.19
○Loop 201 - calc_dt.cpp:49-75 - exec	3.04	1.19
○Loop 200 - calc_dt.cpp:49-49 - exec	0.00	0.00

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