OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone .omp

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: advec_mom.cpp:180-211 [...]	Coverage (incl. loops): 5.84% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 180 - 211

--------------------------------------------------------------------------------

180: #pragma omp parallel for simd collapse(2)

181:     for (int j = (y_min - 1 + 1); j < (y_max + 1 + 2); j++) {

182:       for (int i = (x_min + 1); i < (x_max + 1 + 2); i++)

183:         ({

184:           int upwind, donor, downwind, dif;

185:           double sigma, width, limiter, vdiffuw, vdiffdw, auw, adw, wind, advec_vel_s;

186:           if (node_flux(i, j) < 0.0) {

187:             upwind = j + 2;

188:             donor = j + 1;

189:             downwind = j;

190:             dif = donor;

191:           } else {

192:             upwind = j - 1;

193:             donor = j;

194:             downwind = j + 1;

195:             dif = upwind;

196:           }

197:           sigma = std::fabs(node_flux(i, j)) / (node_mass_pre(i, donor));

198:           width = celldy[j];

199:           vdiffuw = vel1(i, donor) - vel1(i, upwind);

200:           vdiffdw = vel1(i, downwind) - vel1(i, donor);

201:           limiter = 0.0;

202:           if (vdiffuw * vdiffdw > 0.0) {

203:             auw = std::fabs(vdiffuw);

204:             adw = std::fabs(vdiffdw);

205:             wind = 1.0;

206:             if (vdiffdw <= 0.0) wind = -1.0;

207:             limiter =

208:                 wind * std::fmin(std::fmin(width * ((2.0 - sigma) * adw / width + (1.0 + sigma) * auw / celldy[dif]) / 6.0, auw), adw);

209:           }

210:           advec_vel_s = vel1(i, donor) + (1.0 - sigma) * limiter;

211:           mom_flux(i, j) = advec_vel_s * node_flux(i, j);

0x237410 PUSH	%RBP

0x237411 MOV	%RSP,%RBP

0x237414 PUSH	%R15

0x237416 PUSH	%R14

0x237418 PUSH	%R13

0x23741a PUSH	%R12

0x23741c PUSH	%RBX

0x23741d SUB	$0x168,%RSP

0x237424 MOV	(%RDX),%EBX

0x237426 MOV	(%RCX),%R14D

0x237429 ADD	$0x3,%R14D

0x23742d SUB	%EBX,%R14D

0x237430 JLE	237d90

0x237436 MOV	(%R8),%R15D

0x237439 MOV	(%R9),%EAX

0x23743c INC	%R15D

0x23743f ADD	$0x3,%EAX

0x237442 CMP	%R15D,%EAX

0x237445 JLE	237d90

0x23744b SUB	%R15D,%EAX

0x23744e MOV	%RAX,-0x30(%RBP)

0x237452 IMUL	%RAX,%R14

0x237456 DEC	%R14

0x237459 MOVQ	$0,-0xd8(%RBP)

0x237464 MOV	%R14,-0x38(%RBP)

0x237468 MOVQ	$0x1,-0x110(%RBP)

0x237473 MOVL	$0,-0x44(%RBP)

0x23747a MOV	(%RDI),%ESI

0x23747c SUB	$0x8,%RSP

0x237480 LEA	-0x110(%RBP),%RAX

0x237487 LEA	0x26ffa(%RIP),%RDI

0x23748e LEA	-0x44(%RBP),%RCX

0x237492 LEA	-0xd8(%RBP),%R8

0x237499 LEA	-0x38(%RBP),%R9

0x23749d MOV	%ESI,-0x3c(%RBP)

0x2374a0 MOV	$0x22,%EDX

0x2374a5 PUSH	$0x1

0x2374a7 PUSH	$0x1

0x2374a9 PUSH	%RAX

0x2374aa CALL	25ccf0 <@plt_start@+0x530>

0x2374af ADD	$0x20,%RSP

0x2374b3 MOV	-0x38(%RBP),%RAX

0x2374b7 CMP	%R14,%RAX

0x2374ba CMOVL	%RAX,%R14

0x2374be MOV	%R14,-0x38(%RBP)

0x2374c2 MOV	-0xd8(%RBP),%RSI

0x2374c9 CMP	%R14,%RSI

0x2374cc JG	237d81

0x2374d2 MOV	0x30(%RBP),%RAX

0x2374d6 MOV	0x28(%RBP),%RCX

0x2374da MOV	0x20(%RBP),%RDX

0x2374de MOV	0x18(%RBP),%RDI

0x2374e2 MOV	0x10(%RBP),%R8

0x2374e6 MOV	(%R8),%R12

0x2374e9 MOV	0x10(%R8),%R13

0x2374ed MOV	(%RDI),%R8

0x2374f0 MOV	%R8,-0xd0(%RBP)

0x2374f7 MOV	0x10(%RDI),%RDI

0x2374fb MOV	%RDI,-0xc8(%RBP)

0x237502 MOV	(%RCX),%RDI

0x237505 MOV	%RDI,-0xb0(%RBP)

0x23750c MOV	0x10(%RCX),%RCX

0x237510 MOV	%RCX,-0xa8(%RBP)

0x237517 MOV	0x8(%RDX),%RCX

0x23751b MOV	%RCX,-0x90(%RBP)

0x237522 MOV	(%RAX),%RCX

0x237525 MOV	%RCX,-0xc0(%RBP)

0x23752c MOV	0x10(%RAX),%RAX

0x237530 MOV	%RAX,-0xb8(%RBP)

0x237537 MOV	%R14,%RAX

0x23753a SUB	%RSI,%RAX

0x23753d INC	%RAX

0x237540 CMP	$0x4,%RAX

0x237544 JAE	23754e

0x237546 MOV	%RSI,%RAX

0x237549 JMP	237da2

0x23754e MOV	%R13,-0x80(%RBP)

0x237552 MOV	%R12,-0x88(%RBP)

0x237559 MOV	%RAX,-0x100(%RBP)

0x237560 MOV	%RAX,%RCX

0x237563 AND	$-0x4,%RCX

0x237567 LEA	(%RSI,%RCX,1),%RAX

0x23756b MOV	%RAX,-0x68(%RBP)

0x23756f XORPD	%XMM5,%XMM5

0x237573 MOV	%RCX,-0xf8(%RBP)

0x23757a MOV	%R14,-0x70(%RBP)

0x23757e MOV	%RBX,-0x78(%RBP)

0x237582 MOV	%R15D,-0x40(%RBP)

0x237586 JMP	23774d

0x23758b NOPL	(%RAX,%RAX,1)

(180) 0x237590 PSHUFD	$0x55,-0x170(%RBP),%XMM12

(180) 0x23759a MOVD	%XMM12,%ECX

(180) 0x23759f MOVSXD	%ECX,%RCX

(180) 0x2375a2 MOVAPD	-0x120(%RBP),%XMM12

(180) 0x2375ab MOVHPD	(%RDX,%RCX,8),%XMM12

(180) 0x2375b1 MOV	-0x70(%RBP),%R14

(180) 0x2375b5 DIVPD	%XMM12,%XMM8

(180) 0x2375ba ADDPD	%XMM8,%XMM3

(180) 0x2375bf DIVPD	-0x60(%RBP),%XMM6

(180) 0x2375c4 ADDPD	%XMM6,%XMM13

(180) 0x2375c9 MULPD	%XMM13,%XMM0

(180) 0x2375ce MULPD	%XMM3,%XMM1

(180) 0x2375d2 MOVAPD	-0x2623a(%RIP),%XMM6

(180) 0x2375da DIVPD	%XMM6,%XMM0

(180) 0x2375de MOVAPD	%XMM9,%XMM3

(180) 0x2375e3 MINPD	%XMM0,%XMM3

(180) 0x2375e7 CMPPD	$0x3,%XMM0,%XMM0

(180) 0x2375ec ANDPD	%XMM0,%XMM9

(180) 0x2375f1 ANDNPD	%XMM3,%XMM0

(180) 0x2375f5 DIVPD	%XMM6,%XMM1

(180) 0x2375f9 ORPD	%XMM9,%XMM0

(180) 0x2375fe MOVAPD	%XMM10,%XMM3

(180) 0x237603 MINPD	%XMM1,%XMM3

(180) 0x237607 CMPPD	$0x3,%XMM1,%XMM1

(180) 0x23760c ANDPD	%XMM1,%XMM10

(180) 0x237611 ANDNPD	%XMM3,%XMM1

(180) 0x237615 ORPD	%XMM10,%XMM1

(180) 0x23761a MOVAPD	%XMM15,%XMM3

(180) 0x23761f MINPD	%XMM0,%XMM3

(180) 0x237623 CMPPD	$0x3,%XMM0,%XMM0

(180) 0x237628 ANDPD	%XMM0,%XMM15

(180) 0x23762d ANDNPD	%XMM3,%XMM0

(180) 0x237631 ORPD	%XMM15,%XMM0

(180) 0x237636 MOVAPD	%XMM14,%XMM3

(180) 0x23763b MINPD	%XMM1,%XMM3

(180) 0x23763f CMPPD	$0x3,%XMM1,%XMM1

(180) 0x237644 ANDPD	%XMM1,%XMM14

(180) 0x237649 ANDNPD	%XMM3,%XMM1

(180) 0x23764d XORPD	%XMM8,%XMM8

(180) 0x237652 CMPPD	$0x6,%XMM8,%XMM2

(180) 0x237658 ORPD	%XMM14,%XMM1

(180) 0x23765d MOVAPD	%XMM0,%XMM3

(180) 0x237661 MOVAPD	-0x262b9(%RIP),%XMM6

(180) 0x237669 XORPD	%XMM6,%XMM3

(180) 0x23766d ANDPD	%XMM2,%XMM0

(180) 0x237671 ANDNPD	%XMM3,%XMM2

(180) 0x237675 CMPPD	$0x6,%XMM8,%XMM7

(180) 0x23767b ORPD	%XMM0,%XMM2

(180) 0x23767f MOVAPD	%XMM1,%XMM0

(180) 0x237683 XORPD	%XMM6,%XMM0

(180) 0x237687 ANDPD	%XMM7,%XMM1

(180) 0x23768b ANDNPD	%XMM0,%XMM7

(180) 0x23768f ORPD	%XMM1,%XMM7

(180) 0x237693 MOVAPD	-0x180(%RBP),%XMM3

(180) 0x23769b ANDPD	%XMM2,%XMM3

(180) 0x23769f ANDPD	%XMM7,%XMM4

(180) 0x2376a3 MOVAPD	-0x2633b(%RIP),%XMM1

(180) 0x2376ab MOVAPD	%XMM1,%XMM0

(180) 0x2376af SUBPD	%XMM5,%XMM0

(180) 0x2376b3 MULPD	%XMM3,%XMM0

(180) 0x2376b7 SUBPD	%XMM11,%XMM1

(180) 0x2376bc MULPD	%XMM4,%XMM1

(180) 0x2376c0 ADDPD	-0x190(%RBP),%XMM0

(180) 0x2376c8 ADDPD	-0xf0(%RBP),%XMM1

(180) 0x2376d0 MOVAPD	-0x160(%RBP),%XMM2

(180) 0x2376d8 MULPD	%XMM0,%XMM2

(180) 0x2376dc MOVAPD	-0x150(%RBP),%XMM0

(180) 0x2376e4 MULPD	%XMM1,%XMM0

(180) 0x2376e8 MOV	-0xc0(%RBP),%RCX

(180) 0x2376ef MOV	-0xa0(%RBP),%R15

(180) 0x2376f6 IMUL	%RCX,%R15

(180) 0x2376fa IMUL	%RCX,%R9

(180) 0x2376fe ADD	%R13,%R15

(180) 0x237701 ADD	%R12,%R9

(180) 0x237704 MOV	-0xb8(%RBP),%RDX

(180) 0x23770b MOVLPD	%XMM2,(%RDX,%R15,8)

(180) 0x237711 MOVHPD	%XMM2,(%RDX,%R9,8)

(180) 0x237717 IMUL	%RCX,%R11

(180) 0x23771b IMUL	%RCX,%RDI

(180) 0x23771f ADD	%R8,%R11

(180) 0x237722 ADD	%R10,%RDI

(180) 0x237725 MOVLPD	%XMM0,(%RDX,%R11,8)

(180) 0x23772b MOVHPD	%XMM0,(%RDX,%RDI,8)

(180) 0x237730 ADD	$0x4,%RSI

(180) 0x237734 MOV	-0x108(%RBP),%RCX

(180) 0x23773b ADD	$-0x4,%RCX

(180) 0x23773f MOV	-0x40(%RBP),%R15D

(180) 0x237743 XORPD	%XMM5,%XMM5

(180) 0x237747 JE	237d66

(180) 0x23774d MOV	%RSI,%RAX

(180) 0x237750 SHR	$0x20,%RAX

(180) 0x237754 MOV	-0x30(%RBP),%R11

(180) 0x237758 MOV	%RCX,-0x108(%RBP)

(180) 0x23775f JE	2377b0

(180) 0x237761 MOV	%RSI,%RAX

(180) 0x237764 CQTO

(180) 0x237766 IDIV	%R11

(180) 0x237769 MOV	%RDX,%R8

(180) 0x23776c MOV	%RAX,%RDI

(180) 0x23776f LEA	0x1(%RSI),%RAX

(180) 0x237773 MOV	%RAX,%RCX

(180) 0x237776 SHR	$0x20,%RCX

(180) 0x23777a JE	2377c9

(180) 0x23777c CQTO

(180) 0x23777e IDIV	%R11

(180) 0x237781 MOV	%RDX,%R10

(180) 0x237784 MOV	%RAX,%R9

(180) 0x237787 LEA	0x2(%RSI),%RAX

(180) 0x23778b MOV	%RAX,%RCX

(180) 0x23778e SHR	$0x20,%RCX

(180) 0x237792 JE	2377e1

(180) 0x237794 CQTO

(180) 0x237796 IDIV	%R11

(180) 0x237799 MOV	%RDX,%R14

(180) 0x23779c MOV	%RAX,%R11

(180) 0x23779f JMP	2377ec

0x2377a1 NOPW	%CS:(%RAX,%RAX,1)

(180) 0x2377b0 MOV	%ESI,%EAX

(180) 0x2377b2 XOR	%EDX,%EDX

(180) 0x2377b4 DIV	%R11D

(180) 0x2377b7 MOV	%EDX,%R8D

(180) 0x2377ba MOV	%EAX,%EDI

(180) 0x2377bc LEA	0x1(%RSI),%RAX

(180) 0x2377c0 MOV	%RAX,%RCX

(180) 0x2377c3 SHR	$0x20,%RCX

(180) 0x2377c7 JNE	23777c

(180) 0x2377c9 XOR	%EDX,%EDX

(180) 0x2377cb DIV	%R11D

(180) 0x2377ce MOV	%EDX,%R10D

(180) 0x2377d1 MOV	%EAX,%R9D

(180) 0x2377d4 LEA	0x2(%RSI),%RAX

(180) 0x2377d8 MOV	%RAX,%RCX

(180) 0x2377db SHR	$0x20,%RCX

(180) 0x2377df JNE	237794

(180) 0x2377e1 XOR	%EDX,%EDX

(180) 0x2377e3 DIV	%R11D

(180) 0x2377e6 MOV	%EDX,%R14D

(180) 0x2377e9 MOV	%EAX,%R11D

(180) 0x2377ec LEA	0x3(%RSI),%RAX

(180) 0x2377f0 MOV	%RAX,%RCX

(180) 0x2377f3 SHR	$0x20,%RCX

(180) 0x2377f7 MOV	%RSI,-0x98(%RBP)

(180) 0x2377fe JE	237810

(180) 0x237800 CQTO

(180) 0x237802 IDIVQ	-0x30(%RBP)

(180) 0x237806 JMP	237815

0x237808 NOPL	(%RAX,%RAX,1)

(180) 0x237810 XOR	%EDX,%EDX

(180) 0x237812 DIVL	-0x30(%RBP)

(180) 0x237815 ADD	%EBX,%EDI

(180) 0x237817 ADD	%EBX,%R9D

(180) 0x23781a MOVD	%R9D,%XMM0

(180) 0x23781f MOVD	%EDI,%XMM1

(180) 0x237823 PUNPCKLDQ	%XMM0,%XMM1

(180) 0x237827 ADD	%EBX,%R11D

(180) 0x23782a ADD	%EBX,%EAX

(180) 0x23782c MOVD	%EAX,%XMM2

(180) 0x237830 MOVD	%R11D,%XMM0

(180) 0x237835 PUNPCKLDQ	%XMM2,%XMM0

(180) 0x237839 ADD	%R15D,%R8D

(180) 0x23783c ADD	%R15D,%R10D

(180) 0x23783f ADD	%R15D,%R14D

(180) 0x237842 ADD	%R15D,%EDX

(180) 0x237845 MOVSXD	%R8D,%R15

(180) 0x237848 MOVSXD	%R10D,%RSI

(180) 0x23784b MOVSXD	%R14D,%R12

(180) 0x23784e MOVSXD	%EDX,%R13

(180) 0x237851 MOVSXD	%EDI,%RDX

(180) 0x237854 MOVSXD	%R9D,%R9

(180) 0x237857 MOVQ	%R9,%XMM2

(180) 0x23785c MOVQ	%RDX,%XMM4

(180) 0x237861 PUNPCKLQDQ	%XMM2,%XMM4

(180) 0x237865 MOVSXD	%R11D,%R10

(180) 0x237868 MOVSXD	%EAX,%RDI

(180) 0x23786b MOVQ	%RDI,%XMM2

(180) 0x237870 MOVQ	%R10,%XMM8

(180) 0x237875 PUNPCKLQDQ	%XMM2,%XMM8

(180) 0x23787a MOV	-0x88(%RBP),%R14

(180) 0x237881 MOV	%R14,%RCX

(180) 0x237884 MOV	%RDX,%RAX

(180) 0x237887 MOV	%RDX,-0xa0(%RBP)

(180) 0x23788e IMUL	%RDX,%RCX

(180) 0x237892 MOV	%R14,%R8

(180) 0x237895 MOV	%R9,-0xf0(%RBP)

(180) 0x23789c IMUL	%R9,%R8

(180) 0x2378a0 MOV	%R14,%RBX

(180) 0x2378a3 MOV	%R10,-0x60(%RBP)

(180) 0x2378a7 IMUL	%R10,%RBX

(180) 0x2378ab IMUL	%RDI,%R14

(180) 0x2378af ADD	%R15,%RCX

(180) 0x2378b2 MOV	%R15,%R11

(180) 0x2378b5 ADD	%RSI,%R8

(180) 0x2378b8 MOV	%RSI,%R9

(180) 0x2378bb ADD	%R12,%RBX

(180) 0x2378be MOV	-0x80(%RBP),%RDX

(180) 0x2378c2 MOVSD	(%RDX,%RCX,8),%XMM13

(180) 0x2378c8 MOVHPD	(%RDX,%R8,8),%XMM13

(180) 0x2378ce ADD	%R13,%R14

(180) 0x2378d1 MOVSD	(%RDX,%RBX,8),%XMM7

(180) 0x2378d6 MOVHPD	(%RDX,%R14,8),%XMM7

(180) 0x2378dc MOVAPD	%XMM13,-0x160(%RBP)

(180) 0x2378e5 CMPPD	$0x1,%XMM5,%XMM13

(180) 0x2378eb MOVAPD	%XMM13,%XMM3

(180) 0x2378f0 MOVAPD	%XMM7,-0x150(%RBP)

(180) 0x2378f8 CMPPD	$0x1,%XMM5,%XMM7

(180) 0x2378fd MOVAPD	%XMM7,%XMM6

(180) 0x237901 MOVDQA	%XMM1,%XMM15

(180) 0x237906 PCMPEQD	%XMM14,%XMM14

(180) 0x23790b PSUBD	%XMM14,%XMM15

(180) 0x237910 MOVDQA	%XMM0,%XMM12

(180) 0x237915 PSUBD	%XMM14,%XMM12

(180) 0x23791a PXOR	%XMM2,%XMM2

(180) 0x23791e PCMPGTD	%XMM15,%XMM2

(180) 0x237923 MOVDQA	%XMM15,%XMM10

(180) 0x237928 PUNPCKLDQ	%XMM2,%XMM10

(180) 0x23792d PXOR	%XMM2,%XMM2

(180) 0x237931 PCMPGTD	%XMM12,%XMM2

(180) 0x237936 MOVDQA	%XMM12,%XMM9

(180) 0x23793b PUNPCKLDQ	%XMM2,%XMM9

(180) 0x237940 MOVAPD	%XMM13,%XMM5

(180) 0x237945 ANDNPD	%XMM10,%XMM5

(180) 0x23794a MOVDQA	%XMM4,%XMM2

(180) 0x23794e PAND	%XMM13,%XMM2

(180) 0x237953 PAND	%XMM13,%XMM10

(180) 0x237958 PANDN	%XMM4,%XMM13

(180) 0x23795d MOVAPD	%XMM7,%XMM11

(180) 0x237962 ANDNPD	%XMM9,%XMM11

(180) 0x237967 POR	%XMM10,%XMM13

(180) 0x23796c MOVDQA	%XMM8,%XMM4

(180) 0x237971 PAND	%XMM7,%XMM4

(180) 0x237975 PAND	%XMM7,%XMM9

(180) 0x23797a PANDN	%XMM8,%XMM7

(180) 0x23797f POR	%XMM9,%XMM7

(180) 0x237984 MOVQ	%XMM13,%R14

(180) 0x237989 MOV	%R14,%R8

(180) 0x23798c MOV	-0xd0(%RBP),%R15

(180) 0x237993 IMUL	%R15,%R8

(180) 0x237997 PSHUFD	$0x4e,%XMM13,%XMM8

(180) 0x23799d MOVQ	%XMM8,%RDX

(180) 0x2379a2 MOV	%RDX,%RCX

(180) 0x2379a5 IMUL	%R15,%RCX

(180) 0x2379a9 MOVQ	%XMM7,%R10

(180) 0x2379ae ADD	%R11,%R8

(180) 0x2379b1 MOV	-0xc8(%RBP),%RSI

(180) 0x2379b8 MOVSD	(%RSI,%R8,8),%XMM8

(180) 0x2379be MOV	%R10,%RBX

(180) 0x2379c1 IMUL	%R15,%RBX

(180) 0x2379c5 PSHUFD	$0x4e,%XMM7,%XMM7

(180) 0x2379ca ADD	%R9,%RCX

(180) 0x2379cd MOVHPS	(%RSI,%RCX,8),%XMM8

(180) 0x2379d2 MOVAPS	%XMM8,-0x140(%RBP)

(180) 0x2379da MOVQ	%XMM7,%R8

(180) 0x2379df ADD	%R12,%RBX

(180) 0x2379e2 MOVSD	(%RSI,%RBX,8),%XMM7

(180) 0x2379e7 MOV	%R8,%RCX

(180) 0x2379ea IMUL	%R15,%RCX

(180) 0x2379ee ADD	%R13,%RCX

(180) 0x2379f1 MOVHPS	(%RSI,%RCX,8),%XMM7

(180) 0x2379f5 MOVAPS	%XMM7,-0x130(%RBP)

(180) 0x2379fc MOV	-0xb0(%RBP),%RAX

(180) 0x237a03 IMUL	%RAX,%R14

(180) 0x237a07 ADD	%R11,%R14

(180) 0x237a0a MOV	-0xa8(%RBP),%RSI

(180) 0x237a11 MOVSD	(%RSI,%R14,8),%XMM10

(180) 0x237a17 IMUL	%RAX,%RDX

(180) 0x237a1b ADD	%R9,%RDX

(180) 0x237a1e MOVHPD	(%RSI,%RDX,8),%XMM10

(180) 0x237a24 SHUFPS	$-0x18,%XMM3,%XMM3

(180) 0x237a28 SHUFPS	$-0x18,%XMM6,%XMM6

(180) 0x237a2c MOVDQA	%XMM1,%XMM7

(180) 0x237a30 PADDD	%XMM14,%XMM7

(180) 0x237a35 POR	%XMM5,%XMM2

(180) 0x237a39 MOVDQA	%XMM0,%XMM5

(180) 0x237a3d PADDD	%XMM14,%XMM5

(180) 0x237a42 MOVDQA	-0x267ab(%RIP),%XMM8

(180) 0x237a4b PADDD	%XMM8,%XMM1

(180) 0x237a50 PADDD	%XMM8,%XMM0

(180) 0x237a55 POR	%XMM11,%XMM4

(180) 0x237a5a MOVAPS	%XMM3,%XMM8

(180) 0x237a5e ANDNPS	%XMM7,%XMM8

(180) 0x237a62 MOVAPS	%XMM6,%XMM14

(180) 0x237a66 ANDNPS	%XMM5,%XMM14

(180) 0x237a6a PAND	%XMM3,%XMM1

(180) 0x237a6e POR	%XMM8,%XMM1

(180) 0x237a73 PAND	%XMM6,%XMM0

(180) 0x237a77 IMUL	%RAX,%R10

(180) 0x237a7b IMUL	%RAX,%R8

(180) 0x237a7f ADD	%R12,%R10

(180) 0x237a82 ADD	%R13,%R8

(180) 0x237a85 MOVSD	(%RSI,%R10,8),%XMM13

(180) 0x237a8b MOV	%R13,%R10

(180) 0x237a8e MOV	%R11,%R13

(180) 0x237a91 MOVHPD	(%RSI,%R8,8),%XMM13

(180) 0x237a97 MOV	%R12,%R8

(180) 0x237a9a MOV	%R9,%R12

(180) 0x237a9d POR	%XMM14,%XMM0

(180) 0x237aa2 MOVD	%XMM1,%ECX

(180) 0x237aa6 MOVSXD	%ECX,%RCX

(180) 0x237aa9 PSHUFD	$0x55,%XMM1,%XMM1

(180) 0x237aae MOVD	%XMM1,%EDX

(180) 0x237ab2 MOVSXD	%EDX,%RDX

(180) 0x237ab5 IMUL	%RAX,%RCX

(180) 0x237ab9 ADD	%R11,%RCX

(180) 0x237abc MOVSD	(%RSI,%RCX,8),%XMM1

(180) 0x237ac1 MOVD	%XMM0,%ECX

(180) 0x237ac5 MOVSXD	%ECX,%RCX

(180) 0x237ac8 PSHUFD	$0x55,%XMM0,%XMM0

(180) 0x237acd IMUL	%RAX,%RDX

(180) 0x237ad1 ADD	%R9,%RDX

(180) 0x237ad4 MOVHPD	(%RSI,%RDX,8),%XMM1

(180) 0x237ad9 MOVD	%XMM0,%EDX

(180) 0x237add MOVSXD	%EDX,%RDX

(180) 0x237ae0 IMUL	%RAX,%RCX

(180) 0x237ae4 IMUL	%RAX,%RDX

(180) 0x237ae8 ADD	%R8,%RCX

(180) 0x237aeb ADD	%R10,%RDX

(180) 0x237aee MOVAPD	%XMM10,%XMM9

(180) 0x237af3 SUBPD	%XMM1,%XMM9

(180) 0x237af8 MOVSD	(%RSI,%RCX,8),%XMM1

(180) 0x237afd MOVHPD	(%RSI,%RDX,8),%XMM1

(180) 0x237b02 MOVQ	%XMM2,%RCX

(180) 0x237b07 IMUL	%RAX,%RCX

(180) 0x237b0b PSHUFD	$0x4e,%XMM2,%XMM0

(180) 0x237b10 MOVQ	%XMM0,%RDX

(180) 0x237b15 IMUL	%RAX,%RDX

(180) 0x237b19 ADD	%R11,%RCX

(180) 0x237b1c MOVSD	(%RSI,%RCX,8),%XMM2

(180) 0x237b21 MOVQ	%XMM4,%RCX

(180) 0x237b26 IMUL	%RAX,%RCX

(180) 0x237b2a PSHUFD	$0x4e,%XMM4,%XMM0

(180) 0x237b2f ADD	%R9,%RDX

(180) 0x237b32 MOVHPD	(%RSI,%RDX,8),%XMM2

(180) 0x237b37 MOVQ	%XMM0,%RDX

(180) 0x237b3c ADD	%R8,%RCX

(180) 0x237b3f MOVSD	(%RSI,%RCX,8),%XMM7

(180) 0x237b44 IMUL	%RAX,%RDX

(180) 0x237b48 ADD	%R10,%RDX

(180) 0x237b4b MOVHPD	(%RSI,%RDX,8),%XMM7

(180) 0x237b50 SUBPD	%XMM10,%XMM2

(180) 0x237b55 MOVAPD	%XMM9,%XMM11

(180) 0x237b5a MULPD	%XMM2,%XMM11

(180) 0x237b5f XORPS	%XMM5,%XMM5

(180) 0x237b62 UCOMISD	%XMM5,%XMM11

(180) 0x237b67 MOV	-0x90(%RBP),%RDX

(180) 0x237b6e JBE	237b7c

(180) 0x237b70 MOV	-0xa0(%RBP),%RAX

(180) 0x237b77 MOVSD	(%RDX,%RAX,8),%XMM0

(180) 0x237b7c PXOR	%XMM4,%XMM4

(180) 0x237b80 CMPPD	$0x1,%XMM11,%XMM4

(180) 0x237b86 MOVAPD	%XMM4,-0x180(%RBP)

(180) 0x237b8e PEXTRW	$0x4,%XMM4,%EBX

(180) 0x237b93 TEST	$0x1,%BL

(180) 0x237b96 MOVAPD	%XMM10,-0x190(%RBP)

(180) 0x237b9f JE	237bc0

(180) 0x237ba1 MOV	-0xf0(%RBP),%R9

(180) 0x237ba8 MOVHPD	(%RDX,%R9,8),%XMM0

(180) 0x237bae MOV	-0x68(%RBP),%RAX

(180) 0x237bb2 MOV	-0x98(%RBP),%RSI

(180) 0x237bb9 JMP	237bd2

0x237bbb NOPL	(%RAX,%RAX,1)

(180) 0x237bc0 MOV	-0x68(%RBP),%RAX

(180) 0x237bc4 MOV	-0x98(%RBP),%RSI

(180) 0x237bcb MOV	-0xf0(%RBP),%R9

(180) 0x237bd2 MOV	-0x60(%RBP),%R11

(180) 0x237bd6 MOVAPD	%XMM13,%XMM10

(180) 0x237bdb SUBPD	%XMM1,%XMM10

(180) 0x237be0 MOVAPD	%XMM13,-0xf0(%RBP)

(180) 0x237be9 SUBPD	%XMM13,%XMM7

(180) 0x237bee MOVAPD	%XMM10,%XMM13

(180) 0x237bf3 MULPD	%XMM7,%XMM13

(180) 0x237bf8 UCOMISD	%XMM5,%XMM13

(180) 0x237bfd JBE	237c05

(180) 0x237bff MOVSD	(%RDX,%R11,8),%XMM1

(180) 0x237c05 XORPD	%XMM4,%XMM4

(180) 0x237c09 CMPPD	$0x1,%XMM13,%XMM4

(180) 0x237c0f PEXTRW	$0x4,%XMM4,%R14D

(180) 0x237c15 TEST	$0x1,%R14B

(180) 0x237c19 JE	237c20

(180) 0x237c1b MOVHPD	(%RDX,%RDI,8),%XMM1

(180) 0x237c20 PAND	%XMM3,%XMM15

(180) 0x237c25 POR	%XMM8,%XMM15

(180) 0x237c2a UCOMISD	%XMM5,%XMM11

(180) 0x237c2f JBE	237c50

(180) 0x237c31 MOVD	%XMM15,%ECX

(180) 0x237c36 MOVSXD	%ECX,%RCX

(180) 0x237c39 MOVSD	(%RDX,%RCX,8),%XMM8

(180) 0x237c3f TEST	$0x1,%BL

(180) 0x237c42 JNE	237c55

(180) 0x237c44 JMP	237c67

0x237c46 NOPW	%CS:(%RAX,%RAX,1)

(180) 0x237c50 TEST	$0x1,%BL

(180) 0x237c53 JE	237c67

(180) 0x237c55 PSHUFD	$0x55,%XMM15,%XMM3

(180) 0x237c5b MOVD	%XMM3,%ECX

(180) 0x237c5f MOVSXD	%ECX,%RCX

(180) 0x237c62 MOVHPS	(%RDX,%RCX,8),%XMM8

(180) 0x237c67 MOVAPS	%XMM8,-0x60(%RBP)

(180) 0x237c6c MOV	-0x78(%RBP),%RBX

(180) 0x237c70 MOVAPD	-0x140(%RBP),%XMM8

(180) 0x237c79 MOVAPD	-0x130(%RBP),%XMM15

(180) 0x237c82 PAND	%XMM6,%XMM12

(180) 0x237c87 POR	%XMM14,%XMM12

(180) 0x237c8c UCOMISD	%XMM5,%XMM13

(180) 0x237c91 JBE	237ca7

(180) 0x237c93 MOVD	%XMM12,%ECX

(180) 0x237c98 MOVSXD	%ECX,%RCX

(180) 0x237c9b MOVSD	(%RDX,%RCX,8),%XMM3

(180) 0x237ca0 MOVAPS	%XMM3,-0x120(%RBP)

(180) 0x237ca7 MOVDQA	%XMM12,-0x170(%RBP)

(180) 0x237cb0 MOVAPD	-0x160(%RBP),%XMM5

(180) 0x237cb8 MOVAPD	-0x26a40(%RIP),%XMM3

(180) 0x237cc0 ANDPD	%XMM3,%XMM5

(180) 0x237cc4 DIVPD	%XMM8,%XMM5

(180) 0x237cc9 MOVAPD	-0x150(%RBP),%XMM11

(180) 0x237cd2 ANDPD	%XMM3,%XMM11

(180) 0x237cd7 DIVPD	%XMM15,%XMM11

(180) 0x237cdc ANDPD	%XMM3,%XMM9

(180) 0x237ce1 ANDPD	%XMM3,%XMM10

(180) 0x237ce6 MOVAPD	%XMM2,%XMM15

(180) 0x237ceb ANDPD	%XMM3,%XMM15

(180) 0x237cf0 MOVAPD	%XMM7,%XMM14

(180) 0x237cf5 ANDPD	%XMM3,%XMM14

(180) 0x237cfa MOVAPD	-0x269b2(%RIP),%XMM3

(180) 0x237d02 MOVAPD	%XMM3,%XMM13

(180) 0x237d07 SUBPD	%XMM5,%XMM13

(180) 0x237d0c SUBPD	%XMM11,%XMM3

(180) 0x237d11 MULPD	%XMM15,%XMM13

(180) 0x237d16 MULPD	%XMM14,%XMM3

(180) 0x237d1b DIVPD	%XMM0,%XMM13

(180) 0x237d20 DIVPD	%XMM1,%XMM3

(180) 0x237d24 MOVAPD	%XMM5,%XMM6

(180) 0x237d28 MOVAPD	-0x269c1(%RIP),%XMM12

(180) 0x237d31 ADDPD	%XMM12,%XMM6

(180) 0x237d36 MOVAPD	%XMM11,%XMM8

(180) 0x237d3b ADDPD	%XMM12,%XMM8

(180) 0x237d40 MULPD	%XMM9,%XMM6

(180) 0x237d45 MULPD	%XMM10,%XMM8

(180) 0x237d4a TEST	$0x1,%R14B

(180) 0x237d4e JNE	237590

(180) 0x237d54 MOV	-0x70(%RBP),%R14

(180) 0x237d58 MOVAPD	-0x120(%RBP),%XMM12

(180) 0x237d61 JMP	2375b5

0x237d66 MOV	-0xf8(%RBP),%RCX

0x237d6d CMP	%RCX,-0x100(%RBP)

0x237d74 MOV	-0x88(%RBP),%R12

0x237d7b MOV	-0x80(%RBP),%R13

0x237d7f JNE	237da2

0x237d81 LEA	0x26718(%RIP),%RDI

0x237d88 MOV	-0x3c(%RBP),%ESI

0x237d8b CALL	25cd00 <@plt_start@+0x540>

0x237d90 ADD	$0x168,%RSP

0x237d97 POP	%RBX

0x237d98 POP	%R12

0x237d9a POP	%R13

0x237d9c POP	%R14

0x237d9e POP	%R15

0x237da0 POP	%RBP

0x237da1 RET

0x237da2 XORPD	%XMM0,%XMM0

0x237da6 MOVAPD	-0x26b2e(%RIP),%XMM1

0x237dae MOVSD	-0x26cd6(%RIP),%XMM2

0x237db6 MOVAPD	-0x269fe(%RIP),%XMM3

0x237dbe MOVSD	-0x26cf6(%RIP),%XMM4

0x237dc6 MOVAPD	-0x26a1e(%RIP),%XMM5

0x237dce MOVSD	-0x26cce(%RIP),%XMM6

0x237dd6 JMP	237e1d

0x237dd8 NOPL	(%RAX,%RAX,1)

(179) 0x237de0 MOVAPD	%XMM6,%XMM10

(179) 0x237de5 SUBSD	%XMM8,%XMM10

(179) 0x237dea MULSD	%XMM11,%XMM10

(179) 0x237def ADDSD	%XMM9,%XMM10

(179) 0x237df4 MULSD	%XMM10,%XMM7

(179) 0x237df9 IMUL	-0xc0(%RBP),%RSI

(179) 0x237e01 ADD	%RDX,%RSI

(179) 0x237e04 MOV	-0xb8(%RBP),%RAX

(179) 0x237e0b MOVSD	%XMM7,(%RAX,%RSI,8)

(179) 0x237e10 LEA	0x1(%R11),%RAX

(179) 0x237e14 CMP	%R14,%R11

(179) 0x237e17 JGE	237d81

(179) 0x237e1d MOV	%RAX,%RCX

(179) 0x237e20 MOV	%RAX,%R11

(179) 0x237e23 SHR	$0x20,%RCX

(179) 0x237e27 JE	237e40

(179) 0x237e29 CQTO

(179) 0x237e2b IDIVQ	-0x30(%RBP)

(179) 0x237e2f JMP	237e45

0x237e31 NOPW	%CS:(%RAX,%RAX,1)

(179) 0x237e40 XOR	%EDX,%EDX

(179) 0x237e42 DIVL	-0x30(%RBP)

(179) 0x237e45 LEA	(%RBX,%RAX,1),%EDI

(179) 0x237e48 ADD	%R15D,%EDX

(179) 0x237e4b MOVSXD	%EDX,%RDX

(179) 0x237e4e MOVSXD	%EDI,%RSI

(179) 0x237e51 MOV	%R12,%RCX

(179) 0x237e54 IMUL	%RSI,%RCX

(179) 0x237e58 ADD	%RDX,%RCX

(179) 0x237e5b MOVSD	(%R13,%RCX,8),%XMM7

(179) 0x237e62 UCOMISD	%XMM7,%XMM0

(179) 0x237e66 LEA	0x1(%RBX,%RAX,1),%EAX

(179) 0x237e6a MOVSXD	%EAX,%R8

(179) 0x237e6d JBE	237e80

(179) 0x237e6f ADD	$0x2,%EDI

(179) 0x237e72 MOV	%RSI,%RCX

(179) 0x237e75 JMP	237e8a

0x237e77 NOPW	(%RAX,%RAX,1)

(179) 0x237e80 DEC	%EDI

(179) 0x237e82 MOV	%R8,%RCX

(179) 0x237e85 MOV	%RSI,%R8

(179) 0x237e88 MOV	%EDI,%EAX

(179) 0x237e8a MOVAPD	%XMM7,%XMM8

(179) 0x237e8f ANDPD	%XMM1,%XMM8

(179) 0x237e94 MOV	%R8,%R9

(179) 0x237e97 IMUL	-0xd0(%RBP),%R9

(179) 0x237e9f ADD	%RDX,%R9

(179) 0x237ea2 MOV	-0xc8(%RBP),%R10

(179) 0x237ea9 DIVSD	(%R10,%R9,8),%XMM8

(179) 0x237eaf MOV	-0xb0(%RBP),%R9

(179) 0x237eb6 IMUL	%R9,%R8

(179) 0x237eba ADD	%RDX,%R8

(179) 0x237ebd MOV	-0xa8(%RBP),%R10

(179) 0x237ec4 MOVSD	(%R10,%R8,8),%XMM9

(179) 0x237eca MOVSXD	%EDI,%RDI

(179) 0x237ecd IMUL	%R9,%RDI

(179) 0x237ed1 ADD	%RDX,%RDI

(179) 0x237ed4 IMUL	%R9,%RCX

(179) 0x237ed8 ADD	%RDX,%RCX

(179) 0x237edb MOVSD	(%R10,%RCX,8),%XMM10

(179) 0x237ee1 MOVAPD	%XMM9,%XMM11

(179) 0x237ee6 MOVHPD	(%R10,%RDI,8),%XMM11

(179) 0x237eec UNPCKLPD	%XMM9,%XMM10

(179) 0x237ef1 SUBPD	%XMM11,%XMM10

(179) 0x237ef6 MOVAPD	%XMM10,%XMM12

(179) 0x237efb UNPCKHPD	%XMM10,%XMM12

(179) 0x237f00 MULSD	%XMM10,%XMM12

(179) 0x237f05 XORPD	%XMM11,%XMM11

(179) 0x237f0a UCOMISD	%XMM11,%XMM12

(179) 0x237f0f JBE	237de0

(179) 0x237f15 MOV	-0x90(%RBP),%RCX

(179) 0x237f1c MOVSD	(%RCX,%RSI,8),%XMM13

(179) 0x237f22 MOVAPD	%XMM10,%XMM11

(179) 0x237f27 ANDPD	%XMM1,%XMM11

(179) 0x237f2c UNPCKLPD	%XMM8,%XMM14

(179) 0x237f31 MOVAPD	%XMM2,%XMM12

(179) 0x237f36 SUBSD	%XMM8,%XMM12

(179) 0x237f3b ADDPD	%XMM3,%XMM14

(179) 0x237f40 MOVSD	%XMM12,%XMM14

(179) 0x237f45 CLTQ

(179) 0x237f47 MULPD	%XMM11,%XMM14

(179) 0x237f4c MOVAPD	%XMM13,%XMM12

(179) 0x237f51 MOVHPD	(%RCX,%RAX,8),%XMM12

(179) 0x237f57 DIVPD	%XMM12,%XMM14

(179) 0x237f5c MOVAPD	%XMM14,%XMM12

(179) 0x237f61 UNPCKHPD	%XMM14,%XMM12

(179) 0x237f66 ADDSD	%XMM14,%XMM12

(179) 0x237f6b MULSD	%XMM13,%XMM12

(179) 0x237f70 DIVSD	%XMM4,%XMM12

(179) 0x237f75 PSHUFD	$-0x12,%XMM11,%XMM13

(179) 0x237f7b MOVDQA	%XMM13,%XMM14

(179) 0x237f80 MINSD	%XMM12,%XMM14

(179) 0x237f85 CMPSD	$0x3,%XMM12,%XMM12

(179) 0x237f8b MOVAPD	%XMM12,%XMM15

(179) 0x237f90 ANDNPD	%XMM14,%XMM15

(179) 0x237f95 ANDPD	%XMM13,%XMM12

(179) 0x237f9a ORPD	%XMM15,%XMM12

(179) 0x237f9f MOVAPD	%XMM11,%XMM13

(179) 0x237fa4 MINSD	%XMM12,%XMM13

(179) 0x237fa9 CMPSD	$0x3,%XMM12,%XMM12

(179) 0x237faf MOVAPD	%XMM12,%XMM14

(179) 0x237fb4 ANDNPD	%XMM13,%XMM14

(179) 0x237fb9 ANDPD	%XMM11,%XMM12

(179) 0x237fbe ORPD	%XMM14,%XMM12

(179) 0x237fc3 CMPSD	$0x6,%XMM0,%XMM10

(179) 0x237fc9 MOVAPD	%XMM10,%XMM11

(179) 0x237fce ANDPD	%XMM12,%XMM11

(179) 0x237fd3 XORPD	%XMM5,%XMM12

(179) 0x237fd8 ANDNPD	%XMM12,%XMM10

(179) 0x237fdd ORPD	%XMM11,%XMM10

(179) 0x237fe2 MOVAPD	%XMM10,%XMM11

(179) 0x237fe7 JMP	237de0

0x237fec NOPL	(%RAX)

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	advec_mom.cpp:180-211
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:180-211

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 14.50 to 2.13 cycles (6.82x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 14.50 to 1.41 cycles (10.31x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:180
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:180

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVL: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:181

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 256 bytes. The binary function is storing 164 bytes.

General properties

nb instructions	122
nb uops	116
loop length	572
used x86 registers	14
used mmx registers	0
used xmm registers	7
used ymm registers	0
used zmm registers	0
nb stack references	26

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	14.50 cycles
front end	14.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	6.67	6.67	6.67	6.67	6.67	6.67	14.00	14.00	14.00	14.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	6.67	6.67	6.67	6.67	6.67	6.67	14.00	14.00	14.00	14.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	14.50
Dispatch	14.00
Overall L1	14.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	62%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	10%
load	21%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Vector efficiency ratios

INT

all	10%
load	10%
store	11%
mul	12%
add-sub	7%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	20%
load	18%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	12%
load	13%
store	11%
mul	12%
add-sub	7%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 14.50 cycles. At this rate:

6% of peak load performance is reached (17.66 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (11.31 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 237410

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x168,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV (%RDX),%EBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOV (%RCX),%R14D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
ADD $0x3,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
SUB %EBX,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JLE 237d90 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.20+0x980>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV (%R8),%R15D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOV (%R9),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
INC %R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
ADD $0x3,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
CMP %R15D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JLE 237d90 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.20+0x980>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
SUB %R15D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %RAX,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
IMUL %RAX,%R14	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
DEC %R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOVQ $0,-0xd8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %R14,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOVQ $0x1,-0x110(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVL $0,-0x44(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA -0x110(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA 0x26ffa(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x44(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0xd8(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x38(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %ESI,-0x3c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 25ccf0 <@plt_start@+0x530>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV -0x38(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP %R14,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
CMOVL %RAX,%R14	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	1	0.33	scal (12.5%)
MOV %R14,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV -0xd8(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP %R14,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JG 237d81 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.20+0x971>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV 0x30(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x28(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x20(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x18(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x10(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%R8),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV 0x10(%R8),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV (%RDI),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %R8,-0xd0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x10(%RDI),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDI,-0xc8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV (%RCX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDI,-0xb0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x10(%RCX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RCX,-0xa8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x8(%RDX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RCX,-0x90(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV (%RAX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RCX,-0xc0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x10(%RAX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RAX,-0xb8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %R14,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RSI,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
CMP $0x4,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JAE 23754e <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.20+0x13e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %RSI,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 237da2 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.20+0x992>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
MOV %R13,-0x80(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %R12,-0x88(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %RAX,-0x100(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x4,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA (%RSI,%RCX,1),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %RAX,-0x68(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
XORPD %XMM5,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %RCX,-0xf8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %R14,-0x70(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %RBX,-0x78(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %R15D,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
JMP 23774d <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.20+0x33d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0xf8(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP %RCX,-0x100(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
MOV -0x88(%RBP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV -0x80(%RBP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
JNE 237da2 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.20+0x992>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
LEA 0x26718(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV -0x3c(%RBP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CALL 25cd00 <@plt_start@+0x540>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
ADD $0x168,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
XORPD %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOVAPD -0x26b2e(%RIP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (25.0%)
MOVSD -0x26cd6(%RIP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
MOVAPD -0x269fe(%RIP),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (25.0%)
MOVSD -0x26cf6(%RIP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
MOVAPD -0x26a1e(%RIP),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (25.0%)
MOVSD -0x26cce(%RIP),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
JMP 237e1d <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.20+0xa0d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	advec_mom.cpp:180-211
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:180-211

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 14.50 to 2.13 cycles (6.82x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:180
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:180

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVL: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:181

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 256 bytes. The binary function is storing 164 bytes.

General properties

nb instructions	122
nb uops	116
loop length	572
used x86 registers	14
used mmx registers	0
used xmm registers	7
used ymm registers	0
used zmm registers	0
nb stack references	26

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	14.50 cycles
front end	14.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	6.67	6.67	6.67	6.67	6.67	6.67	14.00	14.00	14.00	14.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	6.67	6.67	6.67	6.67	6.67	6.67	14.00	14.00	14.00	14.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	14.50
Dispatch	14.00
Overall L1	14.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	62%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	10%
load	21%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Vector efficiency ratios

INT

all	10%
load	10%
store	11%
mul	12%
add-sub	7%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	20%
load	18%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	12%
load	13%
store	11%
mul	12%
add-sub	7%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 14.50 cycles. At this rate:

6% of peak load performance is reached (17.66 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (11.31 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 237410

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x168,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV (%RDX),%EBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOV (%RCX),%R14D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
ADD $0x3,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
SUB %EBX,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JLE 237d90 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.20+0x980>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV (%R8),%R15D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOV (%R9),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
INC %R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
ADD $0x3,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
CMP %R15D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JLE 237d90 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.20+0x980>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
SUB %R15D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %RAX,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
IMUL %RAX,%R14	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
DEC %R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOVQ $0,-0xd8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %R14,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOVQ $0x1,-0x110(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVL $0,-0x44(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA -0x110(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA 0x26ffa(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x44(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0xd8(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x38(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %ESI,-0x3c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 25ccf0 <@plt_start@+0x530>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV -0x38(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP %R14,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
CMOVL %RAX,%R14	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	1	0.33	scal (12.5%)
MOV %R14,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV -0xd8(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP %R14,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JG 237d81 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.20+0x971>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV 0x30(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x28(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x20(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x18(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x10(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%R8),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV 0x10(%R8),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV (%RDI),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %R8,-0xd0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x10(%RDI),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDI,-0xc8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV (%RCX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDI,-0xb0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x10(%RCX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RCX,-0xa8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x8(%RDX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RCX,-0x90(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV (%RAX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RCX,-0xc0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x10(%RAX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RAX,-0xb8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %R14,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RSI,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
CMP $0x4,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JAE 23754e <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.20+0x13e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %RSI,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 237da2 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.20+0x992>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
MOV %R13,-0x80(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %R12,-0x88(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %RAX,-0x100(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x4,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA (%RSI,%RCX,1),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %RAX,-0x68(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
XORPD %XMM5,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %RCX,-0xf8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %R14,-0x70(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %RBX,-0x78(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %R15D,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
JMP 23774d <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.20+0x33d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0xf8(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP %RCX,-0x100(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
MOV -0x88(%RBP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV -0x80(%RBP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
JNE 237da2 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.20+0x992>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
LEA 0x26718(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV -0x3c(%RBP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CALL 25cd00 <@plt_start@+0x540>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
ADD $0x168,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
XORPD %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOVAPD -0x26b2e(%RIP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (25.0%)
MOVSD -0x26cd6(%RIP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
MOVAPD -0x269fe(%RIP),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (25.0%)
MOVSD -0x26cf6(%RIP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
MOVAPD -0x26a1e(%RIP),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (25.0%)
MOVSD -0x26cce(%RIP),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
JMP 237e1d <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.20+0xa0d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	5.84	2.28
○Loop 180 - advec_mom.cpp:181-211 - exec	5.84	2.28
○Loop 179 - advec_mom.cpp:181-211 - exec	0.00	0.00

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