OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone .omp

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: advec_mom.cpp:167-172 [...]	Coverage (incl. loops): 2.97% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 167 - 172

--------------------------------------------------------------------------------

167: #pragma omp parallel for simd collapse(2)

168:       for (int j = (y_min - 1 + 1); j < (y_max + 2 + 2); j++) {

169:         for (int i = (x_min + 1); i < (x_max + 1 + 2); i++) {

170:           node_mass_post(i, j) = 0.25 * (density1(i + 0, j - 1) * post_vol(i + 0, j - 1) + density1(i, j) * post_vol(i, j) +

171:                                          density1(i - 1, j - 1) * post_vol(i - 1, j - 1) + density1(i - 1, j + 0) * post_vol(i - 1, j + 0));

172:           node_mass_pre(i, j) = node_mass_post(i, j) - node_flux(i + 0, j - 1) + node_flux(i, j);

0x236e20 PUSH	%RBP

0x236e21 MOV	%RSP,%RBP

0x236e24 PUSH	%R15

0x236e26 PUSH	%R14

0x236e28 PUSH	%R13

0x236e2a PUSH	%R12

0x236e2c PUSH	%RBX

0x236e2d SUB	$0x108,%RSP

0x236e34 MOV	(%RDX),%EAX

0x236e36 MOV	(%RCX),%R14D

0x236e39 ADD	$0x4,%R14D

0x236e3d MOV	%RAX,-0x38(%RBP)

0x236e41 SUB	%EAX,%R14D

0x236e44 JLE	2372bd

0x236e4a MOV	(%R8),%EAX

0x236e4d MOV	(%R9),%R12D

0x236e50 MOV	%RAX,-0xa0(%RBP)

0x236e57 INC	%EAX

0x236e59 ADD	$0x3,%R12D

0x236e5d CMP	%EAX,%R12D

0x236e60 JLE	2372bd

0x236e66 MOV	%RAX,-0x30(%RBP)

0x236e6a SUB	%EAX,%R12D

0x236e6d IMUL	%R12,%R14

0x236e71 DEC	%R14

0x236e74 MOVQ	$0,-0xa8(%RBP)

0x236e7f MOV	%R14,-0x40(%RBP)

0x236e83 MOVQ	$0x1,-0x128(%RBP)

0x236e8e MOVL	$0,-0x48(%RBP)

0x236e95 MOV	(%RDI),%ESI

0x236e97 SUB	$0x8,%RSP

0x236e9b LEA	-0x128(%RBP),%RAX

0x236ea2 LEA	0x27597(%RIP),%RDI

0x236ea9 LEA	-0x48(%RBP),%RCX

0x236ead LEA	-0xa8(%RBP),%R8

0x236eb4 LEA	-0x40(%RBP),%R9

0x236eb8 MOV	%ESI,-0x44(%RBP)

0x236ebb MOV	$0x22,%EDX

0x236ec0 PUSH	$0x1

0x236ec2 PUSH	$0x1

0x236ec4 PUSH	%RAX

0x236ec5 CALL	25ccf0 <@plt_start@+0x530>

0x236eca ADD	$0x20,%RSP

0x236ece MOV	-0x40(%RBP),%RAX

0x236ed2 CMP	%R14,%RAX

0x236ed5 CMOVL	%RAX,%R14

0x236ed9 MOV	%R14,-0x40(%RBP)

0x236edd MOV	-0xa8(%RBP),%R9

0x236ee4 CMP	%R14,%R9

0x236ee7 JG	2372ae

0x236eed MOV	0x30(%RBP),%RAX

0x236ef1 MOV	0x28(%RBP),%RCX

0x236ef5 MOV	0x20(%RBP),%RDX

0x236ef9 MOV	0x18(%RBP),%RSI

0x236efd MOV	0x10(%RBP),%RDI

0x236f01 MOV	(%RSI),%R8

0x236f04 MOV	%R8,-0x98(%RBP)

0x236f0b MOV	0x10(%RSI),%RSI

0x236f0f MOV	%RSI,-0x90(%RBP)

0x236f16 MOV	(%RDX),%RSI

0x236f19 MOV	%RSI,-0x88(%RBP)

0x236f20 MOV	0x10(%RDX),%RDX

0x236f24 MOV	%RDX,-0x80(%RBP)

0x236f28 MOV	(%RDI),%RDX

0x236f2b MOV	%RDX,-0x78(%RBP)

0x236f2f MOV	0x10(%RDI),%RDX

0x236f33 MOV	%RDX,-0x70(%RBP)

0x236f37 MOV	(%RAX),%RDX

0x236f3a MOV	%RDX,-0x68(%RBP)

0x236f3e MOV	0x10(%RAX),%RAX

0x236f42 MOV	%RAX,-0x60(%RBP)

0x236f46 MOV	(%RCX),%RAX

0x236f49 MOV	%RAX,-0x58(%RBP)

0x236f4d MOV	0x10(%RCX),%RAX

0x236f51 MOV	%RAX,-0x50(%RBP)

0x236f55 MOV	%R14,%RAX

0x236f58 SUB	%R9,%RAX

0x236f5b INC	%RAX

0x236f5e CMP	$0x2,%RAX

0x236f62 JAE	236f6c

0x236f64 MOV	%R9,%RCX

0x236f67 JMP	2373e9

0x236f6c MOV	%RAX,-0xb8(%RBP)

0x236f73 MOV	%RAX,%RCX

0x236f76 AND	$-0x2,%RCX

0x236f7a LEA	(%R9,%RCX,1),%RAX

0x236f7e MOV	%RAX,-0xc0(%RBP)

0x236f85 MOVAPD	-0x25cdd(%RIP),%XMM0

0x236f8d MOV	%RCX,-0xb0(%RBP)

0x236f94 MOV	%RCX,%RDX

0x236f97 MOV	%R14,-0xd0(%RBP)

0x236f9e MOV	%R12,-0xc8(%RBP)

0x236fa5 JMP	237238

0x236faa NOPW	(%RAX,%RAX,1)

(178) 0x236fb0 CQTO

(178) 0x236fb2 IDIV	%R12

(178) 0x236fb5 MOV	%RAX,%R9

(178) 0x236fb8 MOV	%R9,-0xe0(%RBP)

(178) 0x236fbf MOV	%RDX,-0xf0(%RBP)

(178) 0x236fc6 LEA	(%R10,%R8,1),%R12D

(178) 0x236fca LEA	(%RSI,%RDI,1),%ECX

(178) 0x236fcd ADD	%EDX,%ESI

(178) 0x236fcf MOV	%R10,%RAX

(178) 0x236fd2 MOVSXD	%ECX,%R10

(178) 0x236fd5 MOVSXD	%ESI,%RDX

(178) 0x236fd8 MOV	%RDX,-0xd8(%RBP)

(178) 0x236fdf LEA	-0x1(%RAX,%R8,1),%ECX

(178) 0x236fe4 LEA	-0x1(%RAX,%R9,1),%ESI

(178) 0x236fe9 MOVSXD	%ECX,%RCX

(178) 0x236fec MOVSXD	%ESI,%RBX

(178) 0x236fef MOV	%RBX,-0x110(%RBP)

(178) 0x236ff6 MOV	-0x98(%RBP),%R14

(178) 0x236ffd MOV	%R14,%R13

(178) 0x237000 IMUL	%RCX,%R13

(178) 0x237004 MOV	%RCX,%R11

(178) 0x237007 MOV	%RCX,-0x108(%RBP)

(178) 0x23700e MOV	%R14,%R15

(178) 0x237011 IMUL	%RBX,%R15

(178) 0x237015 MOV	%RDI,-0xe8(%RBP)

(178) 0x23701c LEA	(%R10,%R13,1),%RDI

(178) 0x237020 LEA	(%R15,%RDX,1),%RCX

(178) 0x237024 MOV	-0x90(%RBP),%RSI

(178) 0x23702b MOVSD	(%RSI,%RDI,8),%XMM1

(178) 0x237030 MOVHPD	(%RSI,%RCX,8),%XMM1

(178) 0x237035 MOV	-0x88(%RBP),%R8

(178) 0x23703c MOV	%R8,%R9

(178) 0x23703f IMUL	%R11,%R9

(178) 0x237043 MOV	%R8,%R11

(178) 0x237046 IMUL	%RBX,%R11

(178) 0x23704a MOV	%R10,%RBX

(178) 0x23704d LEA	(%R9,%R10,1),%RDI

(178) 0x237051 MOV	-0x80(%RBP),%RCX

(178) 0x237055 MOVSD	(%RCX,%RDI,8),%XMM2

(178) 0x23705a LEA	(%R11,%RDX,1),%RDI

(178) 0x23705e MOVHPD	(%RCX,%RDI,8),%XMM2

(178) 0x237063 MOVSXD	%R12D,%R12

(178) 0x237066 MOV	%R14,%RDI

(178) 0x237069 IMUL	%R12,%RDI

(178) 0x23706d MOV	%R12,-0xf8(%RBP)

(178) 0x237074 LEA	(%RDI,%R10,1),%RDX

(178) 0x237078 MOV	%R10,-0x100(%RBP)

(178) 0x23707f MOVSD	(%RSI,%RDX,8),%XMM4

(178) 0x237084 MOV	-0xe0(%RBP),%RDX

(178) 0x23708b ADD	%EDX,%EAX

(178) 0x23708d MOVSXD	%EAX,%RDX

(178) 0x237090 MOV	%R14,%RAX

(178) 0x237093 IMUL	%RDX,%RAX

(178) 0x237097 MOV	%RDX,%R14

(178) 0x23709a MOV	-0xd8(%RBP),%RDX

(178) 0x2370a1 LEA	(%RAX,%RDX,1),%R10

(178) 0x2370a5 MOVHPD	(%RSI,%R10,8),%XMM4

(178) 0x2370ab MOV	%R8,%R10

(178) 0x2370ae IMUL	%R12,%R10

(178) 0x2370b2 LEA	(%R10,%RBX,1),%R12

(178) 0x2370b6 MOVSD	(%RCX,%R12,8),%XMM5

(178) 0x2370bc MOV	%R8,%R12

(178) 0x2370bf IMUL	%R14,%R12

(178) 0x2370c3 MOV	%R14,%RBX

(178) 0x2370c6 LEA	(%R12,%RDX,1),%R14

(178) 0x2370ca MOV	%RDX,%R8

(178) 0x2370cd MOVHPD	(%RCX,%R14,8),%XMM5

(178) 0x2370d3 MOV	-0xa0(%RBP),%RDX

(178) 0x2370da MOV	-0xe8(%RBP),%R14

(178) 0x2370e1 ADD	%EDX,%R14D

(178) 0x2370e4 MOVSXD	%R14D,%R14

(178) 0x2370e7 ADD	%R14,%R13

(178) 0x2370ea MOVSD	(%RSI,%R13,8),%XMM6

(178) 0x2370f0 MOV	-0xf0(%RBP),%R13

(178) 0x2370f7 ADD	%EDX,%R13D

(178) 0x2370fa MOVSXD	%R13D,%R13

(178) 0x2370fd ADD	%R13,%R15

(178) 0x237100 MOVHPD	(%RSI,%R15,8),%XMM6

(178) 0x237106 ADD	%R14,%R9

(178) 0x237109 MOVSD	(%RCX,%R9,8),%XMM7

(178) 0x23710f ADD	%R13,%R11

(178) 0x237112 MOVHPD	(%RCX,%R11,8),%XMM7

(178) 0x237118 ADD	%R14,%RDI

(178) 0x23711b MOVSD	(%RSI,%RDI,8),%XMM8

(178) 0x237121 ADD	%R13,%RAX

(178) 0x237124 MOVHPD	(%RSI,%RAX,8),%XMM8

(178) 0x23712a ADD	%R14,%R10

(178) 0x23712d ADD	%R13,%R12

(178) 0x237130 MOVSD	(%RCX,%R10,8),%XMM3

(178) 0x237136 MULPD	%XMM1,%XMM2

(178) 0x23713a MULPD	%XMM4,%XMM5

(178) 0x23713e ADDPD	%XMM2,%XMM5

(178) 0x237142 MULPD	%XMM6,%XMM7

(178) 0x237146 ADDPD	%XMM5,%XMM7

(178) 0x23714a MOVHPD	(%RCX,%R12,8),%XMM3

(178) 0x237150 MULPD	%XMM8,%XMM3

(178) 0x237155 ADDPD	%XMM7,%XMM3

(178) 0x237159 MULPD	%XMM0,%XMM3

(178) 0x23715d MOV	-0x78(%RBP),%RCX

(178) 0x237161 MOV	%RCX,%RAX

(178) 0x237164 MOV	-0xf8(%RBP),%RDI

(178) 0x23716b IMUL	%RDI,%RAX

(178) 0x23716f MOV	-0x100(%RBP),%RSI

(178) 0x237176 ADD	%RSI,%RAX

(178) 0x237179 MOV	-0x70(%RBP),%RDX

(178) 0x23717d MOVLPD	%XMM3,(%RDX,%RAX,8)

(178) 0x237182 MOV	%RCX,%RAX

(178) 0x237185 IMUL	%RBX,%RAX

(178) 0x237189 ADD	%R8,%RAX

(178) 0x23718c MOVHPD	%XMM3,(%RDX,%RAX,8)

(178) 0x237191 MOV	-0x68(%RBP),%RCX

(178) 0x237195 MOV	-0x108(%RBP),%RAX

(178) 0x23719c IMUL	%RCX,%RAX

(178) 0x2371a0 ADD	%RSI,%RAX

(178) 0x2371a3 MOV	-0x60(%RBP),%RDX

(178) 0x2371a7 MOVSD	(%RDX,%RAX,8),%XMM1

(178) 0x2371ac MOV	-0x110(%RBP),%RAX

(178) 0x2371b3 IMUL	%RCX,%RAX

(178) 0x2371b7 ADD	%R8,%RAX

(178) 0x2371ba MOVHPD	(%RDX,%RAX,8),%XMM1

(178) 0x2371bf MOV	%RCX,%RAX

(178) 0x2371c2 IMUL	%RDI,%RAX

(178) 0x2371c6 ADD	%RSI,%RAX

(178) 0x2371c9 MOVSD	(%RDX,%RAX,8),%XMM2

(178) 0x2371ce MOV	%RCX,%RAX

(178) 0x2371d1 IMUL	%RBX,%RAX

(178) 0x2371d5 ADD	%R8,%RAX

(178) 0x2371d8 MOVHPD	(%RDX,%RAX,8),%XMM2

(178) 0x2371dd MOV	-0x58(%RBP),%RAX

(178) 0x2371e1 MOV	%RDI,%RCX

(178) 0x2371e4 IMUL	%RAX,%RCX

(178) 0x2371e8 ADD	%RSI,%RCX

(178) 0x2371eb MOV	%RBX,%RDX

(178) 0x2371ee IMUL	%RAX,%RDX

(178) 0x2371f2 ADD	%R8,%RDX

(178) 0x2371f5 SUBPD	%XMM1,%XMM3

(178) 0x2371f9 ADDPD	%XMM3,%XMM2

(178) 0x2371fd MOV	-0x50(%RBP),%RAX

(178) 0x237201 MOVLPD	%XMM2,(%RAX,%RCX,8)

(178) 0x237206 MOVHPD	%XMM2,(%RAX,%RDX,8)

(178) 0x23720b MOV	-0x120(%RBP),%R9

(178) 0x237212 ADD	$0x2,%R9

(178) 0x237216 MOV	-0x118(%RBP),%RDX

(178) 0x23721d ADD	$-0x2,%RDX

(178) 0x237221 MOV	-0xd0(%RBP),%R14

(178) 0x237228 MOV	-0xc8(%RBP),%R12

(178) 0x23722f MOV	-0xc0(%RBP),%RCX

(178) 0x237236 JE	23729a

(178) 0x237238 MOV	%R9,%RAX

(178) 0x23723b SHR	$0x20,%RAX

(178) 0x23723f MOV	%RDX,-0x118(%RBP)

(178) 0x237246 JE	237260

(178) 0x237248 MOV	%R9,%RAX

(178) 0x23724b CQTO

(178) 0x23724d IDIV	%R12

(178) 0x237250 MOV	%RDX,%RDI

(178) 0x237253 MOV	%RAX,%R8

(178) 0x237256 JMP	23726d

0x237258 NOPL	(%RAX,%RAX,1)

(178) 0x237260 MOV	%R9D,%EAX

(178) 0x237263 XOR	%EDX,%EDX

(178) 0x237265 DIV	%R12D

(178) 0x237268 MOV	%EDX,%EDI

(178) 0x23726a MOV	%EAX,%R8D

(178) 0x23726d MOV	-0x38(%RBP),%R10

(178) 0x237271 MOV	-0x30(%RBP),%RSI

(178) 0x237275 LEA	0x1(%R9),%RAX

(178) 0x237279 MOV	%RAX,%RCX

(178) 0x23727c SHR	$0x20,%RCX

(178) 0x237280 MOV	%R9,-0x120(%RBP)

(178) 0x237287 JNE	236fb0

(178) 0x23728d XOR	%EDX,%EDX

(178) 0x23728f DIV	%R12D

(178) 0x237292 MOV	%EAX,%R9D

(178) 0x237295 JMP	236fb8

0x23729a MOV	-0xb0(%RBP),%RAX

0x2372a1 CMP	%RAX,-0xb8(%RBP)

0x2372a8 JNE	2373e9

0x2372ae LEA	0x271a3(%RIP),%RDI

0x2372b5 MOV	-0x44(%RBP),%ESI

0x2372b8 CALL	25cd00 <@plt_start@+0x540>

0x2372bd ADD	$0x108,%RSP

0x2372c4 POP	%RBX

0x2372c5 POP	%R12

0x2372c7 POP	%R13

0x2372c9 POP	%R14

0x2372cb POP	%R15

0x2372cd POP	%RBP

0x2372ce RET

0x2372cf NOP

(177) 0x2372d0 MOV	%RCX,%RAX

(177) 0x2372d3 CQTO

(177) 0x2372d5 IDIV	%R12

(177) 0x2372d8 MOV	%RCX,%RBX

(177) 0x2372db MOV	-0x30(%RBP),%RSI

(177) 0x2372df MOV	-0x38(%RBP),%RDI

(177) 0x2372e3 LEA	(%RDI,%RAX,1),%ECX

(177) 0x2372e6 ADD	%EDX,%ESI

(177) 0x2372e8 MOVSXD	%ESI,%RSI

(177) 0x2372eb LEA	-0x1(%RDI,%RAX,1),%EAX

(177) 0x2372ef MOVSXD	%EAX,%RDI

(177) 0x2372f2 MOV	-0x98(%RBP),%R10

(177) 0x2372f9 MOV	%R10,%R8

(177) 0x2372fc IMUL	%RDI,%R8

(177) 0x237300 LEA	(%R8,%RSI,1),%RAX

(177) 0x237304 MOV	-0x90(%RBP),%R15

(177) 0x23730b MOVSD	(%R15,%RAX,8),%XMM0

(177) 0x237311 MOV	-0x88(%RBP),%R11

(177) 0x237318 MOV	%R11,%R9

(177) 0x23731b IMUL	%RDI,%R9

(177) 0x23731f MOVSXD	%ECX,%RAX

(177) 0x237322 MOV	%R10,%RCX

(177) 0x237325 IMUL	%RAX,%RCX

(177) 0x237329 LEA	(%RCX,%RSI,1),%R10

(177) 0x23732d MOVSD	(%R15,%R10,8),%XMM1

(177) 0x237333 MOV	%R11,%R10

(177) 0x237336 IMUL	%RAX,%R10

(177) 0x23733a LEA	(%R10,%RSI,1),%R11

(177) 0x23733e MOV	-0x80(%RBP),%R13

(177) 0x237342 MULSD	(%R13,%R11,8),%XMM1

(177) 0x237349 LEA	(%R9,%RSI,1),%R11

(177) 0x23734d MULSD	(%R13,%R11,8),%XMM0

(177) 0x237354 ADD	-0xa0(%RBP),%EDX

(177) 0x23735a MOVSXD	%EDX,%RDX

(177) 0x23735d ADD	%RDX,%R8

(177) 0x237360 MOVSD	(%R15,%R8,8),%XMM2

(177) 0x237366 ADD	%RDX,%R9

(177) 0x237369 MULSD	(%R13,%R9,8),%XMM2

(177) 0x237370 ADD	%RDX,%RCX

(177) 0x237373 MOVSD	(%R15,%RCX,8),%XMM3

(177) 0x237379 ADD	%RDX,%R10

(177) 0x23737c ADDSD	%XMM1,%XMM0

(177) 0x237380 MULSD	(%R13,%R10,8),%XMM3

(177) 0x237387 ADDSD	%XMM0,%XMM2

(177) 0x23738b ADDSD	%XMM2,%XMM3

(177) 0x23738f MULSD	-0x2624f(%RIP),%XMM3

(177) 0x237397 MOV	-0x78(%RBP),%RCX

(177) 0x23739b IMUL	%RAX,%RCX

(177) 0x23739f ADD	%RSI,%RCX

(177) 0x2373a2 MOV	-0x70(%RBP),%RDX

(177) 0x2373a6 MOVSD	%XMM3,(%RDX,%RCX,8)

(177) 0x2373ab MOV	-0x68(%RBP),%RCX

(177) 0x2373af IMUL	%RCX,%RDI

(177) 0x2373b3 ADD	%RSI,%RDI

(177) 0x2373b6 MOV	-0x60(%RBP),%RDX

(177) 0x2373ba SUBSD	(%RDX,%RDI,8),%XMM3

(177) 0x2373bf IMUL	%RAX,%RCX

(177) 0x2373c3 ADD	%RSI,%RCX

(177) 0x2373c6 ADDSD	(%RDX,%RCX,8),%XMM3

(177) 0x2373cb IMUL	-0x58(%RBP),%RAX

(177) 0x2373d0 ADD	%RSI,%RAX

(177) 0x2373d3 MOV	-0x50(%RBP),%RCX

(177) 0x2373d7 MOVSD	%XMM3,(%RCX,%RAX,8)

(177) 0x2373dc CMP	%R14,%RBX

(177) 0x2373df LEA	0x1(%RBX),%RCX

(177) 0x2373e3 JGE	2372ae

(177) 0x2373e9 MOV	%RCX,%RAX

(177) 0x2373ec SHR	$0x20,%RAX

(177) 0x2373f0 JNE	2372d0

(177) 0x2373f6 MOV	%ECX,%EAX

(177) 0x2373f8 XOR	%EDX,%EDX

(177) 0x2373fa DIV	%R12D

(177) 0x2373fd JMP	2372d8

0x237402 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	advec_mom.cpp:167-172
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:167-172

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 13.75 to 1.67 cycles (8.25x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 13.75 to 1.19 cycles (11.58x speedup).

Details

2% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

25% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
0% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:167
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:167

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVL: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:168

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 192 bytes. The binary function is storing 184 bytes.

General properties

nb instructions	111
nb uops	110
loop length	476
used x86 registers	14
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	28

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	13.75 cycles
front end	13.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	6.50	6.50	6.50	6.50	6.50	6.50	13.00	13.00	13.00	13.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	6.50	6.50	6.50	6.50	6.50	6.50	13.00	13.00	13.00	13.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	13.75
Dispatch	13.00
Overall L1	13.75

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	2%
load	25%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	10%
load	8%
store	11%
mul	12%
add-sub	7%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	25%
load	25%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	11%
load	12%
store	11%
mul	12%
add-sub	7%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 13.75 cycles. At this rate:

5% of peak load performance is reached (13.96 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
10% of peak store performance is reached (13.38 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 13.75 to 13.00 cycles (1.06x speedup).

ASM code

In the binary file, the address of the function is: 236e20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x108,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV (%RDX),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RCX),%R14D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
ADD $0x4,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %RAX,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
SUB %EAX,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JLE 2372bd <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.18+0x49d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV (%R8),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%R9),%R12D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOV %RAX,-0xa0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
INC %EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD $0x3,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMP %EAX,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JLE 2372bd <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.18+0x49d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %RAX,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
SUB %EAX,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
IMUL %R12,%R14	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
DEC %R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOVQ $0,-0xa8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %R14,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOVQ $0x1,-0x128(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVL $0,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA -0x128(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA 0x27597(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x48(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0xa8(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x40(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %ESI,-0x44(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 25ccf0 <@plt_start@+0x530>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV -0x40(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP %R14,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
CMOVL %RAX,%R14	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	1	0.33	scal (12.5%)
MOV %R14,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV -0xa8(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP %R14,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JG 2372ae <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.18+0x48e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV 0x30(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x28(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x20(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x18(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x10(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RSI),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %R8,-0x98(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x10(%RSI),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RSI,-0x90(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV (%RDX),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RSI,-0x88(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x10(%RDX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDX,-0x80(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV (%RDI),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDX,-0x78(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x10(%RDI),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDX,-0x70(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV (%RAX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDX,-0x68(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x10(%RAX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RAX,-0x60(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV (%RCX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RAX,-0x58(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x10(%RCX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RAX,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %R14,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %R9,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
CMP $0x2,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JAE 236f6c <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.18+0x14c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %R9,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 2373e9 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.18+0x5c9>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
MOV %RAX,-0xb8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x2,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA (%R9,%RCX,1),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %RAX,-0xc0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOVAPD -0x25cdd(%RIP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (25.0%)
MOV %RCX,-0xb0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %RCX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R14,-0xd0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %R12,-0xc8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
JMP 237238 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.18+0x418>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0xb0(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP %RAX,-0xb8(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
JNE 2373e9 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.18+0x5c9>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
LEA 0x271a3(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV -0x44(%RBP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CALL 25cd00 <@plt_start@+0x540>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
ADD $0x108,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	advec_mom.cpp:167-172
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:167-172

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 13.75 to 1.67 cycles (8.25x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

2% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

25% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
0% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:167
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:167

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVL: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:168

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 192 bytes. The binary function is storing 184 bytes.

General properties

nb instructions	111
nb uops	110
loop length	476
used x86 registers	14
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	28

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	13.75 cycles
front end	13.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	6.50	6.50	6.50	6.50	6.50	6.50	13.00	13.00	13.00	13.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	6.50	6.50	6.50	6.50	6.50	6.50	13.00	13.00	13.00	13.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	13.75
Dispatch	13.00
Overall L1	13.75

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	2%
load	25%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	10%
load	8%
store	11%
mul	12%
add-sub	7%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	25%
load	25%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	11%
load	12%
store	11%
mul	12%
add-sub	7%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 13.75 cycles. At this rate:

5% of peak load performance is reached (13.96 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
10% of peak store performance is reached (13.38 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 236e20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x108,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV (%RDX),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RCX),%R14D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
ADD $0x4,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %RAX,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
SUB %EAX,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JLE 2372bd <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.18+0x49d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV (%R8),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%R9),%R12D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOV %RAX,-0xa0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
INC %EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD $0x3,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMP %EAX,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JLE 2372bd <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.18+0x49d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %RAX,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
SUB %EAX,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
IMUL %R12,%R14	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
DEC %R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOVQ $0,-0xa8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %R14,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOVQ $0x1,-0x128(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVL $0,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA -0x128(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA 0x27597(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x48(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0xa8(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x40(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %ESI,-0x44(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 25ccf0 <@plt_start@+0x530>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV -0x40(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP %R14,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
CMOVL %RAX,%R14	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	1	0.33	scal (12.5%)
MOV %R14,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV -0xa8(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP %R14,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JG 2372ae <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.18+0x48e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV 0x30(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x28(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x20(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x18(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x10(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RSI),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %R8,-0x98(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x10(%RSI),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RSI,-0x90(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV (%RDX),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RSI,-0x88(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x10(%RDX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDX,-0x80(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV (%RDI),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDX,-0x78(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x10(%RDI),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDX,-0x70(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV (%RAX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDX,-0x68(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x10(%RAX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RAX,-0x60(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV (%RCX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RAX,-0x58(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x10(%RCX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RAX,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %R14,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %R9,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
CMP $0x2,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JAE 236f6c <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.18+0x14c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %R9,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 2373e9 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.18+0x5c9>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
MOV %RAX,-0xb8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x2,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA (%R9,%RCX,1),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %RAX,-0xc0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOVAPD -0x25cdd(%RIP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (25.0%)
MOV %RCX,-0xb0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %RCX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R14,-0xd0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %R12,-0xc8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
JMP 237238 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.18+0x418>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0xb0(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP %RAX,-0xb8(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
JNE 2373e9 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.18+0x5c9>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
LEA 0x271a3(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV -0x44(%RBP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CALL 25cd00 <@plt_start@+0x540>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
ADD $0x108,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	2.97	1.16
○Loop 178 - advec_mom.cpp:168-172 - exec	2.97	1.16
○Loop 177 - advec_mom.cpp:168-172 - exec	0.00	0.00

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