OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone .omp

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: advec_mom.cpp:108-139 [...]	Coverage (incl. loops): 5.76% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

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69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 108 - 139

--------------------------------------------------------------------------------

108: #pragma omp parallel for simd collapse(2)

109:     for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) {

110:       for (int i = (x_min - 1 + 1); i < (x_max + 1 + 2); i++)

111:         ({

112:           int upwind, donor, downwind, dif;

113:           double sigma, width, limiter, vdiffuw, vdiffdw, auw, adw, wind, advec_vel_s;

114:           if (node_flux(i, j) < 0.0) {

115:             upwind = i + 2;

116:             donor = i + 1;

117:             downwind = i;

118:             dif = donor;

119:           } else {

120:             upwind = i - 1;

121:             donor = i;

122:             downwind = i + 1;

123:             dif = upwind;

124:           }

125:           sigma = std::fabs(node_flux(i, j)) / (node_mass_pre(donor, j));

126:           width = celldx[i];

127:           vdiffuw = vel1(donor, j) - vel1(upwind, j);

128:           vdiffdw = vel1(downwind, j) - vel1(donor, j);

129:           limiter = 0.0;

130:           if (vdiffuw * vdiffdw > 0.0) {

131:             auw = std::fabs(vdiffuw);

132:             adw = std::fabs(vdiffdw);

133:             wind = 1.0;

134:             if (vdiffdw <= 0.0) wind = -1.0;

135:             limiter =

136:                 wind * std::fmin(std::fmin(width * ((2.0 - sigma) * adw / width + (1.0 + sigma) * auw / celldx[dif]) / 6.0, auw), adw);

137:           }

138:           advec_vel_s = vel1(donor, j) + (1.0 - sigma) * limiter;

139:           mom_flux(i, j) = advec_vel_s * node_flux(i, j);

0x235b60 PUSH	%RBP

0x235b61 MOV	%RSP,%RBP

0x235b64 PUSH	%R15

0x235b66 PUSH	%R14

0x235b68 PUSH	%R13

0x235b6a PUSH	%R12

0x235b6c PUSH	%RBX

0x235b6d SUB	$0x168,%RSP

0x235b74 MOV	(%RDX),%EBX

0x235b76 MOV	(%RCX),%R15D

0x235b79 INC	%EBX

0x235b7b ADD	$0x3,%R15D

0x235b7f SUB	%EBX,%R15D

0x235b82 JLE	2364a4

0x235b88 MOV	(%R8),%R13D

0x235b8b MOV	(%R9),%R14D

0x235b8e ADD	$0x3,%R14D

0x235b92 CMP	%R13D,%R14D

0x235b95 JLE	2364a4

0x235b9b SUB	%R13D,%R14D

0x235b9e IMUL	%R14,%R15

0x235ba2 DEC	%R15

0x235ba5 MOVQ	$0,-0xc8(%RBP)

0x235bb0 MOV	%R15,-0x40(%RBP)

0x235bb4 MOVQ	$0x1,-0x110(%RBP)

0x235bbf MOVL	$0,-0x48(%RBP)

0x235bc6 MOV	(%RDI),%ESI

0x235bc8 SUB	$0x8,%RSP

0x235bcc LEA	-0x110(%RBP),%RAX

0x235bd3 LEA	0x2878e(%RIP),%RDI

0x235bda LEA	-0x48(%RBP),%RCX

0x235bde LEA	-0xc8(%RBP),%R8

0x235be5 LEA	-0x40(%RBP),%R9

0x235be9 MOV	%ESI,-0x44(%RBP)

0x235bec MOV	$0x22,%EDX

0x235bf1 PUSH	$0x1

0x235bf3 PUSH	$0x1

0x235bf5 PUSH	%RAX

0x235bf6 CALL	25ccf0 <@plt_start@+0x530>

0x235bfb ADD	$0x20,%RSP

0x235bff MOV	-0x40(%RBP),%RAX

0x235c03 CMP	%R15,%RAX

0x235c06 CMOVL	%RAX,%R15

0x235c0a MOV	%R15,-0x40(%RBP)

0x235c0e MOV	-0xc8(%RBP),%RSI

0x235c15 CMP	%R15,%RSI

0x235c18 JG	236495

0x235c1e MOV	0x30(%RBP),%RAX

0x235c22 MOV	0x28(%RBP),%RCX

0x235c26 MOV	0x20(%RBP),%RDX

0x235c2a MOV	0x18(%RBP),%RDI

0x235c2e MOV	0x10(%RBP),%R8

0x235c32 MOV	(%R8),%R9

0x235c35 MOV	%R9,-0xc0(%RBP)

0x235c3c MOV	0x10(%R8),%R8

0x235c40 MOV	%R8,-0xb8(%RBP)

0x235c47 MOV	(%RDI),%R8

0x235c4a MOV	%R8,-0xb0(%RBP)

0x235c51 MOV	0x10(%RDI),%RDI

0x235c55 MOV	%RDI,-0xa8(%RBP)

0x235c5c MOV	(%RCX),%RDI

0x235c5f MOV	%RDI,-0xa0(%RBP)

0x235c66 MOV	0x10(%RCX),%R12

0x235c6a MOV	0x8(%RDX),%RCX

0x235c6e MOV	(%RAX),%RDX

0x235c71 MOV	%RDX,-0x98(%RBP)

0x235c78 MOV	0x10(%RAX),%RAX

0x235c7c MOV	%RAX,-0x90(%RBP)

0x235c83 MOV	%R15,%RAX

0x235c86 SUB	%RSI,%RAX

0x235c89 INC	%RAX

0x235c8c CMP	$0x4,%RAX

0x235c90 MOV	%R15,-0x108(%RBP)

0x235c97 JB	2364b6

0x235c9d MOV	%RAX,-0xf0(%RBP)

0x235ca4 MOV	%RAX,%RDX

0x235ca7 AND	$-0x4,%RDX

0x235cab LEA	(%RSI,%RDX,1),%RAX

0x235caf MOV	%RAX,-0xf8(%RBP)

0x235cb6 XORPD	%XMM12,%XMM12

0x235cbb MOV	%RDX,-0xe8(%RBP)

0x235cc2 MOV	%RDX,%R11

0x235cc5 MOV	%R14,-0x38(%RBP)

0x235cc9 MOV	%RCX,-0x100(%RBP)

0x235cd0 MOV	%EBX,-0x2c(%RBP)

0x235cd3 MOV	%R13,-0x68(%RBP)

0x235cd7 JMP	235e93

0x235cdc NOPL	(%RAX)

(172) 0x235ce0 PSHUFD	$0x55,%XMM12,%XMM12

(172) 0x235ce6 MOVD	%XMM12,%EDX

(172) 0x235ceb MOVSXD	%EDX,%RDX

(172) 0x235cee MOVAPD	-0x120(%RBP),%XMM1

(172) 0x235cf6 MOVHPD	(%RCX,%RDX,8),%XMM1

(172) 0x235cfb PXOR	%XMM12,%XMM12

(172) 0x235d00 MOV	-0x78(%RBP),%R11

(172) 0x235d04 DIVPD	%XMM1,%XMM4

(172) 0x235d08 ADDPD	%XMM4,%XMM5

(172) 0x235d0c DIVPD	-0x60(%RBP),%XMM3

(172) 0x235d11 ADDPD	%XMM3,%XMM13

(172) 0x235d16 MULPD	%XMM13,%XMM0

(172) 0x235d1b MULPD	%XMM5,%XMM6

(172) 0x235d1f MOVAPD	-0x24987(%RIP),%XMM1

(172) 0x235d27 DIVPD	%XMM1,%XMM0

(172) 0x235d2b MOVAPD	%XMM9,%XMM3

(172) 0x235d30 MINPD	%XMM0,%XMM3

(172) 0x235d34 CMPPD	$0x3,%XMM0,%XMM0

(172) 0x235d39 ANDPD	%XMM0,%XMM9

(172) 0x235d3e ANDNPD	%XMM3,%XMM0

(172) 0x235d42 DIVPD	%XMM1,%XMM6

(172) 0x235d46 ORPD	%XMM9,%XMM0

(172) 0x235d4b MOVAPD	%XMM10,%XMM3

(172) 0x235d50 MINPD	%XMM6,%XMM3

(172) 0x235d54 CMPPD	$0x3,%XMM6,%XMM6

(172) 0x235d59 ANDPD	%XMM6,%XMM10

(172) 0x235d5e ANDNPD	%XMM3,%XMM6

(172) 0x235d62 ORPD	%XMM10,%XMM6

(172) 0x235d67 MOVAPD	%XMM14,%XMM3

(172) 0x235d6c MINPD	%XMM0,%XMM3

(172) 0x235d70 CMPPD	$0x3,%XMM0,%XMM0

(172) 0x235d75 ANDPD	%XMM0,%XMM14

(172) 0x235d7a ANDNPD	%XMM3,%XMM0

(172) 0x235d7e ORPD	%XMM14,%XMM0

(172) 0x235d83 MOVAPD	%XMM7,%XMM3

(172) 0x235d87 MINPD	%XMM6,%XMM3

(172) 0x235d8b CMPPD	$0x3,%XMM6,%XMM6

(172) 0x235d90 ANDPD	%XMM6,%XMM7

(172) 0x235d94 ANDNPD	%XMM3,%XMM6

(172) 0x235d98 CMPPD	$0x6,%XMM12,%XMM15

(172) 0x235d9e ORPD	%XMM7,%XMM6

(172) 0x235da2 MOVAPD	%XMM0,%XMM3

(172) 0x235da6 MOVAPD	-0x249fe(%RIP),%XMM1

(172) 0x235dae XORPD	%XMM1,%XMM3

(172) 0x235db2 ANDPD	%XMM15,%XMM0

(172) 0x235db7 ANDNPD	%XMM3,%XMM15

(172) 0x235dbc CMPPD	$0x6,%XMM12,%XMM2

(172) 0x235dc2 ORPD	%XMM0,%XMM15

(172) 0x235dc7 MOVAPD	%XMM6,%XMM0

(172) 0x235dcb XORPD	%XMM1,%XMM0

(172) 0x235dcf ANDPD	%XMM2,%XMM6

(172) 0x235dd3 ANDNPD	%XMM0,%XMM2

(172) 0x235dd7 ORPD	%XMM6,%XMM2

(172) 0x235ddb MOVAPD	-0x180(%RBP),%XMM1

(172) 0x235de3 ANDPD	%XMM15,%XMM1

(172) 0x235de8 MOVAPD	-0xe0(%RBP),%XMM3

(172) 0x235df0 ANDPD	%XMM2,%XMM3

(172) 0x235df4 MOVAPD	-0x24a8c(%RIP),%XMM2

(172) 0x235dfc MOVAPD	%XMM2,%XMM0

(172) 0x235e00 SUBPD	%XMM8,%XMM0

(172) 0x235e05 MULPD	%XMM1,%XMM0

(172) 0x235e09 SUBPD	%XMM11,%XMM2

(172) 0x235e0e MULPD	%XMM3,%XMM2

(172) 0x235e12 ADDPD	-0x190(%RBP),%XMM0

(172) 0x235e1a ADDPD	-0x150(%RBP),%XMM2

(172) 0x235e22 MOVAPD	-0x170(%RBP),%XMM1

(172) 0x235e2a MULPD	%XMM0,%XMM1

(172) 0x235e2e MOVAPD	-0x160(%RBP),%XMM0

(172) 0x235e36 MULPD	%XMM2,%XMM0

(172) 0x235e3a MOV	-0x98(%RBP),%RDX

(172) 0x235e41 IMUL	%RDX,%R14

(172) 0x235e45 IMUL	%RDX,%R9

(172) 0x235e49 ADD	-0x80(%RBP),%R14

(172) 0x235e4d ADD	%R8,%R9

(172) 0x235e50 MOV	-0x90(%RBP),%R8

(172) 0x235e57 MOVLPD	%XMM1,(%R8,%R14,8)

(172) 0x235e5d MOVHPD	%XMM1,(%R8,%R9,8)

(172) 0x235e63 IMUL	%RDX,%RDI

(172) 0x235e67 IMUL	%RDX,%RAX

(172) 0x235e6b ADD	%R10,%RDI

(172) 0x235e6e ADD	-0x88(%RBP),%RAX

(172) 0x235e75 MOVLPD	%XMM0,(%R8,%RDI,8)

(172) 0x235e7b MOVHPD	%XMM0,(%R8,%RAX,8)

(172) 0x235e81 ADD	$0x4,%RSI

(172) 0x235e85 ADD	$-0x4,%R11

(172) 0x235e89 MOV	-0x38(%RBP),%R14

(172) 0x235e8d JE	23647e

(172) 0x235e93 MOV	%RSI,%RAX

(172) 0x235e96 SHR	$0x20,%RAX

(172) 0x235e9a JE	235ed0

(172) 0x235e9c MOV	%RSI,%RAX

(172) 0x235e9f CQTO

(172) 0x235ea1 IDIV	%R14

(172) 0x235ea4 MOV	%RDX,%R8

(172) 0x235ea7 MOV	%RAX,%RDI

(172) 0x235eaa LEA	0x1(%RSI),%RAX

(172) 0x235eae MOV	%RAX,%RDX

(172) 0x235eb1 SHR	$0x20,%RDX

(172) 0x235eb5 JE	235ee9

(172) 0x235eb7 CQTO

(172) 0x235eb9 IDIV	%R14

(172) 0x235ebc MOV	%RDX,%R10

(172) 0x235ebf MOV	%RAX,%R9

(172) 0x235ec2 JMP	235ef4

0x235ec4 NOPW	%CS:(%RAX,%RAX,1)

(172) 0x235ed0 MOV	%ESI,%EAX

(172) 0x235ed2 XOR	%EDX,%EDX

(172) 0x235ed4 DIV	%R14D

(172) 0x235ed7 MOV	%EDX,%R8D

(172) 0x235eda MOV	%EAX,%EDI

(172) 0x235edc LEA	0x1(%RSI),%RAX

(172) 0x235ee0 MOV	%RAX,%RDX

(172) 0x235ee3 SHR	$0x20,%RDX

(172) 0x235ee7 JNE	235eb7

(172) 0x235ee9 XOR	%EDX,%EDX

(172) 0x235eeb DIV	%R14D

(172) 0x235eee MOV	%EDX,%R10D

(172) 0x235ef1 MOV	%EAX,%R9D

(172) 0x235ef4 LEA	0x2(%RSI),%RAX

(172) 0x235ef8 MOV	%RAX,%RDX

(172) 0x235efb SHR	$0x20,%RDX

(172) 0x235eff MOV	%R11,-0x78(%RBP)

(172) 0x235f03 JE	235f20

(172) 0x235f05 CQTO

(172) 0x235f07 IDIV	%R14

(172) 0x235f0a MOV	%RDX,%R14

(172) 0x235f0d MOV	%RAX,%R11

(172) 0x235f10 JMP	235f2b

0x235f12 NOPW	%CS:(%RAX,%RAX,1)

(172) 0x235f20 XOR	%EDX,%EDX

(172) 0x235f22 DIV	%R14D

(172) 0x235f25 MOV	%EDX,%R14D

(172) 0x235f28 MOV	%EAX,%R11D

(172) 0x235f2b LEA	0x3(%RSI),%RAX

(172) 0x235f2f MOV	%RAX,%RDX

(172) 0x235f32 SHR	$0x20,%RDX

(172) 0x235f36 MOV	%RSI,-0x70(%RBP)

(172) 0x235f3a JE	235f50

(172) 0x235f3c CQTO

(172) 0x235f3e IDIVQ	-0x38(%RBP)

(172) 0x235f42 JMP	235f55

0x235f44 NOPW	%CS:(%RAX,%RAX,1)

(172) 0x235f50 XOR	%EDX,%EDX

(172) 0x235f52 DIVL	-0x38(%RBP)

(172) 0x235f55 ADD	%EBX,%EDI

(172) 0x235f57 ADD	%EBX,%R9D

(172) 0x235f5a ADD	%EBX,%R11D

(172) 0x235f5d ADD	%EBX,%EAX

(172) 0x235f5f ADD	%R13D,%R8D

(172) 0x235f62 ADD	%R13D,%R10D

(172) 0x235f65 MOVD	%R10D,%XMM0

(172) 0x235f6a MOVD	%R8D,%XMM1

(172) 0x235f6f PUNPCKLDQ	%XMM0,%XMM1

(172) 0x235f73 ADD	%R13D,%R14D

(172) 0x235f76 ADD	%R13D,%EDX

(172) 0x235f79 MOVD	%EDX,%XMM2

(172) 0x235f7d MOVD	%R14D,%XMM0

(172) 0x235f82 PUNPCKLDQ	%XMM2,%XMM0

(172) 0x235f86 MOVSXD	%R8D,%RSI

(172) 0x235f89 MOVSXD	%R10D,%R10

(172) 0x235f8c MOVQ	%R10,%XMM2

(172) 0x235f91 MOVQ	%RSI,%XMM5

(172) 0x235f96 PUNPCKLQDQ	%XMM2,%XMM5

(172) 0x235f9a MOVSXD	%R14D,%RCX

(172) 0x235f9d MOVSXD	%EDX,%RBX

(172) 0x235fa0 MOVQ	%RBX,%XMM2

(172) 0x235fa5 MOVQ	%RCX,%XMM13

(172) 0x235faa MOVSXD	%EDI,%R14

(172) 0x235fad MOVSXD	%R9D,%R9

(172) 0x235fb0 MOVSXD	%R11D,%RDI

(172) 0x235fb3 CLTQ

(172) 0x235fb5 MOV	-0xc0(%RBP),%R15

(172) 0x235fbc MOV	%R15,%RDX

(172) 0x235fbf IMUL	%R14,%RDX

(172) 0x235fc3 MOV	%R15,%R8

(172) 0x235fc6 IMUL	%R9,%R8

(172) 0x235fca MOV	%R15,%R11

(172) 0x235fcd IMUL	%RDI,%R11

(172) 0x235fd1 IMUL	%RAX,%R15

(172) 0x235fd5 MOV	%RSI,%R13

(172) 0x235fd8 MOV	%RSI,-0x80(%RBP)

(172) 0x235fdc ADD	%RSI,%RDX

(172) 0x235fdf MOV	%R10,-0x60(%RBP)

(172) 0x235fe3 ADD	%R10,%R8

(172) 0x235fe6 MOV	%RCX,-0xe0(%RBP)

(172) 0x235fed ADD	%RCX,%R11

(172) 0x235ff0 MOV	-0xb8(%RBP),%R10

(172) 0x235ff7 MOVSD	(%R10,%RDX,8),%XMM15

(172) 0x235ffd MOVHPD	(%R10,%R8,8),%XMM15

(172) 0x236003 MOV	%RBX,%RCX

(172) 0x236006 MOV	%RBX,-0x88(%RBP)

(172) 0x23600d ADD	%RBX,%R15

(172) 0x236010 MOVSD	(%R10,%R11,8),%XMM11

(172) 0x236016 MOVHPD	(%R10,%R15,8),%XMM11

(172) 0x23601c PUNPCKLQDQ	%XMM2,%XMM13

(172) 0x236021 MOVAPD	%XMM15,-0x170(%RBP)

(172) 0x23602a CMPPD	$0x1,%XMM12,%XMM15

(172) 0x236030 MOVAPD	%XMM15,%XMM3

(172) 0x236035 SHUFPS	$-0x18,%XMM15,%XMM3

(172) 0x23603a MOVAPD	%XMM11,-0x160(%RBP)

(172) 0x236043 CMPPD	$0x1,%XMM12,%XMM11

(172) 0x236049 MOVAPD	%XMM11,%XMM4

(172) 0x23604e SHUFPS	$-0x18,%XMM11,%XMM4

(172) 0x236053 MOVDQA	%XMM1,%XMM7

(172) 0x236057 PCMPEQD	%XMM14,%XMM14

(172) 0x23605c PSUBD	%XMM14,%XMM7

(172) 0x236061 MOVDQA	%XMM0,%XMM12

(172) 0x236066 PSUBD	%XMM14,%XMM12

(172) 0x23606b PXOR	%XMM2,%XMM2

(172) 0x23606f PCMPGTD	%XMM7,%XMM2

(172) 0x236073 MOVDQA	%XMM7,%XMM6

(172) 0x236077 PUNPCKLDQ	%XMM2,%XMM6

(172) 0x23607b PXOR	%XMM2,%XMM2

(172) 0x23607f PCMPGTD	%XMM12,%XMM2

(172) 0x236084 MOVDQA	%XMM12,%XMM9

(172) 0x236089 PUNPCKLDQ	%XMM2,%XMM9

(172) 0x23608e MOVAPS	%XMM15,%XMM8

(172) 0x236092 PANDN	%XMM6,%XMM8

(172) 0x236097 MOVDQA	%XMM5,%XMM2

(172) 0x23609b PAND	%XMM15,%XMM2

(172) 0x2360a0 POR	%XMM8,%XMM2

(172) 0x2360a5 MOVDQA	%XMM1,%XMM10

(172) 0x2360aa PADDD	%XMM14,%XMM10

(172) 0x2360af PAND	%XMM15,%XMM6

(172) 0x2360b4 PANDN	%XMM5,%XMM15

(172) 0x2360b9 MOVAPS	%XMM11,%XMM8

(172) 0x2360bd PANDN	%XMM9,%XMM8

(172) 0x2360c2 POR	%XMM6,%XMM15

(172) 0x2360c7 MOVDQA	%XMM13,%XMM6

(172) 0x2360cc PAND	%XMM11,%XMM6

(172) 0x2360d1 PAND	%XMM11,%XMM9

(172) 0x2360d6 PANDN	%XMM13,%XMM11

(172) 0x2360db MOVDQA	%XMM0,%XMM13

(172) 0x2360e0 PADDD	%XMM14,%XMM13

(172) 0x2360e5 MOVDQA	-0x24e4d(%RIP),%XMM5

(172) 0x2360ed PADDD	%XMM5,%XMM1

(172) 0x2360f1 POR	%XMM9,%XMM11

(172) 0x2360f6 MOVAPS	%XMM3,%XMM5

(172) 0x2360f9 ANDNPS	%XMM10,%XMM5

(172) 0x2360fd MOVAPS	%XMM4,%XMM14

(172) 0x236101 ANDNPS	%XMM13,%XMM14

(172) 0x236105 PAND	%XMM3,%XMM1

(172) 0x236109 POR	%XMM5,%XMM1

(172) 0x23610d MOV	-0xb0(%RBP),%R13

(172) 0x236114 MOV	%R13,%RDX

(172) 0x236117 IMUL	%R14,%RDX

(172) 0x23611b MOV	%R13,%R8

(172) 0x23611e IMUL	%R9,%R8

(172) 0x236122 MOV	%R13,%R11

(172) 0x236125 IMUL	%RDI,%R11

(172) 0x236129 IMUL	%RAX,%R13

(172) 0x23612d MOVQ	%XMM15,%R15

(172) 0x236132 ADD	%R15,%RDX

(172) 0x236135 PSHUFD	$0x4e,%XMM15,%XMM9

(172) 0x23613b MOV	-0xa8(%RBP),%RBX

(172) 0x236142 MOVSD	(%RBX,%RDX,8),%XMM10

(172) 0x236148 MOVQ	%XMM9,%R10

(172) 0x23614d ADD	%R10,%R8

(172) 0x236150 MOVHPS	(%RBX,%R8,8),%XMM10

(172) 0x236155 MOVAPS	%XMM10,-0x140(%RBP)

(172) 0x23615d MOVQ	%XMM11,%R8

(172) 0x236162 ADD	%R8,%R11

(172) 0x236165 PSHUFD	$0x4e,%XMM11,%XMM9

(172) 0x23616b MOVSD	(%RBX,%R11,8),%XMM10

(172) 0x236171 MOVQ	%XMM9,%RDX

(172) 0x236176 ADD	%RDX,%R13

(172) 0x236179 MOVHPS	(%RBX,%R13,8),%XMM10

(172) 0x23617e MOVAPS	%XMM10,-0x130(%RBP)

(172) 0x236186 MOV	-0xa0(%RBP),%R11

(172) 0x23618d MOV	%R11,%RCX

(172) 0x236190 IMUL	%R14,%RCX

(172) 0x236194 ADD	%RCX,%R15

(172) 0x236197 MOVSD	(%R12,%R15,8),%XMM13

(172) 0x23619d MOV	%R11,%R15

(172) 0x2361a0 IMUL	%R9,%R15

(172) 0x2361a4 ADD	%R15,%R10

(172) 0x2361a7 MOVHPD	(%R12,%R10,8),%XMM13

(172) 0x2361ad MOV	%R11,%R13

(172) 0x2361b0 IMUL	%RDI,%R13

(172) 0x2361b4 ADD	%R13,%R8

(172) 0x2361b7 MOVD	%XMM1,%R10D

(172) 0x2361bc PSHUFD	$0x55,%XMM1,%XMM1

(172) 0x2361c1 MOVD	%XMM1,%EBX

(172) 0x2361c5 MOVSD	(%R12,%R8,8),%XMM1

(172) 0x2361cb MOV	%R11,%R8

(172) 0x2361ce IMUL	%RAX,%R8

(172) 0x2361d2 ADD	%R8,%RDX

(172) 0x2361d5 MOVHPS	(%R12,%RDX,8),%XMM1

(172) 0x2361da MOVAPS	%XMM1,-0x150(%RBP)

(172) 0x2361e1 PADDD	-0x24f49(%RIP),%XMM0

(172) 0x2361e9 PAND	%XMM4,%XMM0

(172) 0x2361ed POR	%XMM14,%XMM0

(172) 0x2361f2 MOVSXD	%R10D,%RDX

(172) 0x2361f5 MOVSXD	%EBX,%R10

(172) 0x2361f8 ADD	%RCX,%RDX

(172) 0x2361fb ADD	%R15,%R10

(172) 0x2361fe MOVSD	(%R12,%RDX,8),%XMM10

(172) 0x236204 MOVHPD	(%R12,%R10,8),%XMM10

(172) 0x23620a MOVD	%XMM0,%EDX

(172) 0x23620e PSHUFD	$0x55,%XMM0,%XMM0

(172) 0x236213 MOVD	%XMM0,%R10D

(172) 0x236218 MOVSXD	%EDX,%RDX

(172) 0x23621b MOVSXD	%R10D,%R10

(172) 0x23621e ADD	%R13,%RDX

(172) 0x236221 ADD	%R8,%R10

(172) 0x236224 MOVSD	(%R12,%RDX,8),%XMM1

(172) 0x23622a MOVHPD	(%R12,%R10,8),%XMM1

(172) 0x236230 POR	%XMM8,%XMM6

(172) 0x236235 MOVQ	%XMM2,%RDX

(172) 0x23623a ADD	%RCX,%RDX

(172) 0x23623d PSHUFD	$0x4e,%XMM2,%XMM0

(172) 0x236242 MOVQ	%XMM0,%R10

(172) 0x236247 ADD	%R15,%R10

(172) 0x23624a MOVQ	%XMM6,%R11

(172) 0x23624f ADD	%R13,%R11

(172) 0x236252 PSHUFD	$0x4e,%XMM6,%XMM0

(172) 0x236257 MOVQ	%XMM0,%RBX

(172) 0x23625c ADD	%R8,%RBX

(172) 0x23625f MOVSD	(%R12,%RDX,8),%XMM15

(172) 0x236265 MOVHPD	(%R12,%R10,8),%XMM15

(172) 0x23626b MOVAPD	%XMM13,%XMM9

(172) 0x236270 SUBPD	%XMM10,%XMM9

(172) 0x236275 MOVSD	(%R12,%R11,8),%XMM2

(172) 0x23627b MOVHPD	(%R12,%RBX,8),%XMM2

(172) 0x236281 SUBPD	%XMM13,%XMM15

(172) 0x236286 MOVAPD	%XMM9,%XMM11

(172) 0x23628b MULPD	%XMM15,%XMM11

(172) 0x236290 PXOR	%XMM8,%XMM8

(172) 0x236295 UCOMISD	%XMM8,%XMM11

(172) 0x23629a MOV	-0x100(%RBP),%RCX

(172) 0x2362a1 JBE	2362ac

(172) 0x2362a3 MOV	-0x80(%RBP),%RDX

(172) 0x2362a7 MOVSD	(%RCX,%RDX,8),%XMM0

(172) 0x2362ac PXOR	%XMM6,%XMM6

(172) 0x2362b0 CMPPD	$0x1,%XMM11,%XMM6

(172) 0x2362b6 PEXTRW	$0x4,%XMM6,%R13D

(172) 0x2362bc TEST	$0x1,%R13B

(172) 0x2362c0 MOVAPD	%XMM13,-0x190(%RBP)

(172) 0x2362c9 MOVAPS	%XMM6,-0x180(%RBP)

(172) 0x2362d0 JE	2362f0

(172) 0x2362d2 MOV	-0x60(%RBP),%R8

(172) 0x2362d6 MOVHPD	(%RCX,%R8,8),%XMM0

(172) 0x2362dc MOV	-0x2c(%RBP),%EBX

(172) 0x2362df MOV	-0xe0(%RBP),%R10

(172) 0x2362e6 JMP	2362fe

0x2362e8 NOPL	(%RAX,%RAX,1)

(172) 0x2362f0 MOV	-0x2c(%RBP),%EBX

(172) 0x2362f3 MOV	-0xe0(%RBP),%R10

(172) 0x2362fa MOV	-0x60(%RBP),%R8

(172) 0x2362fe MOV	-0x70(%RBP),%RSI

(172) 0x236302 MOVAPD	-0x150(%RBP),%XMM6

(172) 0x23630a MOVAPD	%XMM6,%XMM10

(172) 0x23630f SUBPD	%XMM1,%XMM10

(172) 0x236314 SUBPD	%XMM6,%XMM2

(172) 0x236318 MOVAPD	%XMM10,%XMM13

(172) 0x23631d MULPD	%XMM2,%XMM13

(172) 0x236322 UCOMISD	%XMM8,%XMM13

(172) 0x236327 JBE	23632f

(172) 0x236329 MOVSD	(%RCX,%R10,8),%XMM6

(172) 0x23632f XORPD	%XMM1,%XMM1

(172) 0x236333 CMPPD	$0x1,%XMM13,%XMM1

(172) 0x236339 MOVAPD	%XMM1,-0xe0(%RBP)

(172) 0x236341 PEXTRW	$0x4,%XMM1,%R11D

(172) 0x236347 TEST	$0x1,%R11B

(172) 0x23634b JE	236359

(172) 0x23634d MOV	-0x88(%RBP),%RDX

(172) 0x236354 MOVHPD	(%RCX,%RDX,8),%XMM6

(172) 0x236359 MOVAPD	-0x140(%RBP),%XMM1

(172) 0x236361 PAND	%XMM3,%XMM7

(172) 0x236365 POR	%XMM5,%XMM7

(172) 0x236369 UCOMISD	%XMM8,%XMM11

(172) 0x23636e JBE	23637c

(172) 0x236370 MOVD	%XMM7,%EDX

(172) 0x236374 MOVSXD	%EDX,%RDX

(172) 0x236377 MOVSD	(%RCX,%RDX,8),%XMM5

(172) 0x23637c TEST	$0x1,%R13B

(172) 0x236380 JE	236392

(172) 0x236382 PSHUFD	$0x55,%XMM7,%XMM3

(172) 0x236387 MOVD	%XMM3,%EDX

(172) 0x23638b MOVSXD	%EDX,%RDX

(172) 0x23638e MOVHPS	(%RCX,%RDX,8),%XMM5

(172) 0x236392 MOVAPS	%XMM5,-0x60(%RBP)

(172) 0x236396 MOV	-0x68(%RBP),%R13

(172) 0x23639a MOVAPD	-0x130(%RBP),%XMM5

(172) 0x2363a2 PAND	%XMM4,%XMM12

(172) 0x2363a7 POR	%XMM14,%XMM12

(172) 0x2363ac UCOMISD	%XMM8,%XMM13

(172) 0x2363b1 JBE	2363c7

(172) 0x2363b3 MOVD	%XMM12,%EDX

(172) 0x2363b8 MOVSXD	%EDX,%RDX

(172) 0x2363bb MOVSD	(%RCX,%RDX,8),%XMM3

(172) 0x2363c0 MOVAPS	%XMM3,-0x120(%RBP)

(172) 0x2363c7 MOVAPD	-0x170(%RBP),%XMM8

(172) 0x2363d0 MOVAPD	-0x25158(%RIP),%XMM3

(172) 0x2363d8 ANDPD	%XMM3,%XMM8

(172) 0x2363dd DIVPD	%XMM1,%XMM8

(172) 0x2363e2 MOVAPD	-0x160(%RBP),%XMM11

(172) 0x2363eb ANDPD	%XMM3,%XMM11

(172) 0x2363f0 DIVPD	%XMM5,%XMM11

(172) 0x2363f5 ANDPD	%XMM3,%XMM9

(172) 0x2363fa ANDPD	%XMM3,%XMM10

(172) 0x2363ff MOVAPD	%XMM15,%XMM14

(172) 0x236404 ANDPD	%XMM3,%XMM14

(172) 0x236409 MOVAPD	%XMM2,%XMM7

(172) 0x23640d ANDPD	%XMM3,%XMM7

(172) 0x236411 MOVAPD	-0x250c9(%RIP),%XMM5

(172) 0x236419 MOVAPD	%XMM5,%XMM13

(172) 0x23641e SUBPD	%XMM8,%XMM13

(172) 0x236423 SUBPD	%XMM11,%XMM5

(172) 0x236428 MULPD	%XMM14,%XMM13

(172) 0x23642d MULPD	%XMM7,%XMM5

(172) 0x236431 DIVPD	%XMM0,%XMM13

(172) 0x236436 DIVPD	%XMM6,%XMM5

(172) 0x23643a MOVAPD	%XMM8,%XMM3

(172) 0x23643f MOVAPD	-0x250d7(%RIP),%XMM1

(172) 0x236447 ADDPD	%XMM1,%XMM3

(172) 0x23644b MOVAPD	%XMM11,%XMM4

(172) 0x236450 ADDPD	%XMM1,%XMM4

(172) 0x236454 MULPD	%XMM9,%XMM3

(172) 0x236459 MULPD	%XMM10,%XMM4

(172) 0x23645e TEST	$0x1,%R11B

(172) 0x236462 JNE	235ce0

(172) 0x236468 PXOR	%XMM12,%XMM12

(172) 0x23646d MOV	-0x78(%RBP),%R11

(172) 0x236471 MOVAPD	-0x120(%RBP),%XMM1

(172) 0x236479 JMP	235d04

0x23647e MOV	-0xe8(%RBP),%RAX

0x236485 CMP	%RAX,-0xf0(%RBP)

0x23648c MOV	-0xf8(%RBP),%RSI

0x236493 JNE	2364b6

0x236495 LEA	0x27ee4(%RIP),%RDI

0x23649c MOV	-0x44(%RBP),%ESI

0x23649f CALL	25cd00 <@plt_start@+0x540>

0x2364a4 ADD	$0x168,%RSP

0x2364ab POP	%RBX

0x2364ac POP	%R12

0x2364ae POP	%R13

0x2364b0 POP	%R14

0x2364b2 POP	%R15

0x2364b4 POP	%RBP

0x2364b5 RET

0x2364b6 XORPD	%XMM0,%XMM0

0x2364ba MOVAPD	-0x25242(%RIP),%XMM1

0x2364c2 MOVSD	-0x253ea(%RIP),%XMM2

0x2364ca MOVAPD	-0x25112(%RIP),%XMM3

0x2364d2 MOVSD	-0x2540a(%RIP),%XMM4

0x2364da MOVAPD	-0x25132(%RIP),%XMM5

0x2364e2 MOVSD	-0x253e2(%RIP),%XMM6

0x2364ea MOV	-0xa8(%RBP),%R11

0x2364f1 JMP	236541

0x2364f3 NOPW	%CS:(%RAX,%RAX,1)

(171) 0x236500 MOVAPD	%XMM6,%XMM10

(171) 0x236505 SUBSD	%XMM8,%XMM10

(171) 0x23650a MULSD	%XMM11,%XMM10

(171) 0x23650f ADDSD	%XMM9,%XMM10

(171) 0x236514 MULSD	%XMM10,%XMM7

(171) 0x236519 IMUL	-0x98(%RBP),%RAX

(171) 0x236521 ADD	%RSI,%RAX

(171) 0x236524 MOV	-0x90(%RBP),%RDX

(171) 0x23652b MOVSD	%XMM7,(%RDX,%RAX,8)

(171) 0x236530 LEA	0x1(%R15),%RSI

(171) 0x236534 CMP	-0x108(%RBP),%R15

(171) 0x23653b JGE	236495

(171) 0x236541 MOV	%RSI,%RAX

(171) 0x236544 MOV	%RSI,%R15

(171) 0x236547 SHR	$0x20,%RAX

(171) 0x23654b JE	236560

(171) 0x23654d MOV	%RSI,%RAX

(171) 0x236550 CQTO

(171) 0x236552 IDIV	%R14

(171) 0x236555 JMP	236567

0x236557 NOPW	(%RAX,%RAX,1)

(171) 0x236560 MOV	%ESI,%EAX

(171) 0x236562 XOR	%EDX,%EDX

(171) 0x236564 DIV	%R14D

(171) 0x236567 ADD	%EBX,%EAX

(171) 0x236569 LEA	(%RDX,%R13,1),%EDI

(171) 0x23656d MOVSXD	%EDI,%RSI

(171) 0x236570 CLTQ

(171) 0x236572 MOV	-0xc0(%RBP),%R8

(171) 0x236579 IMUL	%RAX,%R8

(171) 0x23657d ADD	%RSI,%R8

(171) 0x236580 MOV	-0xb8(%RBP),%R9

(171) 0x236587 MOVSD	(%R9,%R8,8),%XMM7

(171) 0x23658d UCOMISD	%XMM7,%XMM0

(171) 0x236591 LEA	0x1(%R13,%RDX,1),%EDX

(171) 0x236596 MOVSXD	%EDX,%R8

(171) 0x236599 JBE	2365b0

(171) 0x23659b ADD	$0x2,%EDI

(171) 0x23659e MOV	%RSI,%R9

(171) 0x2365a1 JMP	2365ba

0x2365a3 NOPW	%CS:(%RAX,%RAX,1)

(171) 0x2365b0 DEC	%EDI

(171) 0x2365b2 MOV	%R8,%R9

(171) 0x2365b5 MOV	%RSI,%R8

(171) 0x2365b8 MOV	%EDI,%EDX

(171) 0x2365ba MOVAPD	%XMM7,%XMM8

(171) 0x2365bf ANDPD	%XMM1,%XMM8

(171) 0x2365c4 MOV	-0xb0(%RBP),%R10

(171) 0x2365cb IMUL	%RAX,%R10

(171) 0x2365cf ADD	%R8,%R10

(171) 0x2365d2 DIVSD	(%R11,%R10,8),%XMM8

(171) 0x2365d8 MOV	-0xa0(%RBP),%R10

(171) 0x2365df IMUL	%RAX,%R10

(171) 0x2365e3 ADD	%R10,%R8

(171) 0x2365e6 MOVSD	(%R12,%R8,8),%XMM9

(171) 0x2365ec MOVSXD	%EDI,%RDI

(171) 0x2365ef ADD	%R10,%RDI

(171) 0x2365f2 ADD	%R9,%R10

(171) 0x2365f5 MOVSD	(%R12,%R10,8),%XMM10

(171) 0x2365fb MOVAPD	%XMM9,%XMM11

(171) 0x236600 MOVHPD	(%R12,%RDI,8),%XMM11

(171) 0x236606 UNPCKLPD	%XMM9,%XMM10

(171) 0x23660b SUBPD	%XMM11,%XMM10

(171) 0x236610 MOVAPD	%XMM10,%XMM12

(171) 0x236615 UNPCKHPD	%XMM10,%XMM12

(171) 0x23661a MULSD	%XMM10,%XMM12

(171) 0x23661f XORPD	%XMM11,%XMM11

(171) 0x236624 UCOMISD	%XMM11,%XMM12

(171) 0x236629 JBE	236500

(171) 0x23662f MOVSD	(%RCX,%RSI,8),%XMM13

(171) 0x236635 MOVAPD	%XMM10,%XMM11

(171) 0x23663a ANDPD	%XMM1,%XMM11

(171) 0x23663f UNPCKLPD	%XMM8,%XMM14

(171) 0x236644 MOVAPD	%XMM2,%XMM12

(171) 0x236649 SUBSD	%XMM8,%XMM12

(171) 0x23664e ADDPD	%XMM3,%XMM14

(171) 0x236653 MOVSD	%XMM12,%XMM14

(171) 0x236658 MOVSXD	%EDX,%RDX

(171) 0x23665b MULPD	%XMM11,%XMM14

(171) 0x236660 MOVAPD	%XMM13,%XMM12

(171) 0x236665 MOVHPD	(%RCX,%RDX,8),%XMM12

(171) 0x23666b DIVPD	%XMM12,%XMM14

(171) 0x236670 MOVAPD	%XMM14,%XMM12

(171) 0x236675 UNPCKHPD	%XMM14,%XMM12

(171) 0x23667a ADDSD	%XMM14,%XMM12

(171) 0x23667f MULSD	%XMM13,%XMM12

(171) 0x236684 DIVSD	%XMM4,%XMM12

(171) 0x236689 PSHUFD	$-0x12,%XMM11,%XMM13

(171) 0x23668f MOVDQA	%XMM13,%XMM14

(171) 0x236694 MINSD	%XMM12,%XMM14

(171) 0x236699 CMPSD	$0x3,%XMM12,%XMM12

(171) 0x23669f MOVAPD	%XMM12,%XMM15

(171) 0x2366a4 ANDNPD	%XMM14,%XMM15

(171) 0x2366a9 ANDPD	%XMM13,%XMM12

(171) 0x2366ae ORPD	%XMM15,%XMM12

(171) 0x2366b3 MOVAPD	%XMM11,%XMM13

(171) 0x2366b8 MINSD	%XMM12,%XMM13

(171) 0x2366bd CMPSD	$0x3,%XMM12,%XMM12

(171) 0x2366c3 MOVAPD	%XMM12,%XMM14

(171) 0x2366c8 ANDNPD	%XMM13,%XMM14

(171) 0x2366cd ANDPD	%XMM11,%XMM12

(171) 0x2366d2 ORPD	%XMM14,%XMM12

(171) 0x2366d7 CMPSD	$0x6,%XMM0,%XMM10

(171) 0x2366dd MOVAPD	%XMM10,%XMM11

(171) 0x2366e2 ANDPD	%XMM12,%XMM11

(171) 0x2366e7 XORPD	%XMM5,%XMM12

(171) 0x2366ec ANDNPD	%XMM12,%XMM10

(171) 0x2366f1 ORPD	%XMM11,%XMM10

(171) 0x2366f6 MOVAPD	%XMM10,%XMM11

(171) 0x2366fb JMP	236500

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	advec_mom.cpp:108-139
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:108-139

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 14.25 to 2.13 cycles (6.71x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 14.25 to 1.34 cycles (10.60x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:108
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:108

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVL: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:109

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 256 bytes. The binary function is storing 156 bytes.

General properties

nb instructions	119
nb uops	114
loop length	582
used x86 registers	15
used mmx registers	0
used xmm registers	8
used ymm registers	0
used zmm registers	0
nb stack references	25

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	14.25 cycles
front end	14.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	6.50	6.50	6.50	6.50	6.50	6.50	13.75	13.75	13.75	13.75	0.00	0.00	0.00	0.00	0.00	0.00
cycles	6.50	6.50	6.50	6.50	6.50	6.50	13.75	13.75	13.75	13.75	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	14.25
Dispatch	13.75
Overall L1	14.25

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	62%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	10%
load	23%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	22%

Vector efficiency ratios

INT

all	10%
load	8%
store	11%
mul	12%
add-sub	7%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	20%
load	18%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	11%
load	13%
store	11%
mul	12%
add-sub	7%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 14.25 cycles. At this rate:

7% of peak load performance is reached (17.96 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (10.95 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 235b60

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x168,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV (%RDX),%EBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOV (%RCX),%R15D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
INC %EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
ADD $0x3,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
SUB %EBX,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JLE 2364a4 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.12+0x944>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV (%R8),%R13D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOV (%R9),%R14D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
ADD $0x3,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMP %R13D,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JLE 2364a4 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.12+0x944>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
SUB %R13D,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
IMUL %R14,%R15	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
DEC %R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOVQ $0,-0xc8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %R15,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOVQ $0x1,-0x110(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVL $0,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA -0x110(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA 0x2878e(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x48(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0xc8(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x40(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %ESI,-0x44(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 25ccf0 <@plt_start@+0x530>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV -0x40(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP %R15,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
CMOVL %RAX,%R15	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	1	0.33	scal (12.5%)
MOV %R15,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV -0xc8(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP %R15,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JG 236495 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.12+0x935>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV 0x30(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x28(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x20(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x18(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x10(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%R8),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %R9,-0xc0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x10(%R8),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %R8,-0xb8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV (%RDI),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %R8,-0xb0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x10(%RDI),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDI,-0xa8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV (%RCX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDI,-0xa0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x10(%RCX),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV 0x8(%RDX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RAX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDX,-0x98(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x10(%RAX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RAX,-0x90(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %R15,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RSI,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
CMP $0x4,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOV %R15,-0x108(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
JB 2364b6 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.12+0x956>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %RAX,-0xf0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %RAX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x4,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA (%RSI,%RDX,1),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %RAX,-0xf8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
XORPD %XMM12,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %RDX,-0xe8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %RDX,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %R14,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %RCX,-0x100(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %EBX,-0x2c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %R13,-0x68(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
JMP 235e93 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.12+0x333>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0xe8(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP %RAX,-0xf0(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
MOV -0xf8(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
JNE 2364b6 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.12+0x956>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
LEA 0x27ee4(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV -0x44(%RBP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CALL 25cd00 <@plt_start@+0x540>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
ADD $0x168,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
XORPD %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOVAPD -0x25242(%RIP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (25.0%)
MOVSD -0x253ea(%RIP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
MOVAPD -0x25112(%RIP),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (25.0%)
MOVSD -0x2540a(%RIP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
MOVAPD -0x25132(%RIP),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (25.0%)
MOVSD -0x253e2(%RIP),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
MOV -0xa8(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
JMP 236541 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.12+0x9e1>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	advec_mom.cpp:108-139
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:108-139

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 14.25 to 2.13 cycles (6.71x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:108
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:108

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVL: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:109

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 256 bytes. The binary function is storing 156 bytes.

General properties

nb instructions	119
nb uops	114
loop length	582
used x86 registers	15
used mmx registers	0
used xmm registers	8
used ymm registers	0
used zmm registers	0
nb stack references	25

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	14.25 cycles
front end	14.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	6.50	6.50	6.50	6.50	6.50	6.50	13.75	13.75	13.75	13.75	0.00	0.00	0.00	0.00	0.00	0.00
cycles	6.50	6.50	6.50	6.50	6.50	6.50	13.75	13.75	13.75	13.75	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	14.25
Dispatch	13.75
Overall L1	14.25

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	62%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	10%
load	23%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	22%

Vector efficiency ratios

INT

all	10%
load	8%
store	11%
mul	12%
add-sub	7%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	20%
load	18%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	11%
load	13%
store	11%
mul	12%
add-sub	7%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 14.25 cycles. At this rate:

7% of peak load performance is reached (17.96 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (10.95 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 235b60

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x168,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV (%RDX),%EBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOV (%RCX),%R15D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
INC %EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
ADD $0x3,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
SUB %EBX,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JLE 2364a4 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.12+0x944>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV (%R8),%R13D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOV (%R9),%R14D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
ADD $0x3,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMP %R13D,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JLE 2364a4 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.12+0x944>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
SUB %R13D,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
IMUL %R14,%R15	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
DEC %R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOVQ $0,-0xc8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %R15,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOVQ $0x1,-0x110(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVL $0,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA -0x110(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA 0x2878e(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x48(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0xc8(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x40(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %ESI,-0x44(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 25ccf0 <@plt_start@+0x530>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV -0x40(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP %R15,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
CMOVL %RAX,%R15	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	1	0.33	scal (12.5%)
MOV %R15,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV -0xc8(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP %R15,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JG 236495 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.12+0x935>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV 0x30(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x28(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x20(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x18(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x10(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%R8),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %R9,-0xc0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x10(%R8),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %R8,-0xb8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV (%RDI),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %R8,-0xb0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x10(%RDI),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDI,-0xa8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV (%RCX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDI,-0xa0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x10(%RCX),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV 0x8(%RDX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RAX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDX,-0x98(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x10(%RAX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RAX,-0x90(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %R15,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RSI,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
CMP $0x4,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOV %R15,-0x108(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
JB 2364b6 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.12+0x956>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %RAX,-0xf0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %RAX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x4,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA (%RSI,%RDX,1),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %RAX,-0xf8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
XORPD %XMM12,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %RDX,-0xe8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %RDX,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %R14,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %RCX,-0x100(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %EBX,-0x2c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %R13,-0x68(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
JMP 235e93 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.12+0x333>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0xe8(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP %RAX,-0xf0(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
MOV -0xf8(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
JNE 2364b6 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.12+0x956>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
LEA 0x27ee4(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV -0x44(%RBP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CALL 25cd00 <@plt_start@+0x540>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
ADD $0x168,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
XORPD %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOVAPD -0x25242(%RIP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (25.0%)
MOVSD -0x253ea(%RIP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
MOVAPD -0x25112(%RIP),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (25.0%)
MOVSD -0x2540a(%RIP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
MOVAPD -0x25132(%RIP),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (25.0%)
MOVSD -0x253e2(%RIP),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
MOV -0xa8(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
JMP 236541 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.12+0x9e1>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	5.76	2.25
○Loop 172 - advec_mom.cpp:109-139 - exec	5.76	2.25
○Loop 171 - advec_mom.cpp:109-139 - exec	0.00	0.00

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ASM code