OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone .omp

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: advec_mom.cpp:95-100 [...]	Coverage (incl. loops): 2.95% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 95 - 100

--------------------------------------------------------------------------------

95: #pragma omp parallel for simd collapse(2)

96:       for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) {

97:         for (int i = (x_min - 1 + 1); i < (x_max + 2 + 2); i++) {

98:           node_mass_post(i, j) = 0.25 * (density1(i + 0, j - 1) * post_vol(i + 0, j - 1) + density1(i, j) * post_vol(i, j) +

99:                                          density1(i - 1, j - 1) * post_vol(i - 1, j - 1) + density1(i - 1, j + 0) * post_vol(i - 1, j + 0));

100:           node_mass_pre(i, j) = node_mass_post(i, j) - node_flux(i - 1, j + 0) + node_flux(i, j);

0x2355f0 PUSH	%RBP

0x2355f1 MOV	%RSP,%RBP

0x2355f4 PUSH	%R15

0x2355f6 PUSH	%R14

0x2355f8 PUSH	%R13

0x2355fa PUSH	%R12

0x2355fc PUSH	%RBX

0x2355fd SUB	$0xd8,%RSP

0x235604 MOV	(%RDX),%EAX

0x235606 MOV	(%RCX),%R15D

0x235609 MOV	%RAX,-0x50(%RBP)

0x23560d INC	%EAX

0x23560f ADD	$0x3,%R15D

0x235613 MOV	%RAX,-0x48(%RBP)

0x235617 SUB	%EAX,%R15D

0x23561a JLE	235a16

0x235620 MOV	(%R8),%R13D

0x235623 MOV	(%R9),%EAX

0x235626 ADD	$0x4,%EAX

0x235629 CMP	%R13D,%EAX

0x23562c JLE	235a16

0x235632 SUB	%R13D,%EAX

0x235635 MOV	%RAX,-0x40(%RBP)

0x235639 IMUL	%RAX,%R15

0x23563d DEC	%R15

0x235640 MOVQ	$0,-0xb0(%RBP)

0x23564b MOV	%R15,-0x58(%RBP)

0x23564f MOVQ	$0x1,-0xf8(%RBP)

0x23565a MOVL	$0,-0x60(%RBP)

0x235661 MOV	(%RDI),%ESI

0x235663 SUB	$0x8,%RSP

0x235667 LEA	-0xf8(%RBP),%RAX

0x23566e LEA	0x28cab(%RIP),%RDI

0x235675 LEA	-0x60(%RBP),%RCX

0x235679 LEA	-0xb0(%RBP),%R8

0x235680 LEA	-0x58(%RBP),%R9

0x235684 MOV	%ESI,-0x5c(%RBP)

0x235687 MOV	$0x22,%EDX

0x23568c PUSH	$0x1

0x23568e PUSH	$0x1

0x235690 PUSH	%RAX

0x235691 CALL	25ccf0 <@plt_start@+0x530>

0x235696 ADD	$0x20,%RSP

0x23569a MOV	-0x58(%RBP),%RAX

0x23569e CMP	%R15,%RAX

0x2356a1 CMOVL	%RAX,%R15

0x2356a5 MOV	%R15,-0x58(%RBP)

0x2356a9 MOV	-0xb0(%RBP),%R11

0x2356b0 CMP	%R15,%R11

0x2356b3 JG	235a07

0x2356b9 MOV	0x30(%RBP),%RAX

0x2356bd MOV	0x28(%RBP),%RCX

0x2356c1 MOV	0x20(%RBP),%RDX

0x2356c5 MOV	0x18(%RBP),%RSI

0x2356c9 MOV	0x10(%RBP),%RDI

0x2356cd MOV	(%RSI),%R10

0x2356d0 MOV	0x10(%RSI),%RSI

0x2356d4 MOV	%RSI,-0xa8(%RBP)

0x2356db MOV	(%RDX),%R14

0x2356de MOV	0x10(%RDX),%RDX

0x2356e2 MOV	%RDX,-0xa0(%RBP)

0x2356e9 MOV	(%RDI),%RDX

0x2356ec MOV	%RDX,-0x98(%RBP)

0x2356f3 MOV	0x10(%RDI),%RDX

0x2356f7 MOV	%RDX,-0x90(%RBP)

0x2356fe MOV	(%RAX),%RDX

0x235701 MOV	%RDX,-0x88(%RBP)

0x235708 MOV	0x10(%RAX),%RAX

0x23570c MOV	%RAX,-0x80(%RBP)

0x235710 MOV	(%RCX),%RAX

0x235713 MOV	%RAX,-0x78(%RBP)

0x235717 MOV	0x10(%RCX),%RAX

0x23571b MOV	%RAX,-0x70(%RBP)

0x23571f MOV	%R15,%RAX

0x235722 SUB	%R11,%RAX

0x235725 INC	%RAX

0x235728 CMP	$0x2,%RAX

0x23572c JAE	235736

0x23572e MOV	%R11,%RCX

0x235731 JMP	235b3a

0x235736 MOV	%R14,-0x68(%RBP)

0x23573a MOV	%R10,-0x38(%RBP)

0x23573e MOV	%R13D,-0x2c(%RBP)

0x235742 MOV	%RAX,-0xc0(%RBP)

0x235749 MOV	%RAX,%RCX

0x23574c AND	$-0x2,%RCX

0x235750 LEA	(%R11,%RCX,1),%RAX

0x235754 MOV	%RAX,-0xc8(%RBP)

0x23575b MOVAPD	-0x244b3(%RIP),%XMM0

0x235763 MOV	%RCX,-0xb8(%RBP)

0x23576a MOV	%RCX,%RDX

0x23576d MOV	%R15,-0xd0(%RBP)

0x235774 MOV	-0xa8(%RBP),%R14

0x23577b JMP	235982

(170) 0x235780 CQTO

(170) 0x235782 IDIV	%R10

(170) 0x235785 MOV	-0x38(%RBP),%R10

(170) 0x235789 LEA	(%R9,%RDI,1),%R13D

(170) 0x23578d LEA	(%R9,%RAX,1),%R12D

(170) 0x235791 MOV	-0x2c(%RBP),%ECX

(170) 0x235794 ADD	%ECX,%R8D

(170) 0x235797 ADD	%ECX,%EDX

(170) 0x235799 MOVSXD	%R8D,%R8

(170) 0x23579c MOVSXD	%EDX,%RDX

(170) 0x23579f ADD	%ESI,%EDI

(170) 0x2357a1 ADD	%ESI,%EAX

(170) 0x2357a3 MOVSXD	%EDI,%R15

(170) 0x2357a6 MOVSXD	%EAX,%RSI

(170) 0x2357a9 MOV	%R10,%R9

(170) 0x2357ac IMUL	%R15,%R9

(170) 0x2357b0 MOV	%R10,%RCX

(170) 0x2357b3 IMUL	%RSI,%RCX

(170) 0x2357b7 MOV	%RCX,-0xe0(%RBP)

(170) 0x2357be LEA	(%R9,%R8,1),%RAX

(170) 0x2357c2 ADD	%RDX,%RCX

(170) 0x2357c5 MOVSD	(%R14,%RAX,8),%XMM1

(170) 0x2357cb MOVHPD	(%R14,%RCX,8),%XMM1

(170) 0x2357d1 MOV	-0x68(%RBP),%RCX

(170) 0x2357d5 IMUL	%RCX,%R15

(170) 0x2357d9 IMUL	%RCX,%RSI

(170) 0x2357dd MOV	%RSI,-0xd8(%RBP)

(170) 0x2357e4 LEA	(%R15,%R8,1),%RDI

(170) 0x2357e8 ADD	%RDX,%RSI

(170) 0x2357eb MOV	-0xa0(%RBP),%RAX

(170) 0x2357f2 MOVSD	(%RAX,%RDI,8),%XMM2

(170) 0x2357f7 MOVHPD	(%RAX,%RSI,8),%XMM2

(170) 0x2357fc MOVSXD	%R13D,%R11

(170) 0x2357ff MOVSXD	%R12D,%RBX

(170) 0x235802 MOV	%R10,%R12

(170) 0x235805 IMUL	%R11,%R12

(170) 0x235809 MOV	%R10,%R13

(170) 0x23580c IMUL	%RBX,%R13

(170) 0x235810 LEA	(%R12,%R8,1),%RDI

(170) 0x235814 LEA	(%RDX,%R13,1),%RSI

(170) 0x235818 MOVSD	(%R14,%RDI,8),%XMM3

(170) 0x23581e MOVHPD	(%R14,%RSI,8),%XMM3

(170) 0x235824 MOV	%RCX,%RDI

(170) 0x235827 IMUL	%R11,%RDI

(170) 0x23582b MOV	%RCX,%RSI

(170) 0x23582e IMUL	%RBX,%RSI

(170) 0x235832 LEA	(%RDI,%R8,1),%R10

(170) 0x235836 MOVSD	(%RAX,%R10,8),%XMM4

(170) 0x23583c LEA	(%RSI,%RDX,1),%R10

(170) 0x235840 MOVHPD	(%RAX,%R10,8),%XMM4

(170) 0x235846 LEA	-0x1(%R9,%R8,1),%R10

(170) 0x23584b MOVSD	(%R14,%R10,8),%XMM5

(170) 0x235851 MOV	-0xe0(%RBP),%RCX

(170) 0x235858 LEA	-0x1(%RCX,%RDX,1),%R9

(170) 0x23585d MOVHPD	(%R14,%R9,8),%XMM5

(170) 0x235863 LEA	-0x1(%R15,%R8,1),%R9

(170) 0x235868 MOVSD	(%RAX,%R9,8),%XMM6

(170) 0x23586e MOV	-0xd8(%RBP),%RCX

(170) 0x235875 LEA	-0x1(%RCX,%RDX,1),%R9

(170) 0x23587a MOVHPD	(%RAX,%R9,8),%XMM6

(170) 0x235880 LEA	-0x1(%R12,%R8,1),%R9

(170) 0x235885 MOVSD	(%R14,%R9,8),%XMM7

(170) 0x23588b MULPD	%XMM1,%XMM2

(170) 0x23588f MULPD	%XMM3,%XMM4

(170) 0x235893 ADDPD	%XMM2,%XMM4

(170) 0x235897 MULPD	%XMM5,%XMM6

(170) 0x23589b ADDPD	%XMM4,%XMM6

(170) 0x23589f LEA	-0x1(%R13,%RDX,1),%R9

(170) 0x2358a4 MOVHPD	(%R14,%R9,8),%XMM7

(170) 0x2358aa LEA	-0x1(%RDI,%R8,1),%RCX

(170) 0x2358af LEA	-0x1(%RSI,%RDX,1),%RSI

(170) 0x2358b4 MOVSD	(%RAX,%RCX,8),%XMM1

(170) 0x2358b9 MOVHPD	(%RAX,%RSI,8),%XMM1

(170) 0x2358be MULPD	%XMM7,%XMM1

(170) 0x2358c2 ADDPD	%XMM6,%XMM1

(170) 0x2358c6 MULPD	%XMM0,%XMM1

(170) 0x2358ca MOV	-0x98(%RBP),%RSI

(170) 0x2358d1 MOV	%RSI,%RCX

(170) 0x2358d4 IMUL	%R11,%RCX

(170) 0x2358d8 IMUL	%RBX,%RSI

(170) 0x2358dc ADD	%R8,%RCX

(170) 0x2358df ADD	%RDX,%RSI

(170) 0x2358e2 MOV	-0x90(%RBP),%RAX

(170) 0x2358e9 MOVLPD	%XMM1,(%RAX,%RCX,8)

(170) 0x2358ee MOVHPD	%XMM1,(%RAX,%RSI,8)

(170) 0x2358f3 MOV	-0x88(%RBP),%RSI

(170) 0x2358fa MOV	%RSI,%RCX

(170) 0x2358fd IMUL	%R11,%RCX

(170) 0x235901 IMUL	%RBX,%RSI

(170) 0x235905 LEA	(%RCX,%R8,1),%R9

(170) 0x235909 DEC	%R9

(170) 0x23590c MOV	-0x80(%RBP),%RAX

(170) 0x235910 MOVSD	(%RAX,%R9,8),%XMM2

(170) 0x235916 LEA	(%RSI,%RDX,1),%R9

(170) 0x23591a DEC	%R9

(170) 0x23591d MOVHPD	(%RAX,%R9,8),%XMM2

(170) 0x235923 ADD	%R8,%RCX

(170) 0x235926 MOVSD	(%RAX,%RCX,8),%XMM3

(170) 0x23592b ADD	%RDX,%RSI

(170) 0x23592e MOVHPD	(%RAX,%RSI,8),%XMM3

(170) 0x235933 MOV	-0x78(%RBP),%RAX

(170) 0x235937 IMUL	%RAX,%R11

(170) 0x23593b ADD	%R8,%R11

(170) 0x23593e IMUL	%RAX,%RBX

(170) 0x235942 ADD	%RDX,%RBX

(170) 0x235945 SUBPD	%XMM2,%XMM1

(170) 0x235949 ADDPD	%XMM1,%XMM3

(170) 0x23594d MOV	-0x70(%RBP),%RAX

(170) 0x235951 MOVLPD	%XMM3,(%RAX,%R11,8)

(170) 0x235957 MOVHPD	%XMM3,(%RAX,%RBX,8)

(170) 0x23595c MOV	-0xf0(%RBP),%R11

(170) 0x235963 ADD	$0x2,%R11

(170) 0x235967 MOV	-0xe8(%RBP),%RDX

(170) 0x23596e ADD	$-0x2,%RDX

(170) 0x235972 MOV	-0xd0(%RBP),%R15

(170) 0x235979 MOV	-0xc8(%RBP),%RCX

(170) 0x235980 JE	2359e7

(170) 0x235982 MOV	%R11,%RAX

(170) 0x235985 SHR	$0x20,%RAX

(170) 0x235989 MOV	-0x40(%RBP),%R10

(170) 0x23598d MOV	%RDX,-0xe8(%RBP)

(170) 0x235994 JE	2359b0

(170) 0x235996 MOV	%R11,%RAX

(170) 0x235999 CQTO

(170) 0x23599b IDIV	%R10

(170) 0x23599e MOV	%RDX,%R8

(170) 0x2359a1 MOV	%RAX,%RDI

(170) 0x2359a4 JMP	2359bd

0x2359a6 NOPW	%CS:(%RAX,%RAX,1)

(170) 0x2359b0 MOV	%R11D,%EAX

(170) 0x2359b3 XOR	%EDX,%EDX

(170) 0x2359b5 DIV	%R10D

(170) 0x2359b8 MOV	%EDX,%R8D

(170) 0x2359bb MOV	%EAX,%EDI

(170) 0x2359bd MOV	-0x50(%RBP),%RSI

(170) 0x2359c1 MOV	-0x48(%RBP),%R9

(170) 0x2359c5 LEA	0x1(%R11),%RAX

(170) 0x2359c9 MOV	%RAX,%RCX

(170) 0x2359cc SHR	$0x20,%RCX

(170) 0x2359d0 MOV	%R11,-0xf0(%RBP)

(170) 0x2359d7 JNE	235780

(170) 0x2359dd XOR	%EDX,%EDX

(170) 0x2359df DIV	%R10D

(170) 0x2359e2 JMP	235785

0x2359e7 MOV	-0xb8(%RBP),%RAX

0x2359ee CMP	%RAX,-0xc0(%RBP)

0x2359f5 MOV	-0x2c(%RBP),%R13D

0x2359f9 MOV	-0x38(%RBP),%R10

0x2359fd MOV	-0x68(%RBP),%R14

0x235a01 JNE	235b3a

0x235a07 LEA	0x2892a(%RIP),%RDI

0x235a0e MOV	-0x5c(%RBP),%ESI

0x235a11 CALL	25cd00 <@plt_start@+0x540>

0x235a16 ADD	$0xd8,%RSP

0x235a1d POP	%RBX

0x235a1e POP	%R12

0x235a20 POP	%R13

0x235a22 POP	%R14

0x235a24 POP	%R15

0x235a26 POP	%RBP

0x235a27 RET

0x235a28 NOPL	(%RAX,%RAX,1)

(169) 0x235a30 MOV	%RCX,%RAX

(169) 0x235a33 CQTO

(169) 0x235a35 IDIVQ	-0x40(%RBP)

(169) 0x235a39 MOV	%RCX,%R12

(169) 0x235a3c MOV	-0x48(%RBP),%RCX

(169) 0x235a40 ADD	%EAX,%ECX

(169) 0x235a42 ADD	%R13D,%EDX

(169) 0x235a45 MOVSXD	%EDX,%RDX

(169) 0x235a48 ADD	-0x50(%RBP),%EAX

(169) 0x235a4b MOVSXD	%EAX,%RSI

(169) 0x235a4e MOV	%R10,%RDI

(169) 0x235a51 IMUL	%RSI,%RDI

(169) 0x235a55 LEA	(%RDI,%RDX,1),%RAX

(169) 0x235a59 MOV	-0xa8(%RBP),%R11

(169) 0x235a60 MOVSD	(%R11,%RAX,8),%XMM0

(169) 0x235a66 IMUL	%R14,%RSI

(169) 0x235a6a MOVSXD	%ECX,%RAX

(169) 0x235a6d MOV	%R10,%RCX

(169) 0x235a70 IMUL	%RAX,%RCX

(169) 0x235a74 LEA	(%RCX,%RDX,1),%R8

(169) 0x235a78 MOVSD	(%R11,%R8,8),%XMM1

(169) 0x235a7e MOV	%R14,%R8

(169) 0x235a81 IMUL	%RAX,%R8

(169) 0x235a85 LEA	(%R8,%RDX,1),%R9

(169) 0x235a89 MOV	-0xa0(%RBP),%RBX

(169) 0x235a90 MULSD	(%RBX,%R9,8),%XMM1

(169) 0x235a96 LEA	(%RSI,%RDX,1),%R9

(169) 0x235a9a MULSD	(%RBX,%R9,8),%XMM0

(169) 0x235aa0 LEA	-0x1(%RDI,%RDX,1),%RDI

(169) 0x235aa5 MOVSD	(%R11,%RDI,8),%XMM2

(169) 0x235aab LEA	-0x1(%RSI,%RDX,1),%RSI

(169) 0x235ab0 MULSD	(%RBX,%RSI,8),%XMM2

(169) 0x235ab5 ADDSD	%XMM1,%XMM0

(169) 0x235ab9 ADDSD	%XMM0,%XMM2

(169) 0x235abd LEA	-0x1(%RCX,%RDX,1),%RCX

(169) 0x235ac2 MOVSD	(%R11,%RCX,8),%XMM0

(169) 0x235ac8 LEA	-0x1(%R8,%RDX,1),%RCX

(169) 0x235acd MULSD	(%RBX,%RCX,8),%XMM0

(169) 0x235ad2 ADDSD	%XMM2,%XMM0

(169) 0x235ad6 MULSD	-0x24996(%RIP),%XMM0

(169) 0x235ade MOV	-0x98(%RBP),%RCX

(169) 0x235ae5 IMUL	%RAX,%RCX

(169) 0x235ae9 ADD	%RDX,%RCX

(169) 0x235aec MOV	-0x90(%RBP),%RSI

(169) 0x235af3 MOVSD	%XMM0,(%RSI,%RCX,8)

(169) 0x235af8 MOV	-0x88(%RBP),%RCX

(169) 0x235aff IMUL	%RAX,%RCX

(169) 0x235b03 LEA	(%RCX,%RDX,1),%RSI

(169) 0x235b07 DEC	%RSI

(169) 0x235b0a MOV	-0x80(%RBP),%RDI

(169) 0x235b0e SUBSD	(%RDI,%RSI,8),%XMM0

(169) 0x235b13 ADD	%RDX,%RCX

(169) 0x235b16 ADDSD	(%RDI,%RCX,8),%XMM0

(169) 0x235b1b IMUL	-0x78(%RBP),%RAX

(169) 0x235b20 ADD	%RDX,%RAX

(169) 0x235b23 MOV	-0x70(%RBP),%RCX

(169) 0x235b27 MOVSD	%XMM0,(%RCX,%RAX,8)

(169) 0x235b2c CMP	%R15,%R12

(169) 0x235b2f LEA	0x1(%R12),%RCX

(169) 0x235b34 JGE	235a07

(169) 0x235b3a MOV	%RCX,%RAX

(169) 0x235b3d SHR	$0x20,%RAX

(169) 0x235b41 JNE	235a30

(169) 0x235b47 MOV	%ECX,%EAX

(169) 0x235b49 XOR	%EDX,%EDX

(169) 0x235b4b DIVL	-0x40(%RBP)

(169) 0x235b4e JMP	235a39

0x235b53 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	advec_mom.cpp:95-100
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:95-100

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 14.25 to 1.67 cycles (8.55x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 14.25 to 1.31 cycles (10.86x speedup).

Details

2% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

10% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
0% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:95
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:95

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVL: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:96

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 220 bytes. The binary function is storing 180 bytes.

General properties

nb instructions	114
nb uops	114
loop length	496
used x86 registers	16
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	28

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	14.25 cycles
front end	14.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	6.50	6.50	6.50	6.50	6.50	6.50	14.00	14.00	14.00	14.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	6.50	6.50	6.50	6.50	6.50	6.50	14.00	14.00	14.00	14.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	14.25
Dispatch	14.00
Overall L1	14.25

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	2%
load	10%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	10%
load	10%
store	11%
mul	12%
add-sub	8%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	25%
load	25%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	11%
load	11%
store	11%
mul	12%
add-sub	8%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 14.25 cycles. At this rate:

6% of peak load performance is reached (15.44 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (12.63 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 2355f0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0xd8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV (%RDX),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RCX),%R15D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOV %RAX,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
INC %EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD $0x3,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %RAX,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
SUB %EAX,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JLE 235a16 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.10+0x426>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV (%R8),%R13D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOV (%R9),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD $0x4,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
CMP %R13D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JLE 235a16 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.10+0x426>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
SUB %R13D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %RAX,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
IMUL %RAX,%R15	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
DEC %R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOVQ $0,-0xb0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %R15,-0x58(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOVQ $0x1,-0xf8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVL $0,-0x60(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA -0xf8(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA 0x28cab(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x60(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0xb0(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x58(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %ESI,-0x5c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 25ccf0 <@plt_start@+0x530>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV -0x58(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP %R15,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
CMOVL %RAX,%R15	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	1	0.33	scal (12.5%)
MOV %R15,-0x58(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV -0xb0(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP %R15,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JG 235a07 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.10+0x417>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV 0x30(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x28(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x20(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x18(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x10(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RSI),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV 0x10(%RSI),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RSI,-0xa8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV (%RDX),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV 0x10(%RDX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDX,-0xa0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV (%RDI),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDX,-0x98(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x10(%RDI),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDX,-0x90(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV (%RAX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDX,-0x88(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x10(%RAX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RAX,-0x80(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV (%RCX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RAX,-0x78(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x10(%RCX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RAX,-0x70(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %R15,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %R11,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
CMP $0x2,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JAE 235736 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.10+0x146>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %R11,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 235b3a <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.10+0x54a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
MOV %R14,-0x68(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %R10,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %R13D,-0x2c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %RAX,-0xc0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x2,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA (%R11,%RCX,1),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %RAX,-0xc8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOVAPD -0x244b3(%RIP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (25.0%)
MOV %RCX,-0xb8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %RCX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15,-0xd0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV -0xa8(%RBP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
JMP 235982 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.10+0x392>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0xb8(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP %RAX,-0xc0(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
MOV -0x2c(%RBP),%R13D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOV -0x38(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV -0x68(%RBP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
JNE 235b3a <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.10+0x54a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
LEA 0x2892a(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV -0x5c(%RBP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CALL 25cd00 <@plt_start@+0x540>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
ADD $0xd8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	advec_mom.cpp:95-100
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:95-100

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 14.25 to 1.67 cycles (8.55x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

2% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

10% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
0% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:95
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:95

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVL: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:96

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 220 bytes. The binary function is storing 180 bytes.

General properties

nb instructions	114
nb uops	114
loop length	496
used x86 registers	16
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	28

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	14.25 cycles
front end	14.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	6.50	6.50	6.50	6.50	6.50	6.50	14.00	14.00	14.00	14.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	6.50	6.50	6.50	6.50	6.50	6.50	14.00	14.00	14.00	14.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	14.25
Dispatch	14.00
Overall L1	14.25

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	2%
load	10%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	10%
load	10%
store	11%
mul	12%
add-sub	8%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	25%
load	25%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	11%
load	11%
store	11%
mul	12%
add-sub	8%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 14.25 cycles. At this rate:

6% of peak load performance is reached (15.44 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (12.63 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 2355f0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0xd8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV (%RDX),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RCX),%R15D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOV %RAX,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
INC %EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD $0x3,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %RAX,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
SUB %EAX,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JLE 235a16 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.10+0x426>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV (%R8),%R13D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOV (%R9),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD $0x4,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
CMP %R13D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JLE 235a16 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.10+0x426>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
SUB %R13D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %RAX,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
IMUL %RAX,%R15	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
DEC %R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOVQ $0,-0xb0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %R15,-0x58(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOVQ $0x1,-0xf8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVL $0,-0x60(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA -0xf8(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA 0x28cab(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x60(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0xb0(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x58(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %ESI,-0x5c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 25ccf0 <@plt_start@+0x530>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV -0x58(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP %R15,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
CMOVL %RAX,%R15	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	1	0.33	scal (12.5%)
MOV %R15,-0x58(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV -0xb0(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP %R15,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JG 235a07 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.10+0x417>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV 0x30(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x28(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x20(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x18(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x10(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RSI),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV 0x10(%RSI),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RSI,-0xa8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV (%RDX),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV 0x10(%RDX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDX,-0xa0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV (%RDI),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDX,-0x98(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x10(%RDI),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDX,-0x90(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV (%RAX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDX,-0x88(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x10(%RAX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RAX,-0x80(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV (%RCX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RAX,-0x78(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x10(%RCX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RAX,-0x70(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %R15,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %R11,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
CMP $0x2,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JAE 235736 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.10+0x146>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %R11,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 235b3a <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.10+0x54a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
MOV %R14,-0x68(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %R10,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %R13D,-0x2c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %RAX,-0xc0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x2,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA (%R11,%RCX,1),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %RAX,-0xc8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOVAPD -0x244b3(%RIP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (25.0%)
MOV %RCX,-0xb8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %RCX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15,-0xd0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV -0xa8(%RBP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
JMP 235982 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.10+0x392>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0xb8(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP %RAX,-0xc0(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
MOV -0x2c(%RBP),%R13D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOV -0x38(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV -0x68(%RBP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
JNE 235b3a <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.10+0x54a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
LEA 0x2892a(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV -0x5c(%RBP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CALL 25cd00 <@plt_start@+0x540>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
ADD $0xd8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	2.95	1.15
○Loop 170 - advec_mom.cpp:96-100 - exec	2.95	1.15
○Loop 169 - advec_mom.cpp:96-100 - exec	0.00	0.00

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