Loop Id: 333 | Module: exec | Source: advec_mom.cpp:181-211 [...] | Coverage: 4.22% |
---|
Loop Id: 333 | Module: exec | Source: advec_mom.cpp:181-211 [...] | Coverage: 4.22% |
---|
0x23bbb0 VSUBPD %ZMM20,%ZMM13,%ZMM19 |
0x23bbb6 VMOVAPD %ZMM24,%ZMM18{%K2}{z} |
0x23bbbc MOV -0x60(%RBP),%RAX [35] |
0x23bbc0 VPMULLQ %ZMM16,%ZMM7,%ZMM16 |
0x23bbc6 KXNORW %K0,%K0,%K1 |
0x23bbca ADD $-0x8,%R8 |
0x23bbce VPADDQ %ZMM14,%ZMM0,%ZMM0 |
0x23bbd4 VFMADD213PD %ZMM21,%ZMM18,%ZMM19 |
0x23bbda VPADDQ %ZMM15,%ZMM16,%ZMM15 |
0x23bbe0 VMULPD %ZMM19,%ZMM17,%ZMM17 |
0x23bbe6 VSCATTERQPD %ZMM17,(%RAX,%ZMM15,8){%K1} [31] |
0x23bbed JE 23c173 |
0x23bbf3 VEXTRACTI32X4 $0x3,%ZMM0,%XMM15 |
0x23bbfa VPEXTRQ $0x1,%XMM8,%RSI |
0x23bc00 VPEXTRQ $0x1,%XMM15,%RAX |
0x23bc06 CQTO |
0x23bc08 IDIV %RSI |
0x23bc0b VMOVQ %XMM8,%RSI |
0x23bc10 VMOVQ %RAX,%XMM16 |
0x23bc16 VMOVQ %XMM15,%RAX |
0x23bc1b CQTO |
0x23bc1d IDIV %RSI |
0x23bc20 VPEXTRQ $0x1,%XMM9,%RSI |
0x23bc26 VMOVQ %RAX,%XMM15 |
0x23bc2b VPUNPCKLQDQ %XMM16,%XMM15,%XMM15 |
0x23bc31 VEXTRACTI32X4 $0x2,%ZMM0,%XMM16 |
0x23bc38 VPEXTRQ $0x1,%XMM16,%RAX |
0x23bc3f CQTO |
0x23bc41 IDIV %RSI |
0x23bc44 VMOVQ %XMM9,%RSI |
0x23bc49 VMOVQ %RAX,%XMM17 |
0x23bc4f VMOVQ %XMM16,%RAX |
0x23bc55 CQTO |
0x23bc57 IDIV %RSI |
0x23bc5a VMOVQ %RAX,%XMM16 |
0x23bc60 VPUNPCKLQDQ %XMM17,%XMM16,%XMM16 |
0x23bc66 VEXTRACTI32X4 $0x1,%YMM1,%XMM17 |
0x23bc6d VINSERTI32X4 $0x1,%XMM15,%YMM16,%YMM15 |
0x23bc74 VEXTRACTI32X4 $0x1,%YMM0,%XMM16 |
0x23bc7b VPEXTRQ $0x1,%XMM17,%RSI |
0x23bc82 VPEXTRQ $0x1,%XMM16,%RAX |
0x23bc89 CQTO |
0x23bc8b IDIV %RSI |
0x23bc8e VMOVQ %XMM17,%RSI |
0x23bc94 VMOVQ %RAX,%XMM18 |
0x23bc9a VMOVQ %XMM16,%RAX |
0x23bca0 CQTO |
0x23bca2 IDIV %RSI |
0x23bca5 VPEXTRQ $0x1,%XMM1,%RSI |
0x23bcab VMOVQ %RAX,%XMM16 |
0x23bcb1 VPEXTRQ $0x1,%XMM0,%RAX |
0x23bcb7 CQTO |
0x23bcb9 VPUNPCKLQDQ %XMM18,%XMM16,%XMM16 |
0x23bcbf IDIV %RSI |
0x23bcc2 VMOVQ %XMM1,%RSI |
0x23bcc7 VMOVQ %RAX,%XMM17 |
0x23bccd VMOVQ %XMM0,%RAX |
0x23bcd2 CQTO |
0x23bcd4 IDIV %RSI |
0x23bcd7 VMOVQ %RAX,%XMM18 |
0x23bcdd VPUNPCKLQDQ %XMM17,%XMM18,%XMM17 |
0x23bce3 VINSERTI32X4 $0x1,%XMM16,%YMM17,%YMM16 |
0x23bcea VINSERTI64X4 $0x1,%YMM15,%ZMM16,%ZMM15 |
0x23bcf1 VPMOVQD %ZMM15,%YMM16 |
0x23bcf7 VPMULLQ %ZMM1,%ZMM15,%ZMM15 |
0x23bcfd VPSUBQ %ZMM15,%ZMM0,%ZMM15 |
0x23bd03 VPMOVQD %ZMM15,%YMM15 |
0x23bd09 VPADDD %YMM16,%YMM2,%YMM20 |
0x23bd0f VPMOVSXDQ %YMM20,%ZMM16 |
0x23bd15 VPADDD %YMM3,%YMM15,%YMM15 |
0x23bd19 VPMOVSXDQ %YMM15,%ZMM15 |
0x23bd1f VPMULLQ %ZMM16,%ZMM4,%ZMM17 |
0x23bd25 VPADDQ %ZMM15,%ZMM17,%ZMM17 |
0x23bd2b VEXTRACTI32X4 $0x1,%YMM17,%XMM18 |
0x23bd32 VMOVQ %XMM17,%RAX |
0x23bd38 VPEXTRQ $0x1,%XMM17,%RDX |
0x23bd3f VMOVQ %XMM18,%RSI |
0x23bd45 VPEXTRQ $0x1,%XMM18,%RBX |
0x23bd4c VEXTRACTI32X4 $0x2,%ZMM17,%XMM18 |
0x23bd53 VEXTRACTI32X4 $0x3,%ZMM17,%XMM17 |
0x23bd5a VMOVSD (%RDI,%RAX,8),%XMM19 [17] |
0x23bd61 VMOVQ %XMM18,%R14 |
0x23bd67 VMOVQ %XMM17,%R13 |
0x23bd6d VPEXTRQ $0x1,%XMM18,%R12 |
0x23bd74 VPEXTRQ $0x1,%XMM17,%R10 |
0x23bd7b VMOVHPD (%RDI,%RDX,8),%XMM19,%XMM19 [21] |
0x23bd82 VMOVSD (%RDI,%R13,8),%XMM17 [16] |
0x23bd89 VMOVSD (%RDI,%R14,8),%XMM18 [19] |
0x23bd90 VMOVHPD (%RDI,%R10,8),%XMM17,%XMM17 [38] |
0x23bd97 VMOVHPD (%RDI,%R12,8),%XMM18,%XMM18 [1] |
0x23bd9e VINSERTF32X4 $0x1,%XMM17,%YMM18,%YMM17 |
0x23bda5 VMOVSD (%RDI,%RSI,8),%XMM18 [20] |
0x23bdac VMOVHPD (%RDI,%RBX,8),%XMM18,%XMM18 [18] |
0x23bdb3 VINSERTF32X4 $0x1,%XMM18,%YMM19,%YMM18 |
0x23bdba VPSUBD %YMM11,%YMM20,%YMM19 |
0x23bdc0 VPMOVSXDQ %YMM19,%ZMM22 |
0x23bdc6 VINSERTF64X4 $0x1,%YMM17,%ZMM18,%ZMM17 |
0x23bdcd VPADDD %YMM11,%YMM20,%YMM18 |
0x23bdd3 VMOVDQA64 %YMM18,%YMM23 |
0x23bdd9 VCMPPD $0x1,%ZMM10,%ZMM17,%K1 |
0x23bde0 VPBLENDMQ %ZMM22,%ZMM16,%ZMM21{%K1} |
0x23bde6 VPADDD -0x391d8(%RIP){1to8},%YMM20,%YMM23{%K1} [30] |
0x23bdf0 VANDPD %ZMM12,%ZMM17,%ZMM20 |
0x23bdf6 VMOVDQA64 %ZMM16,%ZMM22{%K1} |
0x23bdfc VPMULLQ %ZMM22,%ZMM6,%ZMM22 |
0x23be02 VPMULLQ %ZMM21,%ZMM5,%ZMM24 |
0x23be08 VPMULLQ %ZMM21,%ZMM6,%ZMM21 |
0x23be0e VPADDQ %ZMM15,%ZMM22,%ZMM22 |
0x23be14 VPADDQ %ZMM15,%ZMM24,%ZMM24 |
0x23be1a VPADDQ %ZMM15,%ZMM21,%ZMM21 |
0x23be20 VEXTRACTI32X4 $0x1,%YMM24,%XMM25 |
0x23be27 VMOVQ %XMM24,%RAX |
0x23be2d VPEXTRQ $0x1,%XMM24,%RDX |
0x23be34 VMOVQ %XMM25,%RSI |
0x23be3a VPEXTRQ $0x1,%XMM25,%R10 |
0x23be41 VEXTRACTI32X4 $0x2,%ZMM24,%XMM25 |
0x23be48 VEXTRACTI32X4 $0x3,%ZMM24,%XMM24 |
0x23be4f VMOVSD (%R9,%RAX,8),%XMM26 [33] |
0x23be56 VMOVQ %XMM21,%RAX |
0x23be5c VMOVQ %XMM25,%RBX |
0x23be62 VMOVQ %XMM24,%R12 |
0x23be68 VPEXTRQ $0x1,%XMM25,%R14 |
0x23be6f VPEXTRQ $0x1,%XMM24,%R13 |
0x23be76 VMOVHPD (%R9,%RDX,8),%XMM26,%XMM26 [37] |
0x23be7d VPEXTRQ $0x1,%XMM21,%RDX |
0x23be84 VMOVSD (%R9,%R12,8),%XMM24 [32] |
0x23be8b VMOVSD (%R9,%RBX,8),%XMM25 [39] |
0x23be92 VPMOVSXDQ %YMM23,%ZMM23 |
0x23be98 VMOVHPD (%R9,%R13,8),%XMM24,%XMM24 [24] |
0x23be9f VMOVHPD (%R9,%R14,8),%XMM25,%XMM25 [25] |
0x23bea6 VPMULLQ %ZMM23,%ZMM6,%ZMM23 |
0x23beac VPADDQ %ZMM15,%ZMM23,%ZMM23 |
0x23beb2 VINSERTF32X4 $0x1,%XMM24,%YMM25,%YMM24 |
0x23beb9 VMOVSD (%R9,%RSI,8),%XMM25 [40] |
0x23bec0 VMOVHPD (%R9,%R10,8),%XMM25,%XMM25 [15] |
0x23bec7 VINSERTF32X4 $0x1,%XMM25,%YMM26,%YMM25 |
0x23bece VINSERTF64X4 $0x1,%YMM24,%ZMM25,%ZMM24 |
0x23bed5 VMOVSD (%R11,%RAX,8),%XMM25 [42] |
0x23bedc VMOVQ %XMM23,%RAX |
0x23bee2 VMOVHPD (%R11,%RDX,8),%XMM25,%XMM25 [29] |
0x23bee9 VPEXTRQ $0x1,%XMM23,%RDX |
0x23bef0 VDIVPD %ZMM24,%ZMM20,%ZMM20 |
0x23bef6 VEXTRACTI32X4 $0x1,%YMM21,%XMM24 |
0x23befd VMOVQ %XMM24,%RSI |
0x23bf03 VPEXTRQ $0x1,%XMM24,%R10 |
0x23bf0a VEXTRACTI32X4 $0x2,%ZMM21,%XMM24 |
0x23bf11 VEXTRACTI32X4 $0x3,%ZMM21,%XMM21 |
0x23bf18 VMOVQ %XMM24,%R14 |
0x23bf1e VMOVQ %XMM21,%R12 |
0x23bf24 VPEXTRQ $0x1,%XMM24,%RBX |
0x23bf2b VPEXTRQ $0x1,%XMM21,%R13 |
0x23bf32 VMOVSD (%R11,%R12,8),%XMM21 [41] |
0x23bf39 VMOVSD (%R11,%R14,8),%XMM24 [6] |
0x23bf40 VMOVHPD (%R11,%R13,8),%XMM21,%XMM21 [12] |
0x23bf47 VMOVHPD (%R11,%RBX,8),%XMM24,%XMM24 [26] |
0x23bf4e VINSERTF32X4 $0x1,%XMM21,%YMM24,%YMM21 |
0x23bf55 VMOVSD (%R11,%RSI,8),%XMM24 [7] |
0x23bf5c VMOVHPD (%R11,%R10,8),%XMM24,%XMM24 [5] |
0x23bf63 VINSERTF32X4 $0x1,%XMM24,%YMM25,%YMM24 |
0x23bf6a VMOVSD (%R11,%RAX,8),%XMM25 [3] |
0x23bf71 VMOVQ %XMM22,%RAX |
0x23bf77 VMOVHPD (%R11,%RDX,8),%XMM25,%XMM25 [28] |
0x23bf7e VPEXTRQ $0x1,%XMM22,%RDX |
0x23bf85 VINSERTF64X4 $0x1,%YMM21,%ZMM24,%ZMM21 |
0x23bf8c VEXTRACTI32X4 $0x1,%YMM23,%XMM24 |
0x23bf93 VMOVQ %XMM24,%RSI |
0x23bf99 VPEXTRQ $0x1,%XMM24,%R10 |
0x23bfa0 VEXTRACTI32X4 $0x2,%ZMM23,%XMM24 |
0x23bfa7 VEXTRACTI32X4 $0x3,%ZMM23,%XMM23 |
0x23bfae VMOVQ %XMM24,%RBX |
0x23bfb4 VMOVQ %XMM23,%R12 |
0x23bfba VPEXTRQ $0x1,%XMM24,%R14 |
0x23bfc1 VPEXTRQ $0x1,%XMM23,%R13 |
0x23bfc8 VMOVSD (%R11,%R12,8),%XMM23 [2] |
0x23bfcf VMOVSD (%R11,%RBX,8),%XMM24 [22] |
0x23bfd6 VMOVHPD (%R11,%R13,8),%XMM23,%XMM23 [11] |
0x23bfdd VMOVHPD (%R11,%R14,8),%XMM24,%XMM24 [14] |
0x23bfe4 VINSERTF32X4 $0x1,%XMM23,%YMM24,%YMM23 |
0x23bfeb VMOVSD (%R11,%RSI,8),%XMM24 [23] |
0x23bff2 VMOVHPD (%R11,%R10,8),%XMM24,%XMM24 [4] |
0x23bff9 VINSERTF32X4 $0x1,%XMM24,%YMM25,%YMM24 |
0x23c000 VMOVSD (%R11,%RAX,8),%XMM25 [45] |
0x23c007 VMOVHPD (%R11,%RDX,8),%XMM25,%XMM25 [27] |
0x23c00e VINSERTF64X4 $0x1,%YMM23,%ZMM24,%ZMM23 |
0x23c015 VEXTRACTI32X4 $0x1,%YMM22,%XMM24 |
0x23c01c VPEXTRQ $0x1,%XMM24,%RSI |
0x23c023 VMOVQ %XMM24,%R10 |
0x23c029 VEXTRACTI32X4 $0x2,%ZMM22,%XMM24 |
0x23c030 VEXTRACTI32X4 $0x3,%ZMM22,%XMM22 |
0x23c037 VMOVQ %XMM24,%RBX |
0x23c03d VMOVQ %XMM22,%R12 |
0x23c043 VPEXTRQ $0x1,%XMM24,%R14 |
0x23c04a VPEXTRQ $0x1,%XMM22,%R13 |
0x23c051 VSUBPD %ZMM23,%ZMM21,%ZMM23 |
0x23c057 VMOVSD (%R11,%R12,8),%XMM22 [44] |
0x23c05e VMOVSD (%R11,%RBX,8),%XMM24 [8] |
0x23c065 VMOVHPD (%R11,%R13,8),%XMM22,%XMM22 [10] |
0x23c06c VMOVHPD (%R11,%R14,8),%XMM24,%XMM24 [13] |
0x23c073 VINSERTF32X4 $0x1,%XMM22,%YMM24,%YMM22 |
0x23c07a VMOVSD (%R11,%R10,8),%XMM24 [9] |
0x23c081 VMOVHPD (%R11,%RSI,8),%XMM24,%XMM24 [34] |
0x23c088 VINSERTF32X4 $0x1,%XMM24,%YMM25,%YMM24 |
0x23c08f VINSERTF64X4 $0x1,%YMM22,%ZMM24,%ZMM22 |
0x23c096 VSUBPD %ZMM21,%ZMM22,%ZMM22 |
0x23c09c VMULPD %ZMM22,%ZMM23,%ZMM24 |
0x23c0a2 VCMPPD $0x1,%ZMM24,%ZMM10,%K2 |
0x23c0a9 KORTESTB %K2,%K2 |
0x23c0ad JE 23bbb0 |
0x23c0b3 VBROADCASTSD -0x2a8dd(%RIP),%ZMM25 [30] |
0x23c0bd MOV -0x48(%RBP),%RAX [35] |
0x23c0c1 VMOVDQA32 %YMM19,%YMM18{%K1} |
0x23c0c7 KMOVQ %K2,%K1 |
0x23c0cc VPXORD %XMM19,%XMM19,%XMM19 |
0x23c0d2 VANDPD %ZMM12,%ZMM22,%ZMM24 |
0x23c0d8 KMOVQ %K2,%K3 |
0x23c0dd VXORPD %XMM26,%XMM26,%XMM26 |
0x23c0e3 VANDPD %ZMM12,%ZMM23,%ZMM23 |
0x23c0e9 VGATHERQPD (%RAX,%ZMM16,8),%ZMM19{%K1} [43] |
0x23c0f0 VCMPPD $0x6,%ZMM10,%ZMM22,%K1 |
0x23c0f7 VGATHERDPD (%RAX,%YMM18,8),%ZMM26{%K3} [36] |
0x23c0fe VSUBPD %ZMM20,%ZMM25,%ZMM22 |
0x23c104 VADDPD %ZMM13,%ZMM20,%ZMM25 |
0x23c10a VMULPD %ZMM24,%ZMM22,%ZMM22 |
0x23c110 VMULPD %ZMM23,%ZMM25,%ZMM25 |
0x23c116 VDIVPD %ZMM19,%ZMM22,%ZMM22 |
0x23c11c VDIVPD %ZMM26,%ZMM25,%ZMM18 |
0x23c122 VADDPD %ZMM18,%ZMM22,%ZMM18 |
0x23c128 VMULPD %ZMM18,%ZMM19,%ZMM18 |
0x23c12e VDIVPD -0x2a8e8(%RIP){1to8},%ZMM18,%ZMM18 [30] |
0x23c138 VMINPD %ZMM18,%ZMM23,%ZMM19 |
0x23c13e VCMPPD $0x3,%ZMM18,%ZMM18,%K3 |
0x23c145 VMOVAPD %ZMM23,%ZMM19{%K3} |
0x23c14b VMINPD %ZMM19,%ZMM24,%ZMM18 |
0x23c151 VCMPPD $0x3,%ZMM19,%ZMM19,%K3 |
0x23c158 VMOVAPD %ZMM24,%ZMM18{%K3} |
0x23c15e VXORPD -0x2a8d0(%RIP){1to8},%ZMM18,%ZMM24 [30] |
0x23c168 VMOVAPD %ZMM18,%ZMM24{%K1} |
0x23c16e JMP 23bbb0 |
/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp: 181 - 211 |
-------------------------------------------------------------------------------- |
181: for (int j = (y_min - 1 + 1); j < (y_max + 1 + 2); j++) { |
182: for (int i = (x_min + 1); i < (x_max + 1 + 2); i++) |
183: ({ |
184: int upwind, donor, downwind, dif; |
185: double sigma, width, limiter, vdiffuw, vdiffdw, auw, adw, wind, advec_vel_s; |
186: if (node_flux(i, j) < 0.0) { |
[...] |
197: sigma = std::fabs(node_flux(i, j)) / (node_mass_pre(i, donor)); |
198: width = celldy[j]; |
199: vdiffuw = vel1(i, donor) - vel1(i, upwind); |
200: vdiffdw = vel1(i, downwind) - vel1(i, donor); |
201: limiter = 0.0; |
202: if (vdiffuw * vdiffdw > 0.0) { |
203: auw = std::fabs(vdiffuw); |
204: adw = std::fabs(vdiffdw); |
205: wind = 1.0; |
206: if (vdiffdw <= 0.0) wind = -1.0; |
207: limiter = |
208: wind * std::fmin(std::fmin(width * ((2.0 - sigma) * adw / width + (1.0 + sigma) * auw / celldy[dif]) / 6.0, auw), adw); |
209: } |
210: advec_vel_s = vel1(i, donor) + (1.0 - sigma) * limiter; |
211: mom_flux(i, j) = advec_vel_s * node_flux(i, j); |
/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69 |
-------------------------------------------------------------------------------- |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.46 - 2.20 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 2.09 - 2.55 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.37 - 2.06 |
Bottlenecks | |
Function | .omp_outlined..20 |
Source | advec_mom.cpp:181-186,advec_mom.cpp:197-211,context.h:69-69 |
Source loop unroll info | unrolled by 8 |
Source loop unroll confidence level | high |
Unroll/vectorization loop type | main |
Unroll factor | 8 |
CQA cycles | 78.50 - 118.50 |
CQA cycles if no scalar integer | 53.83 |
CQA cycles if FP arith vectorized | 78.50 - 118.50 |
CQA cycles if fully vectorized | 37.63 - 46.50 |
Front-end cycles | 57.50 |
DIV/SQRT cycles | 16.00 |
P0 cycles | 0.50 |
P1 cycles | 8.00 |
P2 cycles | 0.50 |
P3 cycles | 2.50 |
P4 cycles | 15.00 |
P5 cycles | 15.00 |
P6 cycles | 15.00 |
P7 cycles | 46.00 |
P8 cycles | 41.33 |
P9 cycles | 40.79 |
P10 cycles | 44.38 |
P11 cycles | 42.50 |
P12 cycles | 42.50 |
P13 cycles | 78.50 - 118.50 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 223.00 |
Nb uops | 345.00 |
Nb loads | 53.00 |
Nb stores | 1.00 |
Nb stack references | 1.50 |
FLOP/cycle | 1.27 - 0.84 |
Nb FLOP add-sub | 36.00 |
Nb FLOP mul | 28.00 |
Nb FLOP fma | 8.00 |
Nb FLOP div | 20.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 3.99 - 6.07 |
Bytes prefetched | 0.00 |
Bytes loaded | 412.00 |
Bytes stored | 64.00 |
Stride 0 | 2.00 |
Stride 1 | 0.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 26.00 |
Vectorization ratio all | 41.89 |
Vectorization ratio load | 6.65 |
Vectorization ratio store | 100.00 |
Vectorization ratio mul | 100.00 |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | 100.00 |
Vectorization ratio div_sqrt | 22.22 |
Vectorization ratio other | 42.92 |
Vector-efficiency ratio all | 34.13 |
Vector-efficiency ratio load | 17.17 |
Vector-efficiency ratio store | 100.00 |
Vector-efficiency ratio mul | 100.00 |
Vector-efficiency ratio add_sub | 85.61 |
Vector-efficiency ratio fma | 100.00 |
Vector-efficiency ratio div_sqrt | 31.94 |
Vector-efficiency ratio other | 27.89 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.45 - 2.07 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 1.84 - 2.20 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.36 - 1.95 |
Bottlenecks | P8, P9, |
Function | .omp_outlined..20 |
Source | advec_mom.cpp:181-186,advec_mom.cpp:197-211,context.h:69-69 |
Source loop unroll info | unrolled by 8 |
Source loop unroll confidence level | high |
Unroll/vectorization loop type | main |
Unroll factor | 8 |
CQA cycles | 92.00 - 132.00 |
CQA cycles if no scalar integer | 63.67 |
CQA cycles if FP arith vectorized | 92.00 - 132.00 |
CQA cycles if fully vectorized | 50.00 - 60.00 |
Front-end cycles | 67.67 |
DIV/SQRT cycles | 16.00 |
P0 cycles | 0.50 |
P1 cycles | 8.00 |
P2 cycles | 0.50 |
P3 cycles | 3.00 |
P4 cycles | 16.00 |
P5 cycles | 16.00 |
P6 cycles | 16.00 |
P7 cycles | 55.50 |
P8 cycles | 47.50 |
P9 cycles | 47.08 |
P10 cycles | 51.92 |
P11 cycles | 47.50 |
P12 cycles | 47.50 |
P13 cycles | 92.00 - 132.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 238.00 |
Nb uops | 406.00 |
Nb loads | 56.00 |
Nb stores | 1.00 |
Nb stack references | 2.00 |
FLOP/cycle | 1.48 - 1.03 |
Nb FLOP add-sub | 48.00 |
Nb FLOP mul | 40.00 |
Nb FLOP fma | 8.00 |
Nb FLOP div | 32.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 4.21 - 6.04 |
Bytes prefetched | 0.00 |
Bytes loaded | 492.00 |
Bytes stored | 64.00 |
Stride 0 | 2.00 |
Stride 1 | 0.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 27.00 |
Vectorization ratio all | 45.18 |
Vectorization ratio load | 10.87 |
Vectorization ratio store | 100.00 |
Vectorization ratio mul | 100.00 |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | 100.00 |
Vectorization ratio div_sqrt | 33.33 |
Vectorization ratio other | 46.15 |
Vector-efficiency ratio all | 37.45 |
Vector-efficiency ratio load | 20.92 |
Vector-efficiency ratio store | 100.00 |
Vector-efficiency ratio mul | 100.00 |
Vector-efficiency ratio add_sub | 86.84 |
Vector-efficiency ratio fma | 100.00 |
Vector-efficiency ratio div_sqrt | 41.67 |
Vector-efficiency ratio other | 31.38 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.48 - 2.39 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 2.57 - 3.18 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.37 - 2.22 |
Bottlenecks | P8, P9, |
Function | .omp_outlined..20 |
Source | advec_mom.cpp:181-186,advec_mom.cpp:197-211,context.h:69-69 |
Source loop unroll info | unrolled by 8 |
Source loop unroll confidence level | high |
Unroll/vectorization loop type | main |
Unroll factor | 8 |
CQA cycles | 65.00 - 105.00 |
CQA cycles if no scalar integer | 44.00 |
CQA cycles if FP arith vectorized | 65.00 - 105.00 |
CQA cycles if fully vectorized | 25.25 - 33.00 |
Front-end cycles | 47.33 |
DIV/SQRT cycles | 16.00 |
P0 cycles | 0.50 |
P1 cycles | 8.00 |
P2 cycles | 0.50 |
P3 cycles | 2.00 |
P4 cycles | 14.00 |
P5 cycles | 14.00 |
P6 cycles | 14.00 |
P7 cycles | 36.50 |
P8 cycles | 35.17 |
P9 cycles | 34.50 |
P10 cycles | 36.83 |
P11 cycles | 37.50 |
P12 cycles | 37.50 |
P13 cycles | 65.00 - 105.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 208.00 |
Nb uops | 284.00 |
Nb loads | 50.00 |
Nb stores | 1.00 |
Nb stack references | 1.00 |
FLOP/cycle | 0.98 - 0.61 |
Nb FLOP add-sub | 24.00 |
Nb FLOP mul | 16.00 |
Nb FLOP fma | 8.00 |
Nb FLOP div | 8.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 3.77 - 6.09 |
Bytes prefetched | 0.00 |
Bytes loaded | 332.00 |
Bytes stored | 64.00 |
Stride 0 | 2.00 |
Stride 1 | 0.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 25.00 |
Vectorization ratio all | 38.61 |
Vectorization ratio load | 2.44 |
Vectorization ratio store | 100.00 |
Vectorization ratio mul | 100.00 |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | 100.00 |
Vectorization ratio div_sqrt | 11.11 |
Vectorization ratio other | 39.68 |
Vector-efficiency ratio all | 30.82 |
Vector-efficiency ratio load | 13.41 |
Vector-efficiency ratio store | 100.00 |
Vector-efficiency ratio mul | 100.00 |
Vector-efficiency ratio add_sub | 84.38 |
Vector-efficiency ratio fma | 100.00 |
Vector-efficiency ratio div_sqrt | 22.22 |
Vector-efficiency ratio other | 24.40 |
Path / |
Function | .omp_outlined..20 |
Source file and lines | advec_mom.cpp:181-211 |
Module | exec |
nb instructions | 223 |
nb uops | 345 |
loop length | 1379 |
used x86 registers | 13 |
used mmx registers | 0 |
used xmm registers | 15 |
used ymm registers | 17 |
used zmm registers | 21.50 |
nb stack references | 1.50 |
ADD-SUB / MUL ratio | 1.35 |
micro-operation queue | 57.50 cycles |
front end | 57.50 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 16.00 | 0.50 | 8.00 | 0.50 | 2.50 | 14.67 | 14.67 | 14.67 | 40.00 | 40.33 | 40.29 | 40.38 | 42.50 | 42.50 |
cycles | 16.00 | 0.50 | 8.00 | 0.50 | 2.50 | 15.00 | 15.00 | 15.00 | 46.00 | 41.33 | 40.79 | 44.38 | 42.50 | 42.50 |
Cycles executing div or sqrt instructions | 78.50-118.50 |
Longest recurrence chain latency (RecMII) | 1.00 |
Front-end | 57.50 |
Dispatch | 46.50 |
DIV/SQRT | 78.50-118.50 |
Data deps. | 1.00 |
Overall L1 | 78.50-118.50 |
all | 38% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 27% |
all | 47% |
load | 4% |
store | 100% |
mul | 100% |
add-sub | 100% |
fma | 100% |
div/sqrt | 100% |
other | 98% |
all | 41% |
load | 6% |
store | 100% |
mul | 100% |
add-sub | 100% |
fma | 100% |
div/sqrt | 22% |
other | 42% |
all | 29% |
load | 50% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | 80% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 19% |
all | 40% |
load | 16% |
store | 100% |
mul | 100% |
add-sub | 100% |
fma | 100% |
div/sqrt | 100% |
other | 56% |
all | 34% |
load | 17% |
store | 100% |
mul | 100% |
add-sub | 85% |
fma | 100% |
div/sqrt | 31% |
other | 27% |
Function | .omp_outlined..20 |
Source file and lines | advec_mom.cpp:181-211 |
Module | exec |
nb instructions | 238 |
nb uops | 406 |
loop length | 1475 |
used x86 registers | 13 |
used mmx registers | 0 |
used xmm registers | 15 |
used ymm registers | 17 |
used zmm registers | 22 |
nb stack references | 2 |
ADD-SUB / MUL ratio | 1.20 |
micro-operation queue | 67.67 cycles |
front end | 67.67 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 16.00 | 0.50 | 8.00 | 0.50 | 3.00 | 15.33 | 15.33 | 15.33 | 46.50 | 46.50 | 46.58 | 46.42 | 47.50 | 47.50 |
cycles | 16.00 | 0.50 | 8.00 | 0.50 | 3.00 | 16.00 | 16.00 | 16.00 | 55.50 | 47.50 | 47.08 | 51.92 | 47.50 | 47.50 |
Cycles executing div or sqrt instructions | 92.00-132.00 |
Longest recurrence chain latency (RecMII) | 1.00 |
Front-end | 67.67 |
Dispatch | 55.50 |
DIV/SQRT | 92.00-132.00 |
Data deps. | 1.00 |
Overall L1 | 92.00-132.00 |
all | 38% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 28% |
all | 54% |
load | 8% |
store | 100% |
mul | 100% |
add-sub | 100% |
fma | 100% |
div/sqrt | 100% |
other | 97% |
all | 45% |
load | 10% |
store | 100% |
mul | 100% |
add-sub | 100% |
fma | 100% |
div/sqrt | 33% |
other | 46% |
all | 29% |
load | 50% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | 80% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 20% |
all | 48% |
load | 20% |
store | 100% |
mul | 100% |
add-sub | 100% |
fma | 100% |
div/sqrt | 100% |
other | 65% |
all | 37% |
load | 20% |
store | 100% |
mul | 100% |
add-sub | 86% |
fma | 100% |
div/sqrt | 41% |
other | 31% |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VSUBPD %ZMM20,%ZMM13,%ZMM19 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMOVAPD %ZMM24,%ZMM18{%K2}{z} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV -0x60(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
VPMULLQ %ZMM16,%ZMM7,%ZMM16 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 1 |
KXNORW %K0,%K0,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD $-0x8,%R8 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
VPADDQ %ZMM14,%ZMM0,%ZMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.50 |
VFMADD213PD %ZMM21,%ZMM18,%ZMM19 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 1 |
VPADDQ %ZMM15,%ZMM16,%ZMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.50 |
VMULPD %ZMM19,%ZMM17,%ZMM17 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 1 |
VSCATTERQPD %ZMM17,(%RAX,%ZMM15,8){%K1} | 48 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 3.50 | 1.50 | 9 | 9 | 1-40 | 12.14 |
JE 23c173 <.omp_outlined..20+0x773> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
VEXTRACTI32X4 $0x3,%ZMM0,%XMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 4 | 1 |
VPEXTRQ $0x1,%XMM8,%RSI | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 6 | 1 |
VPEXTRQ $0x1,%XMM15,%RAX | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 6 | 1 |
CQTO | |||||||||||||||||
IDIV %RSI | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 9-19 | 7-12 |
VMOVQ %XMM8,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VMOVQ %RAX,%XMM16 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
VMOVQ %XMM15,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
CQTO | |||||||||||||||||
IDIV %RSI | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 9-19 | 7-12 |
VPEXTRQ $0x1,%XMM9,%RSI | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 6 | 1 |
VMOVQ %RAX,%XMM15 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
VPUNPCKLQDQ %XMM16,%XMM15,%XMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 1 | 0.33 |
VEXTRACTI32X4 $0x2,%ZMM0,%XMM16 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 4 | 1 |
VPEXTRQ $0x1,%XMM16,%RAX | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 6 | 1 |
CQTO | |||||||||||||||||
IDIV %RSI | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 9-19 | 7-12 |
VMOVQ %XMM9,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VMOVQ %RAX,%XMM17 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
VMOVQ %XMM16,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
CQTO | |||||||||||||||||
IDIV %RSI | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 9-19 | 7-12 |
VMOVQ %RAX,%XMM16 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
VPUNPCKLQDQ %XMM17,%XMM16,%XMM16 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 1 | 0.33 |
VEXTRACTI32X4 $0x1,%YMM1,%XMM17 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 4 | 0.25 |
VINSERTI32X4 $0x1,%XMM15,%YMM16,%YMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0.50 |
VEXTRACTI32X4 $0x1,%YMM0,%XMM16 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 4 | 0.25 |
VPEXTRQ $0x1,%XMM17,%RSI | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 6 | 1 |
VPEXTRQ $0x1,%XMM16,%RAX | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 6 | 1 |
CQTO | |||||||||||||||||
IDIV %RSI | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 9-19 | 7-12 |
VMOVQ %XMM17,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VMOVQ %RAX,%XMM18 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
VMOVQ %XMM16,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
CQTO | |||||||||||||||||
IDIV %RSI | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 9-19 | 7-12 |
VPEXTRQ $0x1,%XMM1,%RSI | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 6 | 1 |
VMOVQ %RAX,%XMM16 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
VPEXTRQ $0x1,%XMM0,%RAX | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 6 | 1 |
CQTO | |||||||||||||||||
VPUNPCKLQDQ %XMM18,%XMM16,%XMM16 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 1 | 0.33 |
IDIV %RSI | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 9-19 | 7-12 |
VMOVQ %XMM1,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VMOVQ %RAX,%XMM17 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
VMOVQ %XMM0,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
CQTO | |||||||||||||||||
IDIV %RSI | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 9-19 | 7-12 |
VMOVQ %RAX,%XMM18 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
VPUNPCKLQDQ %XMM17,%XMM18,%XMM17 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 1 | 0.33 |
VINSERTI32X4 $0x1,%XMM16,%YMM17,%YMM16 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0.50 |
VINSERTI64X4 $0x1,%YMM15,%ZMM16,%ZMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 1 |
VPMOVQD %ZMM15,%YMM16 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 4 | 1 |
VPMULLQ %ZMM1,%ZMM15,%ZMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 1 |
VPSUBQ %ZMM15,%ZMM0,%ZMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.50 |
VPMOVQD %ZMM15,%YMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 4 | 1 |
VPADDD %YMM16,%YMM2,%YMM20 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.25 |
VPMOVSXDQ %YMM20,%ZMM16 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 4 | 1 |
VPADDD %YMM3,%YMM15,%YMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.25 |
VPMOVSXDQ %YMM15,%ZMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 4 | 1 |
VPMULLQ %ZMM16,%ZMM4,%ZMM17 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 1 |
VPADDQ %ZMM15,%ZMM17,%ZMM17 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.50 |
VEXTRACTI32X4 $0x1,%YMM17,%XMM18 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 4 | 0.25 |
VMOVQ %XMM17,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VPEXTRQ $0x1,%XMM17,%RDX | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 6 | 1 |
VMOVQ %XMM18,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VPEXTRQ $0x1,%XMM18,%RBX | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 6 | 1 |
VEXTRACTI32X4 $0x2,%ZMM17,%XMM18 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 4 | 1 |
VEXTRACTI32X4 $0x3,%ZMM17,%XMM17 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 4 | 1 |
VMOVSD (%RDI,%RAX,8),%XMM19 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVQ %XMM18,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VMOVQ %XMM17,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VPEXTRQ $0x1,%XMM18,%R12 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 6 | 1 |
VPEXTRQ $0x1,%XMM17,%R10 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 6 | 1 |
VMOVHPD (%RDI,%RDX,8),%XMM19,%XMM19 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 9 | 0.50 |
VMOVSD (%RDI,%R13,8),%XMM17 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVSD (%RDI,%R14,8),%XMM18 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVHPD (%RDI,%R10,8),%XMM17,%XMM17 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 9 | 0.50 |
VMOVHPD (%RDI,%R12,8),%XMM18,%XMM18 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 9 | 0.50 |
VINSERTF32X4 $0x1,%XMM17,%YMM18,%YMM17 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0.50 |
VMOVSD (%RDI,%RSI,8),%XMM18 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVHPD (%RDI,%RBX,8),%XMM18,%XMM18 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 9 | 0.50 |
VINSERTF32X4 $0x1,%XMM18,%YMM19,%YMM18 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0.50 |
VPSUBD %YMM11,%YMM20,%YMM19 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.25 |
VPMOVSXDQ %YMM19,%ZMM22 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 4 | 1 |
VINSERTF64X4 $0x1,%YMM17,%ZMM18,%ZMM17 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 1 |
VPADDD %YMM11,%YMM20,%YMM18 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.25 |
VMOVDQA64 %YMM18,%YMM23 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VCMPPD $0x1,%ZMM10,%ZMM17,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 1 |
VPBLENDMQ %ZMM22,%ZMM16,%ZMM21{%K1} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.50 |
VPADDD -0x391d8(%RIP){1to8},%YMM20,%YMM23{%K1} | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.50 |
VANDPD %ZMM12,%ZMM17,%ZMM20 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.50 |
VMOVDQA64 %ZMM16,%ZMM22{%K1} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VPMULLQ %ZMM22,%ZMM6,%ZMM22 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 1 |
VPMULLQ %ZMM21,%ZMM5,%ZMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 1 |
VPMULLQ %ZMM21,%ZMM6,%ZMM21 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 1 |
VPADDQ %ZMM15,%ZMM22,%ZMM22 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.50 |
VPADDQ %ZMM15,%ZMM24,%ZMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.50 |
VPADDQ %ZMM15,%ZMM21,%ZMM21 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.50 |
VEXTRACTI32X4 $0x1,%YMM24,%XMM25 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 4 | 0.25 |
VMOVQ %XMM24,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VPEXTRQ $0x1,%XMM24,%RDX | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 6 | 1 |
VMOVQ %XMM25,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VPEXTRQ $0x1,%XMM25,%R10 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 6 | 1 |
VEXTRACTI32X4 $0x2,%ZMM24,%XMM25 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 4 | 1 |
VEXTRACTI32X4 $0x3,%ZMM24,%XMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 4 | 1 |
VMOVSD (%R9,%RAX,8),%XMM26 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVQ %XMM21,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VMOVQ %XMM25,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VMOVQ %XMM24,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VPEXTRQ $0x1,%XMM25,%R14 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 6 | 1 |
VPEXTRQ $0x1,%XMM24,%R13 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 6 | 1 |
VMOVHPD (%R9,%RDX,8),%XMM26,%XMM26 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 9 | 0.50 |
VPEXTRQ $0x1,%XMM21,%RDX | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 6 | 1 |
VMOVSD (%R9,%R12,8),%XMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVSD (%R9,%RBX,8),%XMM25 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VPMOVSXDQ %YMM23,%ZMM23 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 4 | 1 |
VMOVHPD (%R9,%R13,8),%XMM24,%XMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 9 | 0.50 |
VMOVHPD (%R9,%R14,8),%XMM25,%XMM25 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 9 | 0.50 |
VPMULLQ %ZMM23,%ZMM6,%ZMM23 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 1 |
VPADDQ %ZMM15,%ZMM23,%ZMM23 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.50 |
VINSERTF32X4 $0x1,%XMM24,%YMM25,%YMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0.50 |
VMOVSD (%R9,%RSI,8),%XMM25 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVHPD (%R9,%R10,8),%XMM25,%XMM25 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 9 | 0.50 |
VINSERTF32X4 $0x1,%XMM25,%YMM26,%YMM25 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0.50 |
VINSERTF64X4 $0x1,%YMM24,%ZMM25,%ZMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 1 |
VMOVSD (%R11,%RAX,8),%XMM25 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVQ %XMM23,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VMOVHPD (%R11,%RDX,8),%XMM25,%XMM25 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 9 | 0.50 |
VPEXTRQ $0x1,%XMM23,%RDX | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 6 | 1 |
VDIVPD %ZMM24,%ZMM20,%ZMM20 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13 | 9 |
VEXTRACTI32X4 $0x1,%YMM21,%XMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 4 | 0.25 |
VMOVQ %XMM24,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VPEXTRQ $0x1,%XMM24,%R10 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 6 | 1 |
VEXTRACTI32X4 $0x2,%ZMM21,%XMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 4 | 1 |
VEXTRACTI32X4 $0x3,%ZMM21,%XMM21 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 4 | 1 |
VMOVQ %XMM24,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VMOVQ %XMM21,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VPEXTRQ $0x1,%XMM24,%RBX | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 6 | 1 |
VPEXTRQ $0x1,%XMM21,%R13 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 6 | 1 |
VMOVSD (%R11,%R12,8),%XMM21 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVSD (%R11,%R14,8),%XMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVHPD (%R11,%R13,8),%XMM21,%XMM21 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 9 | 0.50 |
VMOVHPD (%R11,%RBX,8),%XMM24,%XMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 9 | 0.50 |
VINSERTF32X4 $0x1,%XMM21,%YMM24,%YMM21 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0.50 |
VMOVSD (%R11,%RSI,8),%XMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVHPD (%R11,%R10,8),%XMM24,%XMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 9 | 0.50 |
VINSERTF32X4 $0x1,%XMM24,%YMM25,%YMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0.50 |
VMOVSD (%R11,%RAX,8),%XMM25 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVQ %XMM22,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VMOVHPD (%R11,%RDX,8),%XMM25,%XMM25 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 9 | 0.50 |
VPEXTRQ $0x1,%XMM22,%RDX | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 6 | 1 |
VINSERTF64X4 $0x1,%YMM21,%ZMM24,%ZMM21 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 1 |
VEXTRACTI32X4 $0x1,%YMM23,%XMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 4 | 0.25 |
VMOVQ %XMM24,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VPEXTRQ $0x1,%XMM24,%R10 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 6 | 1 |
VEXTRACTI32X4 $0x2,%ZMM23,%XMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 4 | 1 |
VEXTRACTI32X4 $0x3,%ZMM23,%XMM23 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 4 | 1 |
VMOVQ %XMM24,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VMOVQ %XMM23,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VPEXTRQ $0x1,%XMM24,%R14 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 6 | 1 |
VPEXTRQ $0x1,%XMM23,%R13 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 6 | 1 |
VMOVSD (%R11,%R12,8),%XMM23 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVSD (%R11,%RBX,8),%XMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVHPD (%R11,%R13,8),%XMM23,%XMM23 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 9 | 0.50 |
VMOVHPD (%R11,%R14,8),%XMM24,%XMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 9 | 0.50 |
VINSERTF32X4 $0x1,%XMM23,%YMM24,%YMM23 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0.50 |
VMOVSD (%R11,%RSI,8),%XMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVHPD (%R11,%R10,8),%XMM24,%XMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 9 | 0.50 |
VINSERTF32X4 $0x1,%XMM24,%YMM25,%YMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0.50 |
VMOVSD (%R11,%RAX,8),%XMM25 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVHPD (%R11,%RDX,8),%XMM25,%XMM25 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 9 | 0.50 |
VINSERTF64X4 $0x1,%YMM23,%ZMM24,%ZMM23 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 1 |
VEXTRACTI32X4 $0x1,%YMM22,%XMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 4 | 0.25 |
VPEXTRQ $0x1,%XMM24,%RSI | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 6 | 1 |
VMOVQ %XMM24,%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VEXTRACTI32X4 $0x2,%ZMM22,%XMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 4 | 1 |
VEXTRACTI32X4 $0x3,%ZMM22,%XMM22 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 4 | 1 |
VMOVQ %XMM24,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VMOVQ %XMM22,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VPEXTRQ $0x1,%XMM24,%R14 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 6 | 1 |
VPEXTRQ $0x1,%XMM22,%R13 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 6 | 1 |
VSUBPD %ZMM23,%ZMM21,%ZMM23 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMOVSD (%R11,%R12,8),%XMM22 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVSD (%R11,%RBX,8),%XMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVHPD (%R11,%R13,8),%XMM22,%XMM22 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 9 | 0.50 |
VMOVHPD (%R11,%R14,8),%XMM24,%XMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 9 | 0.50 |
VINSERTF32X4 $0x1,%XMM22,%YMM24,%YMM22 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0.50 |
VMOVSD (%R11,%R10,8),%XMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVHPD (%R11,%RSI,8),%XMM24,%XMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 9 | 0.50 |
VINSERTF32X4 $0x1,%XMM24,%YMM25,%YMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0.50 |
VINSERTF64X4 $0x1,%YMM22,%ZMM24,%ZMM22 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 1 |
VSUBPD %ZMM21,%ZMM22,%ZMM22 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMULPD %ZMM22,%ZMM23,%ZMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 1 |
VCMPPD $0x1,%ZMM24,%ZMM10,%K2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 1 |
KORTESTB %K2,%K2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0.50 | 6 | 1 |
JE 23bbb0 <.omp_outlined..20+0x1b0> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
VBROADCASTSD -0x2a8dd(%RIP),%ZMM25 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 5 | 1 |
MOV -0x48(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
VMOVDQA32 %YMM19,%YMM18{%K1} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
KMOVQ %K2,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 |
VPXORD %XMM19,%XMM19,%XMM19 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.25 |
VANDPD %ZMM12,%ZMM22,%ZMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.50 |
KMOVQ %K2,%K3 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 |
VXORPD %XMM26,%XMM26,%XMM26 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VANDPD %ZMM12,%ZMM23,%ZMM23 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.50 |
VGATHERQPD (%RAX,%ZMM16,8),%ZMM19{%K1} | 48 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.75 | 4.58 | 5.08 | 3.58 | 5 | 5 | 0-16 | 8.94 |
VCMPPD $0x6,%ZMM10,%ZMM22,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 1 |
VGATHERDPD (%RAX,%YMM18,8),%ZMM26{%K3} | 46 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1.50 | 3.83 | 4.33 | 3.33 | 5 | 5 | 0-16 | 8 |
VSUBPD %ZMM20,%ZMM25,%ZMM22 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VADDPD %ZMM13,%ZMM20,%ZMM25 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMULPD %ZMM24,%ZMM22,%ZMM22 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 1 |
VMULPD %ZMM23,%ZMM25,%ZMM25 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 1 |
VDIVPD %ZMM19,%ZMM22,%ZMM22 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13 | 9 |
VDIVPD %ZMM26,%ZMM25,%ZMM18 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13 | 9 |
VADDPD %ZMM18,%ZMM22,%ZMM18 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMULPD %ZMM18,%ZMM19,%ZMM18 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 1 |
VDIVPD -0x2a8e8(%RIP){1to8},%ZMM18,%ZMM18 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13 | 9 |
VMINPD %ZMM18,%ZMM23,%ZMM19 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 2 | 1 |
VCMPPD $0x3,%ZMM18,%ZMM18,%K3 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 1 |
VMOVAPD %ZMM23,%ZMM19{%K3} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMINPD %ZMM19,%ZMM24,%ZMM18 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 2 | 1 |
VCMPPD $0x3,%ZMM19,%ZMM19,%K3 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 1 |
VMOVAPD %ZMM24,%ZMM18{%K3} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VXORPD -0x2a8d0(%RIP){1to8},%ZMM18,%ZMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 1 |
VMOVAPD %ZMM18,%ZMM24{%K1} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 23bbb0 <.omp_outlined..20+0x1b0> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
Function | .omp_outlined..20 |
Source file and lines | advec_mom.cpp:181-211 |
Module | exec |
nb instructions | 208 |
nb uops | 284 |
loop length | 1283 |
used x86 registers | 13 |
used mmx registers | 0 |
used xmm registers | 15 |
used ymm registers | 17 |
used zmm registers | 21 |
nb stack references | 1 |
ADD-SUB / MUL ratio | 1.50 |
micro-operation queue | 47.33 cycles |
front end | 47.33 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 16.00 | 0.50 | 8.00 | 0.50 | 2.00 | 14.00 | 14.00 | 14.00 | 33.50 | 34.17 | 34.00 | 34.33 | 37.50 | 37.50 |
cycles | 16.00 | 0.50 | 8.00 | 0.50 | 2.00 | 14.00 | 14.00 | 14.00 | 36.50 | 35.17 | 34.50 | 36.83 | 37.50 | 37.50 |
Cycles executing div or sqrt instructions | 65.00-105.00 |
Longest recurrence chain latency (RecMII) | 1.00 |
Front-end | 47.33 |
Dispatch | 37.50 |
DIV/SQRT | 65.00-105.00 |
Data deps. | 1.00 |
Overall L1 | 65.00-105.00 |
all | 37% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 26% |
all | 40% |
load | 0% |
store | 100% |
mul | 100% |
add-sub | 100% |
fma | 100% |
div/sqrt | 100% |
other | 100% |
all | 38% |
load | 2% |
store | 100% |
mul | 100% |
add-sub | 100% |
fma | 100% |
div/sqrt | 11% |
other | 39% |
all | 29% |
load | 50% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | 80% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 19% |
all | 32% |
load | 12% |
store | 100% |
mul | 100% |
add-sub | 100% |
fma | 100% |
div/sqrt | 100% |
other | 47% |
all | 30% |
load | 13% |
store | 100% |
mul | 100% |
add-sub | 84% |
fma | 100% |
div/sqrt | 22% |
other | 24% |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VSUBPD %ZMM20,%ZMM13,%ZMM19 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMOVAPD %ZMM24,%ZMM18{%K2}{z} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV -0x60(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
VPMULLQ %ZMM16,%ZMM7,%ZMM16 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 1 |
KXNORW %K0,%K0,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD $-0x8,%R8 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
VPADDQ %ZMM14,%ZMM0,%ZMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.50 |
VFMADD213PD %ZMM21,%ZMM18,%ZMM19 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 1 |
VPADDQ %ZMM15,%ZMM16,%ZMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.50 |
VMULPD %ZMM19,%ZMM17,%ZMM17 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 1 |
VSCATTERQPD %ZMM17,(%RAX,%ZMM15,8){%K1} | 48 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 3.50 | 1.50 | 9 | 9 | 1-40 | 12.14 |
JE 23c173 <.omp_outlined..20+0x773> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
VEXTRACTI32X4 $0x3,%ZMM0,%XMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 4 | 1 |
VPEXTRQ $0x1,%XMM8,%RSI | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 6 | 1 |
VPEXTRQ $0x1,%XMM15,%RAX | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 6 | 1 |
CQTO | |||||||||||||||||
IDIV %RSI | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 9-19 | 7-12 |
VMOVQ %XMM8,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VMOVQ %RAX,%XMM16 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
VMOVQ %XMM15,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
CQTO | |||||||||||||||||
IDIV %RSI | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 9-19 | 7-12 |
VPEXTRQ $0x1,%XMM9,%RSI | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 6 | 1 |
VMOVQ %RAX,%XMM15 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
VPUNPCKLQDQ %XMM16,%XMM15,%XMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 1 | 0.33 |
VEXTRACTI32X4 $0x2,%ZMM0,%XMM16 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 4 | 1 |
VPEXTRQ $0x1,%XMM16,%RAX | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 6 | 1 |
CQTO | |||||||||||||||||
IDIV %RSI | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 9-19 | 7-12 |
VMOVQ %XMM9,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VMOVQ %RAX,%XMM17 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
VMOVQ %XMM16,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
CQTO | |||||||||||||||||
IDIV %RSI | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 9-19 | 7-12 |
VMOVQ %RAX,%XMM16 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
VPUNPCKLQDQ %XMM17,%XMM16,%XMM16 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 1 | 0.33 |
VEXTRACTI32X4 $0x1,%YMM1,%XMM17 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 4 | 0.25 |
VINSERTI32X4 $0x1,%XMM15,%YMM16,%YMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0.50 |
VEXTRACTI32X4 $0x1,%YMM0,%XMM16 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 4 | 0.25 |
VPEXTRQ $0x1,%XMM17,%RSI | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 6 | 1 |
VPEXTRQ $0x1,%XMM16,%RAX | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 6 | 1 |
CQTO | |||||||||||||||||
IDIV %RSI | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 9-19 | 7-12 |
VMOVQ %XMM17,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VMOVQ %RAX,%XMM18 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
VMOVQ %XMM16,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
CQTO | |||||||||||||||||
IDIV %RSI | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 9-19 | 7-12 |
VPEXTRQ $0x1,%XMM1,%RSI | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 6 | 1 |
VMOVQ %RAX,%XMM16 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
VPEXTRQ $0x1,%XMM0,%RAX | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 6 | 1 |
CQTO | |||||||||||||||||
VPUNPCKLQDQ %XMM18,%XMM16,%XMM16 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 1 | 0.33 |
IDIV %RSI | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 9-19 | 7-12 |
VMOVQ %XMM1,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VMOVQ %RAX,%XMM17 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
VMOVQ %XMM0,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
CQTO | |||||||||||||||||
IDIV %RSI | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 9-19 | 7-12 |
VMOVQ %RAX,%XMM18 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
VPUNPCKLQDQ %XMM17,%XMM18,%XMM17 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 1 | 0.33 |
VINSERTI32X4 $0x1,%XMM16,%YMM17,%YMM16 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0.50 |
VINSERTI64X4 $0x1,%YMM15,%ZMM16,%ZMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 1 |
VPMOVQD %ZMM15,%YMM16 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 4 | 1 |
VPMULLQ %ZMM1,%ZMM15,%ZMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 1 |
VPSUBQ %ZMM15,%ZMM0,%ZMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.50 |
VPMOVQD %ZMM15,%YMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 4 | 1 |
VPADDD %YMM16,%YMM2,%YMM20 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.25 |
VPMOVSXDQ %YMM20,%ZMM16 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 4 | 1 |
VPADDD %YMM3,%YMM15,%YMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.25 |
VPMOVSXDQ %YMM15,%ZMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 4 | 1 |
VPMULLQ %ZMM16,%ZMM4,%ZMM17 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 1 |
VPADDQ %ZMM15,%ZMM17,%ZMM17 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.50 |
VEXTRACTI32X4 $0x1,%YMM17,%XMM18 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 4 | 0.25 |
VMOVQ %XMM17,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VPEXTRQ $0x1,%XMM17,%RDX | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 6 | 1 |
VMOVQ %XMM18,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VPEXTRQ $0x1,%XMM18,%RBX | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 6 | 1 |
VEXTRACTI32X4 $0x2,%ZMM17,%XMM18 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 4 | 1 |
VEXTRACTI32X4 $0x3,%ZMM17,%XMM17 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 4 | 1 |
VMOVSD (%RDI,%RAX,8),%XMM19 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVQ %XMM18,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VMOVQ %XMM17,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VPEXTRQ $0x1,%XMM18,%R12 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 6 | 1 |
VPEXTRQ $0x1,%XMM17,%R10 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 6 | 1 |
VMOVHPD (%RDI,%RDX,8),%XMM19,%XMM19 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 9 | 0.50 |
VMOVSD (%RDI,%R13,8),%XMM17 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVSD (%RDI,%R14,8),%XMM18 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVHPD (%RDI,%R10,8),%XMM17,%XMM17 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 9 | 0.50 |
VMOVHPD (%RDI,%R12,8),%XMM18,%XMM18 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 9 | 0.50 |
VINSERTF32X4 $0x1,%XMM17,%YMM18,%YMM17 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0.50 |
VMOVSD (%RDI,%RSI,8),%XMM18 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVHPD (%RDI,%RBX,8),%XMM18,%XMM18 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 9 | 0.50 |
VINSERTF32X4 $0x1,%XMM18,%YMM19,%YMM18 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0.50 |
VPSUBD %YMM11,%YMM20,%YMM19 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.25 |
VPMOVSXDQ %YMM19,%ZMM22 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 4 | 1 |
VINSERTF64X4 $0x1,%YMM17,%ZMM18,%ZMM17 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 1 |
VPADDD %YMM11,%YMM20,%YMM18 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.25 |
VMOVDQA64 %YMM18,%YMM23 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VCMPPD $0x1,%ZMM10,%ZMM17,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 1 |
VPBLENDMQ %ZMM22,%ZMM16,%ZMM21{%K1} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.50 |
VPADDD -0x391d8(%RIP){1to8},%YMM20,%YMM23{%K1} | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.50 |
VANDPD %ZMM12,%ZMM17,%ZMM20 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.50 |
VMOVDQA64 %ZMM16,%ZMM22{%K1} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VPMULLQ %ZMM22,%ZMM6,%ZMM22 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 1 |
VPMULLQ %ZMM21,%ZMM5,%ZMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 1 |
VPMULLQ %ZMM21,%ZMM6,%ZMM21 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 1 |
VPADDQ %ZMM15,%ZMM22,%ZMM22 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.50 |
VPADDQ %ZMM15,%ZMM24,%ZMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.50 |
VPADDQ %ZMM15,%ZMM21,%ZMM21 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.50 |
VEXTRACTI32X4 $0x1,%YMM24,%XMM25 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 4 | 0.25 |
VMOVQ %XMM24,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VPEXTRQ $0x1,%XMM24,%RDX | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 6 | 1 |
VMOVQ %XMM25,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VPEXTRQ $0x1,%XMM25,%R10 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 6 | 1 |
VEXTRACTI32X4 $0x2,%ZMM24,%XMM25 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 4 | 1 |
VEXTRACTI32X4 $0x3,%ZMM24,%XMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 4 | 1 |
VMOVSD (%R9,%RAX,8),%XMM26 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVQ %XMM21,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VMOVQ %XMM25,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VMOVQ %XMM24,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VPEXTRQ $0x1,%XMM25,%R14 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 6 | 1 |
VPEXTRQ $0x1,%XMM24,%R13 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 6 | 1 |
VMOVHPD (%R9,%RDX,8),%XMM26,%XMM26 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 9 | 0.50 |
VPEXTRQ $0x1,%XMM21,%RDX | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 6 | 1 |
VMOVSD (%R9,%R12,8),%XMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVSD (%R9,%RBX,8),%XMM25 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VPMOVSXDQ %YMM23,%ZMM23 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 4 | 1 |
VMOVHPD (%R9,%R13,8),%XMM24,%XMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 9 | 0.50 |
VMOVHPD (%R9,%R14,8),%XMM25,%XMM25 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 9 | 0.50 |
VPMULLQ %ZMM23,%ZMM6,%ZMM23 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 1 |
VPADDQ %ZMM15,%ZMM23,%ZMM23 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.50 |
VINSERTF32X4 $0x1,%XMM24,%YMM25,%YMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0.50 |
VMOVSD (%R9,%RSI,8),%XMM25 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVHPD (%R9,%R10,8),%XMM25,%XMM25 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 9 | 0.50 |
VINSERTF32X4 $0x1,%XMM25,%YMM26,%YMM25 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0.50 |
VINSERTF64X4 $0x1,%YMM24,%ZMM25,%ZMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 1 |
VMOVSD (%R11,%RAX,8),%XMM25 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVQ %XMM23,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VMOVHPD (%R11,%RDX,8),%XMM25,%XMM25 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 9 | 0.50 |
VPEXTRQ $0x1,%XMM23,%RDX | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 6 | 1 |
VDIVPD %ZMM24,%ZMM20,%ZMM20 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13 | 9 |
VEXTRACTI32X4 $0x1,%YMM21,%XMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 4 | 0.25 |
VMOVQ %XMM24,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VPEXTRQ $0x1,%XMM24,%R10 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 6 | 1 |
VEXTRACTI32X4 $0x2,%ZMM21,%XMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 4 | 1 |
VEXTRACTI32X4 $0x3,%ZMM21,%XMM21 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 4 | 1 |
VMOVQ %XMM24,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VMOVQ %XMM21,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VPEXTRQ $0x1,%XMM24,%RBX | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 6 | 1 |
VPEXTRQ $0x1,%XMM21,%R13 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 6 | 1 |
VMOVSD (%R11,%R12,8),%XMM21 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVSD (%R11,%R14,8),%XMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVHPD (%R11,%R13,8),%XMM21,%XMM21 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 9 | 0.50 |
VMOVHPD (%R11,%RBX,8),%XMM24,%XMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 9 | 0.50 |
VINSERTF32X4 $0x1,%XMM21,%YMM24,%YMM21 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0.50 |
VMOVSD (%R11,%RSI,8),%XMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVHPD (%R11,%R10,8),%XMM24,%XMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 9 | 0.50 |
VINSERTF32X4 $0x1,%XMM24,%YMM25,%YMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0.50 |
VMOVSD (%R11,%RAX,8),%XMM25 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVQ %XMM22,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VMOVHPD (%R11,%RDX,8),%XMM25,%XMM25 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 9 | 0.50 |
VPEXTRQ $0x1,%XMM22,%RDX | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 6 | 1 |
VINSERTF64X4 $0x1,%YMM21,%ZMM24,%ZMM21 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 1 |
VEXTRACTI32X4 $0x1,%YMM23,%XMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 4 | 0.25 |
VMOVQ %XMM24,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VPEXTRQ $0x1,%XMM24,%R10 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 6 | 1 |
VEXTRACTI32X4 $0x2,%ZMM23,%XMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 4 | 1 |
VEXTRACTI32X4 $0x3,%ZMM23,%XMM23 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 4 | 1 |
VMOVQ %XMM24,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VMOVQ %XMM23,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VPEXTRQ $0x1,%XMM24,%R14 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 6 | 1 |
VPEXTRQ $0x1,%XMM23,%R13 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 6 | 1 |
VMOVSD (%R11,%R12,8),%XMM23 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVSD (%R11,%RBX,8),%XMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVHPD (%R11,%R13,8),%XMM23,%XMM23 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 9 | 0.50 |
VMOVHPD (%R11,%R14,8),%XMM24,%XMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 9 | 0.50 |
VINSERTF32X4 $0x1,%XMM23,%YMM24,%YMM23 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0.50 |
VMOVSD (%R11,%RSI,8),%XMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVHPD (%R11,%R10,8),%XMM24,%XMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 9 | 0.50 |
VINSERTF32X4 $0x1,%XMM24,%YMM25,%YMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0.50 |
VMOVSD (%R11,%RAX,8),%XMM25 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVHPD (%R11,%RDX,8),%XMM25,%XMM25 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 9 | 0.50 |
VINSERTF64X4 $0x1,%YMM23,%ZMM24,%ZMM23 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 1 |
VEXTRACTI32X4 $0x1,%YMM22,%XMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 4 | 0.25 |
VPEXTRQ $0x1,%XMM24,%RSI | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 6 | 1 |
VMOVQ %XMM24,%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VEXTRACTI32X4 $0x2,%ZMM22,%XMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 4 | 1 |
VEXTRACTI32X4 $0x3,%ZMM22,%XMM22 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 4 | 1 |
VMOVQ %XMM24,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VMOVQ %XMM22,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VPEXTRQ $0x1,%XMM24,%R14 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 6 | 1 |
VPEXTRQ $0x1,%XMM22,%R13 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 6 | 1 |
VSUBPD %ZMM23,%ZMM21,%ZMM23 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMOVSD (%R11,%R12,8),%XMM22 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVSD (%R11,%RBX,8),%XMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVHPD (%R11,%R13,8),%XMM22,%XMM22 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 9 | 0.50 |
VMOVHPD (%R11,%R14,8),%XMM24,%XMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 9 | 0.50 |
VINSERTF32X4 $0x1,%XMM22,%YMM24,%YMM22 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0.50 |
VMOVSD (%R11,%R10,8),%XMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVHPD (%R11,%RSI,8),%XMM24,%XMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 9 | 0.50 |
VINSERTF32X4 $0x1,%XMM24,%YMM25,%YMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0.50 |
VINSERTF64X4 $0x1,%YMM22,%ZMM24,%ZMM22 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 1 |
VSUBPD %ZMM21,%ZMM22,%ZMM22 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMULPD %ZMM22,%ZMM23,%ZMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 1 |
VCMPPD $0x1,%ZMM24,%ZMM10,%K2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 1 |
KORTESTB %K2,%K2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0.50 | 6 | 1 |
JE 23bbb0 <.omp_outlined..20+0x1b0> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |