Loop Id: 184 | Module: exec | Source: advec_mom.cpp:74-75 | Coverage: 2.55% |
---|
Loop Id: 184 | Module: exec | Source: advec_mom.cpp:74-75 | Coverage: 2.55% |
---|
0x42de6b VMOVUPD (%R12,%RAX,1),%ZMM0 [1] |
0x42de72 VMOVUPD %ZMM0,(%RBX,%RAX,1) [4] |
0x42de79 VADDPD (%R10,%RAX,1),%ZMM0,%ZMM1 [2] |
0x42de80 VSUBPD (%R9,%RAX,1),%ZMM1,%ZMM9 [5] |
0x42de87 VMOVUPD %ZMM9,(%RDX,%RAX,1) [3] |
0x42de8e VMOVUPD 0x40(%R12,%RAX,1),%ZMM10 [1] |
0x42de96 VMOVUPD %ZMM10,0x40(%RBX,%RAX,1) [4] |
0x42de9e VADDPD 0x40(%R10,%RAX,1),%ZMM10,%ZMM11 [2] |
0x42dea6 VSUBPD 0x40(%R9,%RAX,1),%ZMM11,%ZMM12 [5] |
0x42deae VMOVUPD %ZMM12,0x40(%RDX,%RAX,1) [3] |
0x42deb6 VMOVUPD 0x80(%R12,%RAX,1),%ZMM13 [1] |
0x42debe VMOVUPD %ZMM13,0x80(%RBX,%RAX,1) [4] |
0x42dec6 VADDPD 0x80(%R10,%RAX,1),%ZMM13,%ZMM14 [2] |
0x42dece VSUBPD 0x80(%R9,%RAX,1),%ZMM14,%ZMM15 [5] |
0x42ded6 VMOVUPD %ZMM15,0x80(%RDX,%RAX,1) [3] |
0x42dede VMOVUPD 0xc0(%R12,%RAX,1),%ZMM6 [1] |
0x42dee6 VMOVUPD %ZMM6,0xc0(%RBX,%RAX,1) [4] |
0x42deee VADDPD 0xc0(%R10,%RAX,1),%ZMM6,%ZMM0 [2] |
0x42def6 VSUBPD 0xc0(%R9,%RAX,1),%ZMM0,%ZMM1 [5] |
0x42defe VMOVUPD %ZMM1,0xc0(%RDX,%RAX,1) [3] |
0x42df06 VMOVUPD 0x100(%R12,%RAX,1),%ZMM9 [1] |
0x42df0e VMOVUPD %ZMM9,0x100(%RBX,%RAX,1) [4] |
0x42df16 VADDPD 0x100(%R10,%RAX,1),%ZMM9,%ZMM10 [2] |
0x42df1e VSUBPD 0x100(%R9,%RAX,1),%ZMM10,%ZMM11 [5] |
0x42df26 VMOVUPD %ZMM11,0x100(%RDX,%RAX,1) [3] |
0x42df2e VMOVUPD 0x140(%R12,%RAX,1),%ZMM12 [1] |
0x42df36 VMOVUPD %ZMM12,0x140(%RBX,%RAX,1) [4] |
0x42df3e VADDPD 0x140(%R10,%RAX,1),%ZMM12,%ZMM13 [2] |
0x42df46 VSUBPD 0x140(%R9,%RAX,1),%ZMM13,%ZMM14 [5] |
0x42df4e VMOVUPD %ZMM14,0x140(%RDX,%RAX,1) [3] |
0x42df56 VMOVUPD 0x180(%R12,%RAX,1),%ZMM15 [1] |
0x42df5e VMOVUPD %ZMM15,0x180(%RBX,%RAX,1) [4] |
0x42df66 VADDPD 0x180(%R10,%RAX,1),%ZMM15,%ZMM6 [2] |
0x42df6e VSUBPD 0x180(%R9,%RAX,1),%ZMM6,%ZMM0 [5] |
0x42df76 VMOVUPD %ZMM0,0x180(%RDX,%RAX,1) [3] |
0x42df7e VMOVUPD 0x1c0(%R12,%RAX,1),%ZMM1 [1] |
0x42df86 VMOVUPD %ZMM1,0x1c0(%RBX,%RAX,1) [4] |
0x42df8e VADDPD 0x1c0(%R10,%RAX,1),%ZMM1,%ZMM9 [2] |
0x42df96 VSUBPD 0x1c0(%R9,%RAX,1),%ZMM9,%ZMM10 [5] |
0x42df9e VMOVUPD %ZMM10,0x1c0(%RDX,%RAX,1) [3] |
0x42dfa6 ADD $0x200,%RAX |
0x42dfac CMP %RAX,%R15 |
0x42dfaf JNE 42de6b |
/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp: 74 - 75 |
-------------------------------------------------------------------------------- |
74: post_vol(i, j) = volume(i, j); |
75: pre_vol(i, j) = post_vol(i, j) + vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j); |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 1.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.33 |
Bottlenecks | P5, P6, P7, |
Function | _Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.3 |
Source | advec_mom.cpp:74-75 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 21.33 |
CQA cycles if no scalar integer | 21.33 |
CQA cycles if FP arith vectorized | 21.33 |
CQA cycles if fully vectorized | 21.33 |
Front-end cycles | 9.67 |
DIV/SQRT cycles | 0.50 |
P0 cycles | 0.50 |
P1 cycles | 0.25 |
P2 cycles | 0.25 |
P3 cycles | 0.50 |
P4 cycles | 21.33 |
P5 cycles | 21.33 |
P6 cycles | 21.33 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 16.00 |
P10 cycles | 16.00 |
P11 cycles | 16.00 |
P12 cycles | 16.00 |
P13 cycles | 0.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 43.00 |
Nb uops | 58.00 |
Nb loads | 24.00 |
Nb stores | 16.00 |
Nb stack references | 0.00 |
FLOP/cycle | 6.00 |
Nb FLOP add-sub | 128.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 120.00 |
Bytes prefetched | 0.00 |
Bytes loaded | 1536.00 |
Bytes stored | 1024.00 |
Stride 0 | 0.00 |
Stride 1 | 5.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 100.00 |
Vectorization ratio load | 100.00 |
Vectorization ratio store | 100.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | NA |
Vector-efficiency ratio all | 100.00 |
Vector-efficiency ratio load | 100.00 |
Vector-efficiency ratio store | 100.00 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 100.00 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | NA |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 1.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.33 |
Bottlenecks | P5, P6, P7, |
Function | _Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.3 |
Source | advec_mom.cpp:74-75 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 21.33 |
CQA cycles if no scalar integer | 21.33 |
CQA cycles if FP arith vectorized | 21.33 |
CQA cycles if fully vectorized | 21.33 |
Front-end cycles | 9.67 |
DIV/SQRT cycles | 0.50 |
P0 cycles | 0.50 |
P1 cycles | 0.25 |
P2 cycles | 0.25 |
P3 cycles | 0.50 |
P4 cycles | 21.33 |
P5 cycles | 21.33 |
P6 cycles | 21.33 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 16.00 |
P10 cycles | 16.00 |
P11 cycles | 16.00 |
P12 cycles | 16.00 |
P13 cycles | 0.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 43.00 |
Nb uops | 58.00 |
Nb loads | 24.00 |
Nb stores | 16.00 |
Nb stack references | 0.00 |
FLOP/cycle | 6.00 |
Nb FLOP add-sub | 128.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 120.00 |
Bytes prefetched | 0.00 |
Bytes loaded | 1536.00 |
Bytes stored | 1024.00 |
Stride 0 | 0.00 |
Stride 1 | 5.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 100.00 |
Vectorization ratio load | 100.00 |
Vectorization ratio store | 100.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | NA |
Vector-efficiency ratio all | 100.00 |
Vector-efficiency ratio load | 100.00 |
Vector-efficiency ratio store | 100.00 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 100.00 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | NA |
Path / |
Function | _Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.3 |
Source file and lines | advec_mom.cpp:74-75 |
Module | exec |
nb instructions | 43 |
nb uops | 58 |
loop length | 330 |
used x86 registers | 7 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 10 |
nb stack references | 0 |
micro-operation queue | 9.67 cycles |
front end | 9.67 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 0.50 | 0.50 | 0.25 | 0.25 | 0.50 | 13.33 | 13.33 | 13.33 | 0.00 | 0.00 | 8.00 | 8.00 | 16.00 | 16.00 |
cycles | 0.50 | 0.50 | 0.25 | 0.25 | 0.50 | 21.33 | 21.33 | 21.33 | 0.00 | 0.00 | 16.00 | 16.00 | 16.00 | 16.00 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 1.00 |
Front-end | 9.67 |
Dispatch | 21.33 |
Data deps. | 1.00 |
Overall L1 | 21.33 |
all | 100% |
load | 100% |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 100% |
load | 100% |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VMOVUPD (%R12,%RAX,1),%ZMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM0,(%RBX,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VADDPD (%R10,%RAX,1),%ZMM0,%ZMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VSUBPD (%R9,%RAX,1),%ZMM1,%ZMM9 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM9,(%RDX,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VMOVUPD 0x40(%R12,%RAX,1),%ZMM10 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM10,0x40(%RBX,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VADDPD 0x40(%R10,%RAX,1),%ZMM10,%ZMM11 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VSUBPD 0x40(%R9,%RAX,1),%ZMM11,%ZMM12 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM12,0x40(%RDX,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VMOVUPD 0x80(%R12,%RAX,1),%ZMM13 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM13,0x80(%RBX,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VADDPD 0x80(%R10,%RAX,1),%ZMM13,%ZMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VSUBPD 0x80(%R9,%RAX,1),%ZMM14,%ZMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM15,0x80(%RDX,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VMOVUPD 0xc0(%R12,%RAX,1),%ZMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM6,0xc0(%RBX,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VADDPD 0xc0(%R10,%RAX,1),%ZMM6,%ZMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VSUBPD 0xc0(%R9,%RAX,1),%ZMM0,%ZMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM1,0xc0(%RDX,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VMOVUPD 0x100(%R12,%RAX,1),%ZMM9 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM9,0x100(%RBX,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VADDPD 0x100(%R10,%RAX,1),%ZMM9,%ZMM10 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VSUBPD 0x100(%R9,%RAX,1),%ZMM10,%ZMM11 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM11,0x100(%RDX,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VMOVUPD 0x140(%R12,%RAX,1),%ZMM12 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM12,0x140(%RBX,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VADDPD 0x140(%R10,%RAX,1),%ZMM12,%ZMM13 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VSUBPD 0x140(%R9,%RAX,1),%ZMM13,%ZMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM14,0x140(%RDX,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VMOVUPD 0x180(%R12,%RAX,1),%ZMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM15,0x180(%RBX,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VADDPD 0x180(%R10,%RAX,1),%ZMM15,%ZMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VSUBPD 0x180(%R9,%RAX,1),%ZMM6,%ZMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM0,0x180(%RDX,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VMOVUPD 0x1c0(%R12,%RAX,1),%ZMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM1,0x1c0(%RBX,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VADDPD 0x1c0(%R10,%RAX,1),%ZMM1,%ZMM9 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VSUBPD 0x1c0(%R9,%RAX,1),%ZMM9,%ZMM10 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM10,0x1c0(%RDX,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
ADD $0x200,%RAX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP %RAX,%R15 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JNE 42de6b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.3+0x2fb> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
Function | _Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.3 |
Source file and lines | advec_mom.cpp:74-75 |
Module | exec |
nb instructions | 43 |
nb uops | 58 |
loop length | 330 |
used x86 registers | 7 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 10 |
nb stack references | 0 |
micro-operation queue | 9.67 cycles |
front end | 9.67 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 0.50 | 0.50 | 0.25 | 0.25 | 0.50 | 13.33 | 13.33 | 13.33 | 0.00 | 0.00 | 8.00 | 8.00 | 16.00 | 16.00 |
cycles | 0.50 | 0.50 | 0.25 | 0.25 | 0.50 | 21.33 | 21.33 | 21.33 | 0.00 | 0.00 | 16.00 | 16.00 | 16.00 | 16.00 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 1.00 |
Front-end | 9.67 |
Dispatch | 21.33 |
Data deps. | 1.00 |
Overall L1 | 21.33 |
all | 100% |
load | 100% |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 100% |
load | 100% |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VMOVUPD (%R12,%RAX,1),%ZMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM0,(%RBX,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VADDPD (%R10,%RAX,1),%ZMM0,%ZMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VSUBPD (%R9,%RAX,1),%ZMM1,%ZMM9 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM9,(%RDX,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VMOVUPD 0x40(%R12,%RAX,1),%ZMM10 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM10,0x40(%RBX,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VADDPD 0x40(%R10,%RAX,1),%ZMM10,%ZMM11 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VSUBPD 0x40(%R9,%RAX,1),%ZMM11,%ZMM12 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM12,0x40(%RDX,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VMOVUPD 0x80(%R12,%RAX,1),%ZMM13 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM13,0x80(%RBX,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VADDPD 0x80(%R10,%RAX,1),%ZMM13,%ZMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VSUBPD 0x80(%R9,%RAX,1),%ZMM14,%ZMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM15,0x80(%RDX,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VMOVUPD 0xc0(%R12,%RAX,1),%ZMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM6,0xc0(%RBX,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VADDPD 0xc0(%R10,%RAX,1),%ZMM6,%ZMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VSUBPD 0xc0(%R9,%RAX,1),%ZMM0,%ZMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM1,0xc0(%RDX,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VMOVUPD 0x100(%R12,%RAX,1),%ZMM9 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM9,0x100(%RBX,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VADDPD 0x100(%R10,%RAX,1),%ZMM9,%ZMM10 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VSUBPD 0x100(%R9,%RAX,1),%ZMM10,%ZMM11 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM11,0x100(%RDX,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VMOVUPD 0x140(%R12,%RAX,1),%ZMM12 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM12,0x140(%RBX,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VADDPD 0x140(%R10,%RAX,1),%ZMM12,%ZMM13 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VSUBPD 0x140(%R9,%RAX,1),%ZMM13,%ZMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM14,0x140(%RDX,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VMOVUPD 0x180(%R12,%RAX,1),%ZMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM15,0x180(%RBX,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VADDPD 0x180(%R10,%RAX,1),%ZMM15,%ZMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VSUBPD 0x180(%R9,%RAX,1),%ZMM6,%ZMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM0,0x180(%RDX,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VMOVUPD 0x1c0(%R12,%RAX,1),%ZMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM1,0x1c0(%RBX,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VADDPD 0x1c0(%R10,%RAX,1),%ZMM1,%ZMM9 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VSUBPD 0x1c0(%R9,%RAX,1),%ZMM9,%ZMM10 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMOVUPD %ZMM10,0x1c0(%RDX,%RAX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
ADD $0x200,%RAX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP %RAX,%R15 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JNE 42de6b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.3+0x2fb> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |