Function: _Z16initialise_chunkiR16global_variables._omp_fn.4 | Module: exec | Source: initialise_chunk.cpp:77-82 [...] | Coverage: 0.03% |
---|
Function: _Z16initialise_chunkiR16global_variables._omp_fn.4 | Module: exec | Source: initialise_chunk.cpp:77-82 [...] | Coverage: 0.03% |
---|
/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/initialise_chunk.cpp: 77 - 82 |
-------------------------------------------------------------------------------- |
77: #pragma omp parallel for simd collapse(2) |
78: for (int j = (0); j < (yrange1); j++) { |
79: for (int i = (0); i < (xrange1); i++) { |
80: field.volume(i, j) = dx * dy; |
81: field.xarea(i, j) = field.celldy[j]; |
82: field.yarea(i, j) = field.celldx[i]; |
/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 46 - 69 |
-------------------------------------------------------------------------------- |
46: T &operator[](size_t i) const { return data[i]; } |
[...] |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
0x43b770 PUSH %RBP |
0x43b771 MOV %RSP,%RBP |
0x43b774 PUSH %R15 |
0x43b776 PUSH %R14 |
0x43b778 PUSH %R13 |
0x43b77a PUSH %R12 |
0x43b77c PUSH %RBX |
0x43b77d AND $-0x40,%RSP |
0x43b781 SUB $0x40,%RSP |
0x43b785 MOV 0x1c(%RDI),%EBX |
0x43b788 MOV 0x18(%RDI),%R15D |
0x43b78c MOV %EBX,0x14(%RSP) |
0x43b790 MOV %R15D,0x10(%RSP) |
0x43b795 TEST %EBX,%EBX |
0x43b797 JLE 43bcf3 |
0x43b79d TEST %R15D,%R15D |
0x43b7a0 JLE 43bcf3 |
0x43b7a6 IMUL %R15D,%EBX |
0x43b7aa MOV %RDI,%R14 |
0x43b7ad CALL 404650 <omp_get_num_threads@plt> |
0x43b7b2 MOV %EAX,%R13D |
0x43b7b5 CALL 404540 <omp_get_thread_num@plt> |
0x43b7ba XOR %EDX,%EDX |
0x43b7bc MOV %EAX,%ECX |
0x43b7be MOV %EBX,%EAX |
0x43b7c0 DIV %R13D |
0x43b7c3 MOV %EAX,%R12D |
0x43b7c6 CMP %EDX,%ECX |
0x43b7c8 JB 43bd1c |
0x43b7ce IMUL %R12D,%ECX |
0x43b7d2 LEA (%RCX,%RDX,1),%EDI |
0x43b7d5 LEA (%R12,%RDI,1),%R8D |
0x43b7d9 MOV %R8D,0xc(%RSP) |
0x43b7de CMP %R8D,%EDI |
0x43b7e1 JAE 43bcf3 |
0x43b7e7 MOV 0x10(%RSP),%ECX |
0x43b7eb MOV %EDI,%EAX |
0x43b7ed XOR %EDX,%EDX |
0x43b7ef VMOVSD 0x8(%R14),%XMM11 |
0x43b7f5 VMULSD (%R14),%XMM11,%XMM8 |
0x43b7fa MOV 0x10(%R14),%R14 |
0x43b7fe VBROADCASTSD %XMM8,%YMM12 |
0x43b803 VBROADCASTSD %XMM8,%ZMM6 |
0x43b809 DIV %ECX |
0x43b80b SUB %EDX,%ECX |
0x43b80d MOVSXD %EAX,%R8 |
0x43b810 MOV %EDX,0x3c(%RSP) |
0x43b814 NOPW %CS:(%RAX,%RAX,1) |
0x43b81f NOP |
(245) 0x43b820 CMP %ECX,%R12D |
(245) 0x43b823 CMOVBE %R12D,%ECX |
(245) 0x43b827 LEA (%RDI,%RCX,1),%ESI |
(245) 0x43b82a MOV %ESI,0x38(%RSP) |
(245) 0x43b82e CMP %ESI,%EDI |
(245) 0x43b830 JAE 43bcbf |
(245) 0x43b836 MOV 0x248(%R14),%R10 |
(245) 0x43b83d MOV 0x290(%R14),%R9 |
(245) 0x43b844 MOV 0x2c0(%R14),%R11 |
(245) 0x43b84b LEA -0x1(%RCX),%EAX |
(245) 0x43b84e VMOVQ 0x2a0(%R14),%XMM0 |
(245) 0x43b857 MOV 0x2b8(%R14),%R12 |
(245) 0x43b85e MOV 0x228(%R14),%R13 |
(245) 0x43b865 MOV 0x2d0(%R14),%R15 |
(245) 0x43b86c LEA (%R10,%R8,8),%RBX |
(245) 0x43b870 MOV 0x2a8(%R14),%R10 |
(245) 0x43b877 IMUL %R8,%R9 |
(245) 0x43b87b IMUL %R8,%R11 |
(245) 0x43b87f MOV %R9,0x20(%RSP) |
(245) 0x43b884 MOV %R11,0x30(%RSP) |
(245) 0x43b889 IMUL %R8,%R10 |
(245) 0x43b88d MOV %R10,0x28(%RSP) |
(245) 0x43b892 CMP $0x6,%EAX |
(245) 0x43b895 JBE 43bd10 |
(245) 0x43b89b MOV %ECX,%ESI |
(245) 0x43b89d MOVSXD 0x3c(%RSP),%RAX |
(245) 0x43b8a2 VMOVQ %XMM0,%RDX |
(245) 0x43b8a7 SHR $0x3,%ESI |
(245) 0x43b8aa SAL $0x6,%RSI |
(245) 0x43b8ae MOV %RSI,0x18(%RSP) |
(245) 0x43b8b3 SUB $0x40,%RSI |
(245) 0x43b8b7 LEA (%R9,%RAX,1),%R9 |
(245) 0x43b8bb LEA (%R10,%RAX,1),%R10 |
(245) 0x43b8bf SHR $0x6,%RSI |
(245) 0x43b8c3 LEA (%RDX,%R9,8),%R9 |
(245) 0x43b8c7 INC %RSI |
(245) 0x43b8ca LEA (%R13,%RAX,8),%RDX |
(245) 0x43b8cf ADD %R11,%RAX |
(245) 0x43b8d2 LEA (%R15,%RAX,8),%R11 |
(245) 0x43b8d6 XOR %EAX,%EAX |
(245) 0x43b8d8 AND $0x7,%ESI |
(245) 0x43b8db LEA (%R12,%R10,8),%R10 |
(245) 0x43b8df JE 43ba27 |
(245) 0x43b8e5 CMP $0x1,%RSI |
(245) 0x43b8e9 JE 43b9f6 |
(245) 0x43b8ef CMP $0x2,%RSI |
(245) 0x43b8f3 JE 43b9d0 |
(245) 0x43b8f9 CMP $0x3,%RSI |
(245) 0x43b8fd JE 43b9aa |
(245) 0x43b903 CMP $0x4,%RSI |
(245) 0x43b907 JE 43b984 |
(245) 0x43b909 CMP $0x5,%RSI |
(245) 0x43b90d JE 43b95e |
(245) 0x43b90f CMP $0x6,%RSI |
(245) 0x43b913 JE 43b938 |
(245) 0x43b915 VMOVUPD %ZMM6,(%R9) |
(245) 0x43b91b VBROADCASTSD (%RBX),%ZMM13 |
(245) 0x43b921 MOV $0x40,%EAX |
(245) 0x43b926 VMOVUPD %ZMM13,(%R10) |
(245) 0x43b92c VMOVUPD (%RDX),%ZMM2 |
(245) 0x43b932 VMOVUPD %ZMM2,(%R11) |
(245) 0x43b938 VMOVUPD %ZMM6,(%R9,%RAX,1) |
(245) 0x43b93f VBROADCASTSD (%RBX),%ZMM1 |
(245) 0x43b945 VMOVUPD %ZMM1,(%R10,%RAX,1) |
(245) 0x43b94c VMOVUPD (%RDX,%RAX,1),%ZMM3 |
(245) 0x43b953 VMOVUPD %ZMM3,(%R11,%RAX,1) |
(245) 0x43b95a ADD $0x40,%RAX |
(245) 0x43b95e VMOVUPD %ZMM6,(%R9,%RAX,1) |
(245) 0x43b965 VBROADCASTSD (%RBX),%ZMM4 |
(245) 0x43b96b VMOVUPD %ZMM4,(%R10,%RAX,1) |
(245) 0x43b972 VMOVUPD (%RDX,%RAX,1),%ZMM7 |
(245) 0x43b979 VMOVUPD %ZMM7,(%R11,%RAX,1) |
(245) 0x43b980 ADD $0x40,%RAX |
(245) 0x43b984 VMOVUPD %ZMM6,(%R9,%RAX,1) |
(245) 0x43b98b VBROADCASTSD (%RBX),%ZMM5 |
(245) 0x43b991 VMOVUPD %ZMM5,(%R10,%RAX,1) |
(245) 0x43b998 VMOVUPD (%RDX,%RAX,1),%ZMM9 |
(245) 0x43b99f VMOVUPD %ZMM9,(%R11,%RAX,1) |
(245) 0x43b9a6 ADD $0x40,%RAX |
(245) 0x43b9aa VMOVUPD %ZMM6,(%R9,%RAX,1) |
(245) 0x43b9b1 VBROADCASTSD (%RBX),%ZMM10 |
(245) 0x43b9b7 VMOVUPD %ZMM10,(%R10,%RAX,1) |
(245) 0x43b9be VMOVUPD (%RDX,%RAX,1),%ZMM14 |
(245) 0x43b9c5 VMOVUPD %ZMM14,(%R11,%RAX,1) |
(245) 0x43b9cc ADD $0x40,%RAX |
(245) 0x43b9d0 VMOVUPD %ZMM6,(%R9,%RAX,1) |
(245) 0x43b9d7 VBROADCASTSD (%RBX),%ZMM15 |
(245) 0x43b9dd VMOVUPD %ZMM15,(%R10,%RAX,1) |
(245) 0x43b9e4 VMOVUPD (%RDX,%RAX,1),%ZMM11 |
(245) 0x43b9eb VMOVUPD %ZMM11,(%R11,%RAX,1) |
(245) 0x43b9f2 ADD $0x40,%RAX |
(245) 0x43b9f6 VMOVUPD %ZMM6,(%R9,%RAX,1) |
(245) 0x43b9fd VBROADCASTSD (%RBX),%ZMM13 |
(245) 0x43ba03 VMOVUPD %ZMM13,(%R10,%RAX,1) |
(245) 0x43ba0a VMOVUPD (%RDX,%RAX,1),%ZMM2 |
(245) 0x43ba11 VMOVUPD %ZMM2,(%R11,%RAX,1) |
(245) 0x43ba18 ADD $0x40,%RAX |
(245) 0x43ba1c CMP %RAX,0x18(%RSP) |
(245) 0x43ba21 JE 43bb64 |
(246) 0x43ba27 VMOVUPD %ZMM6,(%R9,%RAX,1) |
(246) 0x43ba2e VBROADCASTSD (%RBX),%ZMM1 |
(246) 0x43ba34 VMOVUPD %ZMM1,(%R10,%RAX,1) |
(246) 0x43ba3b VMOVUPD (%RDX,%RAX,1),%ZMM3 |
(246) 0x43ba42 VMOVUPD %ZMM3,(%R11,%RAX,1) |
(246) 0x43ba49 VMOVUPD %ZMM6,0x40(%R9,%RAX,1) |
(246) 0x43ba51 VBROADCASTSD (%RBX),%ZMM4 |
(246) 0x43ba57 VMOVUPD %ZMM4,0x40(%R10,%RAX,1) |
(246) 0x43ba5f VMOVUPD 0x40(%RDX,%RAX,1),%ZMM7 |
(246) 0x43ba67 VMOVUPD %ZMM7,0x40(%R11,%RAX,1) |
(246) 0x43ba6f VMOVUPD %ZMM6,0x80(%R9,%RAX,1) |
(246) 0x43ba77 VBROADCASTSD (%RBX),%ZMM5 |
(246) 0x43ba7d VMOVUPD %ZMM5,0x80(%R10,%RAX,1) |
(246) 0x43ba85 VMOVUPD 0x80(%RDX,%RAX,1),%ZMM9 |
(246) 0x43ba8d VMOVUPD %ZMM9,0x80(%R11,%RAX,1) |
(246) 0x43ba95 VMOVUPD %ZMM6,0xc0(%R9,%RAX,1) |
(246) 0x43ba9d VBROADCASTSD (%RBX),%ZMM10 |
(246) 0x43baa3 VMOVUPD %ZMM10,0xc0(%R10,%RAX,1) |
(246) 0x43baab VMOVUPD 0xc0(%RDX,%RAX,1),%ZMM14 |
(246) 0x43bab3 VMOVUPD %ZMM14,0xc0(%R11,%RAX,1) |
(246) 0x43babb VMOVUPD %ZMM6,0x100(%R9,%RAX,1) |
(246) 0x43bac3 VBROADCASTSD (%RBX),%ZMM15 |
(246) 0x43bac9 VMOVUPD %ZMM15,0x100(%R10,%RAX,1) |
(246) 0x43bad1 VMOVUPD 0x100(%RDX,%RAX,1),%ZMM11 |
(246) 0x43bad9 VMOVUPD %ZMM11,0x100(%R11,%RAX,1) |
(246) 0x43bae1 VMOVUPD %ZMM6,0x140(%R9,%RAX,1) |
(246) 0x43bae9 VBROADCASTSD (%RBX),%ZMM13 |
(246) 0x43baef VMOVUPD %ZMM13,0x140(%R10,%RAX,1) |
(246) 0x43baf7 VMOVUPD 0x140(%RDX,%RAX,1),%ZMM2 |
(246) 0x43baff VMOVUPD %ZMM2,0x140(%R11,%RAX,1) |
(246) 0x43bb07 VMOVUPD %ZMM6,0x180(%R9,%RAX,1) |
(246) 0x43bb0f VBROADCASTSD (%RBX),%ZMM1 |
(246) 0x43bb15 VMOVUPD %ZMM1,0x180(%R10,%RAX,1) |
(246) 0x43bb1d VMOVUPD 0x180(%RDX,%RAX,1),%ZMM3 |
(246) 0x43bb25 VMOVUPD %ZMM3,0x180(%R11,%RAX,1) |
(246) 0x43bb2d VMOVUPD %ZMM6,0x1c0(%R9,%RAX,1) |
(246) 0x43bb35 VBROADCASTSD (%RBX),%ZMM4 |
(246) 0x43bb3b VMOVUPD %ZMM4,0x1c0(%R10,%RAX,1) |
(246) 0x43bb43 VMOVUPD 0x1c0(%RDX,%RAX,1),%ZMM7 |
(246) 0x43bb4b VMOVUPD %ZMM7,0x1c0(%R11,%RAX,1) |
(246) 0x43bb53 ADD $0x200,%RAX |
(246) 0x43bb59 CMP %RAX,0x18(%RSP) |
(246) 0x43bb5e JNE 43ba27 |
(245) 0x43bb64 MOV 0x3c(%RSP),%R9D |
(245) 0x43bb69 MOV %ECX,%ESI |
(245) 0x43bb6b AND $-0x8,%ESI |
(245) 0x43bb6e ADD %ESI,%EDI |
(245) 0x43bb70 LEA (%RSI,%R9,1),%R11D |
(245) 0x43bb74 TEST $0x7,%CL |
(245) 0x43bb77 JE 43bcbb |
(245) 0x43bb7d SUB %ESI,%ECX |
(245) 0x43bb7f LEA -0x1(%RCX),%R10D |
(245) 0x43bb83 CMP $0x2,%R10D |
(245) 0x43bb87 JBE 43bbeb |
(245) 0x43bb89 MOVSXD 0x3c(%RSP),%RAX |
(245) 0x43bb8e MOV 0x20(%RSP),%RDX |
(245) 0x43bb93 MOV 0x28(%RSP),%R10 |
(245) 0x43bb98 VMOVQ %XMM0,%R9 |
(245) 0x43bb9d VMOVSD (%RBX),%XMM5 |
(245) 0x43bba1 VBROADCASTSD %XMM5,%YMM9 |
(245) 0x43bba6 ADD %RAX,%RDX |
(245) 0x43bba9 ADD %RAX,%R10 |
(245) 0x43bbac ADD %RSI,%RDX |
(245) 0x43bbaf ADD %RSI,%R10 |
(245) 0x43bbb2 VMOVUPD %YMM12,(%R9,%RDX,8) |
(245) 0x43bbb8 LEA (%RAX,%RSI,1),%RDX |
(245) 0x43bbbc MOV 0x30(%RSP),%R9 |
(245) 0x43bbc1 VMOVUPD %YMM9,(%R12,%R10,8) |
(245) 0x43bbc7 VMOVUPD (%R13,%RDX,8),%YMM10 |
(245) 0x43bbce ADD %R9,%RAX |
(245) 0x43bbd1 ADD %RSI,%RAX |
(245) 0x43bbd4 VMOVUPD %YMM10,(%R15,%RAX,8) |
(245) 0x43bbda TEST $0x3,%CL |
(245) 0x43bbdd JE 43bcbb |
(245) 0x43bbe3 AND $-0x4,%ECX |
(245) 0x43bbe6 ADD %ECX,%EDI |
(245) 0x43bbe8 ADD %ECX,%R11D |
(245) 0x43bbeb MOV 0x20(%RSP),%RSI |
(245) 0x43bbf0 MOV 0x28(%RSP),%R9 |
(245) 0x43bbf5 MOVSXD %R11D,%RAX |
(245) 0x43bbf8 VMOVQ %XMM0,%RCX |
(245) 0x43bbfd LEA (%RSI,%RAX,1),%R10 |
(245) 0x43bc01 LEA (%R9,%RAX,1),%RDX |
(245) 0x43bc05 VMOVSD %XMM8,(%RCX,%R10,8) |
(245) 0x43bc0b LEA (,%RAX,8),%R10 |
(245) 0x43bc13 VMOVSD (%RBX),%XMM14 |
(245) 0x43bc17 VMOVSD %XMM14,(%R12,%RDX,8) |
(245) 0x43bc1d VMOVQ %R10,%XMM15 |
(245) 0x43bc22 VMOVSD (%R13,%R10,1),%XMM11 |
(245) 0x43bc29 MOV 0x30(%RSP),%R10 |
(245) 0x43bc2e MOV 0x38(%RSP),%ECX |
(245) 0x43bc32 LEA 0x1(%RDI),%EDX |
(245) 0x43bc35 ADD %R10,%RAX |
(245) 0x43bc38 VMOVSD %XMM11,(%R15,%RAX,8) |
(245) 0x43bc3e LEA 0x1(%R11),%EAX |
(245) 0x43bc42 CMP %ECX,%EDX |
(245) 0x43bc44 JAE 43bcbb |
(245) 0x43bc46 CLTQ |
(245) 0x43bc48 VMOVQ %XMM0,%RCX |
(245) 0x43bc4d ADD $0x2,%EDI |
(245) 0x43bc50 ADD $0x2,%R11D |
(245) 0x43bc54 LEA (%RSI,%RAX,1),%RDX |
(245) 0x43bc58 VMOVSD %XMM8,(%RCX,%RDX,8) |
(245) 0x43bc5d LEA (%R9,%RAX,1),%RDX |
(245) 0x43bc61 VMOVSD (%RBX),%XMM13 |
(245) 0x43bc65 ADD %R10,%RAX |
(245) 0x43bc68 VMOVSD %XMM13,(%R12,%RDX,8) |
(245) 0x43bc6e MOV %R10,%RDX |
(245) 0x43bc71 MOV 0x38(%RSP),%R10D |
(245) 0x43bc76 VMOVQ %XMM15,%RCX |
(245) 0x43bc7b VMOVSD 0x8(%R13,%RCX,1),%XMM2 |
(245) 0x43bc82 VMOVSD %XMM2,(%R15,%RAX,8) |
(245) 0x43bc88 CMP %R10D,%EDI |
(245) 0x43bc8b JAE 43bcbb |
(245) 0x43bc8d MOVSXD %R11D,%RDI |
(245) 0x43bc90 VMOVQ %XMM0,%R11 |
(245) 0x43bc95 ADD %RDI,%RSI |
(245) 0x43bc98 ADD %RDI,%R9 |
(245) 0x43bc9b ADD %RDI,%RDX |
(245) 0x43bc9e VMOVSD %XMM8,(%R11,%RSI,8) |
(245) 0x43bca4 VMOVSD (%RBX),%XMM0 |
(245) 0x43bca8 VMOVSD %XMM0,(%R12,%R9,8) |
(245) 0x43bcae VMOVSD 0x10(%R13,%RCX,1),%XMM1 |
(245) 0x43bcb5 VMOVSD %XMM1,(%R15,%RDX,8) |
(245) 0x43bcbb MOV 0x38(%RSP),%EDI |
(245) 0x43bcbf INC %R8 |
(245) 0x43bcc2 CMP %R8D,0x14(%RSP) |
(245) 0x43bcc7 JLE 43bcf0 |
(245) 0x43bcc9 MOV 0xc(%RSP),%R12D |
(245) 0x43bcce MOV 0x10(%RSP),%ECX |
(245) 0x43bcd2 MOVL $0,0x3c(%RSP) |
(245) 0x43bcda SUB %EDI,%R12D |
(245) 0x43bcdd JMP 43b820 |
0x43bce2 NOPW %CS:(%RAX,%RAX,1) |
0x43bced NOPL (%RAX) |
0x43bcf0 VZEROUPPER |
0x43bcf3 LEA -0x28(%RBP),%RSP |
0x43bcf7 POP %RBX |
0x43bcf8 POP %R12 |
0x43bcfa POP %R13 |
0x43bcfc POP %R14 |
0x43bcfe POP %R15 |
0x43bd00 POP %RBP |
0x43bd01 RET |
0x43bd02 NOPW %CS:(%RAX,%RAX,1) |
0x43bd0d NOPL (%RAX) |
(245) 0x43bd10 MOV 0x3c(%RSP),%R11D |
(245) 0x43bd15 XOR %ESI,%ESI |
(245) 0x43bd17 JMP 43bb7d |
0x43bd1c INC %R12D |
0x43bd1f XOR %EDX,%EDX |
0x43bd21 JMP 43b7ce |
0x43bd26 NOPW %CS:(%RAX,%RAX,1) |
Path / |
Source file and lines | initialise_chunk.cpp:77-82 |
Module | exec |
nb instructions | 66 |
nb uops | 63 |
loop length | 242 |
used x86 registers | 12 |
used mmx registers | 0 |
used xmm registers | 2 |
used ymm registers | 1 |
used zmm registers | 1 |
nb stack references | 5 |
micro-operation queue | 10.50 cycles |
front end | 10.50 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.00 | 4.75 | 4.75 | 4.50 | 6.00 | 4.00 | 4.00 | 4.00 | 0.50 | 1.50 | 1.00 | 0.00 | 0.00 | 0.00 |
cycles | 6.00 | 4.75 | 4.75 | 4.50 | 6.00 | 4.00 | 4.00 | 4.00 | 0.50 | 1.50 | 1.00 | 0.00 | 0.00 | 0.00 |
Cycles executing div or sqrt instructions | 12.00 |
Front-end | 10.50 |
Dispatch | 6.00 |
DIV/SQRT | 12.00 |
Overall L1 | 12.00 |
all | 6% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 11% |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 0% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 5% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 11% |
all | 7% |
load | 6% |
store | 6% |
mul | 6% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 9% |
all | 12% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 12% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
all | 8% |
load | 9% |
store | 6% |
mul | 9% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 10% |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
AND $-0x40,%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB $0x40,%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV 0x1c(%RDI),%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x18(%RDI),%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV %EBX,0x14(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV %R15D,0x10(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
TEST %EBX,%EBX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JLE 43bcf3 <_Z16initialise_chunkiR16global_variables._omp_fn.4+0x583> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
TEST %R15D,%R15D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JLE 43bcf3 <_Z16initialise_chunkiR16global_variables._omp_fn.4+0x583> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
IMUL %R15D,%EBX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %RDI,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CALL 404650 <omp_get_num_threads@plt> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EAX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CALL 404540 <omp_get_thread_num@plt> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV %EAX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EBX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
DIV %R13D | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 10-17 | 6 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP %EDX,%ECX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JB 43bd1c <_Z16initialise_chunkiR16global_variables._omp_fn.4+0x5ac> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
IMUL %R12D,%ECX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%RCX,%RDX,1),%EDI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LEA (%R12,%RDI,1),%R8D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %R8D,0xc(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
CMP %R8D,%EDI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JAE 43bcf3 <_Z16initialise_chunkiR16global_variables._omp_fn.4+0x583> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV 0x10(%RSP),%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV %EDI,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
VMOVSD 0x8(%R14),%XMM11 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMULSD (%R14),%XMM11,%XMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
MOV 0x10(%R14),%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
VBROADCASTSD %XMM8,%YMM12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0.50 |
VBROADCASTSD %XMM8,%ZMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 1 |
DIV %ECX | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 10-17 | 6 |
SUB %EDX,%ECX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOVSXD %EAX,%R8 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %EDX,0x3c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
NOPW %CS:(%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
NOP | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
NOPW %CS:(%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
NOPL (%RAX) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
VZEROUPPER | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
POP %RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
RET | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
NOPW %CS:(%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
NOPL (%RAX) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
INC %R12D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
JMP 43b7ce <_Z16initialise_chunkiR16global_variables._omp_fn.4+0x5e> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
NOPW %CS:(%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
Source file and lines | initialise_chunk.cpp:77-82 |
Module | exec |
nb instructions | 66 |
nb uops | 63 |
loop length | 242 |
used x86 registers | 12 |
used mmx registers | 0 |
used xmm registers | 2 |
used ymm registers | 1 |
used zmm registers | 1 |
nb stack references | 5 |
micro-operation queue | 10.50 cycles |
front end | 10.50 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.00 | 4.75 | 4.75 | 4.50 | 6.00 | 4.00 | 4.00 | 4.00 | 0.50 | 1.50 | 1.00 | 0.00 | 0.00 | 0.00 |
cycles | 6.00 | 4.75 | 4.75 | 4.50 | 6.00 | 4.00 | 4.00 | 4.00 | 0.50 | 1.50 | 1.00 | 0.00 | 0.00 | 0.00 |
Cycles executing div or sqrt instructions | 12.00 |
Front-end | 10.50 |
Dispatch | 6.00 |
DIV/SQRT | 12.00 |
Overall L1 | 12.00 |
all | 6% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 11% |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 0% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 5% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 11% |
all | 7% |
load | 6% |
store | 6% |
mul | 6% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 9% |
all | 12% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 12% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
all | 8% |
load | 9% |
store | 6% |
mul | 9% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 10% |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
AND $-0x40,%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB $0x40,%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV 0x1c(%RDI),%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x18(%RDI),%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV %EBX,0x14(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV %R15D,0x10(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
TEST %EBX,%EBX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JLE 43bcf3 <_Z16initialise_chunkiR16global_variables._omp_fn.4+0x583> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
TEST %R15D,%R15D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JLE 43bcf3 <_Z16initialise_chunkiR16global_variables._omp_fn.4+0x583> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
IMUL %R15D,%EBX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %RDI,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CALL 404650 <omp_get_num_threads@plt> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EAX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CALL 404540 <omp_get_thread_num@plt> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV %EAX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EBX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
DIV %R13D | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 10-17 | 6 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP %EDX,%ECX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JB 43bd1c <_Z16initialise_chunkiR16global_variables._omp_fn.4+0x5ac> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
IMUL %R12D,%ECX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%RCX,%RDX,1),%EDI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LEA (%R12,%RDI,1),%R8D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %R8D,0xc(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
CMP %R8D,%EDI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JAE 43bcf3 <_Z16initialise_chunkiR16global_variables._omp_fn.4+0x583> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV 0x10(%RSP),%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV %EDI,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
VMOVSD 0x8(%R14),%XMM11 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMULSD (%R14),%XMM11,%XMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
MOV 0x10(%R14),%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
VBROADCASTSD %XMM8,%YMM12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0.50 |
VBROADCASTSD %XMM8,%ZMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 1 |
DIV %ECX | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 10-17 | 6 |
SUB %EDX,%ECX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOVSXD %EAX,%R8 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %EDX,0x3c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
NOPW %CS:(%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
NOP | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
NOPW %CS:(%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
NOPL (%RAX) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
VZEROUPPER | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
POP %RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
RET | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
NOPW %CS:(%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
NOPL (%RAX) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
INC %R12D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
JMP 43b7ce <_Z16initialise_chunkiR16global_variables._omp_fn.4+0x5e> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
NOPW %CS:(%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼_Z16initialise_chunkiR16global_variables._omp_fn.4– | 0.03 | 0.02 |
▼Loop 245 - initialise_chunk.cpp:77-82 - exec– | 0 | 0 |
○Loop 246 - initialise_chunk.cpp:80-82 - exec | 0.03 | 0.02 |