Function: _Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buf ... | Module: exec | Source: advec_mom.cpp:85-88 [...] | Coverage: 1.28% |
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Function: _Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buf ... | Module: exec | Source: advec_mom.cpp:85-88 [...] | Coverage: 1.28% |
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/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp: 85 - 88 |
-------------------------------------------------------------------------------- |
85: #pragma omp parallel for simd collapse(2) |
86: for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) { |
87: for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) { |
88: node_flux(i, j) = 0.25 * (mass_flux_x(i + 0, j - 1) + mass_flux_x(i, j) + mass_flux_x(i + 1, j - 1) + mass_flux_x(i + 1, j + 0)); |
/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69 |
-------------------------------------------------------------------------------- |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
0x42e9a0 PUSH %RBP |
0x42e9a1 MOV %RSP,%RBP |
0x42e9a4 PUSH %R15 |
0x42e9a6 PUSH %R14 |
0x42e9a8 PUSH %R13 |
0x42e9aa PUSH %R12 |
0x42e9ac PUSH %RBX |
0x42e9ad AND $-0x40,%RSP |
0x42e9b1 SUB $0x40,%RSP |
0x42e9b5 MOV 0x18(%RDI),%EAX |
0x42e9b8 MOV 0x1c(%RDI),%EDX |
0x42e9bb MOV 0x10(%RDI),%ECX |
0x42e9be MOV 0x14(%RDI),%EBX |
0x42e9c1 ADD $0x3,%EDX |
0x42e9c4 DEC %ECX |
0x42e9c6 LEA 0x1(%RAX),%R12D |
0x42e9ca MOV %EDX,0x1c(%RSP) |
0x42e9ce MOV %ECX,0x18(%RSP) |
0x42e9d2 CMP %EDX,%R12D |
0x42e9d5 JGE 42ee43 |
0x42e9db LEA 0x4(%RBX),%R14D |
0x42e9df MOV %EDX,%EBX |
0x42e9e1 SUB %R12D,%EBX |
0x42e9e4 CMP %R14D,%ECX |
0x42e9e7 JGE 42ee43 |
0x42e9ed MOV %R14D,%ESI |
0x42e9f0 MOV %RDI,%R15 |
0x42e9f3 SUB %ECX,%ESI |
0x42e9f5 MOV %ESI,0x28(%RSP) |
0x42e9f9 CALL 404650 <omp_get_num_threads@plt> |
0x42e9fe MOV %EAX,%R13D |
0x42ea01 CALL 404540 <omp_get_thread_num@plt> |
0x42ea06 XOR %EDX,%EDX |
0x42ea08 MOV %EAX,%ECX |
0x42ea0a MOV 0x28(%RSP),%EAX |
0x42ea0e IMUL %EBX,%EAX |
0x42ea11 DIV %R13D |
0x42ea14 MOV %EAX,%EDI |
0x42ea16 CMP %EDX,%ECX |
0x42ea18 JB 42ee6d |
0x42ea1e IMUL %EDI,%ECX |
0x42ea21 ADD %EDX,%ECX |
0x42ea23 LEA (%RDI,%RCX,1),%R8D |
0x42ea27 MOV %R8D,0x14(%RSP) |
0x42ea2c CMP %R8D,%ECX |
0x42ea2f JAE 42ee43 |
0x42ea35 MOV %ECX,%EAX |
0x42ea37 XOR %EDX,%EDX |
0x42ea39 MOV 0x18(%RSP),%R9D |
0x42ea3e VMOVQ (%R15),%XMM4 |
0x42ea43 DIVL 0x28(%RSP) |
0x42ea47 VMOVQ 0x8(%R15),%XMM3 |
0x42ea4d VMOVSD 0x31d6b(%RIP),%XMM10 |
0x42ea55 VBROADCASTSD %XMM10,%YMM11 |
0x42ea5a VBROADCASTSD %XMM10,%ZMM6 |
0x42ea60 ADD %EDX,%R9D |
0x42ea63 ADD %R12D,%EAX |
0x42ea66 SUB %R9D,%R14D |
0x42ea69 MOV %EAX,0x38(%RSP) |
0x42ea6d CLTQ |
0x42ea6f MOV %R9D,0x3c(%RSP) |
0x42ea74 MOV %RAX,0x20(%RSP) |
0x42ea79 MOV %R14D,%R10D |
0x42ea7c MOV %EDI,%EAX |
0x42ea7e XCHG %AX,%AX |
(187) 0x42ea80 CMP %R10D,%EAX |
(187) 0x42ea83 CMOVA %R10D,%EAX |
(187) 0x42ea87 LEA (%RCX,%RAX,1),%R10D |
(187) 0x42ea8b MOV %R10D,0x2c(%RSP) |
(187) 0x42ea90 CMP %R10D,%ECX |
(187) 0x42ea93 JAE 42ee0b |
(187) 0x42ea99 MOV 0x38(%RSP),%R14D |
(187) 0x42ea9e VMOVQ %XMM4,%R11 |
(187) 0x42eaa3 VMOVQ %XMM3,%RSI |
(187) 0x42eaa8 LEA -0x1(%RAX),%EDI |
(187) 0x42eaab MOV (%R11),%R10 |
(187) 0x42eaae MOV 0x10(%R11),%R15 |
(187) 0x42eab2 MOV 0x20(%RSP),%R11 |
(187) 0x42eab7 LEA -0x1(%R14),%EBX |
(187) 0x42eabb MOV 0x10(%RSI),%R14 |
(187) 0x42eabf MOVSXD %EBX,%R8 |
(187) 0x42eac2 IMUL %R10,%R8 |
(187) 0x42eac6 IMUL %R11,%R10 |
(187) 0x42eaca IMUL (%RSI),%R11 |
(187) 0x42eace MOV %R11,0x30(%RSP) |
(187) 0x42ead3 CMP $0x6,%EDI |
(187) 0x42ead6 JBE 42ee60 |
(187) 0x42eadc MOV %EAX,%R9D |
(187) 0x42eadf MOVSXD 0x3c(%RSP),%RSI |
(187) 0x42eae4 SHR $0x3,%R9D |
(187) 0x42eae8 SAL $0x6,%R9 |
(187) 0x42eaec LEA -0x40(%R9),%RDI |
(187) 0x42eaf0 LEA (%R8,%RSI,1),%RDX |
(187) 0x42eaf4 LEA (%R10,%RSI,1),%R13 |
(187) 0x42eaf8 ADD %R11,%RSI |
(187) 0x42eafb SHR $0x6,%RDI |
(187) 0x42eaff SAL $0x3,%RDX |
(187) 0x42eb03 SAL $0x3,%R13 |
(187) 0x42eb07 INC %RDI |
(187) 0x42eb0a LEA (%R14,%RSI,8),%R11 |
(187) 0x42eb0e XOR %ESI,%ESI |
(187) 0x42eb10 LEA (%R15,%RDX,1),%R12 |
(187) 0x42eb14 AND $0x3,%EDI |
(187) 0x42eb17 LEA (%R15,%R13,1),%RBX |
(187) 0x42eb1b LEA 0x8(%R15,%RDX,1),%RDX |
(187) 0x42eb20 LEA 0x8(%R15,%R13,1),%R13 |
(187) 0x42eb25 JE 42ebd9 |
(187) 0x42eb2b CMP $0x1,%RDI |
(187) 0x42eb2f JE 42eb9c |
(187) 0x42eb31 CMP $0x2,%RDI |
(187) 0x42eb35 JE 42eb68 |
(187) 0x42eb37 VMOVUPD (%R12),%ZMM7 |
(187) 0x42eb3e VMOVUPD (%RDX),%ZMM5 |
(187) 0x42eb44 VADDPD (%RBX),%ZMM7,%ZMM1 |
(187) 0x42eb4a MOV $0x40,%ESI |
(187) 0x42eb4f VADDPD (%R13),%ZMM5,%ZMM12 |
(187) 0x42eb56 VADDPD %ZMM12,%ZMM1,%ZMM0 |
(187) 0x42eb5c VMULPD %ZMM6,%ZMM0,%ZMM2 |
(187) 0x42eb62 VMOVUPD %ZMM2,(%R11) |
(187) 0x42eb68 VMOVUPD (%R12,%RSI,1),%ZMM8 |
(187) 0x42eb6f VMOVUPD (%RDX,%RSI,1),%ZMM13 |
(187) 0x42eb76 VADDPD (%RBX,%RSI,1),%ZMM8,%ZMM9 |
(187) 0x42eb7d VADDPD (%R13,%RSI,1),%ZMM13,%ZMM14 |
(187) 0x42eb85 VADDPD %ZMM14,%ZMM9,%ZMM15 |
(187) 0x42eb8b VMULPD %ZMM6,%ZMM15,%ZMM7 |
(187) 0x42eb91 VMOVUPD %ZMM7,(%R11,%RSI,1) |
(187) 0x42eb98 ADD $0x40,%RSI |
(187) 0x42eb9c VMOVUPD (%R12,%RSI,1),%ZMM1 |
(187) 0x42eba3 VMOVUPD (%RDX,%RSI,1),%ZMM12 |
(187) 0x42ebaa VADDPD (%RBX,%RSI,1),%ZMM1,%ZMM5 |
(187) 0x42ebb1 VADDPD (%R13,%RSI,1),%ZMM12,%ZMM0 |
(187) 0x42ebb9 VADDPD %ZMM0,%ZMM5,%ZMM2 |
(187) 0x42ebbf VMULPD %ZMM6,%ZMM2,%ZMM8 |
(187) 0x42ebc5 VMOVUPD %ZMM8,(%R11,%RSI,1) |
(187) 0x42ebcc ADD $0x40,%RSI |
(187) 0x42ebd0 CMP %RSI,%R9 |
(187) 0x42ebd3 JE 42ecb5 |
(188) 0x42ebd9 VMOVUPD (%R12,%RSI,1),%ZMM9 |
(188) 0x42ebe0 VMOVUPD (%RDX,%RSI,1),%ZMM14 |
(188) 0x42ebe7 VADDPD (%RBX,%RSI,1),%ZMM9,%ZMM13 |
(188) 0x42ebee VADDPD (%R13,%RSI,1),%ZMM14,%ZMM15 |
(188) 0x42ebf6 VADDPD %ZMM15,%ZMM13,%ZMM7 |
(188) 0x42ebfc VMULPD %ZMM6,%ZMM7,%ZMM1 |
(188) 0x42ec02 VMOVUPD %ZMM1,(%R11,%RSI,1) |
(188) 0x42ec09 VMOVUPD 0x40(%R12,%RSI,1),%ZMM5 |
(188) 0x42ec11 VMOVUPD 0x40(%RDX,%RSI,1),%ZMM12 |
(188) 0x42ec19 VADDPD 0x40(%RBX,%RSI,1),%ZMM5,%ZMM2 |
(188) 0x42ec21 VADDPD 0x40(%R13,%RSI,1),%ZMM12,%ZMM0 |
(188) 0x42ec29 VADDPD %ZMM0,%ZMM2,%ZMM8 |
(188) 0x42ec2f VMULPD %ZMM6,%ZMM8,%ZMM9 |
(188) 0x42ec35 VMOVUPD %ZMM9,0x40(%R11,%RSI,1) |
(188) 0x42ec3d VMOVUPD 0x80(%R12,%RSI,1),%ZMM13 |
(188) 0x42ec45 VMOVUPD 0x80(%RDX,%RSI,1),%ZMM15 |
(188) 0x42ec4d VADDPD 0x80(%RBX,%RSI,1),%ZMM13,%ZMM14 |
(188) 0x42ec55 VADDPD 0x80(%R13,%RSI,1),%ZMM15,%ZMM7 |
(188) 0x42ec5d VADDPD %ZMM7,%ZMM14,%ZMM1 |
(188) 0x42ec63 VMULPD %ZMM6,%ZMM1,%ZMM5 |
(188) 0x42ec69 VMOVUPD %ZMM5,0x80(%R11,%RSI,1) |
(188) 0x42ec71 VMOVUPD 0xc0(%R12,%RSI,1),%ZMM2 |
(188) 0x42ec79 VMOVUPD 0xc0(%RDX,%RSI,1),%ZMM12 |
(188) 0x42ec81 VADDPD 0xc0(%RBX,%RSI,1),%ZMM2,%ZMM0 |
(188) 0x42ec89 VADDPD 0xc0(%R13,%RSI,1),%ZMM12,%ZMM8 |
(188) 0x42ec91 VADDPD %ZMM8,%ZMM0,%ZMM9 |
(188) 0x42ec97 VMULPD %ZMM6,%ZMM9,%ZMM13 |
(188) 0x42ec9d VMOVUPD %ZMM13,0xc0(%R11,%RSI,1) |
(188) 0x42eca5 ADD $0x100,%RSI |
(188) 0x42ecac CMP %RSI,%R9 |
(188) 0x42ecaf JNE 42ebd9 |
(187) 0x42ecb5 MOV 0x3c(%RSP),%EBX |
(187) 0x42ecb9 MOV %EAX,%R12D |
(187) 0x42ecbc AND $-0x8,%R12D |
(187) 0x42ecc0 ADD %R12D,%ECX |
(187) 0x42ecc3 LEA (%R12,%RBX,1),%R9D |
(187) 0x42ecc7 TEST $0x7,%AL |
(187) 0x42ecc9 JE 42ee07 |
(187) 0x42eccf SUB %R12D,%EAX |
(187) 0x42ecd2 LEA -0x1(%RAX),%EDX |
(187) 0x42ecd5 CMP $0x2,%EDX |
(187) 0x42ecd8 JBE 42ed35 |
(187) 0x42ecda MOVSXD 0x3c(%RSP),%R13 |
(187) 0x42ecdf MOV 0x30(%RSP),%RSI |
(187) 0x42ece4 LEA (%R10,%R13,1),%RDI |
(187) 0x42ece8 LEA (%R8,%R13,1),%R11 |
(187) 0x42ecec ADD %RSI,%R13 |
(187) 0x42ecef ADD %R12,%RDI |
(187) 0x42ecf2 ADD %R12,%R11 |
(187) 0x42ecf5 ADD %R12,%R13 |
(187) 0x42ecf8 SAL $0x3,%RDI |
(187) 0x42ecfc VMOVUPD 0x8(%R15,%R11,8),%YMM14 |
(187) 0x42ed03 VMOVUPD (%R15,%RDI,1),%YMM7 |
(187) 0x42ed09 VADDPD 0x8(%R15,%RDI,1),%YMM14,%YMM15 |
(187) 0x42ed10 VADDPD (%R15,%R11,8),%YMM7,%YMM1 |
(187) 0x42ed16 VADDPD %YMM1,%YMM15,%YMM5 |
(187) 0x42ed1a VMULPD %YMM11,%YMM5,%YMM2 |
(187) 0x42ed1f VMOVUPD %YMM2,(%R14,%R13,8) |
(187) 0x42ed25 TEST $0x3,%AL |
(187) 0x42ed27 JE 42ee07 |
(187) 0x42ed2d AND $-0x4,%EAX |
(187) 0x42ed30 ADD %EAX,%ECX |
(187) 0x42ed32 ADD %EAX,%R9D |
(187) 0x42ed35 MOV 0x30(%RSP),%R13 |
(187) 0x42ed3a LEA 0x1(%R9),%EAX |
(187) 0x42ed3e MOVSXD %R9D,%R12 |
(187) 0x42ed41 CLTQ |
(187) 0x42ed43 LEA (%RAX,%R8,1),%RBX |
(187) 0x42ed47 LEA (%RAX,%R10,1),%RDX |
(187) 0x42ed4b LEA (%R15,%RBX,8),%RSI |
(187) 0x42ed4f LEA (%R10,%R12,1),%RBX |
(187) 0x42ed53 LEA (%R15,%RDX,8),%RDI |
(187) 0x42ed57 LEA 0x1(%RCX),%EDX |
(187) 0x42ed5a VMOVSD (%R15,%RBX,8),%XMM0 |
(187) 0x42ed60 VMOVSD (%RSI),%XMM8 |
(187) 0x42ed64 VADDSD (%RDI),%XMM8,%XMM9 |
(187) 0x42ed68 LEA (%R13,%R12,1),%R11 |
(187) 0x42ed6d ADD %R8,%R12 |
(187) 0x42ed70 VADDSD (%R15,%R12,8),%XMM0,%XMM12 |
(187) 0x42ed76 MOV 0x2c(%RSP),%R12D |
(187) 0x42ed7b VADDSD %XMM9,%XMM12,%XMM13 |
(187) 0x42ed80 VMULSD %XMM10,%XMM13,%XMM14 |
(187) 0x42ed85 VMOVSD %XMM14,(%R14,%R11,8) |
(187) 0x42ed8b CMP %R12D,%EDX |
(187) 0x42ed8e JAE 42ee07 |
(187) 0x42ed90 LEA 0x2(%R9),%R11D |
(187) 0x42ed94 ADD %R13,%RAX |
(187) 0x42ed97 ADD $0x2,%ECX |
(187) 0x42ed9a VMOVSD (%RDI),%XMM15 |
(187) 0x42ed9e MOVSXD %R11D,%RDX |
(187) 0x42eda1 VADDSD (%RSI),%XMM15,%XMM7 |
(187) 0x42eda5 LEA (%R8,%RDX,1),%RBX |
(187) 0x42eda9 LEA (%R10,%RDX,1),%R11 |
(187) 0x42edad LEA (%R15,%RBX,8),%RBX |
(187) 0x42edb1 LEA (%R15,%R11,8),%R11 |
(187) 0x42edb5 VMOVSD (%R11),%XMM1 |
(187) 0x42edba VADDSD (%RBX),%XMM1,%XMM5 |
(187) 0x42edbe VADDSD %XMM5,%XMM7,%XMM2 |
(187) 0x42edc2 VMULSD %XMM10,%XMM2,%XMM0 |
(187) 0x42edc7 VMOVSD %XMM0,(%R14,%RAX,8) |
(187) 0x42edcd CMP %R12D,%ECX |
(187) 0x42edd0 JAE 42ee07 |
(187) 0x42edd2 ADD $0x3,%R9D |
(187) 0x42edd6 ADD %RDX,%R13 |
(187) 0x42edd9 VMOVSD (%RBX),%XMM9 |
(187) 0x42eddd VADDSD (%R11),%XMM9,%XMM13 |
(187) 0x42ede2 MOVSXD %R9D,%RCX |
(187) 0x42ede5 ADD %RCX,%R8 |
(187) 0x42ede8 ADD %R10,%RCX |
(187) 0x42edeb VMOVSD (%R15,%R8,8),%XMM12 |
(187) 0x42edf1 VADDSD (%R15,%RCX,8),%XMM12,%XMM8 |
(187) 0x42edf7 VADDSD %XMM13,%XMM8,%XMM14 |
(187) 0x42edfc VMULSD %XMM10,%XMM14,%XMM15 |
(187) 0x42ee01 VMOVSD %XMM15,(%R14,%R13,8) |
(187) 0x42ee07 MOV 0x2c(%RSP),%ECX |
(187) 0x42ee0b INCL 0x38(%RSP) |
(187) 0x42ee0f MOV 0x38(%RSP),%R15D |
(187) 0x42ee14 INCQ 0x20(%RSP) |
(187) 0x42ee19 CMP %R15D,0x1c(%RSP) |
(187) 0x42ee1e JLE 42ee40 |
(187) 0x42ee20 MOV 0x14(%RSP),%EAX |
(187) 0x42ee24 MOV 0x18(%RSP),%R8D |
(187) 0x42ee29 MOV 0x28(%RSP),%R10D |
(187) 0x42ee2e SUB %ECX,%EAX |
(187) 0x42ee30 MOV %R8D,0x3c(%RSP) |
(187) 0x42ee35 JMP 42ea80 |
0x42ee3a NOPW (%RAX,%RAX,1) |
0x42ee40 VZEROUPPER |
0x42ee43 LEA -0x28(%RBP),%RSP |
0x42ee47 POP %RBX |
0x42ee48 POP %R12 |
0x42ee4a POP %R13 |
0x42ee4c POP %R14 |
0x42ee4e POP %R15 |
0x42ee50 POP %RBP |
0x42ee51 RET |
0x42ee52 NOPW %CS:(%RAX,%RAX,1) |
0x42ee5d NOPL (%RAX) |
(187) 0x42ee60 MOV 0x3c(%RSP),%R9D |
(187) 0x42ee65 XOR %R12D,%R12D |
(187) 0x42ee68 JMP 42eccf |
0x42ee6d INC %EDI |
0x42ee6f XOR %EDX,%EDX |
0x42ee71 JMP 42ea1e |
0x42ee76 NOPW %CS:(%RAX,%RAX,1) |
Path / |
Source file and lines | advec_mom.cpp:85-88 |
Module | exec |
nb instructions | 81 |
nb uops | 80 |
loop length | 281 |
used x86 registers | 15 |
used mmx registers | 0 |
used xmm registers | 3 |
used ymm registers | 1 |
used zmm registers | 1 |
nb stack references | 8 |
micro-operation queue | 13.33 cycles |
front end | 13.33 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.75 | 6.75 | 6.75 | 6.75 | 6.00 | 6.33 | 6.33 | 6.33 | 0.00 | 1.00 | 1.00 | 0.00 | 0.00 | 0.00 |
cycles | 6.75 | 6.75 | 6.75 | 6.75 | 6.00 | 6.33 | 6.33 | 6.33 | 0.00 | 1.00 | 1.00 | 0.00 | 0.00 | 0.00 |
Cycles executing div or sqrt instructions | 12.00 |
Front-end | 13.33 |
Dispatch | 6.75 |
DIV/SQRT | 12.00 |
Overall L1 | 13.33 |
all | 3% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 7% |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 3% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 7% |
all | 7% |
load | 8% |
store | 7% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 8% |
all | 12% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
all | 8% |
load | 9% |
store | 7% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 8% |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
AND $-0x40,%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB $0x40,%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV 0x18(%RDI),%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x1c(%RDI),%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x10(%RDI),%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x14(%RDI),%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
ADD $0x3,%EDX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
DEC %ECX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LEA 0x1(%RAX),%R12D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %EDX,0x1c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV %ECX,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
CMP %EDX,%R12D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JGE 42ee43 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x4a3> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
LEA 0x4(%RBX),%R14D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SUB %R12D,%EBX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP %R14D,%ECX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JGE 42ee43 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x4a3> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV %R14D,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RDI,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SUB %ECX,%ESI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %ESI,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
CALL 404650 <omp_get_num_threads@plt> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EAX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CALL 404540 <omp_get_thread_num@plt> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV %EAX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x28(%RSP),%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R13D | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 10-17 | 6 |
MOV %EAX,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP %EDX,%ECX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JB 42ee6d <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x4cd> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
IMUL %EDI,%ECX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %EDX,%ECX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LEA (%RDI,%RCX,1),%R8D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %R8D,0x14(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
CMP %R8D,%ECX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JAE 42ee43 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x4a3> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV %ECX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV 0x18(%RSP),%R9D | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
VMOVQ (%R15),%XMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
DIVL 0x28(%RSP) | 3 | 2 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 10-17 | 6 |
VMOVQ 0x8(%R15),%XMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVSD 0x31d6b(%RIP),%XMM10 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VBROADCASTSD %XMM10,%YMM11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0.50 |
VBROADCASTSD %XMM10,%ZMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 1 |
ADD %EDX,%R9D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD %R12D,%EAX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB %R9D,%R14D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %EAX,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
CLTQ | |||||||||||||||||
MOV %R9D,0x3c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV %RAX,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV %R14D,%R10D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EDI,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XCHG %AX,%AX | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
NOPW (%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
VZEROUPPER | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
POP %RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
RET | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
NOPW %CS:(%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
NOPL (%RAX) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
INC %EDI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
JMP 42ea1e <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x7e> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
NOPW %CS:(%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
Source file and lines | advec_mom.cpp:85-88 |
Module | exec |
nb instructions | 81 |
nb uops | 80 |
loop length | 281 |
used x86 registers | 15 |
used mmx registers | 0 |
used xmm registers | 3 |
used ymm registers | 1 |
used zmm registers | 1 |
nb stack references | 8 |
micro-operation queue | 13.33 cycles |
front end | 13.33 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.75 | 6.75 | 6.75 | 6.75 | 6.00 | 6.33 | 6.33 | 6.33 | 0.00 | 1.00 | 1.00 | 0.00 | 0.00 | 0.00 |
cycles | 6.75 | 6.75 | 6.75 | 6.75 | 6.00 | 6.33 | 6.33 | 6.33 | 0.00 | 1.00 | 1.00 | 0.00 | 0.00 | 0.00 |
Cycles executing div or sqrt instructions | 12.00 |
Front-end | 13.33 |
Dispatch | 6.75 |
DIV/SQRT | 12.00 |
Overall L1 | 13.33 |
all | 3% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 7% |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 3% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 7% |
all | 7% |
load | 8% |
store | 7% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 8% |
all | 12% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
all | 8% |
load | 9% |
store | 7% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 8% |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
AND $-0x40,%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB $0x40,%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV 0x18(%RDI),%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x1c(%RDI),%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x10(%RDI),%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x14(%RDI),%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
ADD $0x3,%EDX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
DEC %ECX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LEA 0x1(%RAX),%R12D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %EDX,0x1c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV %ECX,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
CMP %EDX,%R12D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JGE 42ee43 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x4a3> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
LEA 0x4(%RBX),%R14D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SUB %R12D,%EBX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP %R14D,%ECX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JGE 42ee43 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x4a3> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV %R14D,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RDI,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SUB %ECX,%ESI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %ESI,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
CALL 404650 <omp_get_num_threads@plt> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EAX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CALL 404540 <omp_get_thread_num@plt> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV %EAX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x28(%RSP),%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R13D | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 10-17 | 6 |
MOV %EAX,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP %EDX,%ECX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JB 42ee6d <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x4cd> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
IMUL %EDI,%ECX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %EDX,%ECX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LEA (%RDI,%RCX,1),%R8D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %R8D,0x14(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
CMP %R8D,%ECX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JAE 42ee43 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x4a3> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV %ECX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV 0x18(%RSP),%R9D | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
VMOVQ (%R15),%XMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
DIVL 0x28(%RSP) | 3 | 2 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 10-17 | 6 |
VMOVQ 0x8(%R15),%XMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVSD 0x31d6b(%RIP),%XMM10 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VBROADCASTSD %XMM10,%YMM11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0.50 |
VBROADCASTSD %XMM10,%ZMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 1 |
ADD %EDX,%R9D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD %R12D,%EAX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB %R9D,%R14D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %EAX,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
CLTQ | |||||||||||||||||
MOV %R9D,0x3c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV %RAX,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV %R14D,%R10D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EDI,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XCHG %AX,%AX | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
NOPW (%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
VZEROUPPER | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
POP %RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
RET | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
NOPW %CS:(%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
NOPL (%RAX) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
INC %EDI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
JMP 42ea1e <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x7e> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
NOPW %CS:(%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4– | 1.28 | 0.65 |
▼Loop 187 - advec_mom.cpp:87-88 - exec– | 0 | 0 |
○Loop 188 - advec_mom.cpp:88-88 - exec | 1.28 | 0.64 |