Function: .omp_outlined..2.368 | Module: exec | Source: generate_chunk.cpp:85-123 [...] | Coverage: 0.01% |
---|
Function: .omp_outlined..2.368 | Module: exec | Source: generate_chunk.cpp:85-123 [...] | Coverage: 0.01% |
---|
/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/generate_chunk.cpp: 85 - 123 |
-------------------------------------------------------------------------------- |
85: #pragma omp parallel for simd collapse(2) |
86: for (int j = (0); j < (yrange); j++) { |
87: for (int i = (0); i < (xrange); i++) { |
88: double x_cent = state_xmin[state]; |
89: double y_cent = state_ymin[state]; |
90: if (state_geometry[state] == g_rect) { |
91: if (field.vertexx[i + 1] >= state_xmin[state] && field.vertexx[i] < state_xmax[state]) { |
92: if (field.vertexy[j + 1] >= state_ymin[state] && field.vertexy[j] < state_ymax[state]) { |
93: field.energy0(i, j) = state_energy[state]; |
94: field.density0(i, j) = state_density[state]; |
95: for (int kt = j; kt <= j + 1; ++kt) { |
96: for (int jt = i; jt <= i + 1; ++jt) { |
97: field.xvel0(jt, kt) = state_xvel[state]; |
98: field.yvel0(jt, kt) = state_yvel[state]; |
[...] |
105: std::sqrt((field.cellx[i] - x_cent) * (field.cellx[i] - x_cent) + (field.celly[j] - y_cent) * (field.celly[j] - y_cent)); |
106: if (radius <= state_radius[state]) { |
107: field.energy0(i, j) = state_energy[state]; |
108: field.density0(i, j) = state_density[state]; |
109: for (int kt = j; kt <= j + 1; ++kt) { |
110: for (int jt = i; jt <= i + 1; ++jt) { |
111: field.xvel0(jt, kt) = state_xvel[state]; |
112: field.yvel0(jt, kt) = state_yvel[state]; |
113: } |
114: } |
115: } |
116: } else if (state_geometry[state] == g_point) { |
117: if (field.vertexx[i] == x_cent && field.vertexy[j] == y_cent) { |
118: field.energy0(i, j) = state_energy[state]; |
119: field.density0(i, j) = state_density[state]; |
120: for (int kt = j; kt <= j + 1; ++kt) { |
121: for (int jt = i; jt <= i + 1; ++jt) { |
122: field.xvel0(jt, kt) = state_xvel[state]; |
123: field.yvel0(jt, kt) = state_yvel[state]; |
/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 46 - 69 |
-------------------------------------------------------------------------------- |
46: T &operator[](size_t i) const { return data[i]; } |
[...] |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
0x246bd0 PUSH %RBP |
0x246bd1 MOV %RSP,%RBP |
0x246bd4 PUSH %R15 |
0x246bd6 PUSH %R14 |
0x246bd8 PUSH %R13 |
0x246bda PUSH %R12 |
0x246bdc PUSH %RBX |
0x246bdd SUB $0x48,%RSP |
0x246be1 MOV %R9,-0x58(%RBP) |
0x246be5 MOV (%RDX),%R14D |
0x246be8 TEST %R14D,%R14D |
0x246beb JLE 246c7e |
0x246bf1 MOV (%RCX),%R15D |
0x246bf4 TEST %R15D,%R15D |
0x246bf7 JLE 246c7e |
0x246bfd MOV %R8,%RBX |
0x246c00 MOVSXD %R15D,%R12 |
0x246c03 IMUL %R12,%R14 |
0x246c07 DEC %R14 |
0x246c0a MOVQ $0,-0x60(%RBP) |
0x246c12 MOV %R14,-0x40(%RBP) |
0x246c16 MOVQ $0x1,-0x70(%RBP) |
0x246c1e MOVL $0,-0x48(%RBP) |
0x246c25 MOV (%RDI),%ESI |
0x246c27 SUB $0x8,%RSP |
0x246c2b LEA -0x70(%RBP),%RAX |
0x246c2f LEA -0x48(%RBP),%RCX |
0x246c33 LEA -0x60(%RBP),%R8 |
0x246c37 LEA -0x40(%RBP),%R9 |
0x246c3b MOV $0x212498,%EDI |
0x246c40 MOV %ESI,-0x44(%RBP) |
0x246c43 MOV $0x22,%EDX |
0x246c48 PUSH $0x1 |
0x246c4a PUSH $0x1 |
0x246c4c PUSH %RAX |
0x246c4d CALL 261360 <@plt_start@+0x4f0> |
0x246c52 MOV %R12,%R10 |
0x246c55 ADD $0x20,%RSP |
0x246c59 MOV -0x40(%RBP),%RAX |
0x246c5d CMP %R14,%RAX |
0x246c60 CMOVL %RAX,%R14 |
0x246c64 MOV %R14,-0x40(%RBP) |
0x246c68 MOV -0x60(%RBP),%R12 |
0x246c6c CMP %R14,%R12 |
0x246c6f JLE 246c8d |
0x246c71 MOV $0x2124b0,%EDI |
0x246c76 MOV -0x44(%RBP),%ESI |
0x246c79 CALL 261370 <@plt_start@+0x500> |
0x246c7e ADD $0x48,%RSP |
0x246c82 POP %RBX |
0x246c83 POP %R12 |
0x246c85 POP %R13 |
0x246c87 POP %R14 |
0x246c89 POP %R15 |
0x246c8b POP %RBP |
0x246c8c RET |
0x246c8d MOV 0x20(%RBP),%R11 |
0x246c91 MOV 0x18(%RBP),%R14 |
0x246c95 MOV 0x10(%RBP),%R9 |
0x246c99 MOV -0x58(%RBP),%RAX |
0x246c9d MOV (%RAX),%ECX |
0x246c9f MOV %R15D,%EAX |
0x246ca2 NEG %EAX |
0x246ca4 MOV %EAX,-0x30(%RBP) |
0x246ca7 VXORPD %XMM3,%XMM3,%XMM3 |
0x246cab MOV %RBX,-0x50(%RBP) |
0x246caf MOV %R15D,-0x2c(%RBP) |
0x246cb3 MOV %R10,-0x38(%RBP) |
0x246cb7 JMP 246cde |
0x246cb9 NOPL (%RAX) |
(280) 0x246cc0 MOV -0x2c(%RBP),%R15D |
(280) 0x246cc4 MOV -0x38(%RBP),%R10 |
(280) 0x246cc8 MOV 0x18(%RBP),%R14 |
(280) 0x246ccc MOV 0x10(%RBP),%R9 |
(280) 0x246cd0 LEA 0x1(%R12),%RAX |
(280) 0x246cd5 CMP -0x40(%RBP),%R12 |
(280) 0x246cd9 MOV %RAX,%R12 |
(280) 0x246cdc JGE 246c71 |
(280) 0x246cde MOV %R12,%RAX |
(280) 0x246ce1 OR %R10,%RAX |
(280) 0x246ce4 SHR $0x20,%RAX |
(280) 0x246ce8 JE 246d00 |
(280) 0x246cea MOV %R12,%RAX |
(280) 0x246ced CQTO |
(280) 0x246cef IDIV %R10 |
(280) 0x246cf2 MOV %RAX,%R13 |
(280) 0x246cf5 JMP 246d0b |
0x246cf7 NOPW (%RAX,%RAX,1) |
(280) 0x246d00 MOV %R12D,%EAX |
(280) 0x246d03 XOR %EDX,%EDX |
(280) 0x246d05 DIV %R15D |
(280) 0x246d08 MOV %EAX,%R13D |
(280) 0x246d0b MOVSXD %ECX,%RAX |
(280) 0x246d0e MOV 0x8(%RBX),%RSI |
(280) 0x246d12 VMOVSD (%RSI,%RAX,8),%XMM1 |
(280) 0x246d17 MOV 0x8(%R9),%RSI |
(280) 0x246d1b VMOVSD (%RSI,%RAX,8),%XMM0 |
(280) 0x246d20 MOV 0x8(%R14),%RSI |
(280) 0x246d24 MOV (%RSI,%RAX,4),%ESI |
(280) 0x246d27 CMP $0x3,%ESI |
(280) 0x246d2a JE 246f20 |
(280) 0x246d30 CMP $0x2,%ESI |
(280) 0x246d33 JE 2470a0 |
(280) 0x246d39 CMP $0x1,%ESI |
(280) 0x246d3c JNE 246cd0 |
(280) 0x246d3e SAL $0x20,%RDX |
(280) 0x246d42 MOV $0x100000000,%RSI |
(280) 0x246d4c LEA (%RDX,%RSI,1),%RDI |
(280) 0x246d50 MOV 0x258(%R11),%RSI |
(280) 0x246d57 SAR $0x1d,%RDI |
(280) 0x246d5b VMOVSD (%RSI,%RDI,1),%XMM2 |
(280) 0x246d60 VUCOMISD %XMM1,%XMM2 |
(280) 0x246d64 JB 246cd0 |
(280) 0x246d6a MOV %RDX,%RDI |
(280) 0x246d6d SAR $0x1d,%RDI |
(280) 0x246d71 MOV 0x28(%RBP),%R8 |
(280) 0x246d75 MOV 0x8(%R8),%R8 |
(280) 0x246d79 VMOVSD (%R8,%RAX,8),%XMM1 |
(280) 0x246d7f VUCOMISD (%RSI,%RDI,1),%XMM1 |
(280) 0x246d84 JBE 246cd0 |
(280) 0x246d8a MOV %R13,%RSI |
(280) 0x246d8d SAL $0x20,%RSI |
(280) 0x246d91 MOV $0x100000000,%RDI |
(280) 0x246d9b LEA (%RSI,%RDI,1),%R8 |
(280) 0x246d9f MOV 0x278(%R11),%RDI |
(280) 0x246da6 SAR $0x1d,%R8 |
(280) 0x246daa VMOVSD (%RDI,%R8,1),%XMM1 |
(280) 0x246db0 VUCOMISD %XMM0,%XMM1 |
(280) 0x246db4 JB 246cd0 |
(280) 0x246dba MOV %RSI,%R8 |
(280) 0x246dbd SAR $0x1d,%R8 |
(280) 0x246dc1 MOV 0x30(%RBP),%R9 |
(280) 0x246dc5 MOV 0x8(%R9),%R9 |
(280) 0x246dc9 VMOVSD (%R9,%RAX,8),%XMM0 |
(280) 0x246dcf VUCOMISD (%RDI,%R8,1),%XMM0 |
(280) 0x246dd5 JBE 246ccc |
(280) 0x246ddb SAR $0x20,%RDX |
(280) 0x246ddf SAR $0x20,%RSI |
(280) 0x246de3 MOV 0x38(%RBP),%RDI |
(280) 0x246de7 MOV 0x8(%RDI),%RDI |
(280) 0x246deb VMOVSD (%RDI,%RAX,8),%XMM0 |
(280) 0x246df0 MOV 0x40(%R11),%RDI |
(280) 0x246df4 MOV 0x30(%R11),%R8 |
(280) 0x246df8 IMUL %RSI,%R8 |
(280) 0x246dfc ADD %RDX,%R8 |
(280) 0x246dff VMOVSD %XMM0,(%RDI,%R8,8) |
(280) 0x246e05 MOV 0x40(%RBP),%RDI |
(280) 0x246e09 MOV 0x8(%RDI),%RDI |
(280) 0x246e0d VMOVSD (%RDI,%RAX,8),%XMM0 |
(280) 0x246e12 MOV 0x10(%R11),%RDI |
(280) 0x246e16 MOV (%R11),%R8 |
(280) 0x246e19 IMUL %RSI,%R8 |
(280) 0x246e1d ADD %RDX,%R8 |
(280) 0x246e20 VMOVSD %XMM0,(%RDI,%R8,8) |
(280) 0x246e26 MOV 0x48(%RBP),%RDX |
(280) 0x246e2a MOV 0x8(%RDX),%RDI |
(280) 0x246e2e MOV 0xa8(%R11),%R10 |
(280) 0x246e35 MOV 0xb8(%R11),%R8 |
(280) 0x246e3c MOV 0x50(%RBP),%RDX |
(280) 0x246e40 MOV 0x8(%RDX),%R9 |
(280) 0x246e44 MOV 0xe8(%R11),%RDX |
(280) 0x246e4b MOV 0xd8(%R11),%R14 |
(280) 0x246e52 MOV %R14,-0x68(%RBP) |
(280) 0x246e56 MOV -0x30(%RBP),%R11D |
(280) 0x246e5a IMUL %R13D,%R11D |
(280) 0x246e5e ADD %R12D,%R11D |
(280) 0x246e61 MOVSXD %R11D,%R11 |
(280) 0x246e64 MOV %RSI,%R15 |
(280) 0x246e67 IMUL %R10,%R15 |
(280) 0x246e6b MOV %RSI,%R13 |
(280) 0x246e6e IMUL %R14,%R13 |
(280) 0x246e72 VMOVSD (%RDI,%RAX,8),%XMM0 |
(280) 0x246e77 LEA (%R15,%R11,1),%R14 |
(280) 0x246e7b VMOVSD %XMM0,(%R8,%R14,8) |
(280) 0x246e81 VMOVSD (%R9,%RAX,8),%XMM0 |
(280) 0x246e87 LEA (%R13,%R11,1),%R14 |
(280) 0x246e8c VMOVSD %XMM0,(%RDX,%R14,8) |
(280) 0x246e92 VMOVSD (%RDI,%RAX,8),%XMM0 |
(280) 0x246e97 LEA 0x1(%R11,%R15,1),%R14 |
(280) 0x246e9c MOV -0x2c(%RBP),%R15D |
(280) 0x246ea0 VMOVSD %XMM0,(%R8,%R14,8) |
(280) 0x246ea6 VMOVSD (%R9,%RAX,8),%XMM0 |
(280) 0x246eac LEA (%R11,%R13,1),%R14 |
(280) 0x246eb0 INC %R14 |
(280) 0x246eb3 VMOVSD %XMM0,(%RDX,%R14,8) |
(280) 0x246eb9 INC %RSI |
(280) 0x246ebc IMUL %RSI,%R10 |
(280) 0x246ec0 IMUL -0x68(%RBP),%RSI |
(280) 0x246ec5 VMOVSD (%RDI,%RAX,8),%XMM0 |
(280) 0x246eca LEA (%R10,%R11,1),%R14 |
(280) 0x246ece VMOVSD %XMM0,(%R8,%R14,8) |
(280) 0x246ed4 VMOVSD (%R9,%RAX,8),%XMM0 |
(280) 0x246eda LEA (%RSI,%R11,1),%R14 |
(280) 0x246ede VMOVSD %XMM0,(%RDX,%R14,8) |
(280) 0x246ee4 MOV 0x18(%RBP),%R14 |
(280) 0x246ee8 VMOVSD (%RDI,%RAX,8),%XMM0 |
(280) 0x246eed LEA 0x1(%R11,%R10,1),%RDI |
(280) 0x246ef2 MOV -0x38(%RBP),%R10 |
(280) 0x246ef6 VMOVSD %XMM0,(%R8,%RDI,8) |
(280) 0x246efc VMOVSD (%R9,%RAX,8),%XMM0 |
(280) 0x246f02 LEA (%R11,%RSI,1),%RAX |
(280) 0x246f06 INC %RAX |
(280) 0x246f09 MOV 0x20(%RBP),%R11 |
(280) 0x246f0d VMOVSD %XMM0,(%RDX,%RAX,8) |
(280) 0x246f12 JMP 246ccc |
0x246f17 NOPW (%RAX,%RAX,1) |
(280) 0x246f20 MOVSXD %EDX,%RSI |
(280) 0x246f23 MOV 0x258(%R11),%RDX |
(280) 0x246f2a VMOVSD (%RDX,%RSI,8),%XMM2 |
(280) 0x246f2f VUCOMISD %XMM1,%XMM2 |
(280) 0x246f33 JNE 246cd0 |
(280) 0x246f39 JP 246cd0 |
(280) 0x246f3f MOVSXD %R13D,%RDX |
(280) 0x246f42 MOV 0x278(%R11),%RDI |
(280) 0x246f49 VMOVSD (%RDI,%RDX,8),%XMM1 |
(280) 0x246f4e VUCOMISD %XMM0,%XMM1 |
(280) 0x246f52 JNE 246cd0 |
(280) 0x246f58 JP 246cd0 |
(280) 0x246f5e MOV 0x38(%RBP),%RDI |
(280) 0x246f62 MOV 0x8(%RDI),%RDI |
(280) 0x246f66 VMOVSD (%RDI,%RAX,8),%XMM0 |
(280) 0x246f6b MOV 0x40(%R11),%RDI |
(280) 0x246f6f MOV 0x30(%R11),%R8 |
(280) 0x246f73 IMUL %RDX,%R8 |
(280) 0x246f77 ADD %RSI,%R8 |
(280) 0x246f7a VMOVSD %XMM0,(%RDI,%R8,8) |
(280) 0x246f80 MOV 0x40(%RBP),%RDI |
(280) 0x246f84 MOV 0x8(%RDI),%RDI |
(280) 0x246f88 VMOVSD (%RDI,%RAX,8),%XMM0 |
(280) 0x246f8d MOV 0x10(%R11),%RDI |
(280) 0x246f91 MOV (%R11),%R8 |
(280) 0x246f94 IMUL %RDX,%R8 |
(280) 0x246f98 ADD %RSI,%R8 |
(280) 0x246f9b VMOVSD %XMM0,(%RDI,%R8,8) |
(280) 0x246fa1 MOV 0x48(%RBP),%RSI |
(280) 0x246fa5 MOV 0x8(%RSI),%RDI |
(280) 0x246fa9 MOV 0xa8(%R11),%R10 |
(280) 0x246fb0 MOV 0xb8(%R11),%R8 |
(280) 0x246fb7 MOV 0x50(%RBP),%RSI |
(280) 0x246fbb MOV 0x8(%RSI),%R9 |
(280) 0x246fbf MOV 0xe8(%R11),%RSI |
(280) 0x246fc6 MOV 0xd8(%R11),%RBX |
(280) 0x246fcd MOV -0x30(%RBP),%R11D |
(280) 0x246fd1 IMUL %R13D,%R11D |
(280) 0x246fd5 ADD %R12D,%R11D |
(280) 0x246fd8 MOVSXD %R11D,%R11 |
(280) 0x246fdb MOV %RDX,%R14 |
(280) 0x246fde IMUL %R10,%R14 |
(280) 0x246fe2 MOV %RDX,%R15 |
(280) 0x246fe5 IMUL %RBX,%R15 |
(280) 0x246fe9 VMOVSD (%RDI,%RAX,8),%XMM0 |
(280) 0x246fee LEA (%R14,%R11,1),%R13 |
(280) 0x246ff2 VMOVSD %XMM0,(%R8,%R13,8) |
(280) 0x246ff8 VMOVSD (%R9,%RAX,8),%XMM0 |
(280) 0x246ffe LEA (%R15,%R11,1),%R13 |
(280) 0x247002 VMOVSD %XMM0,(%RSI,%R13,8) |
(280) 0x247008 VMOVSD (%RDI,%RAX,8),%XMM0 |
(280) 0x24700d LEA 0x1(%R11,%R14,1),%R14 |
(280) 0x247012 VMOVSD %XMM0,(%R8,%R14,8) |
(280) 0x247018 VMOVSD (%R9,%RAX,8),%XMM0 |
(280) 0x24701e LEA 0x1(%R11,%R15,1),%R14 |
(280) 0x247023 MOV -0x2c(%RBP),%R15D |
(280) 0x247027 VMOVSD %XMM0,(%RSI,%R14,8) |
(280) 0x24702d MOV 0x18(%RBP),%R14 |
(280) 0x247031 INC %RDX |
(280) 0x247034 IMUL %RDX,%R10 |
(280) 0x247038 IMUL %RBX,%RDX |
(280) 0x24703c VMOVSD (%RDI,%RAX,8),%XMM0 |
(280) 0x247041 LEA (%R10,%R11,1),%RBX |
(280) 0x247045 VMOVSD %XMM0,(%R8,%RBX,8) |
(280) 0x24704b VMOVSD (%R9,%RAX,8),%XMM0 |
(280) 0x247051 LEA (%RDX,%R11,1),%RBX |
(280) 0x247055 VMOVSD %XMM0,(%RSI,%RBX,8) |
(280) 0x24705a MOV -0x50(%RBP),%RBX |
(280) 0x24705e VMOVSD (%RDI,%RAX,8),%XMM0 |
(280) 0x247063 LEA 0x1(%R11,%R10,1),%RDI |
(280) 0x247068 MOV -0x38(%RBP),%R10 |
(280) 0x24706c VMOVSD %XMM0,(%R8,%RDI,8) |
(280) 0x247072 VMOVSD (%R9,%RAX,8),%XMM0 |
(280) 0x247078 MOV 0x10(%RBP),%R9 |
(280) 0x24707c LEA (%R11,%RDX,1),%RAX |
(280) 0x247080 INC %RAX |
(280) 0x247083 MOV 0x20(%RBP),%R11 |
(280) 0x247087 VMOVSD %XMM0,(%RSI,%RAX,8) |
(280) 0x24708c JMP 246cd0 |
0x247091 NOPW %CS:(%RAX,%RAX,1) |
(280) 0x2470a0 MOVSXD %EDX,%R15 |
(280) 0x2470a3 MOV 0x218(%R11),%RAX |
(280) 0x2470aa MOV 0x238(%R11),%RCX |
(280) 0x2470b1 VMOVSD (%RAX,%R15,8),%XMM2 |
(280) 0x2470b7 VSUBSD %XMM1,%XMM2,%XMM1 |
(280) 0x2470bb MOVSXD %R13D,%R14 |
(280) 0x2470be VMOVSD (%RCX,%R14,8),%XMM2 |
(280) 0x2470c4 VSUBSD %XMM0,%XMM2,%XMM0 |
(280) 0x2470c8 VMULSD %XMM0,%XMM0,%XMM0 |
(280) 0x2470cc VMULSD %XMM1,%XMM1,%XMM1 |
(280) 0x2470d0 VADDSD %XMM0,%XMM1,%XMM0 |
(280) 0x2470d4 VUCOMISD %XMM3,%XMM0 |
(280) 0x2470d8 JB 2470e0 |
(280) 0x2470da VSQRTSD %XMM0,%XMM0,%XMM0 |
(280) 0x2470de JMP 2470ed |
(280) 0x2470e0 CALL 2613a0 <@plt_start@+0x530> |
(280) 0x2470e5 VXORPD %XMM3,%XMM3,%XMM3 |
(280) 0x2470e9 MOV 0x20(%RBP),%R11 |
(280) 0x2470ed MOV -0x58(%RBP),%RAX |
(280) 0x2470f1 MOV (%RAX),%ECX |
(280) 0x2470f3 MOVSXD %ECX,%RAX |
(280) 0x2470f6 MOV 0x58(%RBP),%RDX |
(280) 0x2470fa MOV 0x8(%RDX),%RDX |
(280) 0x2470fe VMOVSD (%RDX,%RAX,8),%XMM1 |
(280) 0x247103 VUCOMISD %XMM0,%XMM1 |
(280) 0x247107 JB 246cc0 |
(280) 0x24710d MOV 0x38(%RBP),%RDX |
(280) 0x247111 MOV 0x8(%RDX),%RDX |
(280) 0x247115 VMOVSD (%RDX,%RAX,8),%XMM0 |
(280) 0x24711a MOV 0x40(%R11),%RDX |
(280) 0x24711e MOV 0x30(%R11),%RSI |
(280) 0x247122 IMUL %R14,%RSI |
(280) 0x247126 ADD %R15,%RSI |
(280) 0x247129 VMOVSD %XMM0,(%RDX,%RSI,8) |
(280) 0x24712e MOV 0x40(%RBP),%RDX |
(280) 0x247132 MOV 0x8(%RDX),%RDX |
(280) 0x247136 VMOVSD (%RDX,%RAX,8),%XMM0 |
(280) 0x24713b MOV 0x10(%R11),%RDX |
(280) 0x24713f MOV (%R11),%RSI |
(280) 0x247142 IMUL %R14,%RSI |
(280) 0x247146 ADD %R15,%RSI |
(280) 0x247149 VMOVSD %XMM0,(%RDX,%RSI,8) |
(280) 0x24714e MOV 0x48(%RBP),%RDX |
(280) 0x247152 MOV 0x8(%RDX),%RSI |
(280) 0x247156 MOV 0xa8(%R11),%R9 |
(280) 0x24715d MOV 0xb8(%R11),%RDI |
(280) 0x247164 MOV 0x50(%RBP),%RDX |
(280) 0x247168 MOV 0x8(%RDX),%R8 |
(280) 0x24716c MOV 0xe8(%R11),%RDX |
(280) 0x247173 MOV 0x20(%RBP),%R10 |
(280) 0x247177 MOV 0xd8(%R10),%R11 |
(280) 0x24717e MOV -0x30(%RBP),%R10D |
(280) 0x247182 IMUL %R13D,%R10D |
(280) 0x247186 ADD %R12D,%R10D |
(280) 0x247189 MOVSXD %R10D,%R10 |
(280) 0x24718c MOV %R14,%R15 |
(280) 0x24718f IMUL %R9,%R15 |
(280) 0x247193 MOV %R14,%R13 |
(280) 0x247196 IMUL %R11,%R13 |
(280) 0x24719a VMOVSD (%RSI,%RAX,8),%XMM0 |
(280) 0x24719f LEA (%R15,%R10,1),%RBX |
(280) 0x2471a3 VMOVSD %XMM0,(%RDI,%RBX,8) |
(280) 0x2471a8 VMOVSD (%R8,%RAX,8),%XMM0 |
(280) 0x2471ae LEA (%R13,%R10,1),%RBX |
(280) 0x2471b3 VMOVSD %XMM0,(%RDX,%RBX,8) |
(280) 0x2471b8 VMOVSD (%RSI,%RAX,8),%XMM0 |
(280) 0x2471bd LEA 0x1(%R10,%R15,1),%RBX |
(280) 0x2471c2 VMOVSD %XMM0,(%RDI,%RBX,8) |
(280) 0x2471c7 VMOVSD (%R8,%RAX,8),%XMM0 |
(280) 0x2471cd LEA (%R10,%R13,1),%RBX |
(280) 0x2471d1 INC %RBX |
(280) 0x2471d4 VMOVSD %XMM0,(%RDX,%RBX,8) |
(280) 0x2471d9 MOV -0x50(%RBP),%RBX |
(280) 0x2471dd INC %R14 |
(280) 0x2471e0 IMUL %R14,%R9 |
(280) 0x2471e4 IMUL %R11,%R14 |
(280) 0x2471e8 VMOVSD (%RSI,%RAX,8),%XMM0 |
(280) 0x2471ed LEA (%R9,%R10,1),%R11 |
(280) 0x2471f1 VMOVSD %XMM0,(%RDI,%R11,8) |
(280) 0x2471f7 VMOVSD (%R8,%RAX,8),%XMM0 |
(280) 0x2471fd LEA (%R14,%R10,1),%R11 |
(280) 0x247201 VMOVSD %XMM0,(%RDX,%R11,8) |
(280) 0x247207 MOV 0x20(%RBP),%R11 |
(280) 0x24720b VMOVSD (%RSI,%RAX,8),%XMM0 |
(280) 0x247210 LEA 0x1(%R10,%R9,1),%RSI |
(280) 0x247215 VMOVSD %XMM0,(%RDI,%RSI,8) |
(280) 0x24721a VMOVSD (%R8,%RAX,8),%XMM0 |
(280) 0x247220 LEA (%R10,%R14,1),%RAX |
(280) 0x247224 INC %RAX |
(280) 0x247227 VMOVSD %XMM0,(%RDX,%RAX,8) |
(280) 0x24722c JMP 246cc0 |
0x247231 INT $0x3 |
0x247232 INT $0x3 |
0x247233 INT $0x3 |
0x247234 INT $0x3 |
0x247235 INT $0x3 |
0x247236 INT $0x3 |
0x247237 INT $0x3 |
0x247238 INT $0x3 |
0x247239 INT $0x3 |
0x24723a INT $0x3 |
0x24723b INT $0x3 |
0x24723c INT $0x3 |
0x24723d INT $0x3 |
0x24723e INT $0x3 |
0x24723f INT $0x3 |
Path / |
Source file and lines | generate_chunk.cpp:85-123 |
Module | exec |
nb instructions | 88 |
nb uops | 71 |
loop length | 288 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 1 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 13 |
micro-operation queue | 11.83 cycles |
front end | 11.83 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.00 | 6.00 | 5.75 | 5.75 | 3.50 | 8.00 | 8.00 | 8.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 |
cycles | 6.00 | 6.00 | 5.75 | 5.75 | 3.50 | 8.00 | 8.00 | 8.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 |
Cycles executing div or sqrt instructions | NA |
Front-end | 11.83 |
Dispatch | 8.00 |
Overall L1 | 11.83 |
all | 0% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 100% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 3% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 11% |
all | 9% |
load | 9% |
store | 9% |
mul | 12% |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 10% |
all | 25% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 10% |
load | 9% |
store | 9% |
mul | 12% |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
SUB $0x48,%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %R9,-0x58(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV (%RDX),%R14D | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
TEST %R14D,%R14D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JLE 246c7e <.omp_outlined..2.368+0xae> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV (%RCX),%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
TEST %R15D,%R15D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JLE 246c7e <.omp_outlined..2.368+0xae> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV %R8,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOVSXD %R15D,%R12 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
IMUL %R12,%R14 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DEC %R14 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOVQ $0,-0x60(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV %R14,-0x40(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOVQ $0x1,-0x70(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOVL $0,-0x48(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV (%RDI),%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
SUB $0x8,%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LEA -0x70(%RBP),%RAX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LEA -0x48(%RBP),%RCX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LEA -0x60(%RBP),%R8 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LEA -0x40(%RBP),%R9 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV $0x212498,%EDI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %ESI,-0x44(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV $0x22,%EDX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
CALL 261360 <@plt_start@+0x4f0> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R12,%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD $0x20,%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV -0x40(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
CMP %R14,%RAX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMOVL %RAX,%R14 | 1 | 0.50 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %R14,-0x40(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV -0x60(%RBP),%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
CMP %R14,%R12 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JLE 246c8d <.omp_outlined..2.368+0xbd> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV $0x2124b0,%EDI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV -0x44(%RBP),%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
CALL 261370 <@plt_start@+0x500> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
ADD $0x48,%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
POP %RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
RET | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV 0x20(%RBP),%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x18(%RBP),%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x10(%RBP),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV -0x58(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV (%RAX),%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV %R15D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NEG %EAX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %EAX,-0x30(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VXORPD %XMM3,%XMM3,%XMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RBX,-0x50(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV %R15D,-0x2c(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV %R10,-0x38(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
JMP 246cde <.omp_outlined..2.368+0x10e> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
NOPL (%RAX) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
NOPW (%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
NOPW (%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
NOPW %CS:(%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
INT $0x3 | |||||||||||||||||
INT $0x3 | |||||||||||||||||
INT $0x3 | |||||||||||||||||
INT $0x3 | |||||||||||||||||
INT $0x3 | |||||||||||||||||
INT $0x3 | |||||||||||||||||
INT $0x3 | |||||||||||||||||
INT $0x3 | |||||||||||||||||
INT $0x3 | |||||||||||||||||
INT $0x3 | |||||||||||||||||
INT $0x3 | |||||||||||||||||
INT $0x3 | |||||||||||||||||
INT $0x3 | |||||||||||||||||
INT $0x3 | |||||||||||||||||
INT $0x3 |
Source file and lines | generate_chunk.cpp:85-123 |
Module | exec |
nb instructions | 88 |
nb uops | 71 |
loop length | 288 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 1 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 13 |
micro-operation queue | 11.83 cycles |
front end | 11.83 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.00 | 6.00 | 5.75 | 5.75 | 3.50 | 8.00 | 8.00 | 8.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 |
cycles | 6.00 | 6.00 | 5.75 | 5.75 | 3.50 | 8.00 | 8.00 | 8.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 |
Cycles executing div or sqrt instructions | NA |
Front-end | 11.83 |
Dispatch | 8.00 |
Overall L1 | 11.83 |
all | 0% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 100% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 3% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 11% |
all | 9% |
load | 9% |
store | 9% |
mul | 12% |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 10% |
all | 25% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 10% |
load | 9% |
store | 9% |
mul | 12% |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
SUB $0x48,%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %R9,-0x58(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV (%RDX),%R14D | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
TEST %R14D,%R14D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JLE 246c7e <.omp_outlined..2.368+0xae> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV (%RCX),%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
TEST %R15D,%R15D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JLE 246c7e <.omp_outlined..2.368+0xae> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV %R8,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOVSXD %R15D,%R12 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
IMUL %R12,%R14 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DEC %R14 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOVQ $0,-0x60(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV %R14,-0x40(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOVQ $0x1,-0x70(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOVL $0,-0x48(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV (%RDI),%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
SUB $0x8,%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LEA -0x70(%RBP),%RAX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LEA -0x48(%RBP),%RCX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LEA -0x60(%RBP),%R8 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LEA -0x40(%RBP),%R9 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV $0x212498,%EDI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %ESI,-0x44(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV $0x22,%EDX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
CALL 261360 <@plt_start@+0x4f0> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R12,%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD $0x20,%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV -0x40(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
CMP %R14,%RAX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMOVL %RAX,%R14 | 1 | 0.50 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %R14,-0x40(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV -0x60(%RBP),%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
CMP %R14,%R12 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JLE 246c8d <.omp_outlined..2.368+0xbd> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV $0x2124b0,%EDI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV -0x44(%RBP),%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
CALL 261370 <@plt_start@+0x500> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
ADD $0x48,%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
POP %RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
RET | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV 0x20(%RBP),%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x18(%RBP),%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x10(%RBP),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV -0x58(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV (%RAX),%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV %R15D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NEG %EAX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %EAX,-0x30(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VXORPD %XMM3,%XMM3,%XMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RBX,-0x50(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV %R15D,-0x2c(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV %R10,-0x38(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
JMP 246cde <.omp_outlined..2.368+0x10e> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
NOPL (%RAX) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
NOPW (%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
NOPW (%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
NOPW %CS:(%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
INT $0x3 | |||||||||||||||||
INT $0x3 | |||||||||||||||||
INT $0x3 | |||||||||||||||||
INT $0x3 | |||||||||||||||||
INT $0x3 | |||||||||||||||||
INT $0x3 | |||||||||||||||||
INT $0x3 | |||||||||||||||||
INT $0x3 | |||||||||||||||||
INT $0x3 | |||||||||||||||||
INT $0x3 | |||||||||||||||||
INT $0x3 | |||||||||||||||||
INT $0x3 | |||||||||||||||||
INT $0x3 | |||||||||||||||||
INT $0x3 | |||||||||||||||||
INT $0x3 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼.omp_outlined..2.368– | 0.01 | 0.01 |
○Loop 280 - generate_chunk.cpp:86-123 - exec | 0.01 | 0.01 |