Function: _Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_ ... | Module: exec | Source: advec_cell.cpp:146-150 [...] | Coverage: 1.29% |
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Function: _Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_ ... | Module: exec | Source: advec_cell.cpp:146-150 [...] | Coverage: 1.29% |
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/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp: 146 - 150 |
-------------------------------------------------------------------------------- |
146: #pragma omp parallel for simd collapse(2) |
147: for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) { |
148: for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) { |
149: pre_vol(i, j) = volume(i, j) + vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j); |
150: post_vol(i, j) = volume(i, j); |
/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69 |
-------------------------------------------------------------------------------- |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
0x4287d0 PUSH %RBP |
0x4287d1 MOV %RSP,%RBP |
0x4287d4 PUSH %R15 |
0x4287d6 PUSH %R14 |
0x4287d8 PUSH %R13 |
0x4287da PUSH %R12 |
0x4287dc PUSH %RBX |
0x4287dd MOV %RDI,%R15 |
0x4287e0 AND $-0x40,%RSP |
0x4287e4 SUB $0x40,%RSP |
0x4287e8 MOV 0x28(%RDI),%EAX |
0x4287eb MOV 0x2c(%RDI),%EDX |
0x4287ee MOV 0x20(%RDI),%EDI |
0x4287f1 MOV 0x24(%R15),%ECX |
0x4287f5 ADD $0x4,%EDX |
0x4287f8 DEC %EDI |
0x4287fa LEA -0x1(%RAX),%R13D |
0x4287fe MOV %EDX,0x10(%RSP) |
0x428802 MOV %EDI,0xc(%RSP) |
0x428806 CMP %EDX,%R13D |
0x428809 JGE 428cb3 |
0x42880f MOV %EDX,%EBX |
0x428811 LEA 0x4(%RCX),%R14D |
0x428815 SUB %R13D,%EBX |
0x428818 CMP %R14D,%EDI |
0x42881b JGE 428cb3 |
0x428821 MOV %R14D,%ESI |
0x428824 SUB %EDI,%ESI |
0x428826 MOV %ESI,0x14(%RSP) |
0x42882a CALL 404650 <omp_get_num_threads@plt> |
0x42882f MOV %EAX,%R12D |
0x428832 CALL 404540 <omp_get_thread_num@plt> |
0x428837 XOR %EDX,%EDX |
0x428839 MOV %EAX,%EDI |
0x42883b MOV 0x14(%RSP),%EAX |
0x42883f IMUL %EBX,%EAX |
0x428842 DIV %R12D |
0x428845 MOV %EAX,%ECX |
0x428847 CMP %EDX,%EDI |
0x428849 JB 428ced |
0x42884f IMUL %ECX,%EDI |
0x428852 ADD %EDX,%EDI |
0x428854 LEA (%RCX,%RDI,1),%R8D |
0x428858 MOV %R8D,0x8(%RSP) |
0x42885d CMP %R8D,%EDI |
0x428860 JAE 428cb3 |
0x428866 MOV %EDI,%EAX |
0x428868 XOR %EDX,%EDX |
0x42886a MOV 0xc(%RSP),%R9D |
0x42886f VMOVQ (%R15),%XMM3 |
0x428874 DIVL 0x14(%RSP) |
0x428878 VMOVQ 0x8(%R15),%XMM4 |
0x42887e VMOVQ 0x10(%R15),%XMM11 |
0x428884 VMOVQ 0x18(%R15),%XMM1 |
0x42888a ADD %EDX,%R9D |
0x42888d LEA (%RAX,%R13,1),%R10D |
0x428891 SUB %R9D,%R14D |
0x428894 MOVSXD %R10D,%R8 |
0x428897 MOV %R9D,0x3c(%RSP) |
0x42889c NOPL (%RAX) |
(167) 0x4288a0 CMP %R14D,%ECX |
(167) 0x4288a3 CMOVA %R14D,%ECX |
(167) 0x4288a7 LEA (%RDI,%RCX,1),%R11D |
(167) 0x4288ab MOV %R11D,0x38(%RSP) |
(167) 0x4288b0 CMP %R11D,%EDI |
(167) 0x4288b3 JAE 428cd0 |
(167) 0x4288b9 VMOVQ %XMM4,%RBX |
(167) 0x4288be VMOVQ %XMM3,%R15 |
(167) 0x4288c3 LEA 0x1(%R8),%R9 |
(167) 0x4288c7 LEA -0x1(%RCX),%R10D |
(167) 0x4288cb MOV (%RBX),%RSI |
(167) 0x4288ce VMOVQ %XMM11,%RAX |
(167) 0x4288d3 MOV (%R15),%R13 |
(167) 0x4288d6 MOV %R9,0x18(%RSP) |
(167) 0x4288db MOV (%RAX),%R14 |
(167) 0x4288de VMOVQ %XMM1,%RDX |
(167) 0x4288e3 VMOVQ 0x10(%R15),%XMM6 |
(167) 0x4288e9 VMOVQ 0x10(%RAX),%XMM5 |
(167) 0x4288ee MOV 0x10(%RBX),%R12 |
(167) 0x4288f2 MOV 0x10(%RDX),%R15 |
(167) 0x4288f6 IMUL %RSI,%R9 |
(167) 0x4288fa IMUL %R8,%R13 |
(167) 0x4288fe IMUL %R8,%R14 |
(167) 0x428902 IMUL (%RDX),%R8 |
(167) 0x428906 MOV %R9,%R11 |
(167) 0x428909 SUB %RSI,%R11 |
(167) 0x42890c MOV %R13,0x20(%RSP) |
(167) 0x428911 MOV %R11,0x28(%RSP) |
(167) 0x428916 MOV %R14,0x30(%RSP) |
(167) 0x42891b CMP $0x6,%R10D |
(167) 0x42891f JBE 428ce0 |
(167) 0x428925 MOVSXD 0x3c(%RSP),%RAX |
(167) 0x42892a VMOVQ %XMM6,%RSI |
(167) 0x42892f LEA (%R13,%RAX,1),%RBX |
(167) 0x428934 LEA (%R14,%RAX,1),%R14 |
(167) 0x428938 LEA (%R9,%RAX,1),%RDX |
(167) 0x42893c LEA (%R11,%RAX,1),%R11 |
(167) 0x428940 LEA (%RSI,%RBX,8),%R10 |
(167) 0x428944 VMOVQ %XMM5,%RBX |
(167) 0x428949 ADD %R8,%RAX |
(167) 0x42894c LEA (%R12,%RDX,8),%R13 |
(167) 0x428950 LEA (%RBX,%R14,8),%RBX |
(167) 0x428954 MOV %ECX,%R14D |
(167) 0x428957 LEA (%R15,%RAX,8),%RDX |
(167) 0x42895b XOR %EAX,%EAX |
(167) 0x42895d SHR $0x3,%R14D |
(167) 0x428961 SAL $0x6,%R14 |
(167) 0x428965 LEA -0x40(%R14),%RSI |
(167) 0x428969 LEA (%R12,%R11,8),%R11 |
(167) 0x42896d SHR $0x6,%RSI |
(167) 0x428971 INC %RSI |
(167) 0x428974 AND $0x3,%ESI |
(167) 0x428977 JE 428a1a |
(167) 0x42897d CMP $0x1,%RSI |
(167) 0x428981 JE 4289e2 |
(167) 0x428983 CMP $0x2,%RSI |
(167) 0x428987 JE 4289b3 |
(167) 0x428989 VMOVUPD (%R10),%ZMM7 |
(167) 0x42898f VADDPD (%R13),%ZMM7,%ZMM9 |
(167) 0x428996 MOV $0x40,%EAX |
(167) 0x42899b VSUBPD (%R11),%ZMM9,%ZMM0 |
(167) 0x4289a1 VMOVUPD %ZMM0,(%RBX) |
(167) 0x4289a7 VMOVUPD (%R10),%ZMM2 |
(167) 0x4289ad VMOVUPD %ZMM2,(%RDX) |
(167) 0x4289b3 VMOVUPD (%R10,%RAX,1),%ZMM8 |
(167) 0x4289ba VADDPD (%R13,%RAX,1),%ZMM8,%ZMM10 |
(167) 0x4289c2 VSUBPD (%R11,%RAX,1),%ZMM10,%ZMM12 |
(167) 0x4289c9 VMOVUPD %ZMM12,(%RBX,%RAX,1) |
(167) 0x4289d0 VMOVUPD (%R10,%RAX,1),%ZMM13 |
(167) 0x4289d7 VMOVUPD %ZMM13,(%RDX,%RAX,1) |
(167) 0x4289de ADD $0x40,%RAX |
(167) 0x4289e2 VMOVUPD (%R10,%RAX,1),%ZMM14 |
(167) 0x4289e9 VADDPD (%R13,%RAX,1),%ZMM14,%ZMM15 |
(167) 0x4289f1 VSUBPD (%R11,%RAX,1),%ZMM15,%ZMM7 |
(167) 0x4289f8 VMOVUPD %ZMM7,(%RBX,%RAX,1) |
(167) 0x4289ff VMOVUPD (%R10,%RAX,1),%ZMM9 |
(167) 0x428a06 VMOVUPD %ZMM9,(%RDX,%RAX,1) |
(167) 0x428a0d ADD $0x40,%RAX |
(167) 0x428a11 CMP %RAX,%R14 |
(167) 0x428a14 JE 428ae4 |
(168) 0x428a1a VMOVUPD (%R10,%RAX,1),%ZMM0 |
(168) 0x428a21 VADDPD (%R13,%RAX,1),%ZMM0,%ZMM2 |
(168) 0x428a29 VSUBPD (%R11,%RAX,1),%ZMM2,%ZMM8 |
(168) 0x428a30 VMOVUPD %ZMM8,(%RBX,%RAX,1) |
(168) 0x428a37 VMOVUPD (%R10,%RAX,1),%ZMM10 |
(168) 0x428a3e VMOVUPD %ZMM10,(%RDX,%RAX,1) |
(168) 0x428a45 VMOVUPD 0x40(%R10,%RAX,1),%ZMM12 |
(168) 0x428a4d VADDPD 0x40(%R13,%RAX,1),%ZMM12,%ZMM13 |
(168) 0x428a55 VSUBPD 0x40(%R11,%RAX,1),%ZMM13,%ZMM14 |
(168) 0x428a5d VMOVUPD %ZMM14,0x40(%RBX,%RAX,1) |
(168) 0x428a65 VMOVUPD 0x40(%R10,%RAX,1),%ZMM15 |
(168) 0x428a6d VMOVUPD %ZMM15,0x40(%RDX,%RAX,1) |
(168) 0x428a75 VMOVUPD 0x80(%R10,%RAX,1),%ZMM7 |
(168) 0x428a7d VADDPD 0x80(%R13,%RAX,1),%ZMM7,%ZMM9 |
(168) 0x428a85 VSUBPD 0x80(%R11,%RAX,1),%ZMM9,%ZMM0 |
(168) 0x428a8d VMOVUPD %ZMM0,0x80(%RBX,%RAX,1) |
(168) 0x428a95 VMOVUPD 0x80(%R10,%RAX,1),%ZMM2 |
(168) 0x428a9d VMOVUPD %ZMM2,0x80(%RDX,%RAX,1) |
(168) 0x428aa5 VMOVUPD 0xc0(%R10,%RAX,1),%ZMM8 |
(168) 0x428aad VADDPD 0xc0(%R13,%RAX,1),%ZMM8,%ZMM10 |
(168) 0x428ab5 VSUBPD 0xc0(%R11,%RAX,1),%ZMM10,%ZMM12 |
(168) 0x428abd VMOVUPD %ZMM12,0xc0(%RBX,%RAX,1) |
(168) 0x428ac5 VMOVUPD 0xc0(%R10,%RAX,1),%ZMM13 |
(168) 0x428acd VMOVUPD %ZMM13,0xc0(%RDX,%RAX,1) |
(168) 0x428ad5 ADD $0x100,%RAX |
(168) 0x428adb CMP %RAX,%R14 |
(168) 0x428ade JNE 428a1a |
(167) 0x428ae4 MOV 0x3c(%RSP),%R10D |
(167) 0x428ae9 MOV %ECX,%R13D |
(167) 0x428aec AND $-0x8,%R13D |
(167) 0x428af0 ADD %R13D,%EDI |
(167) 0x428af3 LEA (%R13,%R10,1),%R14D |
(167) 0x428af8 TEST $0x7,%CL |
(167) 0x428afb JE 428c77 |
(167) 0x428b01 SUB %R13D,%ECX |
(167) 0x428b04 LEA -0x1(%RCX),%R11D |
(167) 0x428b08 CMP $0x2,%R11D |
(167) 0x428b0c JBE 428b85 |
(167) 0x428b0e MOVSXD 0x3c(%RSP),%RSI |
(167) 0x428b13 MOV 0x20(%RSP),%RBX |
(167) 0x428b18 VMOVQ %XMM6,%RAX |
(167) 0x428b1d LEA (%RBX,%RSI,1),%RDX |
(167) 0x428b21 MOV 0x28(%RSP),%RBX |
(167) 0x428b26 LEA (%R9,%RSI,1),%R11 |
(167) 0x428b2a ADD %R13,%RDX |
(167) 0x428b2d ADD %R13,%R11 |
(167) 0x428b30 LEA (%RAX,%RDX,8),%R10 |
(167) 0x428b34 VMOVUPD (%R12,%R11,8),%YMM14 |
(167) 0x428b3a MOV 0x30(%RSP),%RAX |
(167) 0x428b3f VADDPD (%R10),%YMM14,%YMM15 |
(167) 0x428b44 LEA (%RBX,%RSI,1),%RDX |
(167) 0x428b48 VMOVQ %XMM5,%RBX |
(167) 0x428b4d ADD %R13,%RDX |
(167) 0x428b50 VSUBPD (%R12,%RDX,8),%YMM15,%YMM7 |
(167) 0x428b56 LEA (%RAX,%RSI,1),%R11 |
(167) 0x428b5a ADD %R8,%RSI |
(167) 0x428b5d ADD %R13,%R11 |
(167) 0x428b60 ADD %R13,%RSI |
(167) 0x428b63 VMOVUPD %YMM7,(%RBX,%R11,8) |
(167) 0x428b69 VMOVUPD (%R10),%YMM9 |
(167) 0x428b6e VMOVUPD %YMM9,(%R15,%RSI,8) |
(167) 0x428b74 TEST $0x3,%CL |
(167) 0x428b77 JE 428c77 |
(167) 0x428b7d AND $-0x4,%ECX |
(167) 0x428b80 ADD %ECX,%EDI |
(167) 0x428b82 ADD %ECX,%R14D |
(167) 0x428b85 MOV 0x20(%RSP),%RBX |
(167) 0x428b8a MOVSXD %R14D,%R10 |
(167) 0x428b8d VMOVQ %XMM6,%RCX |
(167) 0x428b92 MOV 0x30(%RSP),%R11 |
(167) 0x428b97 LEA (%R9,%R10,1),%RSI |
(167) 0x428b9b VMOVSD (%R12,%RSI,8),%XMM0 |
(167) 0x428ba1 VMOVQ %XMM5,%RSI |
(167) 0x428ba6 LEA (%RBX,%R10,1),%R13 |
(167) 0x428baa LEA (%R11,%R10,1),%RAX |
(167) 0x428bae LEA (%RCX,%R13,8),%RDX |
(167) 0x428bb2 MOV 0x28(%RSP),%R13 |
(167) 0x428bb7 VADDSD (%RDX),%XMM0,%XMM2 |
(167) 0x428bbb LEA (%R13,%R10,1),%RCX |
(167) 0x428bc0 ADD %R8,%R10 |
(167) 0x428bc3 VSUBSD (%R12,%RCX,8),%XMM2,%XMM8 |
(167) 0x428bc9 VMOVSD %XMM8,(%RSI,%RAX,8) |
(167) 0x428bce VMOVSD (%RDX),%XMM10 |
(167) 0x428bd2 VMOVSD %XMM10,(%R15,%R10,8) |
(167) 0x428bd8 MOV 0x38(%RSP),%R10D |
(167) 0x428bdd LEA 0x1(%RDI),%EDX |
(167) 0x428be0 LEA 0x1(%R14),%EAX |
(167) 0x428be4 CMP %R10D,%EDX |
(167) 0x428be7 JAE 428c77 |
(167) 0x428bed CLTQ |
(167) 0x428bef VMOVQ %XMM6,%RCX |
(167) 0x428bf4 ADD $0x2,%EDI |
(167) 0x428bf7 ADD $0x2,%R14D |
(167) 0x428bfb LEA (%RBX,%RAX,1),%RSI |
(167) 0x428bff LEA (%RCX,%RSI,8),%RDX |
(167) 0x428c03 LEA (%R9,%RAX,1),%RSI |
(167) 0x428c07 LEA (%R11,%RAX,1),%RCX |
(167) 0x428c0b VMOVSD (%R12,%RSI,8),%XMM12 |
(167) 0x428c11 LEA (%R13,%RAX,1),%RSI |
(167) 0x428c16 VADDSD (%RDX),%XMM12,%XMM13 |
(167) 0x428c1a ADD %R8,%RAX |
(167) 0x428c1d VSUBSD (%R12,%RSI,8),%XMM13,%XMM14 |
(167) 0x428c23 VMOVQ %XMM5,%RSI |
(167) 0x428c28 VMOVSD %XMM14,(%RSI,%RCX,8) |
(167) 0x428c2d VMOVSD (%RDX),%XMM15 |
(167) 0x428c31 VMOVSD %XMM15,(%R15,%RAX,8) |
(167) 0x428c37 CMP %R10D,%EDI |
(167) 0x428c3a JAE 428c77 |
(167) 0x428c3c MOVSXD %R14D,%R14 |
(167) 0x428c3f VMOVQ %XMM6,%RDI |
(167) 0x428c44 ADD %R14,%RBX |
(167) 0x428c47 ADD %R14,%R11 |
(167) 0x428c4a ADD %R14,%R9 |
(167) 0x428c4d ADD %R14,%R13 |
(167) 0x428c50 LEA (%RDI,%RBX,8),%RBX |
(167) 0x428c54 ADD %R8,%R14 |
(167) 0x428c57 VMOVSD (%R12,%R9,8),%XMM6 |
(167) 0x428c5d VADDSD (%RBX),%XMM6,%XMM7 |
(167) 0x428c61 VSUBSD (%R12,%R13,8),%XMM7,%XMM9 |
(167) 0x428c67 VMOVSD %XMM9,(%RSI,%R11,8) |
(167) 0x428c6d VMOVSD (%RBX),%XMM5 |
(167) 0x428c71 VMOVSD %XMM5,(%R15,%R14,8) |
(167) 0x428c77 MOV 0x38(%RSP),%EDI |
(167) 0x428c7b MOV 0x18(%RSP),%R8 |
(167) 0x428c80 LEA (%R8),%R9D |
(167) 0x428c83 CMP %R9D,0x10(%RSP) |
(167) 0x428c88 JLE 428cb0 |
(167) 0x428c8a MOV 0x8(%RSP),%ECX |
(167) 0x428c8e MOV 0xc(%RSP),%R15D |
(167) 0x428c93 MOV 0x14(%RSP),%R14D |
(167) 0x428c98 SUB %EDI,%ECX |
(167) 0x428c9a MOV %R15D,0x3c(%RSP) |
(167) 0x428c9f JMP 4288a0 |
0x428ca4 NOPW %CS:(%RAX,%RAX,1) |
0x428caf NOP |
0x428cb0 VZEROUPPER |
0x428cb3 LEA -0x28(%RBP),%RSP |
0x428cb7 POP %RBX |
0x428cb8 POP %R12 |
0x428cba POP %R13 |
0x428cbc POP %R14 |
0x428cbe POP %R15 |
0x428cc0 POP %RBP |
0x428cc1 RET |
0x428cc2 NOPW %CS:(%RAX,%RAX,1) |
0x428ccd NOPL (%RAX) |
(167) 0x428cd0 LEA 0x1(%R8),%R14 |
(167) 0x428cd4 MOV %R14,0x18(%RSP) |
(167) 0x428cd9 JMP 428c7b |
0x428cdb NOPL (%RAX,%RAX,1) |
(167) 0x428ce0 MOV 0x3c(%RSP),%R14D |
(167) 0x428ce5 XOR %R13D,%R13D |
(167) 0x428ce8 JMP 428b01 |
0x428ced INC %ECX |
0x428cef XOR %EDX,%EDX |
0x428cf1 JMP 42884f |
0x428cf6 NOPW %CS:(%RAX,%RAX,1) |
Path / |
Source file and lines | advec_cell.cpp:146-150 |
Module | exec |
nb instructions | 78 |
nb uops | 76 |
loop length | 276 |
used x86 registers | 15 |
used mmx registers | 0 |
used xmm registers | 4 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 6 |
micro-operation queue | 12.67 cycles |
front end | 12.67 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 7.00 | 7.00 | 7.00 | 7.00 | 6.00 | 6.00 | 6.00 | 6.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 |
cycles | 7.00 | 7.00 | 7.00 | 7.00 | 6.00 | 6.00 | 6.00 | 6.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 |
Cycles executing div or sqrt instructions | 12.00 |
Front-end | 12.67 |
Dispatch | 7.00 |
DIV/SQRT | 12.00 |
Overall L1 | 12.67 |
all | 3% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 8% |
all | 7% |
load | 9% |
store | 6% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 8% |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %RDI,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
AND $-0x40,%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB $0x40,%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV 0x28(%RDI),%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x2c(%RDI),%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x20(%RDI),%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x24(%R15),%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
ADD $0x4,%EDX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
DEC %EDI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LEA -0x1(%RAX),%R13D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %EDX,0x10(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV %EDI,0xc(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
CMP %EDX,%R13D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JGE 428cb3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5+0x4e3> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x4(%RCX),%R14D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB %R13D,%EBX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP %R14D,%EDI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JGE 428cb3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5+0x4e3> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV %R14D,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SUB %EDI,%ESI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %ESI,0x14(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
CALL 404650 <omp_get_num_threads@plt> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CALL 404540 <omp_get_thread_num@plt> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV %EAX,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x14(%RSP),%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 10-17 | 6 |
MOV %EAX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP %EDX,%EDI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JB 428ced <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5+0x51d> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
IMUL %ECX,%EDI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %EDX,%EDI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LEA (%RCX,%RDI,1),%R8D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %R8D,0x8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
CMP %R8D,%EDI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JAE 428cb3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5+0x4e3> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV %EDI,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV 0xc(%RSP),%R9D | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
VMOVQ (%R15),%XMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
DIVL 0x14(%RSP) | 3 | 2 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 10-17 | 6 |
VMOVQ 0x8(%R15),%XMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVQ 0x10(%R15),%XMM11 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVQ 0x18(%R15),%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R9D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LEA (%RAX,%R13,1),%R10D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB %R9D,%R14D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOVSXD %R10D,%R8 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %R9D,0x3c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
NOPL (%RAX) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
NOPW %CS:(%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
NOP | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
VZEROUPPER | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
POP %RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
RET | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
NOPW %CS:(%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
NOPL (%RAX) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
NOPL (%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
INC %ECX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
JMP 42884f <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5+0x7f> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
NOPW %CS:(%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
Source file and lines | advec_cell.cpp:146-150 |
Module | exec |
nb instructions | 78 |
nb uops | 76 |
loop length | 276 |
used x86 registers | 15 |
used mmx registers | 0 |
used xmm registers | 4 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 6 |
micro-operation queue | 12.67 cycles |
front end | 12.67 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 7.00 | 7.00 | 7.00 | 7.00 | 6.00 | 6.00 | 6.00 | 6.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 |
cycles | 7.00 | 7.00 | 7.00 | 7.00 | 6.00 | 6.00 | 6.00 | 6.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 |
Cycles executing div or sqrt instructions | 12.00 |
Front-end | 12.67 |
Dispatch | 7.00 |
DIV/SQRT | 12.00 |
Overall L1 | 12.67 |
all | 3% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 8% |
all | 7% |
load | 9% |
store | 6% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 8% |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %RDI,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
AND $-0x40,%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB $0x40,%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV 0x28(%RDI),%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x2c(%RDI),%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x20(%RDI),%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x24(%R15),%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
ADD $0x4,%EDX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
DEC %EDI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LEA -0x1(%RAX),%R13D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %EDX,0x10(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV %EDI,0xc(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
CMP %EDX,%R13D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JGE 428cb3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5+0x4e3> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x4(%RCX),%R14D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB %R13D,%EBX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP %R14D,%EDI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JGE 428cb3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5+0x4e3> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV %R14D,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SUB %EDI,%ESI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %ESI,0x14(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
CALL 404650 <omp_get_num_threads@plt> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CALL 404540 <omp_get_thread_num@plt> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV %EAX,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x14(%RSP),%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 10-17 | 6 |
MOV %EAX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP %EDX,%EDI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JB 428ced <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5+0x51d> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
IMUL %ECX,%EDI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %EDX,%EDI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LEA (%RCX,%RDI,1),%R8D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %R8D,0x8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
CMP %R8D,%EDI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JAE 428cb3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5+0x4e3> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV %EDI,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV 0xc(%RSP),%R9D | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
VMOVQ (%R15),%XMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
DIVL 0x14(%RSP) | 3 | 2 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 10-17 | 6 |
VMOVQ 0x8(%R15),%XMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVQ 0x10(%R15),%XMM11 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVQ 0x18(%R15),%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R9D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LEA (%RAX,%R13,1),%R10D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB %R9D,%R14D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOVSXD %R10D,%R8 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %R9D,0x3c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
NOPL (%RAX) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
NOPW %CS:(%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
NOP | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
VZEROUPPER | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
POP %RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
RET | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
NOPW %CS:(%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
NOPL (%RAX) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
NOPL (%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
INC %ECX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
JMP 42884f <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5+0x7f> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
NOPW %CS:(%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5– | 1.29 | 0.65 |
▼Loop 167 - advec_cell.cpp:146-150 - exec– | 0 | 0 |
○Loop 168 - advec_cell.cpp:149-150 - exec | 1.29 | 0.65 |