Loop Id: 160 | Module: exec | Source: context.h:69-69 [...] | Coverage: 5.34% |
---|
Loop Id: 160 | Module: exec | Source: context.h:69-69 [...] | Coverage: 5.34% |
---|
0x243350 MOV %R8,%R12 |
0x243353 CALL 25f790 <@plt_start@+0x580> |
0x243358 VMOVSD -0x31b20(%RIP),%XMM5 [9] |
0x243360 VMOVSD -0x31b70(%RIP),%XMM4 [9] |
0x243368 MOV %R12,%R8 |
0x24336b MOV 0x10(%RBP),%R11 [10] |
0x24336f MOV 0x18(%RBP),%R10 [10] |
0x243373 MOV 0x20(%RBP),%R9 [10] |
0x243377 MOV -0x40(%RBP),%R12D [10] |
0x24337b MOV -0x2c(%RBP),%EDI [10] |
0x24337e VXORPD %XMM6,%XMM6,%XMM6 |
0x243382 IMUL (%R8),%R15 [2] |
0x243386 MOV 0x10(%R8),%RAX [2] |
0x24338a ADD %RBX,%R15 |
0x24338d VMOVSD %XMM0,(%RAX,%R15,8) [5] |
0x243393 LEA 0x1(%R14),%RAX |
0x243397 CMP -0x38(%RBP),%R14 [10] |
0x24339b MOV %RAX,%R14 |
0x24339e JGE 243302 |
0x2433a4 MOV %R14,%RAX |
0x2433a7 CQTO |
0x2433a9 IDIV %R13 |
0x2433ac MOV (%R11),%RCX [7] |
0x2433af MOV (%R9),%RSI [3] |
0x2433b2 ADD %R12D,%EDX |
0x2433b5 MOVSXD %EDX,%RBX |
0x2433b8 MOV 0x10(%R9),%RDX [3] |
0x2433bc ADD %EDI,%EAX |
0x2433be MOVSXD %EAX,%R15 |
0x2433c1 MOV 0x10(%R11),%RAX [7] |
0x2433c5 IMUL %R15,%RCX |
0x2433c9 IMUL %R15,%RSI |
0x2433cd ADD %RBX,%RCX |
0x2433d0 ADD %RBX,%RSI |
0x2433d3 VMOVSD (%RAX,%RCX,8),%XMM0 [1] |
0x2433d8 VDIVSD %XMM0,%XMM4,%XMM1 |
0x2433dc VMULSD %XMM5,%XMM0,%XMM0 |
0x2433e0 VMULSD (%RDX,%RSI,8),%XMM0,%XMM0 [4] |
0x2433e5 MOV (%R10),%RSI [6] |
0x2433e8 MOV 0x10(%R10),%RDX [6] |
0x2433ec IMUL %R15,%RSI |
0x2433f0 ADD %RBX,%RSI |
0x2433f3 VMOVSD %XMM0,(%RDX,%RSI,8) [8] |
0x2433f8 VMOVSD (%RAX,%RCX,8),%XMM2 [1] |
0x2433fd VMULSD %XMM1,%XMM1,%XMM1 |
0x243401 VMULSD %XMM5,%XMM2,%XMM3 |
0x243405 VMULSD %XMM2,%XMM0,%XMM2 |
0x243409 VFMADD231SD %XMM3,%XMM0,%XMM2 |
0x24340e VMULSD %XMM2,%XMM1,%XMM0 |
0x243412 VUCOMISD %XMM6,%XMM0 |
0x243416 JB 243350 |
0x24341c VSQRTSD %XMM0,%XMM0,%XMM0 |
0x243420 JMP 243382 |
/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69 |
-------------------------------------------------------------------------------- |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/ideal_gas.cpp: 37 - 45 |
-------------------------------------------------------------------------------- |
37: #pragma omp parallel for simd collapse(2) |
38: for (int j = (y_min + 1); j < (y_max + 2); j++) { |
39: for (int i = (x_min + 1); i < (x_max + 2); i++) { |
40: double v = 1.0 / density(i, j); |
41: pressure(i, j) = (1.4 - 1.0) * density(i, j) * energy(i, j); |
42: double pressurebyenergy = (1.4 - 1.0) * density(i, j); |
43: double pressurebyvolume = -density(i, j) * pressure(i, j); |
44: double sound_speed_squared = v * v * (pressure(i, j) * pressurebyenergy - pressurebyvolume); |
45: soundspeed(i, j) = std::sqrt(sound_speed_squared); |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.76 - 2.30 |
CQA speedup if FP arith vectorized | 1.48 |
CQA speedup if fully vectorized | 4.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 2.03 - 2.66 |
Bottlenecks | |
Function | .omp_outlined.#0x243250 |
Source | context.h:69-69,ideal_gas.cpp:37-45 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 16.25 - 21.25 |
CQA cycles if no scalar integer | 9.25 |
CQA cycles if FP arith vectorized | 9.31 - 14.31 |
CQA cycles if fully vectorized | 4.06 - 5.31 |
Front-end cycles | 8.00 |
DIV/SQRT cycles | 4.25 |
P0 cycles | 4.25 |
P1 cycles | 4.00 |
P2 cycles | 4.00 |
P3 cycles | 2.50 |
P4 cycles | 6.00 |
P5 cycles | 6.00 |
P6 cycles | 6.00 |
P7 cycles | 4.25 |
P8 cycles | 4.25 |
P9 cycles | 0.50 |
P10 cycles | 0.50 |
P11 cycles | 1.50 |
P12 cycles | 1.50 |
P13 cycles | 16.25 - 21.25 |
Inter-iter dependencies cycles | 0 |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 46.50 |
Nb uops | 48.00 |
Nb loads | 15.50 |
Nb stores | 2.00 |
Nb stack references | 3.50 |
FLOP/cycle | 0.58 - 0.45 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 6.00 |
Nb FLOP fma | 1.00 |
Nb FLOP div | 1.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.50 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 6.90 - 9.40 |
Bytes prefetched | 0.00 |
Bytes loaded | 120.00 |
Bytes stored | 16.00 |
Stride 0 | 3.50 |
Stride 1 | 0.00 |
Stride n | 0.00 |
Stride unknown | 3.00 |
Stride indirect | 2.00 |
Vectorization ratio all | 2.27 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | 0.00 |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | 0.00 |
Vectorization ratio div_sqrt | 0.00 |
Vectorization ratio other | 10.00 |
Vector-efficiency ratio all | 12.50 |
Vector-efficiency ratio load | 11.72 |
Vector-efficiency ratio store | 12.50 |
Vector-efficiency ratio mul | 12.50 |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | 12.50 |
Vector-efficiency ratio div_sqrt | 12.50 |
Vector-efficiency ratio other | 13.75 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.52 - 1.89 |
CQA speedup if FP arith vectorized | 1.66 |
CQA speedup if fully vectorized | 4.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 2.86 - 3.56 |
Bottlenecks | P8, P9, |
Function | .omp_outlined.#0x243250 |
Source | context.h:69-69,ideal_gas.cpp:37-45 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 20.50 - 25.50 |
CQA cycles if no scalar integer | 13.50 |
CQA cycles if FP arith vectorized | 10.38 - 15.38 |
CQA cycles if fully vectorized | 5.13 - 6.38 |
Front-end cycles | 7.17 |
DIV/SQRT cycles | 4.25 |
P0 cycles | 4.25 |
P1 cycles | 4.00 |
P2 cycles | 4.00 |
P3 cycles | 2.50 |
P4 cycles | 4.67 |
P5 cycles | 4.67 |
P6 cycles | 4.67 |
P7 cycles | 4.50 |
P8 cycles | 4.50 |
P9 cycles | 0.50 |
P10 cycles | 0.50 |
P11 cycles | 1.50 |
P12 cycles | 1.50 |
P13 cycles | 20.50 - 25.50 |
Inter-iter dependencies cycles | 0 |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 42.00 |
Nb uops | 43.00 |
Nb loads | 12.00 |
Nb stores | 2.00 |
Nb stack references | 1.00 |
FLOP/cycle | 0.49 - 0.39 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 6.00 |
Nb FLOP fma | 1.00 |
Nb FLOP div | 1.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 1.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 4.39 - 5.46 |
Bytes prefetched | 0.00 |
Bytes loaded | 96.00 |
Bytes stored | 16.00 |
Stride 0 | 5.00 |
Stride 1 | 0.00 |
Stride n | 0.00 |
Stride unknown | 3.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | 0.00 |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | 0.00 |
Vectorization ratio div_sqrt | 0.00 |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 12.50 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 12.50 |
Vector-efficiency ratio mul | 12.50 |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | 12.50 |
Vector-efficiency ratio div_sqrt | 12.50 |
Vector-efficiency ratio other | 12.50 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 2.40 - 3.40 |
CQA speedup if FP arith vectorized | 1.28 |
CQA speedup if fully vectorized | 4.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.36 - 1.92 |
Bottlenecks | P8, P9, |
Function | .omp_outlined.#0x243250 |
Source | context.h:69-69,ideal_gas.cpp:37-45 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 12.00 - 17.00 |
CQA cycles if no scalar integer | 5.00 |
CQA cycles if FP arith vectorized | 8.25 - 13.25 |
CQA cycles if fully vectorized | 3.00 - 4.25 |
Front-end cycles | 8.83 |
DIV/SQRT cycles | 4.25 |
P0 cycles | 4.25 |
P1 cycles | 4.00 |
P2 cycles | 4.00 |
P3 cycles | 2.50 |
P4 cycles | 7.33 |
P5 cycles | 7.33 |
P6 cycles | 7.33 |
P7 cycles | 4.00 |
P8 cycles | 4.00 |
P9 cycles | 0.50 |
P10 cycles | 0.50 |
P11 cycles | 1.50 |
P12 cycles | 1.50 |
P13 cycles | 12.00 - 17.00 |
Inter-iter dependencies cycles | 0 |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 51.00 |
Nb uops | 53.00 |
Nb loads | 19.00 |
Nb stores | 2.00 |
Nb stack references | 6.00 |
FLOP/cycle | 0.75 - 0.53 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 6.00 |
Nb FLOP fma | 1.00 |
Nb FLOP div | 1.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 9.41 - 13.33 |
Bytes prefetched | 0.00 |
Bytes loaded | 144.00 |
Bytes stored | 16.00 |
Stride 0 | 2.00 |
Stride 1 | 0.00 |
Stride n | 0.00 |
Stride unknown | 3.00 |
Stride indirect | 4.00 |
Vectorization ratio all | 4.55 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | 0.00 |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | 0.00 |
Vectorization ratio div_sqrt | 0.00 |
Vectorization ratio other | 20.00 |
Vector-efficiency ratio all | 12.50 |
Vector-efficiency ratio load | 10.94 |
Vector-efficiency ratio store | 12.50 |
Vector-efficiency ratio mul | 12.50 |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | 12.50 |
Vector-efficiency ratio div_sqrt | 12.50 |
Vector-efficiency ratio other | 15.00 |
Path / |
Function | .omp_outlined.#0x243250 |
Source file and lines | context.h:69-69 |
Module | exec |
nb instructions | 46.50 |
nb uops | 48 |
loop length | 183.50 |
used x86 registers | 15 |
used mmx registers | 0 |
used xmm registers | 7 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 3.50 |
micro-operation queue | 8.00 cycles |
front end | 8.00 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 4.25 | 4.25 | 4.00 | 4.00 | 2.50 | 6.00 | 6.00 | 6.00 | 4.25 | 4.25 | 0.50 | 0.50 | 1.50 | 1.50 |
cycles | 4.25 | 4.25 | 4.00 | 4.00 | 2.50 | 6.00 | 6.00 | 6.00 | 4.25 | 4.25 | 0.50 | 0.50 | 1.50 | 1.50 |
Cycles executing div or sqrt instructions | 16.25-21.25 |
Longest recurrence chain latency (RecMII) | 0.00 |
Front-end | 8.00 |
Dispatch | 6.00 |
DIV/SQRT | 16.25-21.25 |
Data deps. | 0.00 |
Overall L1 | 16.25-21.25 |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 3% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 0% |
div/sqrt | 0% |
other | 25% |
all | 2% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 0% |
div/sqrt | 0% |
other | 10% |
all | 11% |
load | 10% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 12% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 12% |
div/sqrt | 12% |
other | 15% |
all | 12% |
load | 11% |
store | 12% |
mul | 12% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 12% |
div/sqrt | 12% |
other | 13% |
Function | .omp_outlined.#0x243250 |
Source file and lines | context.h:69-69 |
Module | exec |
nb instructions | 42 |
nb uops | 43 |
loop length | 163 |
used x86 registers | 15 |
used mmx registers | 0 |
used xmm registers | 7 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 1 |
micro-operation queue | 7.17 cycles |
front end | 7.17 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 4.25 | 4.25 | 4.00 | 4.00 | 2.50 | 4.67 | 4.67 | 4.67 | 4.50 | 4.50 | 0.50 | 0.50 | 1.50 | 1.50 |
cycles | 4.25 | 4.25 | 4.00 | 4.00 | 2.50 | 4.67 | 4.67 | 4.67 | 4.50 | 4.50 | 0.50 | 0.50 | 1.50 | 1.50 |
Cycles executing div or sqrt instructions | 20.50-25.50 |
Longest recurrence chain latency (RecMII) | 0.00 |
Front-end | 7.17 |
Dispatch | 4.67 |
DIV/SQRT | 20.50-25.50 |
Data deps. | 0.00 |
Overall L1 | 20.50-25.50 |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 0% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 0% |
div/sqrt | 0% |
other | 0% |
all | 0% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 0% |
div/sqrt | 0% |
other | 0% |
all | 12% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 12% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 12% |
div/sqrt | 12% |
other | 12% |
all | 12% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 12% |
div/sqrt | 12% |
other | 12% |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
IMUL (%R8),%R15 | 1 | 0 | 1 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV 0x10(%R8),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
ADD %RBX,%R15 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
VMOVSD %XMM0,(%RAX,%R15,8) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
LEA 0x1(%R14),%RAX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP -0x38(%RBP),%R14 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
MOV %RAX,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JGE 243302 <.omp_outlined.+0xb2> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV %R14,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CQTO | |||||||||||||||||
IDIV %R13 | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 9-19 | 7-12 |
MOV (%R11),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV (%R9),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
ADD %R12D,%EDX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOVSXD %EDX,%RBX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV 0x10(%R9),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
ADD %EDI,%EAX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOVSXD %EAX,%R15 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV 0x10(%R11),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
IMUL %R15,%RCX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
IMUL %R15,%RSI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %RBX,%RCX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD %RBX,%RSI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
VMOVSD (%RAX,%RCX,8),%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VDIVSD %XMM0,%XMM4,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13 | 5 |
VMULSD %XMM5,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMULSD (%RDX,%RSI,8),%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
MOV (%R10),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x10(%R10),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
IMUL %R15,%RSI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %RBX,%RSI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
VMOVSD %XMM0,(%RDX,%RSI,8) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VMOVSD (%RAX,%RCX,8),%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMULSD %XMM1,%XMM1,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMULSD %XMM5,%XMM2,%XMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMULSD %XMM2,%XMM0,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VFMADD231SD %XMM3,%XMM0,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULSD %XMM2,%XMM1,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VUCOMISD %XMM6,%XMM0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0.50 | 6 | 1 |
JB 243350 <.omp_outlined.+0x100> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
VSQRTSD %XMM0,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 21 | 8.50 |
JMP 243382 <.omp_outlined.+0x132> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
Function | .omp_outlined.#0x243250 |
Source file and lines | context.h:69-69 |
Module | exec |
nb instructions | 51 |
nb uops | 53 |
loop length | 204 |
used x86 registers | 15 |
used mmx registers | 0 |
used xmm registers | 7 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 6 |
micro-operation queue | 8.83 cycles |
front end | 8.83 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 4.25 | 4.25 | 4.00 | 4.00 | 2.50 | 7.33 | 7.33 | 7.33 | 4.00 | 4.00 | 0.50 | 0.50 | 1.50 | 1.50 |
cycles | 4.25 | 4.25 | 4.00 | 4.00 | 2.50 | 7.33 | 7.33 | 7.33 | 4.00 | 4.00 | 0.50 | 0.50 | 1.50 | 1.50 |
Cycles executing div or sqrt instructions | 12.00-17.00 |
Longest recurrence chain latency (RecMII) | 0.00 |
Front-end | 8.83 |
Dispatch | 7.33 |
DIV/SQRT | 12.00-17.00 |
Data deps. | 0.00 |
Overall L1 | 12.00-17.00 |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 6% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 0% |
div/sqrt | 0% |
other | 50% |
all | 4% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 0% |
div/sqrt | 0% |
other | 20% |
all | 10% |
load | 8% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 13% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 12% |
div/sqrt | 12% |
other | 18% |
all | 12% |
load | 10% |
store | 12% |
mul | 12% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 12% |
div/sqrt | 12% |
other | 15% |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOV %R8,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CALL 25f790 <@plt_start@+0x580> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VMOVSD -0x31b20(%RIP),%XMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVSD -0x31b70(%RIP),%XMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %R12,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x10(%RBP),%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x18(%RBP),%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x20(%RBP),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV -0x40(%RBP),%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV -0x2c(%RBP),%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
VXORPD %XMM6,%XMM6,%XMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
IMUL (%R8),%R15 | 1 | 0 | 1 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV 0x10(%R8),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
ADD %RBX,%R15 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
VMOVSD %XMM0,(%RAX,%R15,8) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
LEA 0x1(%R14),%RAX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP -0x38(%RBP),%R14 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
MOV %RAX,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JGE 243302 <.omp_outlined.+0xb2> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV %R14,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CQTO | |||||||||||||||||
IDIV %R13 | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 9-19 | 7-12 |
MOV (%R11),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV (%R9),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
ADD %R12D,%EDX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOVSXD %EDX,%RBX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV 0x10(%R9),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
ADD %EDI,%EAX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOVSXD %EAX,%R15 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV 0x10(%R11),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
IMUL %R15,%RCX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
IMUL %R15,%RSI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %RBX,%RCX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD %RBX,%RSI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
VMOVSD (%RAX,%RCX,8),%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VDIVSD %XMM0,%XMM4,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13 | 5 |
VMULSD %XMM5,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMULSD (%RDX,%RSI,8),%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
MOV (%R10),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x10(%R10),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
IMUL %R15,%RSI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %RBX,%RSI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
VMOVSD %XMM0,(%RDX,%RSI,8) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VMOVSD (%RAX,%RCX,8),%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMULSD %XMM1,%XMM1,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMULSD %XMM5,%XMM2,%XMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMULSD %XMM2,%XMM0,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VFMADD231SD %XMM3,%XMM0,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULSD %XMM2,%XMM1,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VUCOMISD %XMM6,%XMM0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0.50 | 6 | 1 |
JB 243350 <.omp_outlined.+0x100> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |