Function: _Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buf ... | Module: exec | Source: advec_mom.cpp:157-160 [...] | Coverage: 1.28% |
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Function: _Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buf ... | Module: exec | Source: advec_mom.cpp:157-160 [...] | Coverage: 1.28% |
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/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp: 157 - 160 |
-------------------------------------------------------------------------------- |
157: #pragma omp parallel for simd collapse(2) |
158: for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) { |
159: for (int i = (x_min + 1); i < (x_max + 1 + 2); i++) { |
160: node_flux(i, j) = 0.25 * (mass_flux_y(i - 1, j + 0) + mass_flux_y(i, j) + mass_flux_y(i - 1, j + 1) + mass_flux_y(i + 0, j + 1)); |
/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69 |
-------------------------------------------------------------------------------- |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
0x42fb90 PUSH %RBP |
0x42fb91 MOV %RSP,%RBP |
0x42fb94 PUSH %R15 |
0x42fb96 PUSH %R14 |
0x42fb98 PUSH %R13 |
0x42fb9a PUSH %R12 |
0x42fb9c PUSH %RBX |
0x42fb9d MOV %RDI,%R14 |
0x42fba0 AND $-0x40,%RSP |
0x42fba4 SUB $0x40,%RSP |
0x42fba8 MOV 0x18(%RDI),%EAX |
0x42fbab MOV 0x1c(%RDI),%EDX |
0x42fbae MOV 0x10(%RDI),%ECX |
0x42fbb1 MOV 0x14(%RDI),%EDI |
0x42fbb4 ADD $0x4,%EDX |
0x42fbb7 INC %ECX |
0x42fbb9 LEA -0x1(%RAX),%R12D |
0x42fbbd MOV %EDX,0x20(%RSP) |
0x42fbc1 MOV %ECX,0x1c(%RSP) |
0x42fbc5 CMP %EDX,%R12D |
0x42fbc8 JGE 430033 |
0x42fbce MOV %EDX,%EBX |
0x42fbd0 LEA 0x3(%RDI),%R15D |
0x42fbd4 SUB %R12D,%EBX |
0x42fbd7 CMP %R15D,%ECX |
0x42fbda JGE 430033 |
0x42fbe0 MOV %R15D,%ESI |
0x42fbe3 SUB %ECX,%ESI |
0x42fbe5 MOV %ESI,0x24(%RSP) |
0x42fbe9 CALL 404650 <omp_get_num_threads@plt> |
0x42fbee MOV %EAX,%R13D |
0x42fbf1 CALL 404540 <omp_get_thread_num@plt> |
0x42fbf6 MOV 0x24(%RSP),%R8D |
0x42fbfb XOR %EDX,%EDX |
0x42fbfd MOV %EAX,%ECX |
0x42fbff IMUL %R8D,%EBX |
0x42fc03 MOV %EBX,%EAX |
0x42fc05 DIV %R13D |
0x42fc08 MOV %EAX,%R11D |
0x42fc0b CMP %EDX,%ECX |
0x42fc0d JB 43005d |
0x42fc13 IMUL %R11D,%ECX |
0x42fc17 ADD %EDX,%ECX |
0x42fc19 LEA (%R11,%RCX,1),%R9D |
0x42fc1d MOV %R9D,0x18(%RSP) |
0x42fc22 CMP %R9D,%ECX |
0x42fc25 JAE 430033 |
0x42fc2b MOV %ECX,%EAX |
0x42fc2d XOR %EDX,%EDX |
0x42fc2f MOV 0x1c(%RSP),%R10D |
0x42fc34 VMOVQ (%R14),%XMM4 |
0x42fc39 DIVL 0x24(%RSP) |
0x42fc3d VMOVQ 0x8(%R14),%XMM3 |
0x42fc43 VMOVSD 0x30b75(%RIP),%XMM9 |
0x42fc4b VBROADCASTSD %XMM9,%YMM10 |
0x42fc50 VBROADCASTSD %XMM9,%ZMM5 |
0x42fc56 ADD %EDX,%R10D |
0x42fc59 ADD %R12D,%EAX |
0x42fc5c MOV %R15D,%EDX |
0x42fc5f CLTQ |
0x42fc61 SUB %R10D,%EDX |
0x42fc64 MOV %R10D,0x3c(%RSP) |
0x42fc69 MOV %RAX,0x30(%RSP) |
0x42fc6e XCHG %AX,%AX |
(193) 0x42fc70 CMP %EDX,%R11D |
(193) 0x42fc73 CMOVBE %R11D,%EDX |
(193) 0x42fc77 LEA (%RCX,%RDX,1),%R11D |
(193) 0x42fc7b MOV %R11D,0x38(%RSP) |
(193) 0x42fc80 CMP %R11D,%ECX |
(193) 0x42fc83 JAE 42fff2 |
(193) 0x42fc89 MOV 0x30(%RSP),%RBX |
(193) 0x42fc8e VMOVQ %XMM4,%R12 |
(193) 0x42fc93 VMOVQ %XMM3,%RDI |
(193) 0x42fc98 LEA -0x1(%RDX),%ESI |
(193) 0x42fc9b MOV (%R12),%R9 |
(193) 0x42fc9f MOV 0x10(%R12),%R14 |
(193) 0x42fca4 MOV 0x10(%RDI),%R15 |
(193) 0x42fca8 MOV %RBX,%R11 |
(193) 0x42fcab IMUL (%RDI),%RBX |
(193) 0x42fcaf IMUL %R9,%R11 |
(193) 0x42fcb3 ADD %R11,%R9 |
(193) 0x42fcb6 MOV %RBX,0x28(%RSP) |
(193) 0x42fcbb CMP $0x6,%ESI |
(193) 0x42fcbe JBE 430050 |
(193) 0x42fcc4 MOVSXD 0x3c(%RSP),%R8 |
(193) 0x42fcc9 XOR %EAX,%EAX |
(193) 0x42fccb LEA (%R8,%R11,1),%RDI |
(193) 0x42fccf LEA (%R8,%R9,1),%RSI |
(193) 0x42fcd3 ADD %RBX,%R8 |
(193) 0x42fcd6 MOV %EDX,%EBX |
(193) 0x42fcd8 SHR $0x3,%EBX |
(193) 0x42fcdb SAL $0x6,%RBX |
(193) 0x42fcdf LEA -0x40(%RBX),%R10 |
(193) 0x42fce3 LEA (%R15,%R8,8),%R8 |
(193) 0x42fce7 SHR $0x6,%R10 |
(193) 0x42fceb SAL $0x3,%RDI |
(193) 0x42fcef SAL $0x3,%RSI |
(193) 0x42fcf3 INC %R10 |
(193) 0x42fcf6 LEA -0x8(%R14,%RDI,1),%R12 |
(193) 0x42fcfb LEA -0x8(%R14,%RSI,1),%R13 |
(193) 0x42fd00 ADD %R14,%RDI |
(193) 0x42fd03 ADD %R14,%RSI |
(193) 0x42fd06 AND $0x3,%R10D |
(193) 0x42fd0a JE 42fdbe |
(193) 0x42fd10 CMP $0x1,%R10 |
(193) 0x42fd14 JE 42fd81 |
(193) 0x42fd16 CMP $0x2,%R10 |
(193) 0x42fd1a JE 42fd4d |
(193) 0x42fd1c VMOVUPD (%R12),%ZMM7 |
(193) 0x42fd23 VMOVUPD (%R13),%ZMM6 |
(193) 0x42fd2a VADDPD (%RDI),%ZMM7,%ZMM1 |
(193) 0x42fd30 MOV $0x40,%EAX |
(193) 0x42fd35 VADDPD (%RSI),%ZMM6,%ZMM11 |
(193) 0x42fd3b VADDPD %ZMM11,%ZMM1,%ZMM0 |
(193) 0x42fd41 VMULPD %ZMM5,%ZMM0,%ZMM2 |
(193) 0x42fd47 VMOVUPD %ZMM2,(%R8) |
(193) 0x42fd4d VMOVUPD (%R12,%RAX,1),%ZMM8 |
(193) 0x42fd54 VMOVUPD (%R13,%RAX,1),%ZMM13 |
(193) 0x42fd5c VADDPD (%RDI,%RAX,1),%ZMM8,%ZMM12 |
(193) 0x42fd63 VADDPD (%RSI,%RAX,1),%ZMM13,%ZMM14 |
(193) 0x42fd6a VADDPD %ZMM14,%ZMM12,%ZMM15 |
(193) 0x42fd70 VMULPD %ZMM5,%ZMM15,%ZMM7 |
(193) 0x42fd76 VMOVUPD %ZMM7,(%R8,%RAX,1) |
(193) 0x42fd7d ADD $0x40,%RAX |
(193) 0x42fd81 VMOVUPD (%R12,%RAX,1),%ZMM1 |
(193) 0x42fd88 VMOVUPD (%R13,%RAX,1),%ZMM11 |
(193) 0x42fd90 VADDPD (%RDI,%RAX,1),%ZMM1,%ZMM6 |
(193) 0x42fd97 VADDPD (%RSI,%RAX,1),%ZMM11,%ZMM0 |
(193) 0x42fd9e VADDPD %ZMM0,%ZMM6,%ZMM2 |
(193) 0x42fda4 VMULPD %ZMM5,%ZMM2,%ZMM8 |
(193) 0x42fdaa VMOVUPD %ZMM8,(%R8,%RAX,1) |
(193) 0x42fdb1 ADD $0x40,%RAX |
(193) 0x42fdb5 CMP %RAX,%RBX |
(193) 0x42fdb8 JE 42fe99 |
(194) 0x42fdbe VMOVUPD (%R12,%RAX,1),%ZMM12 |
(194) 0x42fdc5 VMOVUPD (%R13,%RAX,1),%ZMM14 |
(194) 0x42fdcd VADDPD (%RDI,%RAX,1),%ZMM12,%ZMM13 |
(194) 0x42fdd4 VADDPD (%RSI,%RAX,1),%ZMM14,%ZMM15 |
(194) 0x42fddb VADDPD %ZMM15,%ZMM13,%ZMM7 |
(194) 0x42fde1 VMULPD %ZMM5,%ZMM7,%ZMM1 |
(194) 0x42fde7 VMOVUPD %ZMM1,(%R8,%RAX,1) |
(194) 0x42fdee VMOVUPD 0x40(%R12,%RAX,1),%ZMM6 |
(194) 0x42fdf6 VMOVUPD 0x40(%R13,%RAX,1),%ZMM11 |
(194) 0x42fdfe VADDPD 0x40(%RDI,%RAX,1),%ZMM6,%ZMM2 |
(194) 0x42fe06 VADDPD 0x40(%RSI,%RAX,1),%ZMM11,%ZMM0 |
(194) 0x42fe0e VADDPD %ZMM0,%ZMM2,%ZMM8 |
(194) 0x42fe14 VMULPD %ZMM5,%ZMM8,%ZMM12 |
(194) 0x42fe1a VMOVUPD %ZMM12,0x40(%R8,%RAX,1) |
(194) 0x42fe22 VMOVUPD 0x80(%R12,%RAX,1),%ZMM13 |
(194) 0x42fe2a VMOVUPD 0x80(%R13,%RAX,1),%ZMM15 |
(194) 0x42fe32 VADDPD 0x80(%RDI,%RAX,1),%ZMM13,%ZMM14 |
(194) 0x42fe3a VADDPD 0x80(%RSI,%RAX,1),%ZMM15,%ZMM7 |
(194) 0x42fe42 VADDPD %ZMM7,%ZMM14,%ZMM1 |
(194) 0x42fe48 VMULPD %ZMM5,%ZMM1,%ZMM6 |
(194) 0x42fe4e VMOVUPD %ZMM6,0x80(%R8,%RAX,1) |
(194) 0x42fe56 VMOVUPD 0xc0(%R12,%RAX,1),%ZMM2 |
(194) 0x42fe5e VMOVUPD 0xc0(%R13,%RAX,1),%ZMM11 |
(194) 0x42fe66 VADDPD 0xc0(%RDI,%RAX,1),%ZMM2,%ZMM0 |
(194) 0x42fe6e VADDPD 0xc0(%RSI,%RAX,1),%ZMM11,%ZMM8 |
(194) 0x42fe76 VADDPD %ZMM8,%ZMM0,%ZMM12 |
(194) 0x42fe7c VMULPD %ZMM5,%ZMM12,%ZMM13 |
(194) 0x42fe82 VMOVUPD %ZMM13,0xc0(%R8,%RAX,1) |
(194) 0x42fe8a ADD $0x100,%RAX |
(194) 0x42fe90 CMP %RAX,%RBX |
(194) 0x42fe93 JNE 42fdbe |
(193) 0x42fe99 MOV 0x3c(%RSP),%R12D |
(193) 0x42fe9e MOV %EDX,%R13D |
(193) 0x42fea1 AND $-0x8,%R13D |
(193) 0x42fea5 ADD %R13D,%ECX |
(193) 0x42fea8 ADD %R13D,%R12D |
(193) 0x42feab TEST $0x7,%DL |
(193) 0x42feae JE 42ffee |
(193) 0x42feb4 SUB %R13D,%EDX |
(193) 0x42feb7 LEA -0x1(%RDX),%EDI |
(193) 0x42feba CMP $0x2,%EDI |
(193) 0x42febd JBE 42ff1b |
(193) 0x42febf MOVSXD 0x3c(%RSP),%R8 |
(193) 0x42fec4 MOV 0x28(%RSP),%R10 |
(193) 0x42fec9 LEA (%R9,%R8,1),%RSI |
(193) 0x42fecd LEA (%R11,%R8,1),%RBX |
(193) 0x42fed1 ADD %R13,%RSI |
(193) 0x42fed4 ADD %R13,%RBX |
(193) 0x42fed7 ADD %R10,%R13 |
(193) 0x42feda SAL $0x3,%RSI |
(193) 0x42fede VMOVUPD -0x8(%R14,%RBX,8),%YMM14 |
(193) 0x42fee5 VMOVUPD (%R14,%RSI,1),%YMM7 |
(193) 0x42feeb VADDPD -0x8(%R14,%RSI,1),%YMM14,%YMM15 |
(193) 0x42fef2 ADD %R8,%R13 |
(193) 0x42fef5 VADDPD (%R14,%RBX,8),%YMM7,%YMM1 |
(193) 0x42fefb VADDPD %YMM1,%YMM15,%YMM6 |
(193) 0x42feff VMULPD %YMM10,%YMM6,%YMM2 |
(193) 0x42ff04 VMOVUPD %YMM2,(%R15,%R13,8) |
(193) 0x42ff0a TEST $0x3,%DL |
(193) 0x42ff0d JE 42ffee |
(193) 0x42ff13 AND $-0x4,%EDX |
(193) 0x42ff16 ADD %EDX,%ECX |
(193) 0x42ff18 ADD %EDX,%R12D |
(193) 0x42ff1b MOVSXD %R12D,%RDX |
(193) 0x42ff1e MOV 0x28(%RSP),%RBX |
(193) 0x42ff23 LEA -0x1(%R12),%EAX |
(193) 0x42ff28 LEA (%RDX,%R11,1),%R13 |
(193) 0x42ff2c CLTQ |
(193) 0x42ff2e LEA (%R9,%RDX,1),%R8 |
(193) 0x42ff32 LEA (%R14,%R13,8),%RDI |
(193) 0x42ff36 MOV 0x38(%RSP),%R13D |
(193) 0x42ff3b LEA (%R11,%RAX,1),%R10 |
(193) 0x42ff3f LEA (%R14,%R8,8),%RSI |
(193) 0x42ff43 ADD %R9,%RAX |
(193) 0x42ff46 VMOVSD (%R14,%R10,8),%XMM0 |
(193) 0x42ff4c VMOVSD (%RSI),%XMM8 |
(193) 0x42ff50 VADDSD (%RDI),%XMM8,%XMM12 |
(193) 0x42ff54 VADDSD (%R14,%RAX,8),%XMM0,%XMM11 |
(193) 0x42ff5a VADDSD %XMM12,%XMM11,%XMM13 |
(193) 0x42ff5f VMULSD %XMM9,%XMM13,%XMM14 |
(193) 0x42ff64 LEA 0x1(%R12),%EAX |
(193) 0x42ff69 ADD %RBX,%RDX |
(193) 0x42ff6c VMOVSD %XMM14,(%R15,%RDX,8) |
(193) 0x42ff72 LEA 0x1(%RCX),%EDX |
(193) 0x42ff75 CMP %R13D,%EDX |
(193) 0x42ff78 JAE 42ffee |
(193) 0x42ff7a CLTQ |
(193) 0x42ff7c ADD $0x2,%ECX |
(193) 0x42ff7f VMOVSD (%RSI),%XMM15 |
(193) 0x42ff83 ADD $0x2,%R12D |
(193) 0x42ff87 LEA (%R11,%RAX,1),%R8 |
(193) 0x42ff8b LEA (%R9,%RAX,1),%RDX |
(193) 0x42ff8f ADD %RBX,%RAX |
(193) 0x42ff92 VADDSD (%RDI),%XMM15,%XMM7 |
(193) 0x42ff96 LEA (%R14,%R8,8),%R10 |
(193) 0x42ff9a LEA (%R14,%RDX,8),%R8 |
(193) 0x42ff9e VMOVSD (%R8),%XMM1 |
(193) 0x42ffa3 VADDSD (%R10),%XMM1,%XMM6 |
(193) 0x42ffa8 VADDSD %XMM6,%XMM7,%XMM2 |
(193) 0x42ffac VMULSD %XMM9,%XMM2,%XMM0 |
(193) 0x42ffb1 VMOVSD %XMM0,(%R15,%RAX,8) |
(193) 0x42ffb7 CMP %R13D,%ECX |
(193) 0x42ffba JAE 42ffee |
(193) 0x42ffbc MOVSXD %R12D,%RCX |
(193) 0x42ffbf ADD %RCX,%RBX |
(193) 0x42ffc2 ADD %RCX,%R11 |
(193) 0x42ffc5 ADD %R9,%RCX |
(193) 0x42ffc8 VMOVSD (%R14,%R11,8),%XMM11 |
(193) 0x42ffce VMOVSD (%R14,%RCX,8),%XMM12 |
(193) 0x42ffd4 VADDSD (%R10),%XMM11,%XMM8 |
(193) 0x42ffd9 VADDSD (%R8),%XMM12,%XMM13 |
(193) 0x42ffde VADDSD %XMM13,%XMM8,%XMM14 |
(193) 0x42ffe3 VMULSD %XMM9,%XMM14,%XMM15 |
(193) 0x42ffe8 VMOVSD %XMM15,(%R15,%RBX,8) |
(193) 0x42ffee MOV 0x38(%RSP),%ECX |
(193) 0x42fff2 INCQ 0x30(%RSP) |
(193) 0x42fff7 MOV 0x30(%RSP),%R14 |
(193) 0x42fffc ADD $0,%R14D |
(193) 0x430000 CMP %R14D,0x20(%RSP) |
(193) 0x430005 JLE 430030 |
(193) 0x430007 MOV 0x18(%RSP),%R11D |
(193) 0x43000c MOV 0x1c(%RSP),%R9D |
(193) 0x430011 MOV 0x24(%RSP),%EDX |
(193) 0x430015 SUB %ECX,%R11D |
(193) 0x430018 MOV %R9D,0x3c(%RSP) |
(193) 0x43001d JMP 42fc70 |
0x430022 NOPW %CS:(%RAX,%RAX,1) |
0x43002d NOPL (%RAX) |
0x430030 VZEROUPPER |
0x430033 LEA -0x28(%RBP),%RSP |
0x430037 POP %RBX |
0x430038 POP %R12 |
0x43003a POP %R13 |
0x43003c POP %R14 |
0x43003e POP %R15 |
0x430040 POP %RBP |
0x430041 RET |
0x430042 NOPW %CS:(%RAX,%RAX,1) |
0x43004d NOPL (%RAX) |
(193) 0x430050 MOV 0x3c(%RSP),%R12D |
(193) 0x430055 XOR %R13D,%R13D |
(193) 0x430058 JMP 42feb4 |
0x43005d INC %R11D |
0x430060 XOR %EDX,%EDX |
0x430062 JMP 42fc13 |
0x430067 NOPW (%RAX,%RAX,1) |
Path / |
Source file and lines | advec_mom.cpp:157-160 |
Module | exec |
nb instructions | 81 |
nb uops | 79 |
loop length | 289 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 3 |
used ymm registers | 1 |
used zmm registers | 1 |
nb stack references | 7 |
micro-operation queue | 13.17 cycles |
front end | 13.17 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.75 | 6.75 | 6.75 | 6.75 | 6.00 | 6.00 | 6.00 | 6.00 | 0.00 | 1.00 | 1.00 | 0.00 | 0.00 | 0.00 |
cycles | 6.75 | 6.75 | 6.75 | 6.75 | 6.00 | 6.00 | 6.00 | 6.00 | 0.00 | 1.00 | 1.00 | 0.00 | 0.00 | 0.00 |
Cycles executing div or sqrt instructions | 12.00 |
Front-end | 13.17 |
Dispatch | 6.75 |
DIV/SQRT | 12.00 |
Overall L1 | 13.17 |
all | 3% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 6% |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 2% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 6% |
all | 7% |
load | 8% |
store | 7% |
mul | 6% |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 7% |
all | 12% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
all | 8% |
load | 8% |
store | 7% |
mul | 6% |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 8% |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %RDI,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
AND $-0x40,%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB $0x40,%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV 0x18(%RDI),%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x1c(%RDI),%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x10(%RDI),%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x14(%RDI),%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
ADD $0x4,%EDX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
INC %ECX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LEA -0x1(%RAX),%R12D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %EDX,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV %ECX,0x1c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
CMP %EDX,%R12D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JGE 430033 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.8+0x4a3> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x3(%RDI),%R15D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB %R12D,%EBX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP %R15D,%ECX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JGE 430033 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.8+0x4a3> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV %R15D,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SUB %ECX,%ESI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %ESI,0x24(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
CALL 404650 <omp_get_num_threads@plt> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EAX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CALL 404540 <omp_get_thread_num@plt> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x24(%RSP),%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV %EAX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
IMUL %R8D,%EBX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %EBX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
DIV %R13D | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 10-17 | 6 |
MOV %EAX,%R11D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP %EDX,%ECX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JB 43005d <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.8+0x4cd> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
IMUL %R11D,%ECX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %EDX,%ECX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LEA (%R11,%RCX,1),%R9D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %R9D,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
CMP %R9D,%ECX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JAE 430033 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.8+0x4a3> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV %ECX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV 0x1c(%RSP),%R10D | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
VMOVQ (%R14),%XMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
DIVL 0x24(%RSP) | 3 | 2 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 10-17 | 6 |
VMOVQ 0x8(%R14),%XMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVSD 0x30b75(%RIP),%XMM9 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VBROADCASTSD %XMM9,%YMM10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0.50 |
VBROADCASTSD %XMM9,%ZMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 1 |
ADD %EDX,%R10D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD %R12D,%EAX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %R15D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CLTQ | |||||||||||||||||
SUB %R10D,%EDX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %R10D,0x3c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV %RAX,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
XCHG %AX,%AX | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
NOPW %CS:(%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
NOPL (%RAX) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
VZEROUPPER | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
POP %RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
RET | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
NOPW %CS:(%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
NOPL (%RAX) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
INC %R11D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
JMP 42fc13 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.8+0x83> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
NOPW (%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
Source file and lines | advec_mom.cpp:157-160 |
Module | exec |
nb instructions | 81 |
nb uops | 79 |
loop length | 289 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 3 |
used ymm registers | 1 |
used zmm registers | 1 |
nb stack references | 7 |
micro-operation queue | 13.17 cycles |
front end | 13.17 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.75 | 6.75 | 6.75 | 6.75 | 6.00 | 6.00 | 6.00 | 6.00 | 0.00 | 1.00 | 1.00 | 0.00 | 0.00 | 0.00 |
cycles | 6.75 | 6.75 | 6.75 | 6.75 | 6.00 | 6.00 | 6.00 | 6.00 | 0.00 | 1.00 | 1.00 | 0.00 | 0.00 | 0.00 |
Cycles executing div or sqrt instructions | 12.00 |
Front-end | 13.17 |
Dispatch | 6.75 |
DIV/SQRT | 12.00 |
Overall L1 | 13.17 |
all | 3% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 6% |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 2% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 6% |
all | 7% |
load | 8% |
store | 7% |
mul | 6% |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 7% |
all | 12% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
all | 8% |
load | 8% |
store | 7% |
mul | 6% |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 8% |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %RDI,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
AND $-0x40,%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB $0x40,%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV 0x18(%RDI),%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x1c(%RDI),%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x10(%RDI),%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x14(%RDI),%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
ADD $0x4,%EDX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
INC %ECX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LEA -0x1(%RAX),%R12D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %EDX,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV %ECX,0x1c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
CMP %EDX,%R12D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JGE 430033 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.8+0x4a3> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x3(%RDI),%R15D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB %R12D,%EBX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP %R15D,%ECX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JGE 430033 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.8+0x4a3> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV %R15D,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SUB %ECX,%ESI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %ESI,0x24(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
CALL 404650 <omp_get_num_threads@plt> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EAX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CALL 404540 <omp_get_thread_num@plt> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x24(%RSP),%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV %EAX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
IMUL %R8D,%EBX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %EBX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
DIV %R13D | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 10-17 | 6 |
MOV %EAX,%R11D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP %EDX,%ECX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JB 43005d <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.8+0x4cd> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
IMUL %R11D,%ECX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %EDX,%ECX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LEA (%R11,%RCX,1),%R9D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %R9D,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
CMP %R9D,%ECX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JAE 430033 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.8+0x4a3> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV %ECX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV 0x1c(%RSP),%R10D | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
VMOVQ (%R14),%XMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
DIVL 0x24(%RSP) | 3 | 2 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 10-17 | 6 |
VMOVQ 0x8(%R14),%XMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVSD 0x30b75(%RIP),%XMM9 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VBROADCASTSD %XMM9,%YMM10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0.50 |
VBROADCASTSD %XMM9,%ZMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 1 |
ADD %EDX,%R10D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD %R12D,%EAX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %R15D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CLTQ | |||||||||||||||||
SUB %R10D,%EDX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %R10D,0x3c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV %RAX,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
XCHG %AX,%AX | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
NOPW %CS:(%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
NOPL (%RAX) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
VZEROUPPER | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
POP %RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
RET | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
NOPW %CS:(%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
NOPL (%RAX) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
INC %R11D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
JMP 42fc13 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.8+0x83> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
NOPW (%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.8– | 1.28 | 0.64 |
▼Loop 193 - advec_mom.cpp:159-160 - exec– | 0 | 0 |
○Loop 194 - advec_mom.cpp:160-160 - exec | 1.27 | 0.64 |