Loop Id: 164 | Module: exec | Source: advec_cell.cpp:120-125 | Coverage: 3.39% |
---|
Loop Id: 164 | Module: exec | Source: advec_cell.cpp:120-125 | Coverage: 3.39% |
---|
0x427c28 VMOVUPD (%R9,%RCX,1),%ZMM9 [7] |
0x427c2f VMULPD (%RDI,%RCX,1),%ZMM9,%ZMM10 [2] |
0x427c36 VMOVUPD (%RBX,%RCX,1),%ZMM2 [10] |
0x427c3d VADDPD (%RDI,%RCX,1),%ZMM2,%ZMM7 [2] |
0x427c44 VMOVUPD (%RAX,%RCX,1),%ZMM3 [5] |
0x427c4b VSUBPD (%R13,%RCX,1),%ZMM3,%ZMM26 [6] |
0x427c53 VSUBPD (%RSI,%RCX,1),%ZMM10,%ZMM24 [4] |
0x427c5a VSUBPD (%R15,%RCX,1),%ZMM7,%ZMM0 [1] |
0x427c61 VFMADD231PD (%R8,%RCX,1),%ZMM10,%ZMM26 [8] |
0x427c68 VADDPD (%RDX,%RCX,1),%ZMM24,%ZMM25 [9] |
0x427c6f VDIVPD %ZMM25,%ZMM26,%ZMM1 |
0x427c75 VDIVPD %ZMM0,%ZMM25,%ZMM6 |
0x427c7b VMOVUPD %ZMM6,(%R9,%RCX,1) [7] |
0x427c82 VMOVUPD %ZMM1,(%R8,%RCX,1) [8] |
0x427c89 VMOVUPD 0x40(%R9,%RCX,1),%ZMM4 [7] |
0x427c91 VMULPD 0x40(%RDI,%RCX,1),%ZMM4,%ZMM1 [2] |
0x427c99 VMOVUPD 0x40(%RBX,%RCX,1),%ZMM8 [10] |
0x427ca1 VADDPD 0x40(%RDI,%RCX,1),%ZMM8,%ZMM11 [2] |
0x427ca9 VMOVUPD 0x40(%RAX,%RCX,1),%ZMM5 [5] |
0x427cb1 VSUBPD 0x40(%R13,%RCX,1),%ZMM5,%ZMM29 [6] |
0x427cb9 VSUBPD 0x40(%RSI,%RCX,1),%ZMM1,%ZMM27 [4] |
0x427cc1 VSUBPD 0x40(%R15,%RCX,1),%ZMM11,%ZMM9 [1] |
0x427cc9 VFMADD132PD 0x40(%R8,%RCX,1),%ZMM29,%ZMM1 [8] |
0x427cd1 VADDPD 0x40(%RDX,%RCX,1),%ZMM27,%ZMM28 [9] |
0x427cd9 VDIVPD %ZMM9,%ZMM28,%ZMM10 |
0x427cdf VDIVPD %ZMM28,%ZMM1,%ZMM3 |
0x427ce5 VMOVUPD %ZMM10,0x40(%R9,%RCX,1) [7] |
0x427ced VMOVUPD %ZMM3,0x40(%R8,%RCX,1) [8] |
0x427cf5 SUB $-0x80,%RCX |
0x427cf9 CMP %RCX,0x40(%RSP) [3] |
0x427cfe JNE 427c28 |
/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp: 120 - 125 |
-------------------------------------------------------------------------------- |
120: double pre_mass_s = density1(i, j) * pre_vol(i, j); |
121: double post_mass_s = pre_mass_s + mass_flux_x(i, j) - mass_flux_x(i + 1, j + 0); |
122: double post_ener_s = (energy1(i, j) * pre_mass_s + ener_flux(i, j) - ener_flux(i + 1, j + 0)) / post_mass_s; |
123: double advec_vol_s = pre_vol(i, j) + vol_flux_x(i, j) - vol_flux_x(i + 1, j + 0); |
124: density1(i, j) = post_mass_s / advec_vol_s; |
125: energy1(i, j) = post_ener_s; |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 1.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 2.40 |
Bottlenecks | P8, P9, |
Function | _Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3 |
Source | advec_cell.cpp:120-125 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 36.00 |
CQA cycles if no scalar integer | 36.00 |
CQA cycles if FP arith vectorized | 36.00 |
CQA cycles if fully vectorized | 36.00 |
Front-end cycles | 5.67 |
DIV/SQRT cycles | 0.50 |
P0 cycles | 0.50 |
P1 cycles | 0.25 |
P2 cycles | 0.25 |
P3 cycles | 0.50 |
P4 cycles | 15.00 |
P5 cycles | 15.00 |
P6 cycles | 15.00 |
P7 cycles | 8.00 |
P8 cycles | 8.00 |
P9 cycles | 10.00 |
P10 cycles | 10.00 |
P11 cycles | 4.00 |
P12 cycles | 4.00 |
P13 cycles | 36.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 31.00 |
Nb uops | 34.00 |
Nb loads | 21.00 |
Nb stores | 4.00 |
Nb stack references | 1.00 |
FLOP/cycle | 4.44 |
Nb FLOP add-sub | 80.00 |
Nb FLOP mul | 16.00 |
Nb FLOP fma | 16.00 |
Nb FLOP div | 32.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 42.89 |
Bytes prefetched | 0.00 |
Bytes loaded | 1288.00 |
Bytes stored | 256.00 |
Stride 0 | 1.00 |
Stride 1 | 8.00 |
Stride n | 1.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 100.00 |
Vectorization ratio load | 100.00 |
Vectorization ratio store | 100.00 |
Vectorization ratio mul | 100.00 |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | 100.00 |
Vectorization ratio div_sqrt | 100.00 |
Vectorization ratio other | NA |
Vector-efficiency ratio all | 100.00 |
Vector-efficiency ratio load | 100.00 |
Vector-efficiency ratio store | 100.00 |
Vector-efficiency ratio mul | 100.00 |
Vector-efficiency ratio add_sub | 100.00 |
Vector-efficiency ratio fma | 100.00 |
Vector-efficiency ratio div_sqrt | 100.00 |
Vector-efficiency ratio other | NA |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 1.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 2.40 |
Bottlenecks | P8, P9, |
Function | _Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3 |
Source | advec_cell.cpp:120-125 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 36.00 |
CQA cycles if no scalar integer | 36.00 |
CQA cycles if FP arith vectorized | 36.00 |
CQA cycles if fully vectorized | 36.00 |
Front-end cycles | 5.67 |
DIV/SQRT cycles | 0.50 |
P0 cycles | 0.50 |
P1 cycles | 0.25 |
P2 cycles | 0.25 |
P3 cycles | 0.50 |
P4 cycles | 15.00 |
P5 cycles | 15.00 |
P6 cycles | 15.00 |
P7 cycles | 8.00 |
P8 cycles | 8.00 |
P9 cycles | 10.00 |
P10 cycles | 10.00 |
P11 cycles | 4.00 |
P12 cycles | 4.00 |
P13 cycles | 36.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 31.00 |
Nb uops | 34.00 |
Nb loads | 21.00 |
Nb stores | 4.00 |
Nb stack references | 1.00 |
FLOP/cycle | 4.44 |
Nb FLOP add-sub | 80.00 |
Nb FLOP mul | 16.00 |
Nb FLOP fma | 16.00 |
Nb FLOP div | 32.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 42.89 |
Bytes prefetched | 0.00 |
Bytes loaded | 1288.00 |
Bytes stored | 256.00 |
Stride 0 | 1.00 |
Stride 1 | 8.00 |
Stride n | 1.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 100.00 |
Vectorization ratio load | 100.00 |
Vectorization ratio store | 100.00 |
Vectorization ratio mul | 100.00 |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | 100.00 |
Vectorization ratio div_sqrt | 100.00 |
Vectorization ratio other | NA |
Vector-efficiency ratio all | 100.00 |
Vector-efficiency ratio load | 100.00 |
Vector-efficiency ratio store | 100.00 |
Vector-efficiency ratio mul | 100.00 |
Vector-efficiency ratio add_sub | 100.00 |
Vector-efficiency ratio fma | 100.00 |
Vector-efficiency ratio div_sqrt | 100.00 |
Vector-efficiency ratio other | NA |
Path / |
Function | _Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3 |
Source file and lines | advec_cell.cpp:120-125 |
Module | exec |
nb instructions | 31 |
nb uops | 34 |
loop length | 220 |
used x86 registers | 11 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 18 |
nb stack references | 1 |
ADD-SUB / MUL ratio | 5.00 |
micro-operation queue | 5.67 cycles |
front end | 5.67 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 0.50 | 0.50 | 0.25 | 0.25 | 0.50 | 8.33 | 8.33 | 8.33 | 4.00 | 4.00 | 5.00 | 5.00 | 4.00 | 4.00 |
cycles | 0.50 | 0.50 | 0.25 | 0.25 | 0.50 | 15.00 | 15.00 | 15.00 | 8.00 | 8.00 | 10.00 | 10.00 | 4.00 | 4.00 |
Cycles executing div or sqrt instructions | 36.00 |
Longest recurrence chain latency (RecMII) | 1.00 |
Front-end | 5.67 |
Dispatch | 15.00 |
DIV/SQRT | 36.00 |
Data deps. | 1.00 |
Overall L1 | 36.00 |
all | 100% |
load | 100% |
store | 100% |
mul | 100% |
add-sub | 100% |
fma | 100% |
div/sqrt | 100% |
other | NA (no other vectorizable/vectorized instructions) |
all | 100% |
load | 100% |
store | 100% |
mul | 100% |
add-sub | 100% |
fma | 100% |
div/sqrt | 100% |
other | NA (no other vectorizable/vectorized instructions) |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VMOVUPD (%R9,%RCX,1),%ZMM9 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMULPD (%RDI,%RCX,1),%ZMM9,%ZMM10 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVUPD (%RBX,%RCX,1),%ZMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VADDPD (%RDI,%RCX,1),%ZMM2,%ZMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMOVUPD (%RAX,%RCX,1),%ZMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VSUBPD (%R13,%RCX,1),%ZMM3,%ZMM26 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VSUBPD (%RSI,%RCX,1),%ZMM10,%ZMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VSUBPD (%R15,%RCX,1),%ZMM7,%ZMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VFMADD231PD (%R8,%RCX,1),%ZMM10,%ZMM26 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 1 |
VADDPD (%RDX,%RCX,1),%ZMM24,%ZMM25 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VDIVPD %ZMM25,%ZMM26,%ZMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13 | 9 |
VDIVPD %ZMM0,%ZMM25,%ZMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13 | 9 |
VMOVUPD %ZMM6,(%R9,%RCX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VMOVUPD %ZMM1,(%R8,%RCX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VMOVUPD 0x40(%R9,%RCX,1),%ZMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMULPD 0x40(%RDI,%RCX,1),%ZMM4,%ZMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVUPD 0x40(%RBX,%RCX,1),%ZMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VADDPD 0x40(%RDI,%RCX,1),%ZMM8,%ZMM11 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMOVUPD 0x40(%RAX,%RCX,1),%ZMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VSUBPD 0x40(%R13,%RCX,1),%ZMM5,%ZMM29 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VSUBPD 0x40(%RSI,%RCX,1),%ZMM1,%ZMM27 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VSUBPD 0x40(%R15,%RCX,1),%ZMM11,%ZMM9 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VFMADD132PD 0x40(%R8,%RCX,1),%ZMM29,%ZMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 1 |
VADDPD 0x40(%RDX,%RCX,1),%ZMM27,%ZMM28 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VDIVPD %ZMM9,%ZMM28,%ZMM10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13 | 9 |
VDIVPD %ZMM28,%ZMM1,%ZMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13 | 9 |
VMOVUPD %ZMM10,0x40(%R9,%RCX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VMOVUPD %ZMM3,0x40(%R8,%RCX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
SUB $-0x80,%RCX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP %RCX,0x40(%RSP) | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
JNE 427c28 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x2c8> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
Function | _Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3 |
Source file and lines | advec_cell.cpp:120-125 |
Module | exec |
nb instructions | 31 |
nb uops | 34 |
loop length | 220 |
used x86 registers | 11 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 18 |
nb stack references | 1 |
ADD-SUB / MUL ratio | 5.00 |
micro-operation queue | 5.67 cycles |
front end | 5.67 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 0.50 | 0.50 | 0.25 | 0.25 | 0.50 | 8.33 | 8.33 | 8.33 | 4.00 | 4.00 | 5.00 | 5.00 | 4.00 | 4.00 |
cycles | 0.50 | 0.50 | 0.25 | 0.25 | 0.50 | 15.00 | 15.00 | 15.00 | 8.00 | 8.00 | 10.00 | 10.00 | 4.00 | 4.00 |
Cycles executing div or sqrt instructions | 36.00 |
Longest recurrence chain latency (RecMII) | 1.00 |
Front-end | 5.67 |
Dispatch | 15.00 |
DIV/SQRT | 36.00 |
Data deps. | 1.00 |
Overall L1 | 36.00 |
all | 100% |
load | 100% |
store | 100% |
mul | 100% |
add-sub | 100% |
fma | 100% |
div/sqrt | 100% |
other | NA (no other vectorizable/vectorized instructions) |
all | 100% |
load | 100% |
store | 100% |
mul | 100% |
add-sub | 100% |
fma | 100% |
div/sqrt | 100% |
other | NA (no other vectorizable/vectorized instructions) |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VMOVUPD (%R9,%RCX,1),%ZMM9 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMULPD (%RDI,%RCX,1),%ZMM9,%ZMM10 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVUPD (%RBX,%RCX,1),%ZMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VADDPD (%RDI,%RCX,1),%ZMM2,%ZMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMOVUPD (%RAX,%RCX,1),%ZMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VSUBPD (%R13,%RCX,1),%ZMM3,%ZMM26 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VSUBPD (%RSI,%RCX,1),%ZMM10,%ZMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VSUBPD (%R15,%RCX,1),%ZMM7,%ZMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VFMADD231PD (%R8,%RCX,1),%ZMM10,%ZMM26 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 1 |
VADDPD (%RDX,%RCX,1),%ZMM24,%ZMM25 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VDIVPD %ZMM25,%ZMM26,%ZMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13 | 9 |
VDIVPD %ZMM0,%ZMM25,%ZMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13 | 9 |
VMOVUPD %ZMM6,(%R9,%RCX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VMOVUPD %ZMM1,(%R8,%RCX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VMOVUPD 0x40(%R9,%RCX,1),%ZMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMULPD 0x40(%RDI,%RCX,1),%ZMM4,%ZMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVUPD 0x40(%RBX,%RCX,1),%ZMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VADDPD 0x40(%RDI,%RCX,1),%ZMM8,%ZMM11 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VMOVUPD 0x40(%RAX,%RCX,1),%ZMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VSUBPD 0x40(%R13,%RCX,1),%ZMM5,%ZMM29 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VSUBPD 0x40(%RSI,%RCX,1),%ZMM1,%ZMM27 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VSUBPD 0x40(%R15,%RCX,1),%ZMM11,%ZMM9 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VFMADD132PD 0x40(%R8,%RCX,1),%ZMM29,%ZMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 1 |
VADDPD 0x40(%RDX,%RCX,1),%ZMM27,%ZMM28 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 1 |
VDIVPD %ZMM9,%ZMM28,%ZMM10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13 | 9 |
VDIVPD %ZMM28,%ZMM1,%ZMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13 | 9 |
VMOVUPD %ZMM10,0x40(%R9,%RCX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VMOVUPD %ZMM3,0x40(%R8,%RCX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
SUB $-0x80,%RCX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP %RCX,0x40(%RSP) | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
JNE 427c28 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x2c8> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |