Function: _Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buf ... | Module: exec | Source: advec_mom.cpp:146-149 [...] | Coverage: 4.2% |
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Function: _Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buf ... | Module: exec | Source: advec_mom.cpp:146-149 [...] | Coverage: 4.2% |
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/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp: 146 - 149 |
-------------------------------------------------------------------------------- |
146: #pragma omp parallel for simd collapse(2) |
147: for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) { |
148: for (int i = (x_min + 1); i < (x_max + 1 + 2); i++) { |
149: vel1(i, j) = (vel1(i, j) * node_mass_pre(i, j) + mom_flux(i - 1, j + 0) - mom_flux(i, j)) / node_mass_post(i, j); |
/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69 |
-------------------------------------------------------------------------------- |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
0x42ee80 PUSH %RBP |
0x42ee81 MOV %RSP,%RBP |
0x42ee84 PUSH %R15 |
0x42ee86 PUSH %R14 |
0x42ee88 PUSH %R13 |
0x42ee8a PUSH %R12 |
0x42ee8c PUSH %RBX |
0x42ee8d MOV %RDI,%R15 |
0x42ee90 AND $-0x40,%RSP |
0x42ee94 SUB $0x40,%RSP |
0x42ee98 MOV 0x28(%RDI),%EAX |
0x42ee9b MOV 0x2c(%RDI),%EDX |
0x42ee9e MOV 0x20(%RDI),%ESI |
0x42eea1 MOV 0x24(%RDI),%EDI |
0x42eea4 ADD $0x3,%EDX |
0x42eea7 INC %ESI |
0x42eea9 LEA 0x1(%RAX),%R12D |
0x42eead MOV %EDX,0x18(%RSP) |
0x42eeb1 MOV %ESI,0x14(%RSP) |
0x42eeb5 CMP %EDX,%R12D |
0x42eeb8 JGE 42f363 |
0x42eebe MOV %EDX,%R14D |
0x42eec1 LEA 0x3(%RDI),%R13D |
0x42eec5 SUB %R12D,%R14D |
0x42eec8 CMP %R13D,%ESI |
0x42eecb JGE 42f363 |
0x42eed1 MOV %R13D,%ECX |
0x42eed4 SUB %ESI,%ECX |
0x42eed6 MOV %ECX,0x1c(%RSP) |
0x42eeda CALL 404650 <omp_get_num_threads@plt> |
0x42eedf MOV %EAX,%EBX |
0x42eee1 CALL 404540 <omp_get_thread_num@plt> |
0x42eee6 MOV 0x1c(%RSP),%R8D |
0x42eeeb XOR %EDX,%EDX |
0x42eeed MOV %EAX,%ESI |
0x42eeef IMUL %R8D,%R14D |
0x42eef3 MOV %R14D,%EAX |
0x42eef6 DIV %EBX |
0x42eef8 MOV %EAX,%R9D |
0x42eefb CMP %EDX,%ESI |
0x42eefd JB 42f38b |
0x42ef03 IMUL %R9D,%ESI |
0x42ef07 ADD %EDX,%ESI |
0x42ef09 LEA (%R9,%RSI,1),%R10D |
0x42ef0d MOV %R10D,0x10(%RSP) |
0x42ef12 CMP %R10D,%ESI |
0x42ef15 JAE 42f363 |
0x42ef1b MOV %ESI,%EAX |
0x42ef1d XOR %EDX,%EDX |
0x42ef1f MOV 0x14(%RSP),%R11D |
0x42ef24 VMOVQ (%R15),%XMM3 |
0x42ef29 DIVL 0x1c(%RSP) |
0x42ef2d VMOVQ 0x10(%R15),%XMM11 |
0x42ef33 VMOVQ 0x18(%R15),%XMM10 |
0x42ef39 MOV %R9D,%ECX |
0x42ef3c VMOVQ 0x8(%R15),%XMM1 |
0x42ef42 ADD %EDX,%R11D |
0x42ef45 LEA (%RAX,%R12,1),%R12D |
0x42ef49 SUB %R11D,%R13D |
0x42ef4c MOVSXD %R12D,%R8 |
0x42ef4f MOV %R11D,0x3c(%RSP) |
0x42ef54 NOPW %CS:(%RAX,%RAX,1) |
0x42ef5f NOP |
(189) 0x42ef60 CMP %R13D,%ECX |
(189) 0x42ef63 CMOVA %R13D,%ECX |
(189) 0x42ef67 LEA (%RSI,%RCX,1),%R13D |
(189) 0x42ef6b MOV %R13D,0x38(%RSP) |
(189) 0x42ef70 CMP %R13D,%ESI |
(189) 0x42ef73 JAE 42f336 |
(189) 0x42ef79 VMOVQ %XMM3,%R15 |
(189) 0x42ef7e VMOVQ %XMM11,%R14 |
(189) 0x42ef83 LEA -0x1(%RCX),%EAX |
(189) 0x42ef86 VMOVQ %XMM1,%R10 |
(189) 0x42ef8b MOV (%R15),%RDI |
(189) 0x42ef8e MOV (%R14),%RBX |
(189) 0x42ef91 VMOVQ %XMM10,%R9 |
(189) 0x42ef96 MOV (%R10),%R11 |
(189) 0x42ef99 MOV 0x10(%R9),%R12 |
(189) 0x42ef9d MOV (%R9),%R9 |
(189) 0x42efa0 VMOVQ 0x10(%R15),%XMM5 |
(189) 0x42efa6 VMOVQ 0x10(%R14),%XMM4 |
(189) 0x42efac MOV 0x10(%R10),%R15 |
(189) 0x42efb0 IMUL %R8,%RDI |
(189) 0x42efb4 IMUL %R8,%RBX |
(189) 0x42efb8 IMUL %R8,%R11 |
(189) 0x42efbc IMUL %R8,%R9 |
(189) 0x42efc0 MOV %RDI,0x20(%RSP) |
(189) 0x42efc5 MOV %RBX,0x28(%RSP) |
(189) 0x42efca MOV %R11,0x30(%RSP) |
(189) 0x42efcf CMP $0x6,%EAX |
(189) 0x42efd2 JBE 42f380 |
(189) 0x42efd8 MOVSXD 0x3c(%RSP),%R13 |
(189) 0x42efdd VMOVQ %XMM5,%R10 |
(189) 0x42efe2 LEA (%RDI,%R13,1),%R14 |
(189) 0x42efe6 LEA (%RBX,%R13,1),%RAX |
(189) 0x42efea LEA (%R9,%R13,1),%RDI |
(189) 0x42efee ADD %R11,%R13 |
(189) 0x42eff1 LEA (%R10,%R14,8),%RDX |
(189) 0x42eff5 MOV %ECX,%R14D |
(189) 0x42eff8 LEA (%R15,%R13,8),%R11 |
(189) 0x42effc VMOVQ %XMM4,%RBX |
(189) 0x42f001 SHR $0x3,%R14D |
(189) 0x42f005 SAL $0x6,%R14 |
(189) 0x42f009 LEA -0x40(%R14),%R13 |
(189) 0x42f00d LEA (%RBX,%RAX,8),%RBX |
(189) 0x42f011 XOR %EAX,%EAX |
(189) 0x42f013 SHR $0x6,%R13 |
(189) 0x42f017 SAL $0x3,%RDI |
(189) 0x42f01b INC %R13 |
(189) 0x42f01e LEA -0x8(%R12,%RDI,1),%R10 |
(189) 0x42f023 ADD %R12,%RDI |
(189) 0x42f026 AND $0x3,%R13D |
(189) 0x42f02a JE 42f0ca |
(189) 0x42f030 CMP $0x1,%R13 |
(189) 0x42f034 JE 42f093 |
(189) 0x42f036 CMP $0x2,%R13 |
(189) 0x42f03a JE 42f065 |
(189) 0x42f03c VMOVUPD (%RDX),%ZMM2 |
(189) 0x42f042 VMOVUPD (%RDI),%ZMM7 |
(189) 0x42f048 VFMSUB132PD (%RBX),%ZMM7,%ZMM2 |
(189) 0x42f04e VADDPD (%R10),%ZMM2,%ZMM0 |
(189) 0x42f054 MOV $0x40,%EAX |
(189) 0x42f059 VDIVPD (%R11),%ZMM0,%ZMM6 |
(189) 0x42f05f VMOVUPD %ZMM6,(%RDX) |
(189) 0x42f065 VMOVUPD (%RDX,%RAX,1),%ZMM8 |
(189) 0x42f06c VMOVUPD (%RDI,%RAX,1),%ZMM9 |
(189) 0x42f073 VFMSUB132PD (%RBX,%RAX,1),%ZMM9,%ZMM8 |
(189) 0x42f07a VADDPD (%R10,%RAX,1),%ZMM8,%ZMM12 |
(189) 0x42f081 VDIVPD (%R11,%RAX,1),%ZMM12,%ZMM13 |
(189) 0x42f088 VMOVUPD %ZMM13,(%RDX,%RAX,1) |
(189) 0x42f08f ADD $0x40,%RAX |
(189) 0x42f093 VMOVUPD (%RDX,%RAX,1),%ZMM14 |
(189) 0x42f09a VMOVUPD (%RDI,%RAX,1),%ZMM15 |
(189) 0x42f0a1 VFMSUB132PD (%RBX,%RAX,1),%ZMM15,%ZMM14 |
(189) 0x42f0a8 VADDPD (%R10,%RAX,1),%ZMM14,%ZMM2 |
(189) 0x42f0af VDIVPD (%R11,%RAX,1),%ZMM2,%ZMM7 |
(189) 0x42f0b6 VMOVUPD %ZMM7,(%RDX,%RAX,1) |
(189) 0x42f0bd ADD $0x40,%RAX |
(189) 0x42f0c1 CMP %RAX,%R14 |
(189) 0x42f0c4 JE 42f193 |
(190) 0x42f0ca VMOVUPD (%RDI,%RAX,1),%ZMM6 |
(190) 0x42f0d1 VMOVUPD (%RDX,%RAX,1),%ZMM0 |
(190) 0x42f0d8 VFMSUB132PD (%RBX,%RAX,1),%ZMM6,%ZMM0 |
(190) 0x42f0df VADDPD (%R10,%RAX,1),%ZMM0,%ZMM8 |
(190) 0x42f0e6 VMOVUPD 0x40(%RDX,%RAX,1),%ZMM12 |
(190) 0x42f0ee VMOVUPD 0x80(%RDX,%RAX,1),%ZMM2 |
(190) 0x42f0f6 VDIVPD (%R11,%RAX,1),%ZMM8,%ZMM9 |
(190) 0x42f0fd VMOVUPD 0xc0(%RDX,%RAX,1),%ZMM8 |
(190) 0x42f105 VMOVUPD %ZMM9,(%RDX,%RAX,1) |
(190) 0x42f10c VMOVUPD 0x40(%RDI,%RAX,1),%ZMM13 |
(190) 0x42f114 VFMSUB132PD 0x40(%RBX,%RAX,1),%ZMM13,%ZMM12 |
(190) 0x42f11c VADDPD 0x40(%R10,%RAX,1),%ZMM12,%ZMM14 |
(190) 0x42f124 VDIVPD 0x40(%R11,%RAX,1),%ZMM14,%ZMM15 |
(190) 0x42f12c VMOVUPD %ZMM15,0x40(%RDX,%RAX,1) |
(190) 0x42f134 VMOVUPD 0x80(%RDI,%RAX,1),%ZMM7 |
(190) 0x42f13c VFMSUB132PD 0x80(%RBX,%RAX,1),%ZMM7,%ZMM2 |
(190) 0x42f144 VADDPD 0x80(%R10,%RAX,1),%ZMM2,%ZMM0 |
(190) 0x42f14c VDIVPD 0x80(%R11,%RAX,1),%ZMM0,%ZMM6 |
(190) 0x42f154 VMOVUPD %ZMM6,0x80(%RDX,%RAX,1) |
(190) 0x42f15c VMOVUPD 0xc0(%RDI,%RAX,1),%ZMM9 |
(190) 0x42f164 VFMSUB132PD 0xc0(%RBX,%RAX,1),%ZMM9,%ZMM8 |
(190) 0x42f16c VADDPD 0xc0(%R10,%RAX,1),%ZMM8,%ZMM12 |
(190) 0x42f174 VDIVPD 0xc0(%R11,%RAX,1),%ZMM12,%ZMM13 |
(190) 0x42f17c VMOVUPD %ZMM13,0xc0(%RDX,%RAX,1) |
(190) 0x42f184 ADD $0x100,%RAX |
(190) 0x42f18a CMP %RAX,%R14 |
(190) 0x42f18d JNE 42f0ca |
(189) 0x42f193 MOV 0x3c(%RSP),%EBX |
(189) 0x42f197 MOV %ECX,%EDX |
(189) 0x42f199 AND $-0x8,%EDX |
(189) 0x42f19c ADD %EDX,%ESI |
(189) 0x42f19e LEA (%RDX,%RBX,1),%EDI |
(189) 0x42f1a1 TEST $0x7,%CL |
(189) 0x42f1a4 JE 42f332 |
(189) 0x42f1aa SUB %EDX,%ECX |
(189) 0x42f1ac LEA -0x1(%RCX),%R10D |
(189) 0x42f1b0 CMP $0x2,%R10D |
(189) 0x42f1b4 JBE 42f228 |
(189) 0x42f1b6 MOVSXD 0x3c(%RSP),%R11 |
(189) 0x42f1bb MOV 0x20(%RSP),%R14 |
(189) 0x42f1c0 MOV %EDX,%EDX |
(189) 0x42f1c2 VMOVQ %XMM5,%RAX |
(189) 0x42f1c7 MOV 0x30(%RSP),%RBX |
(189) 0x42f1cc LEA (%R14,%R11,1),%R13 |
(189) 0x42f1d0 ADD %RDX,%R13 |
(189) 0x42f1d3 LEA (%RBX,%R11,1),%R14 |
(189) 0x42f1d7 LEA (%RAX,%R13,8),%R10 |
(189) 0x42f1db MOV 0x28(%RSP),%RAX |
(189) 0x42f1e0 LEA (%R9,%R11,1),%R13 |
(189) 0x42f1e4 ADD %RDX,%R14 |
(189) 0x42f1e7 ADD %RDX,%R13 |
(189) 0x42f1ea VMOVUPD (%R10),%YMM14 |
(189) 0x42f1ef VMOVUPD -0x8(%R12,%R13,8),%YMM15 |
(189) 0x42f1f6 ADD %RAX,%R11 |
(189) 0x42f1f9 ADD %RDX,%R11 |
(189) 0x42f1fc VMOVQ %XMM4,%RDX |
(189) 0x42f201 VFMADD132PD (%RDX,%R11,8),%YMM15,%YMM14 |
(189) 0x42f207 VSUBPD (%R12,%R13,8),%YMM14,%YMM2 |
(189) 0x42f20d VDIVPD (%R15,%R14,8),%YMM2,%YMM7 |
(189) 0x42f213 VMOVUPD %YMM7,(%R10) |
(189) 0x42f218 TEST $0x3,%CL |
(189) 0x42f21b JE 42f332 |
(189) 0x42f221 AND $-0x4,%ECX |
(189) 0x42f224 ADD %ECX,%ESI |
(189) 0x42f226 ADD %ECX,%EDI |
(189) 0x42f228 MOV 0x20(%RSP),%RBX |
(189) 0x42f22d MOV 0x28(%RSP),%R10 |
(189) 0x42f232 MOVSXD %EDI,%R14 |
(189) 0x42f235 VMOVQ %XMM5,%RCX |
(189) 0x42f23a LEA -0x1(%RDI),%EDX |
(189) 0x42f23d LEA (%RBX,%R14,1),%R11 |
(189) 0x42f241 LEA (%R10,%R14,1),%R13 |
(189) 0x42f245 LEA (%RCX,%R11,8),%RAX |
(189) 0x42f249 VMOVQ %XMM4,%R11 |
(189) 0x42f24e MOVSXD %EDX,%RCX |
(189) 0x42f251 MOV 0x38(%RSP),%EDX |
(189) 0x42f255 VMOVSD (%R11,%R13,8),%XMM0 |
(189) 0x42f25b MOV 0x30(%RSP),%R11 |
(189) 0x42f260 LEA (%R9,%R14,1),%R13 |
(189) 0x42f264 ADD %R9,%RCX |
(189) 0x42f267 LEA (%R12,%R13,8),%R13 |
(189) 0x42f26b VMOVSD (%R12,%RCX,8),%XMM6 |
(189) 0x42f271 VFMADD132SD (%RAX),%XMM6,%XMM0 |
(189) 0x42f276 VSUBSD (%R13),%XMM0,%XMM8 |
(189) 0x42f27c ADD %R11,%R14 |
(189) 0x42f27f VDIVSD (%R15,%R14,8),%XMM8,%XMM9 |
(189) 0x42f285 LEA 0x1(%RSI),%R14D |
(189) 0x42f289 VMOVSD %XMM9,(%RAX) |
(189) 0x42f28d LEA 0x1(%RDI),%EAX |
(189) 0x42f290 CMP %EDX,%R14D |
(189) 0x42f293 JAE 42f332 |
(189) 0x42f299 CLTQ |
(189) 0x42f29b VMOVQ %XMM5,%R14 |
(189) 0x42f2a0 ADD $0x2,%ESI |
(189) 0x42f2a3 ADD $0x2,%EDI |
(189) 0x42f2a6 LEA (%RBX,%RAX,1),%RCX |
(189) 0x42f2aa LEA (%R14,%RCX,8),%RDX |
(189) 0x42f2ae LEA (%R10,%RAX,1),%R14 |
(189) 0x42f2b2 LEA (%R9,%RAX,1),%RCX |
(189) 0x42f2b6 ADD %R11,%RAX |
(189) 0x42f2b9 VMOVQ %RDX,%XMM12 |
(189) 0x42f2be VMOVQ %XMM4,%RDX |
(189) 0x42f2c3 LEA (%R12,%RCX,8),%RCX |
(189) 0x42f2c7 VMOVSD (%RDX,%R14,8),%XMM13 |
(189) 0x42f2cd VMOVQ %XMM12,%R14 |
(189) 0x42f2d2 VMOVSD (%RCX),%XMM14 |
(189) 0x42f2d6 VFMSUB132SD (%R14),%XMM14,%XMM13 |
(189) 0x42f2db VADDSD (%R13),%XMM13,%XMM15 |
(189) 0x42f2e1 VDIVSD (%R15,%RAX,8),%XMM15,%XMM2 |
(189) 0x42f2e7 MOV 0x38(%RSP),%EAX |
(189) 0x42f2eb MOV %R11,%R13 |
(189) 0x42f2ee VMOVSD %XMM2,(%R14) |
(189) 0x42f2f3 CMP %EAX,%ESI |
(189) 0x42f2f5 JAE 42f332 |
(189) 0x42f2f7 MOVSXD %EDI,%RDI |
(189) 0x42f2fa VMOVQ %XMM5,%RSI |
(189) 0x42f2ff VMOVQ %XMM4,%R14 |
(189) 0x42f304 ADD %RDI,%RBX |
(189) 0x42f307 ADD %RDI,%R10 |
(189) 0x42f30a ADD %RDI,%R9 |
(189) 0x42f30d ADD %RDI,%R13 |
(189) 0x42f310 LEA (%RSI,%RBX,8),%RDX |
(189) 0x42f314 VMOVSD (%R12,%R9,8),%XMM4 |
(189) 0x42f31a VMOVSD (%RDX),%XMM5 |
(189) 0x42f31e VFMSUB132SD (%R14,%R10,8),%XMM4,%XMM5 |
(189) 0x42f324 VADDSD (%RCX),%XMM5,%XMM7 |
(189) 0x42f328 VDIVSD (%R15,%R13,8),%XMM7,%XMM0 |
(189) 0x42f32e VMOVSD %XMM0,(%RDX) |
(189) 0x42f332 MOV 0x38(%RSP),%ESI |
(189) 0x42f336 INC %R8 |
(189) 0x42f339 LEA (%R8),%R12D |
(189) 0x42f33c CMP %R12D,0x18(%RSP) |
(189) 0x42f341 JLE 42f360 |
(189) 0x42f343 MOV 0x10(%RSP),%ECX |
(189) 0x42f347 MOV 0x14(%RSP),%R9D |
(189) 0x42f34c MOV 0x1c(%RSP),%R13D |
(189) 0x42f351 SUB %ESI,%ECX |
(189) 0x42f353 MOV %R9D,0x3c(%RSP) |
(189) 0x42f358 JMP 42ef60 |
0x42f35d NOPL (%RAX) |
0x42f360 VZEROUPPER |
0x42f363 LEA -0x28(%RBP),%RSP |
0x42f367 POP %RBX |
0x42f368 POP %R12 |
0x42f36a POP %R13 |
0x42f36c POP %R14 |
0x42f36e POP %R15 |
0x42f370 POP %RBP |
0x42f371 RET |
0x42f372 NOPW %CS:(%RAX,%RAX,1) |
0x42f37d NOPL (%RAX) |
(189) 0x42f380 MOV 0x3c(%RSP),%EDI |
(189) 0x42f384 XOR %EDX,%EDX |
(189) 0x42f386 JMP 42f1aa |
0x42f38b INC %R9D |
0x42f38e XOR %EDX,%EDX |
0x42f390 JMP 42ef03 |
0x42f395 NOPW %CS:(%RAX,%RAX,1) |
Path / |
Source file and lines | advec_mom.cpp:146-149 |
Module | exec |
nb instructions | 79 |
nb uops | 78 |
loop length | 280 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 4 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 6 |
micro-operation queue | 13.00 cycles |
front end | 13.00 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 7.00 | 7.00 | 7.00 | 7.00 | 6.00 | 6.00 | 6.00 | 6.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 |
cycles | 7.00 | 7.00 | 7.00 | 7.00 | 6.00 | 6.00 | 6.00 | 6.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 |
Cycles executing div or sqrt instructions | 12.00 |
Front-end | 13.00 |
Dispatch | 7.00 |
DIV/SQRT | 12.00 |
Overall L1 | 13.00 |
all | 3% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 7% |
all | 7% |
load | 9% |
store | 6% |
mul | 6% |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 8% |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %RDI,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
AND $-0x40,%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB $0x40,%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV 0x28(%RDI),%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x2c(%RDI),%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x20(%RDI),%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x24(%RDI),%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
ADD $0x3,%EDX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
INC %ESI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LEA 0x1(%RAX),%R12D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %EDX,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV %ESI,0x14(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
CMP %EDX,%R12D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JGE 42f363 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x4e3> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV %EDX,%R14D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x3(%RDI),%R13D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB %R12D,%R14D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP %R13D,%ESI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JGE 42f363 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x4e3> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV %R13D,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SUB %ESI,%ECX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %ECX,0x1c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
CALL 404650 <omp_get_num_threads@plt> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EAX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CALL 404540 <omp_get_thread_num@plt> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x1c(%RSP),%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV %EAX,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
IMUL %R8D,%R14D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %R14D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
DIV %EBX | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 10-17 | 6 |
MOV %EAX,%R9D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP %EDX,%ESI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JB 42f38b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x50b> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
IMUL %R9D,%ESI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %EDX,%ESI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LEA (%R9,%RSI,1),%R10D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %R10D,0x10(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
CMP %R10D,%ESI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JAE 42f363 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x4e3> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV %ESI,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV 0x14(%RSP),%R11D | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
VMOVQ (%R15),%XMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
DIVL 0x1c(%RSP) | 3 | 2 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 10-17 | 6 |
VMOVQ 0x10(%R15),%XMM11 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVQ 0x18(%R15),%XMM10 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %R9D,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVQ 0x8(%R15),%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R11D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LEA (%RAX,%R12,1),%R12D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB %R11D,%R13D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOVSXD %R12D,%R8 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %R11D,0x3c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
NOPW %CS:(%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
NOP | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
NOPL (%RAX) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
VZEROUPPER | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
POP %RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
RET | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
NOPW %CS:(%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
NOPL (%RAX) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
INC %R9D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
JMP 42ef03 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x83> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
NOPW %CS:(%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
Source file and lines | advec_mom.cpp:146-149 |
Module | exec |
nb instructions | 79 |
nb uops | 78 |
loop length | 280 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 4 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 6 |
micro-operation queue | 13.00 cycles |
front end | 13.00 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 7.00 | 7.00 | 7.00 | 7.00 | 6.00 | 6.00 | 6.00 | 6.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 |
cycles | 7.00 | 7.00 | 7.00 | 7.00 | 6.00 | 6.00 | 6.00 | 6.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 |
Cycles executing div or sqrt instructions | 12.00 |
Front-end | 13.00 |
Dispatch | 7.00 |
DIV/SQRT | 12.00 |
Overall L1 | 13.00 |
all | 3% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 7% |
all | 7% |
load | 9% |
store | 6% |
mul | 6% |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 8% |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %RDI,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
AND $-0x40,%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB $0x40,%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV 0x28(%RDI),%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x2c(%RDI),%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x20(%RDI),%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x24(%RDI),%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
ADD $0x3,%EDX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
INC %ESI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LEA 0x1(%RAX),%R12D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %EDX,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV %ESI,0x14(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
CMP %EDX,%R12D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JGE 42f363 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x4e3> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV %EDX,%R14D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x3(%RDI),%R13D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB %R12D,%R14D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP %R13D,%ESI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JGE 42f363 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x4e3> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV %R13D,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SUB %ESI,%ECX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %ECX,0x1c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
CALL 404650 <omp_get_num_threads@plt> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EAX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CALL 404540 <omp_get_thread_num@plt> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x1c(%RSP),%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV %EAX,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
IMUL %R8D,%R14D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %R14D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
DIV %EBX | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 10-17 | 6 |
MOV %EAX,%R9D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP %EDX,%ESI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JB 42f38b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x50b> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
IMUL %R9D,%ESI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %EDX,%ESI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LEA (%R9,%RSI,1),%R10D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %R10D,0x10(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
CMP %R10D,%ESI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JAE 42f363 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x4e3> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV %ESI,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV 0x14(%RSP),%R11D | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
VMOVQ (%R15),%XMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
DIVL 0x1c(%RSP) | 3 | 2 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 10-17 | 6 |
VMOVQ 0x10(%R15),%XMM11 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVQ 0x18(%R15),%XMM10 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %R9D,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVQ 0x8(%R15),%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R11D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LEA (%RAX,%R12,1),%R12D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB %R11D,%R13D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOVSXD %R12D,%R8 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %R11D,0x3c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
NOPW %CS:(%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
NOP | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
NOPL (%RAX) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
VZEROUPPER | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
POP %RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
RET | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
NOPW %CS:(%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
NOPL (%RAX) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
INC %R9D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
JMP 42ef03 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x83> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
NOPW %CS:(%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7– | 4.2 | 2.11 |
▼Loop 189 - advec_mom.cpp:148-149 - exec– | 0.01 | 0.01 |
○Loop 190 - advec_mom.cpp:149-149 - exec | 4.19 | 2.11 |