Function: _Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buf ... | Module: exec | Source: advec_mom.cpp:218-221 [...] | Coverage: 4.32% |
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Function: _Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buf ... | Module: exec | Source: advec_mom.cpp:218-221 [...] | Coverage: 4.32% |
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/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp: 218 - 221 |
-------------------------------------------------------------------------------- |
218: #pragma omp parallel for simd collapse(2) |
219: for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) { |
220: for (int i = (x_min + 1); i < (x_max + 1 + 2); i++) { |
221: vel1(i, j) = (vel1(i, j) * node_mass_pre(i, j) + mom_flux(i + 0, j - 1) - mom_flux(i, j)) / node_mass_post(i, j); |
/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69 |
-------------------------------------------------------------------------------- |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
0x430070 PUSH %RBP |
0x430071 MOV %RSP,%RBP |
0x430074 PUSH %R15 |
0x430076 PUSH %R14 |
0x430078 PUSH %R13 |
0x43007a PUSH %R12 |
0x43007c PUSH %RBX |
0x43007d AND $-0x40,%RSP |
0x430081 SUB $0x40,%RSP |
0x430085 MOV 0x28(%RDI),%EAX |
0x430088 MOV 0x2c(%RDI),%ECX |
0x43008b MOV 0x20(%RDI),%ESI |
0x43008e MOV 0x24(%RDI),%EDX |
0x430091 ADD $0x3,%ECX |
0x430094 INC %ESI |
0x430096 LEA 0x1(%RAX),%R15D |
0x43009a MOV %ECX,0x14(%RSP) |
0x43009e MOV %ESI,0x10(%RSP) |
0x4300a2 CMP %ECX,%R15D |
0x4300a5 JGE 430593 |
0x4300ab MOV %ECX,%EBX |
0x4300ad LEA 0x3(%RDX),%R13D |
0x4300b1 SUB %R15D,%EBX |
0x4300b4 CMP %R13D,%ESI |
0x4300b7 JGE 430593 |
0x4300bd MOV %RDI,%R14 |
0x4300c0 MOV %R13D,%EDI |
0x4300c3 SUB %ESI,%EDI |
0x4300c5 MOV %EDI,0x30(%RSP) |
0x4300c9 CALL 404650 <omp_get_num_threads@plt> |
0x4300ce MOV %EAX,%R12D |
0x4300d1 CALL 404540 <omp_get_thread_num@plt> |
0x4300d6 XOR %EDX,%EDX |
0x4300d8 MOV %EAX,%ESI |
0x4300da MOV 0x30(%RSP),%EAX |
0x4300de IMUL %EBX,%EAX |
0x4300e1 DIV %R12D |
0x4300e4 MOV %EAX,%R8D |
0x4300e7 CMP %EDX,%ESI |
0x4300e9 JB 4305bb |
0x4300ef IMUL %R8D,%ESI |
0x4300f3 ADD %EDX,%ESI |
0x4300f5 LEA (%R8,%RSI,1),%R9D |
0x4300f9 MOV %R9D,0xc(%RSP) |
0x4300fe CMP %R9D,%ESI |
0x430101 JAE 430593 |
0x430107 MOV %ESI,%EAX |
0x430109 XOR %EDX,%EDX |
0x43010b MOV 0x10(%RSP),%R10D |
0x430110 VMOVQ (%R14),%XMM11 |
0x430115 DIVL 0x30(%RSP) |
0x430119 VMOVQ 0x10(%R14),%XMM10 |
0x43011f VMOVQ 0x18(%R14),%XMM9 |
0x430125 VMOVQ 0x8(%R14),%XMM8 |
0x43012b ADD %R10D,%EDX |
0x43012e ADD %R15D,%EAX |
0x430131 SUB %EDX,%R13D |
0x430134 MOV %EDX,0x3c(%RSP) |
0x430138 MOVSXD %EAX,%R15 |
0x43013b MOV %R8D,%EDX |
0x43013e MOV %EAX,0x38(%RSP) |
0x430142 NOPW %CS:(%RAX,%RAX,1) |
0x43014d NOPL (%RAX) |
(195) 0x430150 CMP %R13D,%EDX |
(195) 0x430153 CMOVA %R13D,%EDX |
(195) 0x430157 LEA (%RSI,%RDX,1),%R11D |
(195) 0x43015b MOV %R11D,0x34(%RSP) |
(195) 0x430160 CMP %R11D,%ESI |
(195) 0x430163 JAE 430555 |
(195) 0x430169 VMOVQ %XMM11,%R13 |
(195) 0x43016e VMOVQ %XMM10,%RBX |
(195) 0x430173 MOV 0x38(%RSP),%R8D |
(195) 0x430178 LEA -0x1(%RDX),%R11D |
(195) 0x43017c VMOVQ %XMM8,%R10 |
(195) 0x430181 MOV (%R13),%R12 |
(195) 0x430185 VMOVQ 0x10(%R13),%XMM0 |
(195) 0x43018b VMOVQ 0x10(%RBX),%XMM6 |
(195) 0x430190 MOV (%RBX),%R13 |
(195) 0x430193 MOV (%R10),%RBX |
(195) 0x430196 VMOVQ 0x10(%R10),%XMM2 |
(195) 0x43019c VMOVQ %XMM9,%RDI |
(195) 0x4301a1 MOV (%RDI),%R9 |
(195) 0x4301a4 MOV 0x10(%RDI),%R14 |
(195) 0x4301a8 LEA -0x1(%R8),%EAX |
(195) 0x4301ac IMUL %R15,%R12 |
(195) 0x4301b0 MOVSXD %EAX,%R8 |
(195) 0x4301b3 IMUL %R15,%R13 |
(195) 0x4301b7 IMUL %R15,%RBX |
(195) 0x4301bb IMUL %R9,%R8 |
(195) 0x4301bf MOV %R12,0x18(%RSP) |
(195) 0x4301c4 IMUL %R15,%R9 |
(195) 0x4301c8 MOV %R13,0x20(%RSP) |
(195) 0x4301cd MOV %RBX,0x28(%RSP) |
(195) 0x4301d2 CMP $0x6,%R11D |
(195) 0x4301d6 JBE 4305b0 |
(195) 0x4301dc MOVSXD 0x3c(%RSP),%R10 |
(195) 0x4301e1 VMOVQ %XMM0,%RAX |
(195) 0x4301e6 VMOVQ %XMM6,%RDI |
(195) 0x4301eb LEA (%R10,%R12,1),%R12 |
(195) 0x4301ef LEA (%R10,%R13,1),%R13 |
(195) 0x4301f3 LEA (%R10,%R8,1),%RCX |
(195) 0x4301f7 LEA (%RAX,%R12,8),%R11 |
(195) 0x4301fb LEA (%RDI,%R13,8),%R12 |
(195) 0x4301ff LEA (%R10,%R9,1),%R13 |
(195) 0x430203 ADD %RBX,%R10 |
(195) 0x430206 VMOVQ %XMM2,%RBX |
(195) 0x43020b LEA (%R14,%RCX,8),%RAX |
(195) 0x43020f XOR %ECX,%ECX |
(195) 0x430211 LEA (%R14,%R13,8),%R13 |
(195) 0x430215 LEA (%RBX,%R10,8),%RBX |
(195) 0x430219 MOV %EDX,%R10D |
(195) 0x43021c SHR $0x3,%R10D |
(195) 0x430220 SAL $0x6,%R10 |
(195) 0x430224 LEA -0x40(%R10),%RDI |
(195) 0x430228 SHR $0x6,%RDI |
(195) 0x43022c INC %RDI |
(195) 0x43022f AND $0x3,%EDI |
(195) 0x430232 JE 4302d6 |
(195) 0x430238 CMP $0x1,%RDI |
(195) 0x43023c JE 43029e |
(195) 0x43023e CMP $0x2,%RDI |
(195) 0x430242 JE 43026f |
(195) 0x430244 VMOVUPD (%R11),%ZMM1 |
(195) 0x43024a VMOVUPD (%R13),%ZMM3 |
(195) 0x430251 VFMSUB132PD (%R12),%ZMM3,%ZMM1 |
(195) 0x430258 VADDPD (%RAX),%ZMM1,%ZMM4 |
(195) 0x43025e MOV $0x40,%ECX |
(195) 0x430263 VDIVPD (%RBX),%ZMM4,%ZMM5 |
(195) 0x430269 VMOVUPD %ZMM5,(%R11) |
(195) 0x43026f VMOVUPD (%R11,%RCX,1),%ZMM7 |
(195) 0x430276 VMOVUPD (%R13,%RCX,1),%ZMM12 |
(195) 0x43027e VFMSUB132PD (%R12,%RCX,1),%ZMM12,%ZMM7 |
(195) 0x430285 VADDPD (%RAX,%RCX,1),%ZMM7,%ZMM13 |
(195) 0x43028c VDIVPD (%RBX,%RCX,1),%ZMM13,%ZMM14 |
(195) 0x430293 VMOVUPD %ZMM14,(%R11,%RCX,1) |
(195) 0x43029a ADD $0x40,%RCX |
(195) 0x43029e VMOVUPD (%R11,%RCX,1),%ZMM15 |
(195) 0x4302a5 VMOVUPD (%R13,%RCX,1),%ZMM1 |
(195) 0x4302ad VFMSUB132PD (%R12,%RCX,1),%ZMM1,%ZMM15 |
(195) 0x4302b4 VADDPD (%RAX,%RCX,1),%ZMM15,%ZMM3 |
(195) 0x4302bb VDIVPD (%RBX,%RCX,1),%ZMM3,%ZMM4 |
(195) 0x4302c2 VMOVUPD %ZMM4,(%R11,%RCX,1) |
(195) 0x4302c9 ADD $0x40,%RCX |
(195) 0x4302cd CMP %RCX,%R10 |
(195) 0x4302d0 JE 4303a1 |
(196) 0x4302d6 VMOVUPD (%R13,%RCX,1),%ZMM7 |
(196) 0x4302de VMOVUPD (%R11,%RCX,1),%ZMM5 |
(196) 0x4302e5 VFMSUB132PD (%R12,%RCX,1),%ZMM7,%ZMM5 |
(196) 0x4302ec VADDPD (%RAX,%RCX,1),%ZMM5,%ZMM12 |
(196) 0x4302f3 VMOVUPD 0x40(%R11,%RCX,1),%ZMM14 |
(196) 0x4302fb VMOVUPD 0x80(%R11,%RCX,1),%ZMM4 |
(196) 0x430303 VDIVPD (%RBX,%RCX,1),%ZMM12,%ZMM13 |
(196) 0x43030a VMOVUPD %ZMM13,(%R11,%RCX,1) |
(196) 0x430311 VMOVUPD 0x40(%R13,%RCX,1),%ZMM15 |
(196) 0x430319 VFMSUB132PD 0x40(%R12,%RCX,1),%ZMM15,%ZMM14 |
(196) 0x430321 VADDPD 0x40(%RAX,%RCX,1),%ZMM14,%ZMM1 |
(196) 0x430329 VMOVUPD 0xc0(%R11,%RCX,1),%ZMM13 |
(196) 0x430331 VDIVPD 0x40(%RBX,%RCX,1),%ZMM1,%ZMM3 |
(196) 0x430339 VMOVUPD %ZMM3,0x40(%R11,%RCX,1) |
(196) 0x430341 VMOVUPD 0x80(%R13,%RCX,1),%ZMM5 |
(196) 0x430349 VFMSUB132PD 0x80(%R12,%RCX,1),%ZMM5,%ZMM4 |
(196) 0x430351 VADDPD 0x80(%RAX,%RCX,1),%ZMM4,%ZMM7 |
(196) 0x430359 VDIVPD 0x80(%RBX,%RCX,1),%ZMM7,%ZMM12 |
(196) 0x430361 VMOVUPD %ZMM12,0x80(%R11,%RCX,1) |
(196) 0x430369 VMOVUPD 0xc0(%R13,%RCX,1),%ZMM14 |
(196) 0x430371 VFMSUB132PD 0xc0(%R12,%RCX,1),%ZMM14,%ZMM13 |
(196) 0x430379 VADDPD 0xc0(%RAX,%RCX,1),%ZMM13,%ZMM15 |
(196) 0x430381 VDIVPD 0xc0(%RBX,%RCX,1),%ZMM15,%ZMM1 |
(196) 0x430389 VMOVUPD %ZMM1,0xc0(%R11,%RCX,1) |
(196) 0x430391 ADD $0x100,%RCX |
(196) 0x430398 CMP %RCX,%R10 |
(196) 0x43039b JNE 4302d6 |
(195) 0x4303a1 MOV 0x3c(%RSP),%R11D |
(195) 0x4303a6 MOV %EDX,%ECX |
(195) 0x4303a8 AND $-0x8,%ECX |
(195) 0x4303ab ADD %ECX,%ESI |
(195) 0x4303ad LEA (%RCX,%R11,1),%EDI |
(195) 0x4303b1 TEST $0x7,%DL |
(195) 0x4303b4 JE 430551 |
(195) 0x4303ba SUB %ECX,%EDX |
(195) 0x4303bc LEA -0x1(%RDX),%R12D |
(195) 0x4303c0 CMP $0x2,%R12D |
(195) 0x4303c4 JBE 430443 |
(195) 0x4303c6 MOVSXD 0x3c(%RSP),%RAX |
(195) 0x4303cb MOV 0x18(%RSP),%R13 |
(195) 0x4303d0 VMOVQ %XMM0,%RBX |
(195) 0x4303d5 MOV 0x28(%RSP),%R11 |
(195) 0x4303da LEA (%R13,%RAX,1),%R10 |
(195) 0x4303df LEA (%R11,%RAX,1),%R13 |
(195) 0x4303e3 ADD %RCX,%R10 |
(195) 0x4303e6 ADD %RCX,%R13 |
(195) 0x4303e9 LEA (%RBX,%R10,8),%R12 |
(195) 0x4303ed MOV 0x20(%RSP),%RBX |
(195) 0x4303f2 LEA (%R8,%RAX,1),%R10 |
(195) 0x4303f6 ADD %RCX,%R10 |
(195) 0x4303f9 VMOVUPD (%R12),%YMM4 |
(195) 0x4303ff ADD %RAX,%RBX |
(195) 0x430402 ADD %R9,%RAX |
(195) 0x430405 ADD %RCX,%RAX |
(195) 0x430408 ADD %RCX,%RBX |
(195) 0x43040b VMOVQ %XMM6,%RCX |
(195) 0x430410 VMOVUPD (%R14,%RAX,8),%YMM3 |
(195) 0x430416 VMOVQ %XMM2,%RAX |
(195) 0x43041b VFMSUB132PD (%RCX,%RBX,8),%YMM3,%YMM4 |
(195) 0x430421 VADDPD (%R14,%R10,8),%YMM4,%YMM5 |
(195) 0x430427 VDIVPD (%RAX,%R13,8),%YMM5,%YMM7 |
(195) 0x43042d VMOVUPD %YMM7,(%R12) |
(195) 0x430433 TEST $0x3,%DL |
(195) 0x430436 JE 430551 |
(195) 0x43043c AND $-0x4,%EDX |
(195) 0x43043f ADD %EDX,%ESI |
(195) 0x430441 ADD %EDX,%EDI |
(195) 0x430443 MOV 0x18(%RSP),%RBX |
(195) 0x430448 MOVSXD %EDI,%RAX |
(195) 0x43044b VMOVQ %XMM0,%R12 |
(195) 0x430450 VMOVQ %XMM6,%R13 |
(195) 0x430455 LEA (%R8,%RAX,1),%RCX |
(195) 0x430459 LEA (%R9,%RAX,1),%R10 |
(195) 0x43045d VMOVSD (%R14,%R10,8),%XMM13 |
(195) 0x430463 LEA (%RBX,%RAX,1),%RDX |
(195) 0x430467 LEA (%R12,%RDX,8),%RDX |
(195) 0x43046b MOV 0x20(%RSP),%R12 |
(195) 0x430470 LEA (%R12,%RAX,1),%R11 |
(195) 0x430474 VMOVSD (%R13,%R11,8),%XMM12 |
(195) 0x43047b MOV 0x28(%RSP),%R13 |
(195) 0x430480 MOV 0x34(%RSP),%R11D |
(195) 0x430485 VFMSUB132SD (%RDX),%XMM13,%XMM12 |
(195) 0x43048a VADDSD (%R14,%RCX,8),%XMM12,%XMM14 |
(195) 0x430490 VMOVQ %XMM2,%RCX |
(195) 0x430495 ADD %R13,%RAX |
(195) 0x430498 VDIVSD (%RCX,%RAX,8),%XMM14,%XMM15 |
(195) 0x43049d VMOVSD %XMM15,(%RDX) |
(195) 0x4304a1 LEA 0x1(%RSI),%EDX |
(195) 0x4304a4 LEA 0x1(%RDI),%EAX |
(195) 0x4304a7 CMP %R11D,%EDX |
(195) 0x4304aa JAE 430551 |
(195) 0x4304b0 CLTQ |
(195) 0x4304b2 VMOVQ %XMM0,%RCX |
(195) 0x4304b7 ADD $0x2,%ESI |
(195) 0x4304ba ADD $0x2,%EDI |
(195) 0x4304bd LEA (%RBX,%RAX,1),%R10 |
(195) 0x4304c1 LEA (%R12,%RAX,1),%R11 |
(195) 0x4304c5 LEA (%RCX,%R10,8),%RDX |
(195) 0x4304c9 LEA (%R9,%RAX,1),%R10 |
(195) 0x4304cd LEA (%R8,%RAX,1),%RCX |
(195) 0x4304d1 ADD %R13,%RAX |
(195) 0x4304d4 VMOVQ %R10,%XMM4 |
(195) 0x4304d9 VMOVQ %XMM6,%R10 |
(195) 0x4304de VMOVSD (%R10,%R11,8),%XMM1 |
(195) 0x4304e4 VMOVQ %XMM4,%R11 |
(195) 0x4304e9 VMOVSD (%R14,%R11,8),%XMM3 |
(195) 0x4304ef VFMSUB132SD (%RDX),%XMM3,%XMM1 |
(195) 0x4304f4 VADDSD (%R14,%RCX,8),%XMM1,%XMM5 |
(195) 0x4304fa MOV %R13,%RCX |
(195) 0x4304fd VMOVQ %XMM2,%R13 |
(195) 0x430502 VDIVSD (%R13,%RAX,8),%XMM5,%XMM7 |
(195) 0x430509 MOV 0x34(%RSP),%EAX |
(195) 0x43050d VMOVSD %XMM7,(%RDX) |
(195) 0x430511 CMP %EAX,%ESI |
(195) 0x430513 JAE 430551 |
(195) 0x430515 MOVSXD %EDI,%RDI |
(195) 0x430518 VMOVQ %XMM0,%RSI |
(195) 0x43051d ADD %RDI,%RBX |
(195) 0x430520 ADD %RDI,%R8 |
(195) 0x430523 ADD %RDI,%R12 |
(195) 0x430526 ADD %RDI,%R9 |
(195) 0x430529 LEA (%RSI,%RBX,8),%RDX |
(195) 0x43052d ADD %RDI,%RCX |
(195) 0x430530 VMOVSD (%R14,%R9,8),%XMM6 |
(195) 0x430536 VMOVSD (%RDX),%XMM0 |
(195) 0x43053a VFMSUB132SD (%R10,%R12,8),%XMM6,%XMM0 |
(195) 0x430540 VADDSD (%R14,%R8,8),%XMM0,%XMM12 |
(195) 0x430546 VDIVSD (%R13,%RCX,8),%XMM12,%XMM2 |
(195) 0x43054d VMOVSD %XMM2,(%RDX) |
(195) 0x430551 MOV 0x34(%RSP),%ESI |
(195) 0x430555 INCL 0x38(%RSP) |
(195) 0x430559 MOV 0x38(%RSP),%R9D |
(195) 0x43055e INC %R15 |
(195) 0x430561 CMP %R9D,0x14(%RSP) |
(195) 0x430566 JLE 430590 |
(195) 0x430568 MOV 0xc(%RSP),%EDX |
(195) 0x43056c MOV 0x10(%RSP),%R8D |
(195) 0x430571 MOV 0x30(%RSP),%R13D |
(195) 0x430576 SUB %ESI,%EDX |
(195) 0x430578 MOV %R8D,0x3c(%RSP) |
(195) 0x43057d JMP 430150 |
0x430582 NOPW %CS:(%RAX,%RAX,1) |
0x43058d NOPL (%RAX) |
0x430590 VZEROUPPER |
0x430593 LEA -0x28(%RBP),%RSP |
0x430597 POP %RBX |
0x430598 POP %R12 |
0x43059a POP %R13 |
0x43059c POP %R14 |
0x43059e POP %R15 |
0x4305a0 POP %RBP |
0x4305a1 RET |
0x4305a2 NOPW %CS:(%RAX,%RAX,1) |
0x4305ad NOPL (%RAX) |
(195) 0x4305b0 MOV 0x3c(%RSP),%EDI |
(195) 0x4305b4 XOR %ECX,%ECX |
(195) 0x4305b6 JMP 4303ba |
0x4305bb INC %R8D |
0x4305be XOR %EDX,%EDX |
0x4305c0 JMP 4300ef |
0x4305c5 NOPW %CS:(%RAX,%RAX,1) |
Path / |
Source file and lines | advec_mom.cpp:218-221 |
Module | exec |
nb instructions | 80 |
nb uops | 78 |
loop length | 291 |
used x86 registers | 15 |
used mmx registers | 0 |
used xmm registers | 4 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 7 |
micro-operation queue | 13.00 cycles |
front end | 13.00 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 7.00 | 7.00 | 7.00 | 7.00 | 6.00 | 6.33 | 6.33 | 6.33 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 |
cycles | 7.00 | 7.00 | 7.00 | 7.00 | 6.00 | 6.33 | 6.33 | 6.33 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 |
Cycles executing div or sqrt instructions | 12.00 |
Front-end | 13.00 |
Dispatch | 7.00 |
DIV/SQRT | 12.00 |
Overall L1 | 13.00 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 12% |
all | 8% |
load | 9% |
store | 6% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 9% |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
AND $-0x40,%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB $0x40,%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV 0x28(%RDI),%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x2c(%RDI),%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x20(%RDI),%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x24(%RDI),%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
ADD $0x3,%ECX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
INC %ESI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LEA 0x1(%RAX),%R15D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %ECX,0x14(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV %ESI,0x10(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
CMP %ECX,%R15D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JGE 430593 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.11+0x523> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV %ECX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x3(%RDX),%R13D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB %R15D,%EBX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP %R13D,%ESI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JGE 430593 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.11+0x523> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV %RDI,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R13D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SUB %ESI,%EDI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %EDI,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
CALL 404650 <omp_get_num_threads@plt> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CALL 404540 <omp_get_thread_num@plt> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV %EAX,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x30(%RSP),%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 10-17 | 6 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP %EDX,%ESI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JB 4305bb <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.11+0x54b> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
IMUL %R8D,%ESI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %EDX,%ESI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LEA (%R8,%RSI,1),%R9D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %R9D,0xc(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
CMP %R9D,%ESI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JAE 430593 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.11+0x523> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV %ESI,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV 0x10(%RSP),%R10D | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
VMOVQ (%R14),%XMM11 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
DIVL 0x30(%RSP) | 3 | 2 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 10-17 | 6 |
VMOVQ 0x10(%R14),%XMM10 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVQ 0x18(%R14),%XMM9 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVQ 0x8(%R14),%XMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ADD %R10D,%EDX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD %R15D,%EAX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB %EDX,%R13D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %EDX,0x3c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOVSXD %EAX,%R15 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %R8D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
NOPW %CS:(%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
NOPL (%RAX) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
NOPW %CS:(%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
NOPL (%RAX) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
VZEROUPPER | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
POP %RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
RET | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
NOPW %CS:(%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
NOPL (%RAX) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
INC %R8D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
JMP 4300ef <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.11+0x7f> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
NOPW %CS:(%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
Source file and lines | advec_mom.cpp:218-221 |
Module | exec |
nb instructions | 80 |
nb uops | 78 |
loop length | 291 |
used x86 registers | 15 |
used mmx registers | 0 |
used xmm registers | 4 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 7 |
micro-operation queue | 13.00 cycles |
front end | 13.00 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 7.00 | 7.00 | 7.00 | 7.00 | 6.00 | 6.33 | 6.33 | 6.33 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 |
cycles | 7.00 | 7.00 | 7.00 | 7.00 | 6.00 | 6.33 | 6.33 | 6.33 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 |
Cycles executing div or sqrt instructions | 12.00 |
Front-end | 13.00 |
Dispatch | 7.00 |
DIV/SQRT | 12.00 |
Overall L1 | 13.00 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 12% |
all | 8% |
load | 9% |
store | 6% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 9% |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
AND $-0x40,%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB $0x40,%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV 0x28(%RDI),%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x2c(%RDI),%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x20(%RDI),%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x24(%RDI),%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
ADD $0x3,%ECX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
INC %ESI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LEA 0x1(%RAX),%R15D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %ECX,0x14(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV %ESI,0x10(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
CMP %ECX,%R15D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JGE 430593 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.11+0x523> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV %ECX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x3(%RDX),%R13D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB %R15D,%EBX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP %R13D,%ESI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JGE 430593 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.11+0x523> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV %RDI,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R13D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SUB %ESI,%EDI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %EDI,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
CALL 404650 <omp_get_num_threads@plt> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CALL 404540 <omp_get_thread_num@plt> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV %EAX,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x30(%RSP),%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 10-17 | 6 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP %EDX,%ESI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JB 4305bb <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.11+0x54b> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
IMUL %R8D,%ESI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %EDX,%ESI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LEA (%R8,%RSI,1),%R9D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %R9D,0xc(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
CMP %R9D,%ESI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JAE 430593 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.11+0x523> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV %ESI,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV 0x10(%RSP),%R10D | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
VMOVQ (%R14),%XMM11 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
DIVL 0x30(%RSP) | 3 | 2 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 10-17 | 6 |
VMOVQ 0x10(%R14),%XMM10 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVQ 0x18(%R14),%XMM9 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVQ 0x8(%R14),%XMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ADD %R10D,%EDX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD %R15D,%EAX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB %EDX,%R13D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %EDX,0x3c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOVSXD %EAX,%R15 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %R8D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
NOPW %CS:(%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
NOPL (%RAX) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
NOPW %CS:(%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
NOPL (%RAX) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
VZEROUPPER | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
POP %RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
RET | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
NOPW %CS:(%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
NOPL (%RAX) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
INC %R8D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
JMP 4300ef <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.11+0x7f> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
NOPW %CS:(%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.11– | 4.32 | 2.18 |
▼Loop 195 - advec_mom.cpp:220-221 - exec– | 0.01 | 0.01 |
○Loop 196 - advec_mom.cpp:221-221 - exec | 4.32 | 2.17 |