Function: _Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0 | Module: exec | Source: revert.cpp:34-38 [...] | Coverage: 2.59% |
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Function: _Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0 | Module: exec | Source: revert.cpp:34-38 [...] | Coverage: 2.59% |
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/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/revert.cpp: 34 - 38 |
-------------------------------------------------------------------------------- |
34: #pragma omp parallel for simd collapse(2) |
35: for (int j = (y_min + 1); j < (y_max + 2); j++) { |
36: for (int i = (x_min + 1); i < (x_max + 2); i++) { |
37: density1(i, j) = density0(i, j); |
38: energy1(i, j) = energy0(i, j); |
/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69 |
-------------------------------------------------------------------------------- |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
0x443080 PUSH %RBP |
0x443081 MOV %RSP,%RBP |
0x443084 PUSH %R15 |
0x443086 PUSH %R14 |
0x443088 PUSH %R13 |
0x44308a PUSH %R12 |
0x44308c PUSH %RBX |
0x44308d MOV %RDI,%R13 |
0x443090 AND $-0x40,%RSP |
0x443094 SUB $0x40,%RSP |
0x443098 MOV 0x28(%RDI),%EAX |
0x44309b MOV 0x2c(%RDI),%EDX |
0x44309e MOV 0x20(%RDI),%EDI |
0x4430a1 MOV 0x24(%R13),%ECX |
0x4430a5 ADD $0x2,%EDX |
0x4430a8 LEA 0x1(%RDI),%EBX |
0x4430ab LEA 0x1(%RAX),%R14D |
0x4430af MOV %EDX,0x10(%RSP) |
0x4430b3 MOV %EBX,0xc(%RSP) |
0x4430b7 CMP %EDX,%R14D |
0x4430ba JGE 4435b3 |
0x4430c0 MOV %EDX,%R12D |
0x4430c3 LEA 0x2(%RCX),%R15D |
0x4430c7 SUB %R14D,%R12D |
0x4430ca CMP %R15D,%EBX |
0x4430cd JGE 4435b3 |
0x4430d3 MOV %R15D,%ESI |
0x4430d6 SUB %EBX,%ESI |
0x4430d8 MOV %ESI,0x14(%RSP) |
0x4430dc CALL 404650 <omp_get_num_threads@plt> |
0x4430e1 MOV %EAX,%EBX |
0x4430e3 CALL 404540 <omp_get_thread_num@plt> |
0x4430e8 XOR %EDX,%EDX |
0x4430ea MOV %EAX,%R8D |
0x4430ed MOV 0x14(%RSP),%EAX |
0x4430f1 IMUL %R12D,%EAX |
0x4430f5 DIV %EBX |
0x4430f7 MOV %EAX,%R12D |
0x4430fa CMP %EDX,%R8D |
0x4430fd JB 4435dd |
0x443103 IMUL %R12D,%R8D |
0x443107 LEA (%R8,%RDX,1),%EDI |
0x44310b LEA (%R12,%RDI,1),%R9D |
0x44310f MOV %R9D,0x8(%RSP) |
0x443114 CMP %R9D,%EDI |
0x443117 JAE 4435b3 |
0x44311d MOV %EDI,%EAX |
0x44311f XOR %EDX,%EDX |
0x443121 MOV 0xc(%RSP),%R10D |
0x443126 VMOVQ (%R13),%XMM3 |
0x44312c DIVL 0x14(%RSP) |
0x443130 VMOVQ 0x8(%R13),%XMM4 |
0x443136 VMOVQ 0x10(%R13),%XMM2 |
0x44313c VMOVQ 0x18(%R13),%XMM1 |
0x443142 ADD %EDX,%R10D |
0x443145 LEA (%RAX,%R14,1),%R11D |
0x443149 SUB %R10D,%R15D |
0x44314c MOVSXD %R11D,%R8 |
0x44314f MOV %R10D,0x3c(%RSP) |
0x443154 NOPW %CS:(%RAX,%RAX,1) |
0x44315f NOP |
(281) 0x443160 CMP %R15D,%R12D |
(281) 0x443163 MOV %R15D,%ECX |
(281) 0x443166 CMOVBE %R12D,%ECX |
(281) 0x44316a LEA (%RDI,%RCX,1),%R15D |
(281) 0x44316e MOV %R15D,0x38(%RSP) |
(281) 0x443173 CMP %R15D,%EDI |
(281) 0x443176 JAE 44357f |
(281) 0x44317c VMOVQ %XMM3,%R13 |
(281) 0x443181 VMOVQ %XMM4,%R14 |
(281) 0x443186 VMOVQ %XMM2,%RSI |
(281) 0x44318b VMOVQ %XMM1,%RAX |
(281) 0x443190 MOV (%R13),%RDX |
(281) 0x443194 MOV (%R14),%R9 |
(281) 0x443197 MOV (%RSI),%R15 |
(281) 0x44319a MOV (%RAX),%R11 |
(281) 0x44319d MOV 0x10(%R14),%R12 |
(281) 0x4431a1 MOV 0x10(%RSI),%R14 |
(281) 0x4431a5 LEA -0x1(%RCX),%ESI |
(281) 0x4431a8 MOV 0x10(%R13),%RBX |
(281) 0x4431ac MOV 0x10(%RAX),%R13 |
(281) 0x4431b0 IMUL %R8,%RDX |
(281) 0x4431b4 IMUL %R8,%R9 |
(281) 0x4431b8 IMUL %R8,%R15 |
(281) 0x4431bc IMUL %R8,%R11 |
(281) 0x4431c0 MOV %RDX,0x18(%RSP) |
(281) 0x4431c5 MOV %R9,0x20(%RSP) |
(281) 0x4431ca MOV %R15,0x28(%RSP) |
(281) 0x4431cf MOV %R11,0x30(%RSP) |
(281) 0x4431d4 CMP $0x6,%ESI |
(281) 0x4431d7 JBE 4435d0 |
(281) 0x4431dd MOVSXD 0x3c(%RSP),%RAX |
(281) 0x4431e2 LEA (%R15,%RAX,1),%RSI |
(281) 0x4431e6 MOV 0x30(%RSP),%R15 |
(281) 0x4431eb LEA (%RDX,%RAX,1),%RDX |
(281) 0x4431ef LEA (%R9,%RAX,1),%R10 |
(281) 0x4431f3 LEA (%R14,%RSI,8),%R9 |
(281) 0x4431f7 LEA (%RBX,%RDX,8),%R11 |
(281) 0x4431fb LEA (%R12,%R10,8),%R10 |
(281) 0x4431ff ADD %R15,%RAX |
(281) 0x443202 MOV %ECX,%R15D |
(281) 0x443205 SHR $0x3,%R15D |
(281) 0x443209 SAL $0x6,%R15 |
(281) 0x44320d LEA -0x40(%R15),%RSI |
(281) 0x443211 LEA (%R13,%RAX,8),%RDX |
(281) 0x443216 XOR %EAX,%EAX |
(281) 0x443218 SHR $0x6,%RSI |
(281) 0x44321c INC %RSI |
(281) 0x44321f AND $0x7,%ESI |
(281) 0x443222 JE 44333e |
(281) 0x443228 CMP $0x1,%RSI |
(281) 0x44322c JE 443315 |
(281) 0x443232 CMP $0x2,%RSI |
(281) 0x443236 JE 4432f5 |
(281) 0x44323c CMP $0x3,%RSI |
(281) 0x443240 JE 4432d5 |
(281) 0x443246 CMP $0x4,%RSI |
(281) 0x44324a JE 4432b5 |
(281) 0x44324c CMP $0x5,%RSI |
(281) 0x443250 JE 443295 |
(281) 0x443252 CMP $0x6,%RSI |
(281) 0x443256 JE 443275 |
(281) 0x443258 VMOVUPD (%R11),%ZMM5 |
(281) 0x44325e MOV $0x40,%EAX |
(281) 0x443263 VMOVUPD %ZMM5,(%R10) |
(281) 0x443269 VMOVUPD (%R9),%ZMM6 |
(281) 0x44326f VMOVUPD %ZMM6,(%RDX) |
(281) 0x443275 VMOVUPD (%R11,%RAX,1),%ZMM7 |
(281) 0x44327c VMOVUPD %ZMM7,(%R10,%RAX,1) |
(281) 0x443283 VMOVUPD (%R9,%RAX,1),%ZMM0 |
(281) 0x44328a VMOVUPD %ZMM0,(%RDX,%RAX,1) |
(281) 0x443291 ADD $0x40,%RAX |
(281) 0x443295 VMOVUPD (%R11,%RAX,1),%ZMM8 |
(281) 0x44329c VMOVUPD %ZMM8,(%R10,%RAX,1) |
(281) 0x4432a3 VMOVUPD (%R9,%RAX,1),%ZMM9 |
(281) 0x4432aa VMOVUPD %ZMM9,(%RDX,%RAX,1) |
(281) 0x4432b1 ADD $0x40,%RAX |
(281) 0x4432b5 VMOVUPD (%R11,%RAX,1),%ZMM10 |
(281) 0x4432bc VMOVUPD %ZMM10,(%R10,%RAX,1) |
(281) 0x4432c3 VMOVUPD (%R9,%RAX,1),%ZMM11 |
(281) 0x4432ca VMOVUPD %ZMM11,(%RDX,%RAX,1) |
(281) 0x4432d1 ADD $0x40,%RAX |
(281) 0x4432d5 VMOVUPD (%R11,%RAX,1),%ZMM12 |
(281) 0x4432dc VMOVUPD %ZMM12,(%R10,%RAX,1) |
(281) 0x4432e3 VMOVUPD (%R9,%RAX,1),%ZMM13 |
(281) 0x4432ea VMOVUPD %ZMM13,(%RDX,%RAX,1) |
(281) 0x4432f1 ADD $0x40,%RAX |
(281) 0x4432f5 VMOVUPD (%R11,%RAX,1),%ZMM14 |
(281) 0x4432fc VMOVUPD %ZMM14,(%R10,%RAX,1) |
(281) 0x443303 VMOVUPD (%R9,%RAX,1),%ZMM15 |
(281) 0x44330a VMOVUPD %ZMM15,(%RDX,%RAX,1) |
(281) 0x443311 ADD $0x40,%RAX |
(281) 0x443315 VMOVUPD (%R11,%RAX,1),%ZMM5 |
(281) 0x44331c VMOVUPD %ZMM5,(%R10,%RAX,1) |
(281) 0x443323 VMOVUPD (%R9,%RAX,1),%ZMM6 |
(281) 0x44332a VMOVUPD %ZMM6,(%RDX,%RAX,1) |
(281) 0x443331 ADD $0x40,%RAX |
(281) 0x443335 CMP %RAX,%R15 |
(281) 0x443338 JE 443449 |
(282) 0x44333e VMOVUPD (%R11,%RAX,1),%ZMM7 |
(282) 0x443345 VMOVUPD %ZMM7,(%R10,%RAX,1) |
(282) 0x44334c VMOVUPD (%R9,%RAX,1),%ZMM0 |
(282) 0x443353 VMOVUPD %ZMM0,(%RDX,%RAX,1) |
(282) 0x44335a VMOVUPD 0x40(%R11,%RAX,1),%ZMM8 |
(282) 0x443362 VMOVUPD %ZMM8,0x40(%R10,%RAX,1) |
(282) 0x44336a VMOVUPD 0x40(%R9,%RAX,1),%ZMM9 |
(282) 0x443372 VMOVUPD %ZMM9,0x40(%RDX,%RAX,1) |
(282) 0x44337a VMOVUPD 0x80(%R11,%RAX,1),%ZMM10 |
(282) 0x443382 VMOVUPD %ZMM10,0x80(%R10,%RAX,1) |
(282) 0x44338a VMOVUPD 0x80(%R9,%RAX,1),%ZMM11 |
(282) 0x443392 VMOVUPD %ZMM11,0x80(%RDX,%RAX,1) |
(282) 0x44339a VMOVUPD 0xc0(%R11,%RAX,1),%ZMM12 |
(282) 0x4433a2 VMOVUPD %ZMM12,0xc0(%R10,%RAX,1) |
(282) 0x4433aa VMOVUPD 0xc0(%R9,%RAX,1),%ZMM13 |
(282) 0x4433b2 VMOVUPD %ZMM13,0xc0(%RDX,%RAX,1) |
(282) 0x4433ba VMOVUPD 0x100(%R11,%RAX,1),%ZMM14 |
(282) 0x4433c2 VMOVUPD %ZMM14,0x100(%R10,%RAX,1) |
(282) 0x4433ca VMOVUPD 0x100(%R9,%RAX,1),%ZMM15 |
(282) 0x4433d2 VMOVUPD %ZMM15,0x100(%RDX,%RAX,1) |
(282) 0x4433da VMOVUPD 0x140(%R11,%RAX,1),%ZMM5 |
(282) 0x4433e2 VMOVUPD %ZMM5,0x140(%R10,%RAX,1) |
(282) 0x4433ea VMOVUPD 0x140(%R9,%RAX,1),%ZMM6 |
(282) 0x4433f2 VMOVUPD %ZMM6,0x140(%RDX,%RAX,1) |
(282) 0x4433fa VMOVUPD 0x180(%R11,%RAX,1),%ZMM7 |
(282) 0x443402 VMOVUPD %ZMM7,0x180(%R10,%RAX,1) |
(282) 0x44340a VMOVUPD 0x180(%R9,%RAX,1),%ZMM0 |
(282) 0x443412 VMOVUPD %ZMM0,0x180(%RDX,%RAX,1) |
(282) 0x44341a VMOVUPD 0x1c0(%R11,%RAX,1),%ZMM8 |
(282) 0x443422 VMOVUPD %ZMM8,0x1c0(%R10,%RAX,1) |
(282) 0x44342a VMOVUPD 0x1c0(%R9,%RAX,1),%ZMM9 |
(282) 0x443432 VMOVUPD %ZMM9,0x1c0(%RDX,%RAX,1) |
(282) 0x44343a ADD $0x200,%RAX |
(282) 0x443440 CMP %RAX,%R15 |
(282) 0x443443 JNE 44333e |
(281) 0x443449 MOV 0x3c(%RSP),%R11D |
(281) 0x44344e MOV %ECX,%R9D |
(281) 0x443451 AND $-0x8,%R9D |
(281) 0x443455 ADD %R9D,%EDI |
(281) 0x443458 LEA (%R9,%R11,1),%R15D |
(281) 0x44345c TEST $0x7,%CL |
(281) 0x44345f JE 44357b |
(281) 0x443465 SUB %R9D,%ECX |
(281) 0x443468 LEA -0x1(%RCX),%R10D |
(281) 0x44346c CMP $0x2,%R10D |
(281) 0x443470 JBE 4434cc |
(281) 0x443472 MOVSXD 0x3c(%RSP),%RSI |
(281) 0x443477 MOV 0x18(%RSP),%RDX |
(281) 0x44347c MOV 0x20(%RSP),%RAX |
(281) 0x443481 MOV 0x28(%RSP),%R11 |
(281) 0x443486 MOV 0x30(%RSP),%R10 |
(281) 0x44348b ADD %RSI,%RDX |
(281) 0x44348e ADD %RSI,%RAX |
(281) 0x443491 ADD %R9,%RDX |
(281) 0x443494 ADD %RSI,%R11 |
(281) 0x443497 ADD %R9,%RAX |
(281) 0x44349a ADD %R10,%RSI |
(281) 0x44349d VMOVUPD (%RBX,%RDX,8),%YMM10 |
(281) 0x4434a2 ADD %R9,%R11 |
(281) 0x4434a5 ADD %R9,%RSI |
(281) 0x4434a8 VMOVUPD %YMM10,(%R12,%RAX,8) |
(281) 0x4434ae VMOVUPD (%R14,%R11,8),%YMM11 |
(281) 0x4434b4 VMOVUPD %YMM11,(%R13,%RSI,8) |
(281) 0x4434bb TEST $0x3,%CL |
(281) 0x4434be JE 44357b |
(281) 0x4434c4 AND $-0x4,%ECX |
(281) 0x4434c7 ADD %ECX,%EDI |
(281) 0x4434c9 ADD %ECX,%R15D |
(281) 0x4434cc MOV 0x18(%RSP),%RCX |
(281) 0x4434d1 MOVSXD %R15D,%RAX |
(281) 0x4434d4 MOV 0x20(%RSP),%RSI |
(281) 0x4434d9 MOV 0x30(%RSP),%R10 |
(281) 0x4434de LEA (%RCX,%RAX,1),%R9 |
(281) 0x4434e2 LEA (%RSI,%RAX,1),%RDX |
(281) 0x4434e6 VMOVSD (%RBX,%R9,8),%XMM12 |
(281) 0x4434ec MOV 0x28(%RSP),%R9 |
(281) 0x4434f1 VMOVSD %XMM12,(%R12,%RDX,8) |
(281) 0x4434f7 LEA 0x1(%RDI),%EDX |
(281) 0x4434fa LEA (%R9,%RAX,1),%R11 |
(281) 0x4434fe ADD %R10,%RAX |
(281) 0x443501 VMOVSD (%R14,%R11,8),%XMM13 |
(281) 0x443507 MOV 0x38(%RSP),%R11D |
(281) 0x44350c VMOVSD %XMM13,(%R13,%RAX,8) |
(281) 0x443513 LEA 0x1(%R15),%EAX |
(281) 0x443517 CMP %R11D,%EDX |
(281) 0x44351a JAE 44357b |
(281) 0x44351c CLTQ |
(281) 0x44351e ADD $0x2,%EDI |
(281) 0x443521 ADD $0x2,%R15D |
(281) 0x443525 LEA (%RCX,%RAX,1),%RDX |
(281) 0x443529 VMOVSD (%RBX,%RDX,8),%XMM14 |
(281) 0x44352e LEA (%RSI,%RAX,1),%RDX |
(281) 0x443532 VMOVSD %XMM14,(%R12,%RDX,8) |
(281) 0x443538 LEA (%R9,%RAX,1),%RDX |
(281) 0x44353c ADD %R10,%RAX |
(281) 0x44353f VMOVSD (%R14,%RDX,8),%XMM15 |
(281) 0x443545 MOV %R10,%RDX |
(281) 0x443548 VMOVSD %XMM15,(%R13,%RAX,8) |
(281) 0x44354f CMP %R11D,%EDI |
(281) 0x443552 JAE 44357b |
(281) 0x443554 MOVSXD %R15D,%RDI |
(281) 0x443557 ADD %RDI,%RCX |
(281) 0x44355a ADD %RDI,%RSI |
(281) 0x44355d ADD %RDI,%R9 |
(281) 0x443560 ADD %RDI,%RDX |
(281) 0x443563 VMOVSD (%RBX,%RCX,8),%XMM5 |
(281) 0x443568 VMOVSD %XMM5,(%R12,%RSI,8) |
(281) 0x44356e VMOVSD (%R14,%R9,8),%XMM6 |
(281) 0x443574 VMOVSD %XMM6,(%R13,%RDX,8) |
(281) 0x44357b MOV 0x38(%RSP),%EDI |
(281) 0x44357f INC %R8 |
(281) 0x443582 LEA (%R8),%EBX |
(281) 0x443585 CMP %EBX,0x10(%RSP) |
(281) 0x443589 JLE 4435b0 |
(281) 0x44358b MOV 0x8(%RSP),%R12D |
(281) 0x443590 MOV 0xc(%RSP),%R14D |
(281) 0x443595 MOV 0x14(%RSP),%R15D |
(281) 0x44359a SUB %EDI,%R12D |
(281) 0x44359d MOV %R14D,0x3c(%RSP) |
(281) 0x4435a2 JMP 443160 |
0x4435a7 NOPW (%RAX,%RAX,1) |
0x4435b0 VZEROUPPER |
0x4435b3 LEA -0x28(%RBP),%RSP |
0x4435b7 POP %RBX |
0x4435b8 POP %R12 |
0x4435ba POP %R13 |
0x4435bc POP %R14 |
0x4435be POP %R15 |
0x4435c0 POP %RBP |
0x4435c1 RET |
0x4435c2 NOPW %CS:(%RAX,%RAX,1) |
0x4435cd NOPL (%RAX) |
(281) 0x4435d0 MOV 0x3c(%RSP),%R15D |
(281) 0x4435d5 XOR %R9D,%R9D |
(281) 0x4435d8 JMP 443465 |
0x4435dd INC %R12D |
0x4435e0 XOR %EDX,%EDX |
0x4435e2 JMP 443103 |
0x4435e7 NOPW (%RAX,%RAX,1) |
Path / |
Source file and lines | revert.cpp:34-38 |
Module | exec |
nb instructions | 77 |
nb uops | 76 |
loop length | 284 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 4 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 6 |
micro-operation queue | 12.67 cycles |
front end | 12.67 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 7.00 | 7.00 | 7.00 | 7.00 | 6.00 | 6.00 | 6.00 | 6.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 |
cycles | 7.00 | 7.00 | 7.00 | 7.00 | 6.00 | 6.00 | 6.00 | 6.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 |
Cycles executing div or sqrt instructions | 12.00 |
Front-end | 12.67 |
Dispatch | 7.00 |
DIV/SQRT | 12.00 |
Overall L1 | 12.67 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 14% |
all | 8% |
load | 10% |
store | 6% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 8% |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %RDI,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
AND $-0x40,%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB $0x40,%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV 0x28(%RDI),%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x2c(%RDI),%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x20(%RDI),%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x24(%R13),%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
ADD $0x2,%EDX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LEA 0x1(%RDI),%EBX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LEA 0x1(%RAX),%R14D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %EDX,0x10(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV %EBX,0xc(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
CMP %EDX,%R14D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JGE 4435b3 <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x533> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV %EDX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x2(%RCX),%R15D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB %R14D,%R12D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP %R15D,%EBX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JGE 4435b3 <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x533> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV %R15D,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SUB %EBX,%ESI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %ESI,0x14(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
CALL 404650 <omp_get_num_threads@plt> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EAX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CALL 404540 <omp_get_thread_num@plt> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x14(%RSP),%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
IMUL %R12D,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %EBX | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 10-17 | 6 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP %EDX,%R8D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JB 4435dd <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x55d> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
IMUL %R12D,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%EDI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LEA (%R12,%RDI,1),%R9D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %R9D,0x8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
CMP %R9D,%EDI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JAE 4435b3 <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x533> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV %EDI,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV 0xc(%RSP),%R10D | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
VMOVQ (%R13),%XMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
DIVL 0x14(%RSP) | 3 | 2 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 10-17 | 6 |
VMOVQ 0x8(%R13),%XMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVQ 0x10(%R13),%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVQ 0x18(%R13),%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R10D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LEA (%RAX,%R14,1),%R11D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB %R10D,%R15D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOVSXD %R11D,%R8 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %R10D,0x3c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
NOPW %CS:(%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
NOP | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
NOPW (%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
VZEROUPPER | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
POP %RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
RET | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
NOPW %CS:(%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
NOPL (%RAX) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
INC %R12D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
JMP 443103 <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x83> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
NOPW (%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
Source file and lines | revert.cpp:34-38 |
Module | exec |
nb instructions | 77 |
nb uops | 76 |
loop length | 284 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 4 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 6 |
micro-operation queue | 12.67 cycles |
front end | 12.67 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 7.00 | 7.00 | 7.00 | 7.00 | 6.00 | 6.00 | 6.00 | 6.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 |
cycles | 7.00 | 7.00 | 7.00 | 7.00 | 6.00 | 6.00 | 6.00 | 6.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 |
Cycles executing div or sqrt instructions | 12.00 |
Front-end | 12.67 |
Dispatch | 7.00 |
DIV/SQRT | 12.00 |
Overall L1 | 12.67 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 14% |
all | 8% |
load | 10% |
store | 6% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 8% |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %RDI,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
AND $-0x40,%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB $0x40,%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV 0x28(%RDI),%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x2c(%RDI),%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x20(%RDI),%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x24(%R13),%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
ADD $0x2,%EDX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LEA 0x1(%RDI),%EBX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LEA 0x1(%RAX),%R14D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %EDX,0x10(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV %EBX,0xc(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
CMP %EDX,%R14D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JGE 4435b3 <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x533> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV %EDX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x2(%RCX),%R15D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB %R14D,%R12D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP %R15D,%EBX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JGE 4435b3 <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x533> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV %R15D,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SUB %EBX,%ESI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %ESI,0x14(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
CALL 404650 <omp_get_num_threads@plt> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EAX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CALL 404540 <omp_get_thread_num@plt> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x14(%RSP),%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
IMUL %R12D,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %EBX | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 10-17 | 6 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP %EDX,%R8D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JB 4435dd <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x55d> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
IMUL %R12D,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%EDI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LEA (%R12,%RDI,1),%R9D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %R9D,0x8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
CMP %R9D,%EDI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JAE 4435b3 <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x533> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV %EDI,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV 0xc(%RSP),%R10D | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
VMOVQ (%R13),%XMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
DIVL 0x14(%RSP) | 3 | 2 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 10-17 | 6 |
VMOVQ 0x8(%R13),%XMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVQ 0x10(%R13),%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVQ 0x18(%R13),%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R10D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LEA (%RAX,%R14,1),%R11D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB %R10D,%R15D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOVSXD %R11D,%R8 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %R10D,0x3c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
NOPW %CS:(%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
NOP | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
NOPW (%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
VZEROUPPER | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
POP %RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
RET | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
NOPW %CS:(%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
NOPL (%RAX) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
INC %R12D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
JMP 443103 <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x83> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
NOPW (%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0– | 2.59 | 1.31 |
▼Loop 281 - revert.cpp:36-38 - exec– | 0 | 0 |
○Loop 282 - revert.cpp:37-38 - exec | 2.59 | 1.3 |