Function: _Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buf ... | Module: exec | Source: advec_mom.cpp:53-57 [...] | Coverage: 2.95% |
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Function: _Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buf ... | Module: exec | Source: advec_mom.cpp:53-57 [...] | Coverage: 2.95% |
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/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp: 53 - 57 |
-------------------------------------------------------------------------------- |
53: #pragma omp parallel for simd collapse(2) |
54: for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) { |
55: for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) { |
56: post_vol(i, j) = volume(i, j) + vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j); |
57: pre_vol(i, j) = post_vol(i, j) + vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j); |
/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69 |
-------------------------------------------------------------------------------- |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
0x42cea0 PUSH %RBP |
0x42cea1 MOV %RSP,%RBP |
0x42cea4 PUSH %R15 |
0x42cea6 PUSH %R14 |
0x42cea8 PUSH %R13 |
0x42ceaa PUSH %R12 |
0x42ceac PUSH %RBX |
0x42cead AND $-0x40,%RSP |
0x42ceb1 ADD $-0x80,%RSP |
0x42ceb5 MOV 0x30(%RDI),%EAX |
0x42ceb8 MOV 0x34(%RDI),%EDX |
0x42cebb MOV 0x28(%RDI),%ESI |
0x42cebe MOV 0x2c(%RDI),%EBX |
0x42cec1 ADD $0x4,%EDX |
0x42cec4 LEA -0x1(%RSI),%ECX |
0x42cec7 LEA -0x1(%RAX),%R15D |
0x42cecb MOV %EDX,0x38(%RSP) |
0x42cecf MOV %ECX,0x34(%RSP) |
0x42ced3 CMP %EDX,%R15D |
0x42ced6 JGE 42d4c3 |
0x42cedc LEA 0x4(%RBX),%R13D |
0x42cee0 MOV %EDX,%EBX |
0x42cee2 SUB %R15D,%EBX |
0x42cee5 CMP %R13D,%ECX |
0x42cee8 JGE 42d4c3 |
0x42ceee MOV %RDI,%R14 |
0x42cef1 MOV %R13D,%EDI |
0x42cef4 SUB %ECX,%EDI |
0x42cef6 MOV %EDI,0x3c(%RSP) |
0x42cefa CALL 404650 <omp_get_num_threads@plt> |
0x42ceff MOV %EAX,%R12D |
0x42cf02 CALL 404540 <omp_get_thread_num@plt> |
0x42cf07 XOR %EDX,%EDX |
0x42cf09 MOV %EAX,%R8D |
0x42cf0c MOV 0x3c(%RSP),%EAX |
0x42cf10 IMUL %EBX,%EAX |
0x42cf13 DIV %R12D |
0x42cf16 MOV %EAX,%ECX |
0x42cf18 CMP %EDX,%R8D |
0x42cf1b JB 42d4fc |
0x42cf21 IMUL %ECX,%R8D |
0x42cf25 LEA (%R8,%RDX,1),%R8D |
0x42cf29 LEA (%RCX,%R8,1),%R9D |
0x42cf2d MOV %R9D,0x30(%RSP) |
0x42cf32 CMP %R9D,%R8D |
0x42cf35 JAE 42d4c3 |
0x42cf3b MOV %R8D,%EAX |
0x42cf3e XOR %EDX,%EDX |
0x42cf40 MOV 0x34(%RSP),%R10D |
0x42cf45 VMOVQ 0x10(%R14),%XMM13 |
0x42cf4b DIVL 0x3c(%RSP) |
0x42cf4f VMOVQ (%R14),%XMM12 |
0x42cf54 VMOVQ 0x20(%R14),%XMM11 |
0x42cf5a VMOVQ 0x8(%R14),%XMM10 |
0x42cf60 VMOVQ 0x18(%R14),%XMM9 |
0x42cf66 ADD %EDX,%R10D |
0x42cf69 LEA (%RAX,%R15,1),%R11D |
0x42cf6d SUB %R10D,%R13D |
0x42cf70 MOVSXD %R11D,%RDI |
0x42cf73 MOV %R10D,0x7c(%RSP) |
0x42cf78 NOPL (%RAX,%RAX,1) |
(179) 0x42cf80 CMP %R13D,%ECX |
(179) 0x42cf83 CMOVA %R13D,%ECX |
(179) 0x42cf87 LEA (%R8,%RCX,1),%R13D |
(179) 0x42cf8b MOV %R13D,0x78(%RSP) |
(179) 0x42cf90 CMP %R13D,%R8D |
(179) 0x42cf93 JAE 42d4e0 |
(179) 0x42cf99 VMOVQ %XMM13,%RSI |
(179) 0x42cf9e VMOVQ %XMM11,%R12 |
(179) 0x42cfa3 LEA 0x1(%RDI),%R15 |
(179) 0x42cfa7 VMOVQ %XMM12,%RBX |
(179) 0x42cfac MOV (%RSI),%R14 |
(179) 0x42cfaf MOV (%R12),%R13 |
(179) 0x42cfb3 VMOVQ %XMM10,%RAX |
(179) 0x42cfb8 MOV (%RBX),%R10 |
(179) 0x42cfbb MOV (%RAX),%R11 |
(179) 0x42cfbe VMOVQ 0x10(%RSI),%XMM18 |
(179) 0x42cfc5 VMOVQ %XMM9,%RSI |
(179) 0x42cfca MOV %R15,0x40(%RSP) |
(179) 0x42cfcf VMOVQ 0x10(%R12),%XMM1 |
(179) 0x42cfd6 VMOVQ 0x10(%RSI),%XMM3 |
(179) 0x42cfdb MOV 0x10(%RBX),%R9 |
(179) 0x42cfdf MOV 0x10(%RAX),%R12 |
(179) 0x42cfe3 IMUL %RDI,%R14 |
(179) 0x42cfe7 IMUL %RDI,%R10 |
(179) 0x42cfeb IMUL %RDI,%R13 |
(179) 0x42cfef IMUL (%RSI),%RDI |
(179) 0x42cff3 MOV %R14,0x48(%RSP) |
(179) 0x42cff8 IMUL %R11,%R15 |
(179) 0x42cffc MOV %R10,0x50(%RSP) |
(179) 0x42d001 MOV %R13,0x58(%RSP) |
(179) 0x42d006 MOV %R15,%RDX |
(179) 0x42d009 MOV %R15,0x68(%RSP) |
(179) 0x42d00e SUB %R11,%RDX |
(179) 0x42d011 MOV %RDI,0x60(%RSP) |
(179) 0x42d016 LEA -0x1(%RCX),%EDI |
(179) 0x42d019 MOV %RDX,0x70(%RSP) |
(179) 0x42d01e CMP $0x6,%EDI |
(179) 0x42d021 JBE 42d4f0 |
(179) 0x42d027 MOVSXD 0x7c(%RSP),%RAX |
(179) 0x42d02c VMOVQ %XMM18,%RSI |
(179) 0x42d032 LEA (%R14,%RAX,1),%R11 |
(179) 0x42d036 LEA (%R13,%RAX,1),%R13 |
(179) 0x42d03b VMOVQ %XMM1,%R14 |
(179) 0x42d040 LEA 0x1(%R10,%RAX,1),%R10 |
(179) 0x42d045 LEA (%R14,%R13,8),%R13 |
(179) 0x42d049 MOV 0x60(%RSP),%R14 |
(179) 0x42d04e LEA (%R15,%RAX,1),%R15 |
(179) 0x42d052 LEA (%RDX,%RAX,1),%RDX |
(179) 0x42d056 LEA (%R12,%R15,8),%RBX |
(179) 0x42d05a VMOVQ %XMM3,%R15 |
(179) 0x42d05f LEA (%RSI,%R11,8),%R11 |
(179) 0x42d063 SAL $0x3,%R10 |
(179) 0x42d067 LEA (%R9,%R10,1),%RSI |
(179) 0x42d06b LEA -0x8(%R9,%R10,1),%RDI |
(179) 0x42d070 LEA (%R12,%RDX,8),%R10 |
(179) 0x42d074 ADD %R14,%RAX |
(179) 0x42d077 LEA (%R15,%RAX,8),%RDX |
(179) 0x42d07b MOV %ECX,%R15D |
(179) 0x42d07e XOR %EAX,%EAX |
(179) 0x42d080 SHR $0x3,%R15D |
(179) 0x42d084 SAL $0x6,%R15 |
(179) 0x42d088 LEA -0x40(%R15),%R14 |
(179) 0x42d08c SHR $0x6,%R14 |
(179) 0x42d090 INC %R14 |
(179) 0x42d093 AND $0x3,%R14D |
(179) 0x42d097 JE 42d160 |
(179) 0x42d09d CMP $0x1,%R14 |
(179) 0x42d0a1 JE 42d11b |
(179) 0x42d0a3 CMP $0x2,%R14 |
(179) 0x42d0a7 JE 42d0df |
(179) 0x42d0a9 VMOVUPD (%R11),%ZMM7 |
(179) 0x42d0af VADDPD (%RSI),%ZMM7,%ZMM0 |
(179) 0x42d0b5 MOV $0x40,%EAX |
(179) 0x42d0ba VSUBPD (%RDI),%ZMM0,%ZMM4 |
(179) 0x42d0c0 VMOVUPD %ZMM4,(%R13) |
(179) 0x42d0c7 VMOVUPD (%RBX),%ZMM2 |
(179) 0x42d0cd VSUBPD (%R10),%ZMM2,%ZMM5 |
(179) 0x42d0d3 VADDPD %ZMM4,%ZMM5,%ZMM6 |
(179) 0x42d0d9 VMOVUPD %ZMM6,(%RDX) |
(179) 0x42d0df VMOVUPD (%R11,%RAX,1),%ZMM8 |
(179) 0x42d0e6 VADDPD (%RSI,%RAX,1),%ZMM8,%ZMM14 |
(179) 0x42d0ed VSUBPD (%RDI,%RAX,1),%ZMM14,%ZMM15 |
(179) 0x42d0f4 VMOVUPD %ZMM15,(%R13,%RAX,1) |
(179) 0x42d0fc VMOVUPD (%RBX,%RAX,1),%ZMM7 |
(179) 0x42d103 VSUBPD (%R10,%RAX,1),%ZMM7,%ZMM0 |
(179) 0x42d10a VADDPD %ZMM15,%ZMM0,%ZMM4 |
(179) 0x42d110 VMOVUPD %ZMM4,(%RDX,%RAX,1) |
(179) 0x42d117 ADD $0x40,%RAX |
(179) 0x42d11b VMOVUPD (%R11,%RAX,1),%ZMM2 |
(179) 0x42d122 VADDPD (%RSI,%RAX,1),%ZMM2,%ZMM5 |
(179) 0x42d129 VSUBPD (%RDI,%RAX,1),%ZMM5,%ZMM6 |
(179) 0x42d130 VMOVUPD %ZMM6,(%R13,%RAX,1) |
(179) 0x42d138 VMOVUPD (%RBX,%RAX,1),%ZMM8 |
(179) 0x42d13f VSUBPD (%R10,%RAX,1),%ZMM8,%ZMM14 |
(179) 0x42d146 VADDPD %ZMM6,%ZMM14,%ZMM15 |
(179) 0x42d14c VMOVUPD %ZMM15,(%RDX,%RAX,1) |
(179) 0x42d153 ADD $0x40,%RAX |
(179) 0x42d157 CMP %RAX,%R15 |
(179) 0x42d15a JE 42d261 |
(180) 0x42d160 VMOVUPD (%R11,%RAX,1),%ZMM7 |
(180) 0x42d167 VADDPD (%RSI,%RAX,1),%ZMM7,%ZMM0 |
(180) 0x42d16e VSUBPD (%RDI,%RAX,1),%ZMM0,%ZMM4 |
(180) 0x42d175 VMOVUPD %ZMM4,(%R13,%RAX,1) |
(180) 0x42d17d VMOVUPD (%RBX,%RAX,1),%ZMM2 |
(180) 0x42d184 VSUBPD (%R10,%RAX,1),%ZMM2,%ZMM5 |
(180) 0x42d18b VADDPD %ZMM4,%ZMM5,%ZMM6 |
(180) 0x42d191 VMOVUPD %ZMM6,(%RDX,%RAX,1) |
(180) 0x42d198 VMOVUPD 0x40(%R11,%RAX,1),%ZMM8 |
(180) 0x42d1a0 VADDPD 0x40(%RSI,%RAX,1),%ZMM8,%ZMM14 |
(180) 0x42d1a8 VSUBPD 0x40(%RDI,%RAX,1),%ZMM14,%ZMM15 |
(180) 0x42d1b0 VMOVUPD %ZMM15,0x40(%R13,%RAX,1) |
(180) 0x42d1b8 VMOVUPD 0x40(%RBX,%RAX,1),%ZMM7 |
(180) 0x42d1c0 VSUBPD 0x40(%R10,%RAX,1),%ZMM7,%ZMM0 |
(180) 0x42d1c8 VADDPD %ZMM15,%ZMM0,%ZMM4 |
(180) 0x42d1ce VMOVUPD %ZMM4,0x40(%RDX,%RAX,1) |
(180) 0x42d1d6 VMOVUPD 0x80(%R11,%RAX,1),%ZMM2 |
(180) 0x42d1de VADDPD 0x80(%RSI,%RAX,1),%ZMM2,%ZMM5 |
(180) 0x42d1e6 VSUBPD 0x80(%RDI,%RAX,1),%ZMM5,%ZMM6 |
(180) 0x42d1ee VMOVUPD %ZMM6,0x80(%R13,%RAX,1) |
(180) 0x42d1f6 VMOVUPD 0x80(%RBX,%RAX,1),%ZMM8 |
(180) 0x42d1fe VSUBPD 0x80(%R10,%RAX,1),%ZMM8,%ZMM14 |
(180) 0x42d206 VADDPD %ZMM6,%ZMM14,%ZMM15 |
(180) 0x42d20c VMOVUPD %ZMM15,0x80(%RDX,%RAX,1) |
(180) 0x42d214 VMOVUPD 0xc0(%R11,%RAX,1),%ZMM7 |
(180) 0x42d21c VADDPD 0xc0(%RSI,%RAX,1),%ZMM7,%ZMM0 |
(180) 0x42d224 VSUBPD 0xc0(%RDI,%RAX,1),%ZMM0,%ZMM4 |
(180) 0x42d22c VMOVUPD %ZMM4,0xc0(%R13,%RAX,1) |
(180) 0x42d234 VMOVUPD 0xc0(%RBX,%RAX,1),%ZMM2 |
(180) 0x42d23c VSUBPD 0xc0(%R10,%RAX,1),%ZMM2,%ZMM5 |
(180) 0x42d244 VADDPD %ZMM4,%ZMM5,%ZMM6 |
(180) 0x42d24a VMOVUPD %ZMM6,0xc0(%RDX,%RAX,1) |
(180) 0x42d252 ADD $0x100,%RAX |
(180) 0x42d258 CMP %RAX,%R15 |
(180) 0x42d25b JNE 42d160 |
(179) 0x42d261 MOV 0x7c(%RSP),%R11D |
(179) 0x42d266 MOV %ECX,%EBX |
(179) 0x42d268 AND $-0x8,%EBX |
(179) 0x42d26b ADD %EBX,%R8D |
(179) 0x42d26e LEA (%RBX,%R11,1),%R14D |
(179) 0x42d272 TEST $0x7,%CL |
(179) 0x42d275 JE 42d492 |
(179) 0x42d27b SUB %EBX,%ECX |
(179) 0x42d27d LEA -0x1(%RCX),%ESI |
(179) 0x42d280 CMP $0x2,%ESI |
(179) 0x42d283 JBE 42d32b |
(179) 0x42d289 MOVSXD 0x7c(%RSP),%R13 |
(179) 0x42d28e MOV 0x50(%RSP),%RDI |
(179) 0x42d293 MOV 0x48(%RSP),%R15 |
(179) 0x42d298 MOV %EBX,%R10D |
(179) 0x42d29b VMOVQ %XMM18,%R11 |
(179) 0x42d2a1 MOV 0x58(%RSP),%RSI |
(179) 0x42d2a6 LEA (%RDI,%R13,1),%RBX |
(179) 0x42d2aa LEA (%R15,%R13,1),%RAX |
(179) 0x42d2ae LEA 0x1(%R10,%RBX,1),%RDX |
(179) 0x42d2b3 ADD %R10,%RAX |
(179) 0x42d2b6 LEA (%RSI,%R13,1),%RDI |
(179) 0x42d2ba VMOVQ %XMM1,%RBX |
(179) 0x42d2bf VMOVUPD (%R9,%RDX,8),%YMM8 |
(179) 0x42d2c5 VSUBPD -0x8(%R9,%RDX,8),%YMM8,%YMM14 |
(179) 0x42d2cc MOV 0x68(%RSP),%RDX |
(179) 0x42d2d1 ADD %R10,%RDI |
(179) 0x42d2d4 VADDPD (%R11,%RAX,8),%YMM14,%YMM15 |
(179) 0x42d2da MOV 0x70(%RSP),%RAX |
(179) 0x42d2df MOV 0x60(%RSP),%RSI |
(179) 0x42d2e4 LEA (%RDX,%R13,1),%R15 |
(179) 0x42d2e8 LEA (%RAX,%R13,1),%R11 |
(179) 0x42d2ec ADD %R10,%R15 |
(179) 0x42d2ef ADD %RSI,%R13 |
(179) 0x42d2f2 ADD %R10,%R11 |
(179) 0x42d2f5 ADD %R10,%R13 |
(179) 0x42d2f8 VMOVQ %XMM3,%R10 |
(179) 0x42d2fd VMOVUPD %YMM15,(%RBX,%RDI,8) |
(179) 0x42d302 VMOVUPD (%R12,%R15,8),%YMM7 |
(179) 0x42d308 VSUBPD (%R12,%R11,8),%YMM7,%YMM0 |
(179) 0x42d30e VADDPD %YMM15,%YMM0,%YMM4 |
(179) 0x42d313 VMOVUPD %YMM4,(%R10,%R13,8) |
(179) 0x42d319 TEST $0x3,%CL |
(179) 0x42d31c JE 42d492 |
(179) 0x42d322 AND $-0x4,%ECX |
(179) 0x42d325 ADD %ECX,%R8D |
(179) 0x42d328 ADD %ECX,%R14D |
(179) 0x42d32b MOV 0x50(%RSP),%RBX |
(179) 0x42d330 LEA 0x1(%R14),%ECX |
(179) 0x42d334 MOV 0x58(%RSP),%R11 |
(179) 0x42d339 MOVSXD %R14D,%RAX |
(179) 0x42d33c MOVSXD %ECX,%RDX |
(179) 0x42d33f VMOVQ %XMM18,%R10 |
(179) 0x42d345 VMOVQ %XMM1,%RCX |
(179) 0x42d34a LEA (%RBX,%RDX,1),%R13 |
(179) 0x42d34e LEA (%RBX,%RAX,1),%R15 |
(179) 0x42d352 LEA (%R9,%R13,8),%RDI |
(179) 0x42d356 LEA (%R11,%RAX,1),%R13 |
(179) 0x42d35a VMOVSD (%RDI),%XMM2 |
(179) 0x42d35e VMOVQ %RDI,%XMM5 |
(179) 0x42d363 MOV 0x48(%RSP),%RDI |
(179) 0x42d368 VSUBSD (%R9,%R15,8),%XMM2,%XMM6 |
(179) 0x42d36e LEA (%RDI,%RAX,1),%RSI |
(179) 0x42d372 VADDSD (%R10,%RSI,8),%XMM6,%XMM8 |
(179) 0x42d378 MOV 0x68(%RSP),%R10 |
(179) 0x42d37d VMOVSD %XMM8,(%RCX,%R13,8) |
(179) 0x42d383 MOV 0x60(%RSP),%R13 |
(179) 0x42d388 MOV 0x70(%RSP),%RCX |
(179) 0x42d38d LEA (%R10,%RAX,1),%RSI |
(179) 0x42d391 LEA (%R13,%RAX,1),%R15 |
(179) 0x42d396 VMOVSD (%R12,%RSI,8),%XMM14 |
(179) 0x42d39c MOV 0x78(%RSP),%ESI |
(179) 0x42d3a0 ADD %RCX,%RAX |
(179) 0x42d3a3 VSUBSD (%R12,%RAX,8),%XMM14,%XMM15 |
(179) 0x42d3a9 VMOVQ %XMM3,%RAX |
(179) 0x42d3ae VADDSD %XMM8,%XMM15,%XMM7 |
(179) 0x42d3b3 VMOVSD %XMM7,(%RAX,%R15,8) |
(179) 0x42d3b9 LEA 0x1(%R8),%R15D |
(179) 0x42d3bd CMP %ESI,%R15D |
(179) 0x42d3c0 JAE 42d492 |
(179) 0x42d3c6 LEA 0x2(%R14),%EAX |
(179) 0x42d3ca LEA (%RDX,%RDI,1),%RSI |
(179) 0x42d3ce ADD $0x2,%R8D |
(179) 0x42d3d2 CLTQ |
(179) 0x42d3d4 LEA (%RBX,%RAX,1),%RCX |
(179) 0x42d3d8 LEA (%R9,%RCX,8),%R15 |
(179) 0x42d3dc VMOVQ %XMM18,%RCX |
(179) 0x42d3e2 VMOVSD (%RCX,%RSI,8),%XMM0 |
(179) 0x42d3e7 VMOVQ %XMM5,%RSI |
(179) 0x42d3ec LEA (%R11,%RDX,1),%RCX |
(179) 0x42d3f0 VADDSD (%R15),%XMM0,%XMM4 |
(179) 0x42d3f5 VSUBSD (%RSI),%XMM4,%XMM5 |
(179) 0x42d3f9 VMOVQ %XMM1,%RSI |
(179) 0x42d3fe VMOVSD %XMM5,(%RSI,%RCX,8) |
(179) 0x42d403 LEA (%R10,%RDX,1),%RSI |
(179) 0x42d407 MOV 0x70(%RSP),%R10 |
(179) 0x42d40c LEA (%R13,%RDX,1),%RCX |
(179) 0x42d411 VMOVSD (%R12,%RSI,8),%XMM2 |
(179) 0x42d417 ADD %R10,%RDX |
(179) 0x42d41a VSUBSD (%R12,%RDX,8),%XMM2,%XMM6 |
(179) 0x42d420 VMOVQ %XMM3,%RDX |
(179) 0x42d425 VADDSD %XMM5,%XMM6,%XMM8 |
(179) 0x42d429 VMOVSD %XMM8,(%RDX,%RCX,8) |
(179) 0x42d42e MOV 0x78(%RSP),%ECX |
(179) 0x42d432 CMP %ECX,%R8D |
(179) 0x42d435 JAE 42d492 |
(179) 0x42d437 ADD $0x3,%R14D |
(179) 0x42d43b ADD %RAX,%RDI |
(179) 0x42d43e ADD %RAX,%R11 |
(179) 0x42d441 ADD %RAX,%R13 |
(179) 0x42d444 MOVSXD %R14D,%R8 |
(179) 0x42d447 VMOVQ %XMM1,%R14 |
(179) 0x42d44c ADD %RBX,%R8 |
(179) 0x42d44f MOV 0x68(%RSP),%RBX |
(179) 0x42d454 VMOVSD (%R9,%R8,8),%XMM14 |
(179) 0x42d45a VMOVQ %XMM18,%R9 |
(179) 0x42d460 VADDSD (%R9,%RDI,8),%XMM14,%XMM15 |
(179) 0x42d466 VSUBSD (%R15),%XMM15,%XMM7 |
(179) 0x42d46b MOV 0x70(%RSP),%R15 |
(179) 0x42d470 VMOVSD %XMM7,(%R14,%R11,8) |
(179) 0x42d476 ADD %RAX,%RBX |
(179) 0x42d479 VMOVSD (%R12,%RBX,8),%XMM1 |
(179) 0x42d47f ADD %RAX,%R15 |
(179) 0x42d482 VSUBSD (%R12,%R15,8),%XMM1,%XMM0 |
(179) 0x42d488 VADDSD %XMM7,%XMM0,%XMM4 |
(179) 0x42d48c VMOVSD %XMM4,(%RDX,%R13,8) |
(179) 0x42d492 MOV 0x78(%RSP),%R8D |
(179) 0x42d497 MOV 0x40(%RSP),%RDI |
(179) 0x42d49c LEA (%RDI),%ESI |
(179) 0x42d49e CMP %ESI,0x38(%RSP) |
(179) 0x42d4a2 JLE 42d4c0 |
(179) 0x42d4a4 MOV 0x30(%RSP),%ECX |
(179) 0x42d4a8 MOV 0x34(%RSP),%R10D |
(179) 0x42d4ad MOV 0x3c(%RSP),%R13D |
(179) 0x42d4b2 SUB %R8D,%ECX |
(179) 0x42d4b5 MOV %R10D,0x7c(%RSP) |
(179) 0x42d4ba JMP 42cf80 |
0x42d4bf NOP |
0x42d4c0 VZEROUPPER |
0x42d4c3 LEA -0x28(%RBP),%RSP |
0x42d4c7 POP %RBX |
0x42d4c8 POP %R12 |
0x42d4ca POP %R13 |
0x42d4cc POP %R14 |
0x42d4ce POP %R15 |
0x42d4d0 POP %RBP |
0x42d4d1 RET |
0x42d4d2 NOPW %CS:(%RAX,%RAX,1) |
0x42d4dd NOPL (%RAX) |
(179) 0x42d4e0 LEA 0x1(%RDI),%R15 |
(179) 0x42d4e4 MOV %R15,0x40(%RSP) |
(179) 0x42d4e9 JMP 42d497 |
0x42d4eb NOPL (%RAX,%RAX,1) |
(179) 0x42d4f0 MOV 0x7c(%RSP),%R14D |
(179) 0x42d4f5 XOR %EBX,%EBX |
(179) 0x42d4f7 JMP 42d27b |
0x42d4fc INC %ECX |
0x42d4fe XOR %EDX,%EDX |
0x42d500 JMP 42cf21 |
0x42d505 NOPW %CS:(%RAX,%RAX,1) |
Path / |
Source file and lines | advec_mom.cpp:53-57 |
Module | exec |
nb instructions | 78 |
nb uops | 77 |
loop length | 282 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 5 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 6 |
micro-operation queue | 12.83 cycles |
front end | 12.83 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 7.00 | 7.00 | 7.00 | 7.00 | 6.00 | 6.33 | 6.33 | 6.33 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 |
cycles | 7.00 | 7.00 | 7.00 | 7.00 | 6.00 | 6.33 | 6.33 | 6.33 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 |
Cycles executing div or sqrt instructions | 12.00 |
Front-end | 12.83 |
Dispatch | 7.00 |
DIV/SQRT | 12.00 |
Overall L1 | 12.83 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 16% |
all | 8% |
load | 10% |
store | 6% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 9% |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
AND $-0x40,%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD $-0x80,%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV 0x30(%RDI),%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x34(%RDI),%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x28(%RDI),%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x2c(%RDI),%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
ADD $0x4,%EDX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LEA -0x1(%RSI),%ECX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LEA -0x1(%RAX),%R15D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %EDX,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV %ECX,0x34(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
CMP %EDX,%R15D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JGE 42d4c3 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x623> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
LEA 0x4(%RBX),%R13D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SUB %R15D,%EBX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP %R13D,%ECX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JGE 42d4c3 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x623> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV %RDI,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R13D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SUB %ECX,%EDI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %EDI,0x3c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
CALL 404650 <omp_get_num_threads@plt> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CALL 404540 <omp_get_thread_num@plt> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x3c(%RSP),%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 10-17 | 6 |
MOV %EAX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP %EDX,%R8D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JB 42d4fc <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x65c> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
IMUL %ECX,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%R8D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LEA (%RCX,%R8,1),%R9D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %R9D,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
CMP %R9D,%R8D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JAE 42d4c3 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x623> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV %R8D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV 0x34(%RSP),%R10D | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
VMOVQ 0x10(%R14),%XMM13 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
DIVL 0x3c(%RSP) | 3 | 2 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 10-17 | 6 |
VMOVQ (%R14),%XMM12 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVQ 0x20(%R14),%XMM11 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVQ 0x8(%R14),%XMM10 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVQ 0x18(%R14),%XMM9 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R10D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LEA (%RAX,%R15,1),%R11D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB %R10D,%R13D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOVSXD %R11D,%RDI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %R10D,0x7c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
NOPL (%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
NOP | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
VZEROUPPER | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
POP %RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
RET | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
NOPW %CS:(%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
NOPL (%RAX) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
NOPL (%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
INC %ECX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
JMP 42cf21 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x81> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
NOPW %CS:(%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
Source file and lines | advec_mom.cpp:53-57 |
Module | exec |
nb instructions | 78 |
nb uops | 77 |
loop length | 282 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 5 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 6 |
micro-operation queue | 12.83 cycles |
front end | 12.83 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 7.00 | 7.00 | 7.00 | 7.00 | 6.00 | 6.33 | 6.33 | 6.33 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 |
cycles | 7.00 | 7.00 | 7.00 | 7.00 | 6.00 | 6.33 | 6.33 | 6.33 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 |
Cycles executing div or sqrt instructions | 12.00 |
Front-end | 12.83 |
Dispatch | 7.00 |
DIV/SQRT | 12.00 |
Overall L1 | 12.83 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 16% |
all | 8% |
load | 10% |
store | 6% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 9% |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
AND $-0x40,%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD $-0x80,%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV 0x30(%RDI),%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x34(%RDI),%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x28(%RDI),%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x2c(%RDI),%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
ADD $0x4,%EDX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LEA -0x1(%RSI),%ECX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LEA -0x1(%RAX),%R15D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %EDX,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV %ECX,0x34(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
CMP %EDX,%R15D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JGE 42d4c3 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x623> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
LEA 0x4(%RBX),%R13D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SUB %R15D,%EBX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP %R13D,%ECX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JGE 42d4c3 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x623> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV %RDI,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R13D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SUB %ECX,%EDI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %EDI,0x3c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
CALL 404650 <omp_get_num_threads@plt> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CALL 404540 <omp_get_thread_num@plt> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x3c(%RSP),%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 10-17 | 6 |
MOV %EAX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP %EDX,%R8D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JB 42d4fc <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x65c> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
IMUL %ECX,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%R8D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LEA (%RCX,%R8,1),%R9D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %R9D,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
CMP %R9D,%R8D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JAE 42d4c3 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x623> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV %R8D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV 0x34(%RSP),%R10D | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
VMOVQ 0x10(%R14),%XMM13 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
DIVL 0x3c(%RSP) | 3 | 2 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 10-17 | 6 |
VMOVQ (%R14),%XMM12 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVQ 0x20(%R14),%XMM11 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVQ 0x8(%R14),%XMM10 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVQ 0x18(%R14),%XMM9 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R10D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LEA (%RAX,%R15,1),%R11D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB %R10D,%R13D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOVSXD %R11D,%RDI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %R10D,0x7c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
NOPL (%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
NOP | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
VZEROUPPER | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
POP %RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
RET | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
NOPW %CS:(%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
NOPL (%RAX) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
NOPL (%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
INC %ECX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
JMP 42cf21 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x81> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
NOPW %CS:(%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1– | 2.95 | 1.49 |
▼Loop 179 - advec_mom.cpp:53-57 - exec– | 0 | 0 |
○Loop 180 - advec_mom.cpp:56-57 - exec | 2.95 | 1.48 |