Function: _Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0 | Module: exec | Source: reset_field.cpp:34-38 [...] | Coverage: 2.53% |
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Function: _Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0 | Module: exec | Source: reset_field.cpp:34-38 [...] | Coverage: 2.53% |
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/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/reset_field.cpp: 34 - 38 |
-------------------------------------------------------------------------------- |
34: #pragma omp parallel for simd collapse(2) |
35: for (int j = (y_min + 1); j < (y_max + 2); j++) { |
36: for (int i = (x_min + 1); i < (x_max + 2); i++) { |
37: density0(i, j) = density1(i, j); |
38: energy0(i, j) = energy1(i, j); |
/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69 |
-------------------------------------------------------------------------------- |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
0x442920 PUSH %RBP |
0x442921 MOV %RSP,%RBP |
0x442924 PUSH %R15 |
0x442926 PUSH %R14 |
0x442928 PUSH %R13 |
0x44292a PUSH %R12 |
0x44292c PUSH %RBX |
0x44292d MOV %RDI,%R13 |
0x442930 AND $-0x40,%RSP |
0x442934 SUB $0x40,%RSP |
0x442938 MOV 0x28(%RDI),%EAX |
0x44293b MOV 0x2c(%RDI),%EDX |
0x44293e MOV 0x20(%RDI),%EDI |
0x442941 MOV 0x24(%R13),%ECX |
0x442945 ADD $0x2,%EDX |
0x442948 LEA 0x1(%RDI),%EBX |
0x44294b LEA 0x1(%RAX),%R14D |
0x44294f MOV %EDX,0x10(%RSP) |
0x442953 MOV %EBX,0xc(%RSP) |
0x442957 CMP %EDX,%R14D |
0x44295a JGE 442e53 |
0x442960 MOV %EDX,%R12D |
0x442963 LEA 0x2(%RCX),%R15D |
0x442967 SUB %R14D,%R12D |
0x44296a CMP %R15D,%EBX |
0x44296d JGE 442e53 |
0x442973 MOV %R15D,%ESI |
0x442976 SUB %EBX,%ESI |
0x442978 MOV %ESI,0x14(%RSP) |
0x44297c CALL 404650 <omp_get_num_threads@plt> |
0x442981 MOV %EAX,%EBX |
0x442983 CALL 404540 <omp_get_thread_num@plt> |
0x442988 XOR %EDX,%EDX |
0x44298a MOV %EAX,%R8D |
0x44298d MOV 0x14(%RSP),%EAX |
0x442991 IMUL %R12D,%EAX |
0x442995 DIV %EBX |
0x442997 MOV %EAX,%R12D |
0x44299a CMP %EDX,%R8D |
0x44299d JB 442e7d |
0x4429a3 IMUL %R12D,%R8D |
0x4429a7 LEA (%R8,%RDX,1),%EDI |
0x4429ab LEA (%R12,%RDI,1),%R9D |
0x4429af MOV %R9D,0x8(%RSP) |
0x4429b4 CMP %R9D,%EDI |
0x4429b7 JAE 442e53 |
0x4429bd MOV %EDI,%EAX |
0x4429bf XOR %EDX,%EDX |
0x4429c1 MOV 0xc(%RSP),%R10D |
0x4429c6 VMOVQ 0x8(%R13),%XMM3 |
0x4429cc DIVL 0x14(%RSP) |
0x4429d0 VMOVQ (%R13),%XMM4 |
0x4429d6 VMOVQ 0x18(%R13),%XMM2 |
0x4429dc VMOVQ 0x10(%R13),%XMM1 |
0x4429e2 ADD %EDX,%R10D |
0x4429e5 LEA (%RAX,%R14,1),%R11D |
0x4429e9 SUB %R10D,%R15D |
0x4429ec MOVSXD %R11D,%R8 |
0x4429ef MOV %R10D,0x3c(%RSP) |
0x4429f4 NOPW %CS:(%RAX,%RAX,1) |
0x4429ff NOP |
(278) 0x442a00 CMP %R15D,%R12D |
(278) 0x442a03 MOV %R15D,%ECX |
(278) 0x442a06 CMOVBE %R12D,%ECX |
(278) 0x442a0a LEA (%RDI,%RCX,1),%R15D |
(278) 0x442a0e MOV %R15D,0x38(%RSP) |
(278) 0x442a13 CMP %R15D,%EDI |
(278) 0x442a16 JAE 442e1f |
(278) 0x442a1c VMOVQ %XMM3,%R13 |
(278) 0x442a21 VMOVQ %XMM4,%R14 |
(278) 0x442a26 VMOVQ %XMM2,%RSI |
(278) 0x442a2b VMOVQ %XMM1,%RAX |
(278) 0x442a30 MOV (%R13),%RDX |
(278) 0x442a34 MOV (%R14),%R9 |
(278) 0x442a37 MOV (%RSI),%R15 |
(278) 0x442a3a MOV (%RAX),%R11 |
(278) 0x442a3d MOV 0x10(%R14),%R12 |
(278) 0x442a41 MOV 0x10(%RSI),%R14 |
(278) 0x442a45 LEA -0x1(%RCX),%ESI |
(278) 0x442a48 MOV 0x10(%R13),%RBX |
(278) 0x442a4c MOV 0x10(%RAX),%R13 |
(278) 0x442a50 IMUL %R8,%RDX |
(278) 0x442a54 IMUL %R8,%R9 |
(278) 0x442a58 IMUL %R8,%R15 |
(278) 0x442a5c IMUL %R8,%R11 |
(278) 0x442a60 MOV %RDX,0x18(%RSP) |
(278) 0x442a65 MOV %R9,0x20(%RSP) |
(278) 0x442a6a MOV %R15,0x28(%RSP) |
(278) 0x442a6f MOV %R11,0x30(%RSP) |
(278) 0x442a74 CMP $0x6,%ESI |
(278) 0x442a77 JBE 442e70 |
(278) 0x442a7d MOVSXD 0x3c(%RSP),%RAX |
(278) 0x442a82 LEA (%R15,%RAX,1),%RSI |
(278) 0x442a86 MOV 0x30(%RSP),%R15 |
(278) 0x442a8b LEA (%RDX,%RAX,1),%RDX |
(278) 0x442a8f LEA (%R9,%RAX,1),%R10 |
(278) 0x442a93 LEA (%R14,%RSI,8),%R9 |
(278) 0x442a97 LEA (%RBX,%RDX,8),%R11 |
(278) 0x442a9b LEA (%R12,%R10,8),%R10 |
(278) 0x442a9f ADD %R15,%RAX |
(278) 0x442aa2 MOV %ECX,%R15D |
(278) 0x442aa5 SHR $0x3,%R15D |
(278) 0x442aa9 SAL $0x6,%R15 |
(278) 0x442aad LEA -0x40(%R15),%RSI |
(278) 0x442ab1 LEA (%R13,%RAX,8),%RDX |
(278) 0x442ab6 XOR %EAX,%EAX |
(278) 0x442ab8 SHR $0x6,%RSI |
(278) 0x442abc INC %RSI |
(278) 0x442abf AND $0x7,%ESI |
(278) 0x442ac2 JE 442bde |
(278) 0x442ac8 CMP $0x1,%RSI |
(278) 0x442acc JE 442bb5 |
(278) 0x442ad2 CMP $0x2,%RSI |
(278) 0x442ad6 JE 442b95 |
(278) 0x442adc CMP $0x3,%RSI |
(278) 0x442ae0 JE 442b75 |
(278) 0x442ae6 CMP $0x4,%RSI |
(278) 0x442aea JE 442b55 |
(278) 0x442aec CMP $0x5,%RSI |
(278) 0x442af0 JE 442b35 |
(278) 0x442af2 CMP $0x6,%RSI |
(278) 0x442af6 JE 442b15 |
(278) 0x442af8 VMOVUPD (%R11),%ZMM5 |
(278) 0x442afe MOV $0x40,%EAX |
(278) 0x442b03 VMOVUPD %ZMM5,(%R10) |
(278) 0x442b09 VMOVUPD (%R9),%ZMM6 |
(278) 0x442b0f VMOVUPD %ZMM6,(%RDX) |
(278) 0x442b15 VMOVUPD (%R11,%RAX,1),%ZMM7 |
(278) 0x442b1c VMOVUPD %ZMM7,(%R10,%RAX,1) |
(278) 0x442b23 VMOVUPD (%R9,%RAX,1),%ZMM0 |
(278) 0x442b2a VMOVUPD %ZMM0,(%RDX,%RAX,1) |
(278) 0x442b31 ADD $0x40,%RAX |
(278) 0x442b35 VMOVUPD (%R11,%RAX,1),%ZMM8 |
(278) 0x442b3c VMOVUPD %ZMM8,(%R10,%RAX,1) |
(278) 0x442b43 VMOVUPD (%R9,%RAX,1),%ZMM9 |
(278) 0x442b4a VMOVUPD %ZMM9,(%RDX,%RAX,1) |
(278) 0x442b51 ADD $0x40,%RAX |
(278) 0x442b55 VMOVUPD (%R11,%RAX,1),%ZMM10 |
(278) 0x442b5c VMOVUPD %ZMM10,(%R10,%RAX,1) |
(278) 0x442b63 VMOVUPD (%R9,%RAX,1),%ZMM11 |
(278) 0x442b6a VMOVUPD %ZMM11,(%RDX,%RAX,1) |
(278) 0x442b71 ADD $0x40,%RAX |
(278) 0x442b75 VMOVUPD (%R11,%RAX,1),%ZMM12 |
(278) 0x442b7c VMOVUPD %ZMM12,(%R10,%RAX,1) |
(278) 0x442b83 VMOVUPD (%R9,%RAX,1),%ZMM13 |
(278) 0x442b8a VMOVUPD %ZMM13,(%RDX,%RAX,1) |
(278) 0x442b91 ADD $0x40,%RAX |
(278) 0x442b95 VMOVUPD (%R11,%RAX,1),%ZMM14 |
(278) 0x442b9c VMOVUPD %ZMM14,(%R10,%RAX,1) |
(278) 0x442ba3 VMOVUPD (%R9,%RAX,1),%ZMM15 |
(278) 0x442baa VMOVUPD %ZMM15,(%RDX,%RAX,1) |
(278) 0x442bb1 ADD $0x40,%RAX |
(278) 0x442bb5 VMOVUPD (%R11,%RAX,1),%ZMM5 |
(278) 0x442bbc VMOVUPD %ZMM5,(%R10,%RAX,1) |
(278) 0x442bc3 VMOVUPD (%R9,%RAX,1),%ZMM6 |
(278) 0x442bca VMOVUPD %ZMM6,(%RDX,%RAX,1) |
(278) 0x442bd1 ADD $0x40,%RAX |
(278) 0x442bd5 CMP %RAX,%R15 |
(278) 0x442bd8 JE 442ce9 |
(279) 0x442bde VMOVUPD (%R11,%RAX,1),%ZMM7 |
(279) 0x442be5 VMOVUPD %ZMM7,(%R10,%RAX,1) |
(279) 0x442bec VMOVUPD (%R9,%RAX,1),%ZMM0 |
(279) 0x442bf3 VMOVUPD %ZMM0,(%RDX,%RAX,1) |
(279) 0x442bfa VMOVUPD 0x40(%R11,%RAX,1),%ZMM8 |
(279) 0x442c02 VMOVUPD %ZMM8,0x40(%R10,%RAX,1) |
(279) 0x442c0a VMOVUPD 0x40(%R9,%RAX,1),%ZMM9 |
(279) 0x442c12 VMOVUPD %ZMM9,0x40(%RDX,%RAX,1) |
(279) 0x442c1a VMOVUPD 0x80(%R11,%RAX,1),%ZMM10 |
(279) 0x442c22 VMOVUPD %ZMM10,0x80(%R10,%RAX,1) |
(279) 0x442c2a VMOVUPD 0x80(%R9,%RAX,1),%ZMM11 |
(279) 0x442c32 VMOVUPD %ZMM11,0x80(%RDX,%RAX,1) |
(279) 0x442c3a VMOVUPD 0xc0(%R11,%RAX,1),%ZMM12 |
(279) 0x442c42 VMOVUPD %ZMM12,0xc0(%R10,%RAX,1) |
(279) 0x442c4a VMOVUPD 0xc0(%R9,%RAX,1),%ZMM13 |
(279) 0x442c52 VMOVUPD %ZMM13,0xc0(%RDX,%RAX,1) |
(279) 0x442c5a VMOVUPD 0x100(%R11,%RAX,1),%ZMM14 |
(279) 0x442c62 VMOVUPD %ZMM14,0x100(%R10,%RAX,1) |
(279) 0x442c6a VMOVUPD 0x100(%R9,%RAX,1),%ZMM15 |
(279) 0x442c72 VMOVUPD %ZMM15,0x100(%RDX,%RAX,1) |
(279) 0x442c7a VMOVUPD 0x140(%R11,%RAX,1),%ZMM5 |
(279) 0x442c82 VMOVUPD %ZMM5,0x140(%R10,%RAX,1) |
(279) 0x442c8a VMOVUPD 0x140(%R9,%RAX,1),%ZMM6 |
(279) 0x442c92 VMOVUPD %ZMM6,0x140(%RDX,%RAX,1) |
(279) 0x442c9a VMOVUPD 0x180(%R11,%RAX,1),%ZMM7 |
(279) 0x442ca2 VMOVUPD %ZMM7,0x180(%R10,%RAX,1) |
(279) 0x442caa VMOVUPD 0x180(%R9,%RAX,1),%ZMM0 |
(279) 0x442cb2 VMOVUPD %ZMM0,0x180(%RDX,%RAX,1) |
(279) 0x442cba VMOVUPD 0x1c0(%R11,%RAX,1),%ZMM8 |
(279) 0x442cc2 VMOVUPD %ZMM8,0x1c0(%R10,%RAX,1) |
(279) 0x442cca VMOVUPD 0x1c0(%R9,%RAX,1),%ZMM9 |
(279) 0x442cd2 VMOVUPD %ZMM9,0x1c0(%RDX,%RAX,1) |
(279) 0x442cda ADD $0x200,%RAX |
(279) 0x442ce0 CMP %RAX,%R15 |
(279) 0x442ce3 JNE 442bde |
(278) 0x442ce9 MOV 0x3c(%RSP),%R11D |
(278) 0x442cee MOV %ECX,%R9D |
(278) 0x442cf1 AND $-0x8,%R9D |
(278) 0x442cf5 ADD %R9D,%EDI |
(278) 0x442cf8 LEA (%R9,%R11,1),%R15D |
(278) 0x442cfc TEST $0x7,%CL |
(278) 0x442cff JE 442e1b |
(278) 0x442d05 SUB %R9D,%ECX |
(278) 0x442d08 LEA -0x1(%RCX),%R10D |
(278) 0x442d0c CMP $0x2,%R10D |
(278) 0x442d10 JBE 442d6c |
(278) 0x442d12 MOVSXD 0x3c(%RSP),%RSI |
(278) 0x442d17 MOV 0x18(%RSP),%RDX |
(278) 0x442d1c MOV 0x20(%RSP),%RAX |
(278) 0x442d21 MOV 0x28(%RSP),%R11 |
(278) 0x442d26 MOV 0x30(%RSP),%R10 |
(278) 0x442d2b ADD %RSI,%RDX |
(278) 0x442d2e ADD %RSI,%RAX |
(278) 0x442d31 ADD %R9,%RDX |
(278) 0x442d34 ADD %RSI,%R11 |
(278) 0x442d37 ADD %R9,%RAX |
(278) 0x442d3a ADD %R10,%RSI |
(278) 0x442d3d VMOVUPD (%RBX,%RDX,8),%YMM10 |
(278) 0x442d42 ADD %R9,%R11 |
(278) 0x442d45 ADD %R9,%RSI |
(278) 0x442d48 VMOVUPD %YMM10,(%R12,%RAX,8) |
(278) 0x442d4e VMOVUPD (%R14,%R11,8),%YMM11 |
(278) 0x442d54 VMOVUPD %YMM11,(%R13,%RSI,8) |
(278) 0x442d5b TEST $0x3,%CL |
(278) 0x442d5e JE 442e1b |
(278) 0x442d64 AND $-0x4,%ECX |
(278) 0x442d67 ADD %ECX,%EDI |
(278) 0x442d69 ADD %ECX,%R15D |
(278) 0x442d6c MOV 0x18(%RSP),%RCX |
(278) 0x442d71 MOVSXD %R15D,%RAX |
(278) 0x442d74 MOV 0x20(%RSP),%RSI |
(278) 0x442d79 MOV 0x30(%RSP),%R10 |
(278) 0x442d7e LEA (%RCX,%RAX,1),%R9 |
(278) 0x442d82 LEA (%RSI,%RAX,1),%RDX |
(278) 0x442d86 VMOVSD (%RBX,%R9,8),%XMM12 |
(278) 0x442d8c MOV 0x28(%RSP),%R9 |
(278) 0x442d91 VMOVSD %XMM12,(%R12,%RDX,8) |
(278) 0x442d97 LEA 0x1(%RDI),%EDX |
(278) 0x442d9a LEA (%R9,%RAX,1),%R11 |
(278) 0x442d9e ADD %R10,%RAX |
(278) 0x442da1 VMOVSD (%R14,%R11,8),%XMM13 |
(278) 0x442da7 MOV 0x38(%RSP),%R11D |
(278) 0x442dac VMOVSD %XMM13,(%R13,%RAX,8) |
(278) 0x442db3 LEA 0x1(%R15),%EAX |
(278) 0x442db7 CMP %R11D,%EDX |
(278) 0x442dba JAE 442e1b |
(278) 0x442dbc CLTQ |
(278) 0x442dbe ADD $0x2,%EDI |
(278) 0x442dc1 ADD $0x2,%R15D |
(278) 0x442dc5 LEA (%RCX,%RAX,1),%RDX |
(278) 0x442dc9 VMOVSD (%RBX,%RDX,8),%XMM14 |
(278) 0x442dce LEA (%RSI,%RAX,1),%RDX |
(278) 0x442dd2 VMOVSD %XMM14,(%R12,%RDX,8) |
(278) 0x442dd8 LEA (%R9,%RAX,1),%RDX |
(278) 0x442ddc ADD %R10,%RAX |
(278) 0x442ddf VMOVSD (%R14,%RDX,8),%XMM15 |
(278) 0x442de5 MOV %R10,%RDX |
(278) 0x442de8 VMOVSD %XMM15,(%R13,%RAX,8) |
(278) 0x442def CMP %R11D,%EDI |
(278) 0x442df2 JAE 442e1b |
(278) 0x442df4 MOVSXD %R15D,%RDI |
(278) 0x442df7 ADD %RDI,%RCX |
(278) 0x442dfa ADD %RDI,%RSI |
(278) 0x442dfd ADD %RDI,%R9 |
(278) 0x442e00 ADD %RDI,%RDX |
(278) 0x442e03 VMOVSD (%RBX,%RCX,8),%XMM5 |
(278) 0x442e08 VMOVSD %XMM5,(%R12,%RSI,8) |
(278) 0x442e0e VMOVSD (%R14,%R9,8),%XMM6 |
(278) 0x442e14 VMOVSD %XMM6,(%R13,%RDX,8) |
(278) 0x442e1b MOV 0x38(%RSP),%EDI |
(278) 0x442e1f INC %R8 |
(278) 0x442e22 LEA (%R8),%EBX |
(278) 0x442e25 CMP %EBX,0x10(%RSP) |
(278) 0x442e29 JLE 442e50 |
(278) 0x442e2b MOV 0x8(%RSP),%R12D |
(278) 0x442e30 MOV 0xc(%RSP),%R14D |
(278) 0x442e35 MOV 0x14(%RSP),%R15D |
(278) 0x442e3a SUB %EDI,%R12D |
(278) 0x442e3d MOV %R14D,0x3c(%RSP) |
(278) 0x442e42 JMP 442a00 |
0x442e47 NOPW (%RAX,%RAX,1) |
0x442e50 VZEROUPPER |
0x442e53 LEA -0x28(%RBP),%RSP |
0x442e57 POP %RBX |
0x442e58 POP %R12 |
0x442e5a POP %R13 |
0x442e5c POP %R14 |
0x442e5e POP %R15 |
0x442e60 POP %RBP |
0x442e61 RET |
0x442e62 NOPW %CS:(%RAX,%RAX,1) |
0x442e6d NOPL (%RAX) |
(278) 0x442e70 MOV 0x3c(%RSP),%R15D |
(278) 0x442e75 XOR %R9D,%R9D |
(278) 0x442e78 JMP 442d05 |
0x442e7d INC %R12D |
0x442e80 XOR %EDX,%EDX |
0x442e82 JMP 4429a3 |
0x442e87 NOPW (%RAX,%RAX,1) |
Path / |
Source file and lines | reset_field.cpp:34-38 |
Module | exec |
nb instructions | 77 |
nb uops | 76 |
loop length | 284 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 4 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 6 |
micro-operation queue | 12.67 cycles |
front end | 12.67 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 7.00 | 7.00 | 7.00 | 7.00 | 6.00 | 6.00 | 6.00 | 6.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 |
cycles | 7.00 | 7.00 | 7.00 | 7.00 | 6.00 | 6.00 | 6.00 | 6.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 |
Cycles executing div or sqrt instructions | 12.00 |
Front-end | 12.67 |
Dispatch | 7.00 |
DIV/SQRT | 12.00 |
Overall L1 | 12.67 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 14% |
all | 8% |
load | 10% |
store | 6% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 8% |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %RDI,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
AND $-0x40,%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB $0x40,%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV 0x28(%RDI),%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x2c(%RDI),%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x20(%RDI),%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x24(%R13),%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
ADD $0x2,%EDX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LEA 0x1(%RDI),%EBX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LEA 0x1(%RAX),%R14D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %EDX,0x10(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV %EBX,0xc(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
CMP %EDX,%R14D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JGE 442e53 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x533> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV %EDX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x2(%RCX),%R15D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB %R14D,%R12D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP %R15D,%EBX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JGE 442e53 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x533> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV %R15D,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SUB %EBX,%ESI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %ESI,0x14(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
CALL 404650 <omp_get_num_threads@plt> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EAX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CALL 404540 <omp_get_thread_num@plt> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x14(%RSP),%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
IMUL %R12D,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %EBX | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 10-17 | 6 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP %EDX,%R8D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JB 442e7d <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x55d> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
IMUL %R12D,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%EDI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LEA (%R12,%RDI,1),%R9D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %R9D,0x8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
CMP %R9D,%EDI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JAE 442e53 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x533> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV %EDI,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV 0xc(%RSP),%R10D | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
VMOVQ 0x8(%R13),%XMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
DIVL 0x14(%RSP) | 3 | 2 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 10-17 | 6 |
VMOVQ (%R13),%XMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVQ 0x18(%R13),%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVQ 0x10(%R13),%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R10D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LEA (%RAX,%R14,1),%R11D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB %R10D,%R15D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOVSXD %R11D,%R8 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %R10D,0x3c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
NOPW %CS:(%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
NOP | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
NOPW (%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
VZEROUPPER | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
POP %RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
RET | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
NOPW %CS:(%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
NOPL (%RAX) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
INC %R12D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
JMP 4429a3 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x83> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
NOPW (%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
Source file and lines | reset_field.cpp:34-38 |
Module | exec |
nb instructions | 77 |
nb uops | 76 |
loop length | 284 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 4 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 6 |
micro-operation queue | 12.67 cycles |
front end | 12.67 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 7.00 | 7.00 | 7.00 | 7.00 | 6.00 | 6.00 | 6.00 | 6.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 |
cycles | 7.00 | 7.00 | 7.00 | 7.00 | 6.00 | 6.00 | 6.00 | 6.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 |
Cycles executing div or sqrt instructions | 12.00 |
Front-end | 12.67 |
Dispatch | 7.00 |
DIV/SQRT | 12.00 |
Overall L1 | 12.67 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 14% |
all | 8% |
load | 10% |
store | 6% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 8% |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %RDI,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
AND $-0x40,%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB $0x40,%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV 0x28(%RDI),%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x2c(%RDI),%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x20(%RDI),%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x24(%R13),%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
ADD $0x2,%EDX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LEA 0x1(%RDI),%EBX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LEA 0x1(%RAX),%R14D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %EDX,0x10(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV %EBX,0xc(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
CMP %EDX,%R14D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JGE 442e53 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x533> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV %EDX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x2(%RCX),%R15D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB %R14D,%R12D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP %R15D,%EBX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JGE 442e53 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x533> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV %R15D,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SUB %EBX,%ESI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %ESI,0x14(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
CALL 404650 <omp_get_num_threads@plt> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EAX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CALL 404540 <omp_get_thread_num@plt> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x14(%RSP),%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
IMUL %R12D,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %EBX | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 10-17 | 6 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP %EDX,%R8D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JB 442e7d <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x55d> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
IMUL %R12D,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%EDI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LEA (%R12,%RDI,1),%R9D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %R9D,0x8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
CMP %R9D,%EDI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JAE 442e53 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x533> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV %EDI,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV 0xc(%RSP),%R10D | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
VMOVQ 0x8(%R13),%XMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
DIVL 0x14(%RSP) | 3 | 2 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 10-17 | 6 |
VMOVQ (%R13),%XMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVQ 0x18(%R13),%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVQ 0x10(%R13),%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R10D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LEA (%RAX,%R14,1),%R11D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB %R10D,%R15D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOVSXD %R11D,%R8 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %R10D,0x3c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
NOPW %CS:(%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
NOP | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
NOPW (%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
VZEROUPPER | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
POP %RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
RET | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
NOPW %CS:(%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
NOPL (%RAX) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
INC %R12D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
JMP 4429a3 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x83> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
NOPW (%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0– | 2.53 | 1.27 |
▼Loop 278 - reset_field.cpp:36-38 - exec– | 0 | 0 |
○Loop 279 - reset_field.cpp:37-38 - exec | 2.53 | 1.27 |