Function: _Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1 | Module: exec | Source: reset_field.cpp:44-48 [...] | Coverage: 2.6% |
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Function: _Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1 | Module: exec | Source: reset_field.cpp:44-48 [...] | Coverage: 2.6% |
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/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/reset_field.cpp: 44 - 48 |
-------------------------------------------------------------------------------- |
44: #pragma omp parallel for simd collapse(2) |
45: for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) { |
46: for (int i = (x_min + 1); i < (x_max + 1 + 2); i++) { |
47: xvel0(i, j) = xvel1(i, j); |
48: yvel0(i, j) = yvel1(i, j); |
/beegfs/hackathon/users/eoseret/qaas_runs/170-854-8685/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69 |
-------------------------------------------------------------------------------- |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
0x4423b0 PUSH %RBP |
0x4423b1 MOV %RSP,%RBP |
0x4423b4 PUSH %R15 |
0x4423b6 PUSH %R14 |
0x4423b8 PUSH %R13 |
0x4423ba PUSH %R12 |
0x4423bc PUSH %RBX |
0x4423bd MOV %RDI,%R13 |
0x4423c0 AND $-0x40,%RSP |
0x4423c4 SUB $0x40,%RSP |
0x4423c8 MOV 0x28(%RDI),%EAX |
0x4423cb MOV 0x2c(%RDI),%EDX |
0x4423ce MOV 0x20(%RDI),%EDI |
0x4423d1 MOV 0x24(%R13),%ECX |
0x4423d5 ADD $0x3,%EDX |
0x4423d8 LEA 0x1(%RDI),%EBX |
0x4423db LEA 0x1(%RAX),%R14D |
0x4423df MOV %EDX,0x10(%RSP) |
0x4423e3 MOV %EBX,0xc(%RSP) |
0x4423e7 CMP %EDX,%R14D |
0x4423ea JGE 4428e3 |
0x4423f0 MOV %EDX,%R12D |
0x4423f3 LEA 0x3(%RCX),%R15D |
0x4423f7 SUB %R14D,%R12D |
0x4423fa CMP %R15D,%EBX |
0x4423fd JGE 4428e3 |
0x442403 MOV %R15D,%ESI |
0x442406 SUB %EBX,%ESI |
0x442408 MOV %ESI,0x14(%RSP) |
0x44240c CALL 404650 <omp_get_num_threads@plt> |
0x442411 MOV %EAX,%EBX |
0x442413 CALL 404540 <omp_get_thread_num@plt> |
0x442418 XOR %EDX,%EDX |
0x44241a MOV %EAX,%R8D |
0x44241d MOV 0x14(%RSP),%EAX |
0x442421 IMUL %R12D,%EAX |
0x442425 DIV %EBX |
0x442427 MOV %EAX,%R12D |
0x44242a CMP %EDX,%R8D |
0x44242d JB 44290d |
0x442433 IMUL %R12D,%R8D |
0x442437 LEA (%R8,%RDX,1),%EDI |
0x44243b LEA (%R12,%RDI,1),%R9D |
0x44243f MOV %R9D,0x8(%RSP) |
0x442444 CMP %R9D,%EDI |
0x442447 JAE 4428e3 |
0x44244d MOV %EDI,%EAX |
0x44244f XOR %EDX,%EDX |
0x442451 MOV 0xc(%RSP),%R10D |
0x442456 VMOVQ 0x8(%R13),%XMM3 |
0x44245c DIVL 0x14(%RSP) |
0x442460 VMOVQ (%R13),%XMM4 |
0x442466 VMOVQ 0x18(%R13),%XMM2 |
0x44246c VMOVQ 0x10(%R13),%XMM1 |
0x442472 ADD %EDX,%R10D |
0x442475 LEA (%RAX,%R14,1),%R11D |
0x442479 SUB %R10D,%R15D |
0x44247c MOVSXD %R11D,%R8 |
0x44247f MOV %R10D,0x3c(%RSP) |
0x442484 NOPW %CS:(%RAX,%RAX,1) |
0x44248f NOP |
(276) 0x442490 CMP %R15D,%R12D |
(276) 0x442493 MOV %R15D,%ECX |
(276) 0x442496 CMOVBE %R12D,%ECX |
(276) 0x44249a LEA (%RDI,%RCX,1),%R15D |
(276) 0x44249e MOV %R15D,0x38(%RSP) |
(276) 0x4424a3 CMP %R15D,%EDI |
(276) 0x4424a6 JAE 4428af |
(276) 0x4424ac VMOVQ %XMM3,%R13 |
(276) 0x4424b1 VMOVQ %XMM4,%R14 |
(276) 0x4424b6 VMOVQ %XMM2,%RSI |
(276) 0x4424bb VMOVQ %XMM1,%RAX |
(276) 0x4424c0 MOV (%R13),%RDX |
(276) 0x4424c4 MOV (%R14),%R9 |
(276) 0x4424c7 MOV (%RSI),%R15 |
(276) 0x4424ca MOV (%RAX),%R11 |
(276) 0x4424cd MOV 0x10(%R14),%R12 |
(276) 0x4424d1 MOV 0x10(%RSI),%R14 |
(276) 0x4424d5 LEA -0x1(%RCX),%ESI |
(276) 0x4424d8 MOV 0x10(%R13),%RBX |
(276) 0x4424dc MOV 0x10(%RAX),%R13 |
(276) 0x4424e0 IMUL %R8,%RDX |
(276) 0x4424e4 IMUL %R8,%R9 |
(276) 0x4424e8 IMUL %R8,%R15 |
(276) 0x4424ec IMUL %R8,%R11 |
(276) 0x4424f0 MOV %RDX,0x18(%RSP) |
(276) 0x4424f5 MOV %R9,0x20(%RSP) |
(276) 0x4424fa MOV %R15,0x28(%RSP) |
(276) 0x4424ff MOV %R11,0x30(%RSP) |
(276) 0x442504 CMP $0x6,%ESI |
(276) 0x442507 JBE 442900 |
(276) 0x44250d MOVSXD 0x3c(%RSP),%RAX |
(276) 0x442512 LEA (%R15,%RAX,1),%RSI |
(276) 0x442516 MOV 0x30(%RSP),%R15 |
(276) 0x44251b LEA (%RDX,%RAX,1),%RDX |
(276) 0x44251f LEA (%R9,%RAX,1),%R10 |
(276) 0x442523 LEA (%R14,%RSI,8),%R9 |
(276) 0x442527 LEA (%RBX,%RDX,8),%R11 |
(276) 0x44252b LEA (%R12,%R10,8),%R10 |
(276) 0x44252f ADD %R15,%RAX |
(276) 0x442532 MOV %ECX,%R15D |
(276) 0x442535 SHR $0x3,%R15D |
(276) 0x442539 SAL $0x6,%R15 |
(276) 0x44253d LEA -0x40(%R15),%RSI |
(276) 0x442541 LEA (%R13,%RAX,8),%RDX |
(276) 0x442546 XOR %EAX,%EAX |
(276) 0x442548 SHR $0x6,%RSI |
(276) 0x44254c INC %RSI |
(276) 0x44254f AND $0x7,%ESI |
(276) 0x442552 JE 44266e |
(276) 0x442558 CMP $0x1,%RSI |
(276) 0x44255c JE 442645 |
(276) 0x442562 CMP $0x2,%RSI |
(276) 0x442566 JE 442625 |
(276) 0x44256c CMP $0x3,%RSI |
(276) 0x442570 JE 442605 |
(276) 0x442576 CMP $0x4,%RSI |
(276) 0x44257a JE 4425e5 |
(276) 0x44257c CMP $0x5,%RSI |
(276) 0x442580 JE 4425c5 |
(276) 0x442582 CMP $0x6,%RSI |
(276) 0x442586 JE 4425a5 |
(276) 0x442588 VMOVUPD (%R11),%ZMM5 |
(276) 0x44258e MOV $0x40,%EAX |
(276) 0x442593 VMOVUPD %ZMM5,(%R10) |
(276) 0x442599 VMOVUPD (%R9),%ZMM6 |
(276) 0x44259f VMOVUPD %ZMM6,(%RDX) |
(276) 0x4425a5 VMOVUPD (%R11,%RAX,1),%ZMM7 |
(276) 0x4425ac VMOVUPD %ZMM7,(%R10,%RAX,1) |
(276) 0x4425b3 VMOVUPD (%R9,%RAX,1),%ZMM0 |
(276) 0x4425ba VMOVUPD %ZMM0,(%RDX,%RAX,1) |
(276) 0x4425c1 ADD $0x40,%RAX |
(276) 0x4425c5 VMOVUPD (%R11,%RAX,1),%ZMM8 |
(276) 0x4425cc VMOVUPD %ZMM8,(%R10,%RAX,1) |
(276) 0x4425d3 VMOVUPD (%R9,%RAX,1),%ZMM9 |
(276) 0x4425da VMOVUPD %ZMM9,(%RDX,%RAX,1) |
(276) 0x4425e1 ADD $0x40,%RAX |
(276) 0x4425e5 VMOVUPD (%R11,%RAX,1),%ZMM10 |
(276) 0x4425ec VMOVUPD %ZMM10,(%R10,%RAX,1) |
(276) 0x4425f3 VMOVUPD (%R9,%RAX,1),%ZMM11 |
(276) 0x4425fa VMOVUPD %ZMM11,(%RDX,%RAX,1) |
(276) 0x442601 ADD $0x40,%RAX |
(276) 0x442605 VMOVUPD (%R11,%RAX,1),%ZMM12 |
(276) 0x44260c VMOVUPD %ZMM12,(%R10,%RAX,1) |
(276) 0x442613 VMOVUPD (%R9,%RAX,1),%ZMM13 |
(276) 0x44261a VMOVUPD %ZMM13,(%RDX,%RAX,1) |
(276) 0x442621 ADD $0x40,%RAX |
(276) 0x442625 VMOVUPD (%R11,%RAX,1),%ZMM14 |
(276) 0x44262c VMOVUPD %ZMM14,(%R10,%RAX,1) |
(276) 0x442633 VMOVUPD (%R9,%RAX,1),%ZMM15 |
(276) 0x44263a VMOVUPD %ZMM15,(%RDX,%RAX,1) |
(276) 0x442641 ADD $0x40,%RAX |
(276) 0x442645 VMOVUPD (%R11,%RAX,1),%ZMM5 |
(276) 0x44264c VMOVUPD %ZMM5,(%R10,%RAX,1) |
(276) 0x442653 VMOVUPD (%R9,%RAX,1),%ZMM6 |
(276) 0x44265a VMOVUPD %ZMM6,(%RDX,%RAX,1) |
(276) 0x442661 ADD $0x40,%RAX |
(276) 0x442665 CMP %RAX,%R15 |
(276) 0x442668 JE 442779 |
(277) 0x44266e VMOVUPD (%R11,%RAX,1),%ZMM7 |
(277) 0x442675 VMOVUPD %ZMM7,(%R10,%RAX,1) |
(277) 0x44267c VMOVUPD (%R9,%RAX,1),%ZMM0 |
(277) 0x442683 VMOVUPD %ZMM0,(%RDX,%RAX,1) |
(277) 0x44268a VMOVUPD 0x40(%R11,%RAX,1),%ZMM8 |
(277) 0x442692 VMOVUPD %ZMM8,0x40(%R10,%RAX,1) |
(277) 0x44269a VMOVUPD 0x40(%R9,%RAX,1),%ZMM9 |
(277) 0x4426a2 VMOVUPD %ZMM9,0x40(%RDX,%RAX,1) |
(277) 0x4426aa VMOVUPD 0x80(%R11,%RAX,1),%ZMM10 |
(277) 0x4426b2 VMOVUPD %ZMM10,0x80(%R10,%RAX,1) |
(277) 0x4426ba VMOVUPD 0x80(%R9,%RAX,1),%ZMM11 |
(277) 0x4426c2 VMOVUPD %ZMM11,0x80(%RDX,%RAX,1) |
(277) 0x4426ca VMOVUPD 0xc0(%R11,%RAX,1),%ZMM12 |
(277) 0x4426d2 VMOVUPD %ZMM12,0xc0(%R10,%RAX,1) |
(277) 0x4426da VMOVUPD 0xc0(%R9,%RAX,1),%ZMM13 |
(277) 0x4426e2 VMOVUPD %ZMM13,0xc0(%RDX,%RAX,1) |
(277) 0x4426ea VMOVUPD 0x100(%R11,%RAX,1),%ZMM14 |
(277) 0x4426f2 VMOVUPD %ZMM14,0x100(%R10,%RAX,1) |
(277) 0x4426fa VMOVUPD 0x100(%R9,%RAX,1),%ZMM15 |
(277) 0x442702 VMOVUPD %ZMM15,0x100(%RDX,%RAX,1) |
(277) 0x44270a VMOVUPD 0x140(%R11,%RAX,1),%ZMM5 |
(277) 0x442712 VMOVUPD %ZMM5,0x140(%R10,%RAX,1) |
(277) 0x44271a VMOVUPD 0x140(%R9,%RAX,1),%ZMM6 |
(277) 0x442722 VMOVUPD %ZMM6,0x140(%RDX,%RAX,1) |
(277) 0x44272a VMOVUPD 0x180(%R11,%RAX,1),%ZMM7 |
(277) 0x442732 VMOVUPD %ZMM7,0x180(%R10,%RAX,1) |
(277) 0x44273a VMOVUPD 0x180(%R9,%RAX,1),%ZMM0 |
(277) 0x442742 VMOVUPD %ZMM0,0x180(%RDX,%RAX,1) |
(277) 0x44274a VMOVUPD 0x1c0(%R11,%RAX,1),%ZMM8 |
(277) 0x442752 VMOVUPD %ZMM8,0x1c0(%R10,%RAX,1) |
(277) 0x44275a VMOVUPD 0x1c0(%R9,%RAX,1),%ZMM9 |
(277) 0x442762 VMOVUPD %ZMM9,0x1c0(%RDX,%RAX,1) |
(277) 0x44276a ADD $0x200,%RAX |
(277) 0x442770 CMP %RAX,%R15 |
(277) 0x442773 JNE 44266e |
(276) 0x442779 MOV 0x3c(%RSP),%R11D |
(276) 0x44277e MOV %ECX,%R9D |
(276) 0x442781 AND $-0x8,%R9D |
(276) 0x442785 ADD %R9D,%EDI |
(276) 0x442788 LEA (%R9,%R11,1),%R15D |
(276) 0x44278c TEST $0x7,%CL |
(276) 0x44278f JE 4428ab |
(276) 0x442795 SUB %R9D,%ECX |
(276) 0x442798 LEA -0x1(%RCX),%R10D |
(276) 0x44279c CMP $0x2,%R10D |
(276) 0x4427a0 JBE 4427fc |
(276) 0x4427a2 MOVSXD 0x3c(%RSP),%RSI |
(276) 0x4427a7 MOV 0x18(%RSP),%RDX |
(276) 0x4427ac MOV 0x20(%RSP),%RAX |
(276) 0x4427b1 MOV 0x28(%RSP),%R11 |
(276) 0x4427b6 MOV 0x30(%RSP),%R10 |
(276) 0x4427bb ADD %RSI,%RDX |
(276) 0x4427be ADD %RSI,%RAX |
(276) 0x4427c1 ADD %R9,%RDX |
(276) 0x4427c4 ADD %RSI,%R11 |
(276) 0x4427c7 ADD %R9,%RAX |
(276) 0x4427ca ADD %R10,%RSI |
(276) 0x4427cd VMOVUPD (%RBX,%RDX,8),%YMM10 |
(276) 0x4427d2 ADD %R9,%R11 |
(276) 0x4427d5 ADD %R9,%RSI |
(276) 0x4427d8 VMOVUPD %YMM10,(%R12,%RAX,8) |
(276) 0x4427de VMOVUPD (%R14,%R11,8),%YMM11 |
(276) 0x4427e4 VMOVUPD %YMM11,(%R13,%RSI,8) |
(276) 0x4427eb TEST $0x3,%CL |
(276) 0x4427ee JE 4428ab |
(276) 0x4427f4 AND $-0x4,%ECX |
(276) 0x4427f7 ADD %ECX,%EDI |
(276) 0x4427f9 ADD %ECX,%R15D |
(276) 0x4427fc MOV 0x18(%RSP),%RCX |
(276) 0x442801 MOVSXD %R15D,%RAX |
(276) 0x442804 MOV 0x20(%RSP),%RSI |
(276) 0x442809 MOV 0x30(%RSP),%R10 |
(276) 0x44280e LEA (%RCX,%RAX,1),%R9 |
(276) 0x442812 LEA (%RSI,%RAX,1),%RDX |
(276) 0x442816 VMOVSD (%RBX,%R9,8),%XMM12 |
(276) 0x44281c MOV 0x28(%RSP),%R9 |
(276) 0x442821 VMOVSD %XMM12,(%R12,%RDX,8) |
(276) 0x442827 LEA 0x1(%RDI),%EDX |
(276) 0x44282a LEA (%R9,%RAX,1),%R11 |
(276) 0x44282e ADD %R10,%RAX |
(276) 0x442831 VMOVSD (%R14,%R11,8),%XMM13 |
(276) 0x442837 MOV 0x38(%RSP),%R11D |
(276) 0x44283c VMOVSD %XMM13,(%R13,%RAX,8) |
(276) 0x442843 LEA 0x1(%R15),%EAX |
(276) 0x442847 CMP %R11D,%EDX |
(276) 0x44284a JAE 4428ab |
(276) 0x44284c CLTQ |
(276) 0x44284e ADD $0x2,%EDI |
(276) 0x442851 ADD $0x2,%R15D |
(276) 0x442855 LEA (%RCX,%RAX,1),%RDX |
(276) 0x442859 VMOVSD (%RBX,%RDX,8),%XMM14 |
(276) 0x44285e LEA (%RSI,%RAX,1),%RDX |
(276) 0x442862 VMOVSD %XMM14,(%R12,%RDX,8) |
(276) 0x442868 LEA (%R9,%RAX,1),%RDX |
(276) 0x44286c ADD %R10,%RAX |
(276) 0x44286f VMOVSD (%R14,%RDX,8),%XMM15 |
(276) 0x442875 MOV %R10,%RDX |
(276) 0x442878 VMOVSD %XMM15,(%R13,%RAX,8) |
(276) 0x44287f CMP %R11D,%EDI |
(276) 0x442882 JAE 4428ab |
(276) 0x442884 MOVSXD %R15D,%RDI |
(276) 0x442887 ADD %RDI,%RCX |
(276) 0x44288a ADD %RDI,%RSI |
(276) 0x44288d ADD %RDI,%R9 |
(276) 0x442890 ADD %RDI,%RDX |
(276) 0x442893 VMOVSD (%RBX,%RCX,8),%XMM5 |
(276) 0x442898 VMOVSD %XMM5,(%R12,%RSI,8) |
(276) 0x44289e VMOVSD (%R14,%R9,8),%XMM6 |
(276) 0x4428a4 VMOVSD %XMM6,(%R13,%RDX,8) |
(276) 0x4428ab MOV 0x38(%RSP),%EDI |
(276) 0x4428af INC %R8 |
(276) 0x4428b2 LEA (%R8),%EBX |
(276) 0x4428b5 CMP %EBX,0x10(%RSP) |
(276) 0x4428b9 JLE 4428e0 |
(276) 0x4428bb MOV 0x8(%RSP),%R12D |
(276) 0x4428c0 MOV 0xc(%RSP),%R14D |
(276) 0x4428c5 MOV 0x14(%RSP),%R15D |
(276) 0x4428ca SUB %EDI,%R12D |
(276) 0x4428cd MOV %R14D,0x3c(%RSP) |
(276) 0x4428d2 JMP 442490 |
0x4428d7 NOPW (%RAX,%RAX,1) |
0x4428e0 VZEROUPPER |
0x4428e3 LEA -0x28(%RBP),%RSP |
0x4428e7 POP %RBX |
0x4428e8 POP %R12 |
0x4428ea POP %R13 |
0x4428ec POP %R14 |
0x4428ee POP %R15 |
0x4428f0 POP %RBP |
0x4428f1 RET |
0x4428f2 NOPW %CS:(%RAX,%RAX,1) |
0x4428fd NOPL (%RAX) |
(276) 0x442900 MOV 0x3c(%RSP),%R15D |
(276) 0x442905 XOR %R9D,%R9D |
(276) 0x442908 JMP 442795 |
0x44290d INC %R12D |
0x442910 XOR %EDX,%EDX |
0x442912 JMP 442433 |
0x442917 NOPW (%RAX,%RAX,1) |
Path / |
Source file and lines | reset_field.cpp:44-48 |
Module | exec |
nb instructions | 77 |
nb uops | 76 |
loop length | 284 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 4 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 6 |
micro-operation queue | 12.67 cycles |
front end | 12.67 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 7.00 | 7.00 | 7.00 | 7.00 | 6.00 | 6.00 | 6.00 | 6.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 |
cycles | 7.00 | 7.00 | 7.00 | 7.00 | 6.00 | 6.00 | 6.00 | 6.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 |
Cycles executing div or sqrt instructions | 12.00 |
Front-end | 12.67 |
Dispatch | 7.00 |
DIV/SQRT | 12.00 |
Overall L1 | 12.67 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 14% |
all | 8% |
load | 10% |
store | 6% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 8% |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %RDI,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
AND $-0x40,%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB $0x40,%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV 0x28(%RDI),%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x2c(%RDI),%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x20(%RDI),%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x24(%R13),%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
ADD $0x3,%EDX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LEA 0x1(%RDI),%EBX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LEA 0x1(%RAX),%R14D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %EDX,0x10(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV %EBX,0xc(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
CMP %EDX,%R14D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JGE 4428e3 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x533> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV %EDX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x3(%RCX),%R15D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB %R14D,%R12D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP %R15D,%EBX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JGE 4428e3 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x533> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV %R15D,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SUB %EBX,%ESI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %ESI,0x14(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
CALL 404650 <omp_get_num_threads@plt> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EAX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CALL 404540 <omp_get_thread_num@plt> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x14(%RSP),%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
IMUL %R12D,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %EBX | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 10-17 | 6 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP %EDX,%R8D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JB 44290d <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x55d> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
IMUL %R12D,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%EDI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LEA (%R12,%RDI,1),%R9D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %R9D,0x8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
CMP %R9D,%EDI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JAE 4428e3 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x533> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV %EDI,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV 0xc(%RSP),%R10D | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
VMOVQ 0x8(%R13),%XMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
DIVL 0x14(%RSP) | 3 | 2 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 10-17 | 6 |
VMOVQ (%R13),%XMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVQ 0x18(%R13),%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVQ 0x10(%R13),%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R10D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LEA (%RAX,%R14,1),%R11D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB %R10D,%R15D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOVSXD %R11D,%R8 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %R10D,0x3c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
NOPW %CS:(%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
NOP | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
NOPW (%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
VZEROUPPER | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
POP %RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
RET | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
NOPW %CS:(%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
NOPL (%RAX) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
INC %R12D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
JMP 442433 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x83> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
NOPW (%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
Source file and lines | reset_field.cpp:44-48 |
Module | exec |
nb instructions | 77 |
nb uops | 76 |
loop length | 284 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 4 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 6 |
micro-operation queue | 12.67 cycles |
front end | 12.67 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 7.00 | 7.00 | 7.00 | 7.00 | 6.00 | 6.00 | 6.00 | 6.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 |
cycles | 7.00 | 7.00 | 7.00 | 7.00 | 6.00 | 6.00 | 6.00 | 6.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 |
Cycles executing div or sqrt instructions | 12.00 |
Front-end | 12.67 |
Dispatch | 7.00 |
DIV/SQRT | 12.00 |
Overall L1 | 12.67 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 14% |
all | 8% |
load | 10% |
store | 6% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 8% |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %RDI,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
AND $-0x40,%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB $0x40,%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV 0x28(%RDI),%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x2c(%RDI),%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x20(%RDI),%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x24(%R13),%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
ADD $0x3,%EDX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LEA 0x1(%RDI),%EBX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LEA 0x1(%RAX),%R14D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %EDX,0x10(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV %EBX,0xc(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
CMP %EDX,%R14D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JGE 4428e3 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x533> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV %EDX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x3(%RCX),%R15D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB %R14D,%R12D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP %R15D,%EBX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JGE 4428e3 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x533> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV %R15D,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SUB %EBX,%ESI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %ESI,0x14(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
CALL 404650 <omp_get_num_threads@plt> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EAX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CALL 404540 <omp_get_thread_num@plt> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x14(%RSP),%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
IMUL %R12D,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %EBX | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 10-17 | 6 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP %EDX,%R8D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JB 44290d <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x55d> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
IMUL %R12D,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%EDI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LEA (%R12,%RDI,1),%R9D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %R9D,0x8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
CMP %R9D,%EDI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JAE 4428e3 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x533> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV %EDI,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV 0xc(%RSP),%R10D | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
VMOVQ 0x8(%R13),%XMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
DIVL 0x14(%RSP) | 3 | 2 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 10-17 | 6 |
VMOVQ (%R13),%XMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVQ 0x18(%R13),%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVQ 0x10(%R13),%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R10D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LEA (%RAX,%R14,1),%R11D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB %R10D,%R15D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOVSXD %R11D,%R8 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %R10D,0x3c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
NOPW %CS:(%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
NOP | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
NOPW (%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
VZEROUPPER | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
POP %RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
RET | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
NOPW %CS:(%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
NOPL (%RAX) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
INC %R12D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
JMP 442433 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x83> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
NOPW (%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1– | 2.6 | 1.31 |
▼Loop 276 - reset_field.cpp:46-48 - exec– | 0 | 0.01 |
○Loop 277 - reset_field.cpp:47-48 - exec | 2.6 | 1.3 |