Function: _Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0 | Module: exec | Source: reset_field.cpp:34-38 [...] | Coverage: 1.71% |
---|
Function: _Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0 | Module: exec | Source: reset_field.cpp:34-38 [...] | Coverage: 1.71% |
---|
/home/eoseret/qaas_runs_CPU_9468/171-112-9712/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/reset_field.cpp: 34 - 38 |
-------------------------------------------------------------------------------- |
34: #pragma omp parallel for simd collapse(2) |
35: for (int j = (y_min + 1); j < (y_max + 2); j++) { |
36: for (int i = (x_min + 1); i < (x_max + 2); i++) { |
37: density0(i, j) = density1(i, j); |
38: energy0(i, j) = energy1(i, j); |
/home/eoseret/qaas_runs_CPU_9468/171-112-9712/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69 |
-------------------------------------------------------------------------------- |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
0x440860 PUSH %RBP |
0x440861 MOV %RSP,%RBP |
0x440864 PUSH %R15 |
0x440866 PUSH %R14 |
0x440868 PUSH %R13 |
0x44086a PUSH %R12 |
0x44086c PUSH %RBX |
0x44086d AND $-0x40,%RSP |
0x440871 ADD $-0x80,%RSP |
0x440875 MOV 0x28(%RDI),%EAX |
0x440878 MOV 0x2c(%RDI),%EDX |
0x44087b MOV 0x20(%RDI),%EBX |
0x44087e MOV 0x24(%RDI),%ECX |
0x440881 ADD $0x2,%EDX |
0x440884 LEA 0x1(%RAX),%R15D |
0x440888 LEA 0x1(%RBX),%ESI |
0x44088b MOV %EDX,0x50(%RSP) |
0x44088f MOV %ESI,0x4c(%RSP) |
0x440893 CMP %EDX,%R15D |
0x440896 JGE 440d8b |
0x44089c MOV %EDX,%EBX |
0x44089e LEA 0x2(%RCX),%R14D |
0x4408a2 SUB %R15D,%EBX |
0x4408a5 CMP %R14D,%ESI |
0x4408a8 JGE 440d8b |
0x4408ae MOV %RDI,%R13 |
0x4408b1 MOV %R14D,%EDI |
0x4408b4 SUB %ESI,%EDI |
0x4408b6 MOV %EDI,0x54(%RSP) |
0x4408ba CALL 404650 <omp_get_num_threads@plt> |
0x4408bf MOV %EAX,%R12D |
0x4408c2 CALL 404540 <omp_get_thread_num@plt> |
0x4408c7 XOR %EDX,%EDX |
0x4408c9 MOV %EAX,%R8D |
0x4408cc MOV 0x54(%RSP),%EAX |
0x4408d0 IMUL %EBX,%EAX |
0x4408d3 DIV %R12D |
0x4408d6 MOV %EAX,%R12D |
0x4408d9 CMP %EDX,%R8D |
0x4408dc JB 440dac |
0x4408e2 IMUL %R12D,%R8D |
0x4408e6 LEA (%R8,%RDX,1),%R9D |
0x4408ea LEA (%R12,%R9,1),%R10D |
0x4408ee MOV %R10D,0x48(%RSP) |
0x4408f3 CMP %R10D,%R9D |
0x4408f6 JAE 440d8b |
0x4408fc MOV %R9D,%EAX |
0x4408ff XOR %EDX,%EDX |
0x440901 MOV 0x4c(%RSP),%R11D |
0x440906 MOV (%R13),%RSI |
0x44090a DIVL 0x54(%RSP) |
0x44090e MOV 0x10(%R13),%RBX |
0x440912 MOV %RSI,0x38(%RSP) |
0x440917 MOV %RBX,0x28(%RSP) |
0x44091c ADD %EDX,%R11D |
0x44091f ADD %R15D,%EAX |
0x440922 MOV %R14D,%EDX |
0x440925 MOV 0x8(%R13),%R15 |
0x440929 MOV 0x18(%R13),%R14 |
0x44092d MOV %R11D,0x7c(%RSP) |
0x440932 SUB %R11D,%EDX |
0x440935 MOVSXD %EAX,%RBX |
0x440938 MOV %R15,0x40(%RSP) |
0x44093d MOV %R14,0x30(%RSP) |
0x440942 NOPW (%RAX,%RAX,1) |
(281) 0x440948 CMP %EDX,%R12D |
(281) 0x44094b CMOVBE %R12D,%EDX |
(281) 0x44094f LEA (%R9,%RDX,1),%ECX |
(281) 0x440953 MOV %ECX,0x78(%RSP) |
(281) 0x440957 CMP %ECX,%R9D |
(281) 0x44095a JAE 440d5d |
(281) 0x440960 MOV 0x30(%RSP),%R12 |
(281) 0x440965 MOV 0x38(%RSP),%RDI |
(281) 0x44096a LEA -0x1(%RDX),%EAX |
(281) 0x44096d MOV 0x28(%RSP),%RCX |
(281) 0x440972 MOV 0x40(%RSP),%R13 |
(281) 0x440977 MOV (%R12),%RSI |
(281) 0x44097b MOV (%RDI),%R8 |
(281) 0x44097e MOV (%RCX),%R10 |
(281) 0x440981 MOV (%R13),%R11 |
(281) 0x440985 IMUL %RBX,%R8 |
(281) 0x440989 MOV 0x10(%R13),%R15 |
(281) 0x44098d MOV 0x10(%RDI),%R14 |
(281) 0x440991 IMUL %RBX,%RSI |
(281) 0x440995 MOV 0x10(%R12),%R13 |
(281) 0x44099a MOV 0x10(%RCX),%R12 |
(281) 0x44099e IMUL %RBX,%R10 |
(281) 0x4409a2 IMUL %RBX,%R11 |
(281) 0x4409a6 MOV %R8,0x60(%RSP) |
(281) 0x4409ab MOV %RSI,0x68(%RSP) |
(281) 0x4409b0 MOV %R10,0x70(%RSP) |
(281) 0x4409b5 CMP $0x6,%EAX |
(281) 0x4409b8 JBE 440da0 |
(281) 0x4409be MOVSXD 0x7c(%RSP),%RAX |
(281) 0x4409c3 LEA (%R8,%RAX,1),%RCX |
(281) 0x4409c7 LEA (%R11,%RAX,1),%RDI |
(281) 0x4409cb LEA (%R14,%RCX,8),%R8 |
(281) 0x4409cf MOV 0x70(%RSP),%RCX |
(281) 0x4409d4 LEA (%RSI,%RAX,1),%RSI |
(281) 0x4409d8 LEA (%R15,%RDI,8),%R10 |
(281) 0x4409dc LEA (%R13,%RSI,8),%RDI |
(281) 0x4409e1 ADD %RCX,%RAX |
(281) 0x4409e4 MOV %EDX,%ECX |
(281) 0x4409e6 SHR $0x3,%ECX |
(281) 0x4409e9 LEA (%R12,%RAX,8),%RSI |
(281) 0x4409ed XOR %EAX,%EAX |
(281) 0x4409ef SAL $0x6,%RCX |
(281) 0x4409f3 MOV %RCX,0x58(%RSP) |
(281) 0x4409f8 SUB $0x40,%RCX |
(281) 0x4409fc SHR $0x6,%RCX |
(281) 0x440a00 INC %RCX |
(281) 0x440a03 AND $0x7,%ECX |
(281) 0x440a06 JE 440b24 |
(281) 0x440a0c CMP $0x1,%RCX |
(281) 0x440a10 JE 440af9 |
(281) 0x440a16 CMP $0x2,%RCX |
(281) 0x440a1a JE 440ad9 |
(281) 0x440a20 CMP $0x3,%RCX |
(281) 0x440a24 JE 440ab9 |
(281) 0x440a2a CMP $0x4,%RCX |
(281) 0x440a2e JE 440a99 |
(281) 0x440a30 CMP $0x5,%RCX |
(281) 0x440a34 JE 440a79 |
(281) 0x440a36 CMP $0x6,%RCX |
(281) 0x440a3a JE 440a59 |
(281) 0x440a3c VMOVUPD (%R10),%ZMM3 |
(281) 0x440a42 MOV $0x40,%EAX |
(281) 0x440a47 VMOVUPD %ZMM3,(%R8) |
(281) 0x440a4d VMOVUPD (%RDI),%ZMM4 |
(281) 0x440a53 VMOVUPD %ZMM4,(%RSI) |
(281) 0x440a59 VMOVUPD (%R10,%RAX,1),%ZMM1 |
(281) 0x440a60 VMOVUPD %ZMM1,(%R8,%RAX,1) |
(281) 0x440a67 VMOVUPD (%RDI,%RAX,1),%ZMM2 |
(281) 0x440a6e VMOVUPD %ZMM2,(%RSI,%RAX,1) |
(281) 0x440a75 ADD $0x40,%RAX |
(281) 0x440a79 VMOVUPD (%R10,%RAX,1),%ZMM0 |
(281) 0x440a80 VMOVUPD %ZMM0,(%R8,%RAX,1) |
(281) 0x440a87 VMOVUPD (%RDI,%RAX,1),%ZMM5 |
(281) 0x440a8e VMOVUPD %ZMM5,(%RSI,%RAX,1) |
(281) 0x440a95 ADD $0x40,%RAX |
(281) 0x440a99 VMOVUPD (%R10,%RAX,1),%ZMM6 |
(281) 0x440aa0 VMOVUPD %ZMM6,(%R8,%RAX,1) |
(281) 0x440aa7 VMOVUPD (%RDI,%RAX,1),%ZMM7 |
(281) 0x440aae VMOVUPD %ZMM7,(%RSI,%RAX,1) |
(281) 0x440ab5 ADD $0x40,%RAX |
(281) 0x440ab9 VMOVUPD (%R10,%RAX,1),%ZMM8 |
(281) 0x440ac0 VMOVUPD %ZMM8,(%R8,%RAX,1) |
(281) 0x440ac7 VMOVUPD (%RDI,%RAX,1),%ZMM9 |
(281) 0x440ace VMOVUPD %ZMM9,(%RSI,%RAX,1) |
(281) 0x440ad5 ADD $0x40,%RAX |
(281) 0x440ad9 VMOVUPD (%R10,%RAX,1),%ZMM10 |
(281) 0x440ae0 VMOVUPD %ZMM10,(%R8,%RAX,1) |
(281) 0x440ae7 VMOVUPD (%RDI,%RAX,1),%ZMM11 |
(281) 0x440aee VMOVUPD %ZMM11,(%RSI,%RAX,1) |
(281) 0x440af5 ADD $0x40,%RAX |
(281) 0x440af9 VMOVUPD (%R10,%RAX,1),%ZMM12 |
(281) 0x440b00 VMOVUPD %ZMM12,(%R8,%RAX,1) |
(281) 0x440b07 VMOVUPD (%RDI,%RAX,1),%ZMM13 |
(281) 0x440b0e VMOVUPD %ZMM13,(%RSI,%RAX,1) |
(281) 0x440b15 ADD $0x40,%RAX |
(281) 0x440b19 CMP %RAX,0x58(%RSP) |
(281) 0x440b1e JE 440c31 |
(282) 0x440b24 VMOVUPD (%R10,%RAX,1),%ZMM14 |
(282) 0x440b2b VMOVUPD %ZMM14,(%R8,%RAX,1) |
(282) 0x440b32 VMOVUPD (%RDI,%RAX,1),%ZMM15 |
(282) 0x440b39 VMOVUPD %ZMM15,(%RSI,%RAX,1) |
(282) 0x440b40 VMOVUPD 0x40(%R10,%RAX,1),%ZMM3 |
(282) 0x440b48 VMOVUPD %ZMM3,0x40(%R8,%RAX,1) |
(282) 0x440b50 VMOVUPD 0x40(%RDI,%RAX,1),%ZMM4 |
(282) 0x440b58 VMOVUPD %ZMM4,0x40(%RSI,%RAX,1) |
(282) 0x440b60 VMOVUPD 0x80(%R10,%RAX,1),%ZMM1 |
(282) 0x440b68 VMOVUPD %ZMM1,0x80(%R8,%RAX,1) |
(282) 0x440b70 VMOVUPD 0x80(%RDI,%RAX,1),%ZMM2 |
(282) 0x440b78 VMOVUPD %ZMM2,0x80(%RSI,%RAX,1) |
(282) 0x440b80 VMOVUPD 0xc0(%R10,%RAX,1),%ZMM0 |
(282) 0x440b88 VMOVUPD %ZMM0,0xc0(%R8,%RAX,1) |
(282) 0x440b90 VMOVUPD 0xc0(%RDI,%RAX,1),%ZMM5 |
(282) 0x440b98 VMOVUPD %ZMM5,0xc0(%RSI,%RAX,1) |
(282) 0x440ba0 VMOVUPD 0x100(%R10,%RAX,1),%ZMM6 |
(282) 0x440ba8 VMOVUPD %ZMM6,0x100(%R8,%RAX,1) |
(282) 0x440bb0 VMOVUPD 0x100(%RDI,%RAX,1),%ZMM7 |
(282) 0x440bb8 VMOVUPD %ZMM7,0x100(%RSI,%RAX,1) |
(282) 0x440bc0 VMOVUPD 0x140(%R10,%RAX,1),%ZMM8 |
(282) 0x440bc8 VMOVUPD %ZMM8,0x140(%R8,%RAX,1) |
(282) 0x440bd0 VMOVUPD 0x140(%RDI,%RAX,1),%ZMM9 |
(282) 0x440bd8 VMOVUPD %ZMM9,0x140(%RSI,%RAX,1) |
(282) 0x440be0 VMOVUPD 0x180(%R10,%RAX,1),%ZMM10 |
(282) 0x440be8 VMOVUPD %ZMM10,0x180(%R8,%RAX,1) |
(282) 0x440bf0 VMOVUPD 0x180(%RDI,%RAX,1),%ZMM11 |
(282) 0x440bf8 VMOVUPD %ZMM11,0x180(%RSI,%RAX,1) |
(282) 0x440c00 VMOVUPD 0x1c0(%R10,%RAX,1),%ZMM12 |
(282) 0x440c08 VMOVUPD %ZMM12,0x1c0(%R8,%RAX,1) |
(282) 0x440c10 VMOVUPD 0x1c0(%RDI,%RAX,1),%ZMM13 |
(282) 0x440c18 VMOVUPD %ZMM13,0x1c0(%RSI,%RAX,1) |
(282) 0x440c20 ADD $0x200,%RAX |
(282) 0x440c26 CMP %RAX,0x58(%RSP) |
(282) 0x440c2b JNE 440b24 |
(281) 0x440c31 MOV 0x7c(%RSP),%R10D |
(281) 0x440c36 MOV %EDX,%R8D |
(281) 0x440c39 AND $-0x8,%R8D |
(281) 0x440c3d ADD %R8D,%R9D |
(281) 0x440c40 LEA (%R8,%R10,1),%ESI |
(281) 0x440c44 TEST $0x7,%DL |
(281) 0x440c47 JE 440d58 |
(281) 0x440c4d SUB %R8D,%EDX |
(281) 0x440c50 LEA -0x1(%RDX),%EDI |
(281) 0x440c53 CMP $0x2,%EDI |
(281) 0x440c56 JBE 440caf |
(281) 0x440c58 MOVSXD 0x7c(%RSP),%RCX |
(281) 0x440c5d MOV 0x60(%RSP),%R10 |
(281) 0x440c62 MOV 0x68(%RSP),%RDI |
(281) 0x440c67 LEA (%R11,%RCX,1),%RAX |
(281) 0x440c6b ADD %RCX,%R10 |
(281) 0x440c6e ADD %R8,%RAX |
(281) 0x440c71 ADD %RCX,%RDI |
(281) 0x440c74 ADD %R8,%R10 |
(281) 0x440c77 VMOVUPD (%R15,%RAX,8),%YMM14 |
(281) 0x440c7d MOV 0x70(%RSP),%RAX |
(281) 0x440c82 ADD %R8,%RDI |
(281) 0x440c85 VMOVUPD %YMM14,(%R14,%R10,8) |
(281) 0x440c8b ADD %RAX,%RCX |
(281) 0x440c8e VMOVUPD (%R13,%RDI,8),%YMM15 |
(281) 0x440c95 ADD %R8,%RCX |
(281) 0x440c98 VMOVUPD %YMM15,(%R12,%RCX,8) |
(281) 0x440c9e TEST $0x3,%DL |
(281) 0x440ca1 JE 440d58 |
(281) 0x440ca7 AND $-0x4,%EDX |
(281) 0x440caa ADD %EDX,%R9D |
(281) 0x440cad ADD %EDX,%ESI |
(281) 0x440caf MOVSXD %ESI,%R10 |
(281) 0x440cb2 MOV 0x60(%RSP),%RCX |
(281) 0x440cb7 MOV 0x68(%RSP),%RDI |
(281) 0x440cbc LEA (%R11,%R10,1),%RDX |
(281) 0x440cc0 VMOVSD (%R15,%RDX,8),%XMM3 |
(281) 0x440cc6 LEA (%RCX,%R10,1),%R8 |
(281) 0x440cca LEA (%RDI,%R10,1),%RAX |
(281) 0x440cce LEA 0x1(%R9),%EDX |
(281) 0x440cd2 VMOVSD %XMM3,(%R14,%R8,8) |
(281) 0x440cd8 MOV 0x70(%RSP),%R8 |
(281) 0x440cdd VMOVSD (%R13,%RAX,8),%XMM4 |
(281) 0x440ce4 LEA 0x1(%RSI),%EAX |
(281) 0x440ce7 ADD %R8,%R10 |
(281) 0x440cea VMOVSD %XMM4,(%R12,%R10,8) |
(281) 0x440cf0 MOV 0x78(%RSP),%R10D |
(281) 0x440cf5 CMP %R10D,%EDX |
(281) 0x440cf8 JAE 440d58 |
(281) 0x440cfa CLTQ |
(281) 0x440cfc ADD $0x2,%R9D |
(281) 0x440d00 ADD $0x2,%ESI |
(281) 0x440d03 LEA (%R11,%RAX,1),%RDX |
(281) 0x440d07 VMOVSD (%R15,%RDX,8),%XMM1 |
(281) 0x440d0d LEA (%RCX,%RAX,1),%RDX |
(281) 0x440d11 VMOVSD %XMM1,(%R14,%RDX,8) |
(281) 0x440d17 LEA (%RDI,%RAX,1),%RDX |
(281) 0x440d1b ADD %R8,%RAX |
(281) 0x440d1e VMOVSD (%R13,%RDX,8),%XMM2 |
(281) 0x440d25 VMOVSD %XMM2,(%R12,%RAX,8) |
(281) 0x440d2b CMP %R10D,%R9D |
(281) 0x440d2e JAE 440d58 |
(281) 0x440d30 MOVSXD %ESI,%R9 |
(281) 0x440d33 ADD %R9,%R11 |
(281) 0x440d36 ADD %R9,%RCX |
(281) 0x440d39 ADD %R9,%RDI |
(281) 0x440d3c ADD %R9,%R8 |
(281) 0x440d3f VMOVSD (%R15,%R11,8),%XMM0 |
(281) 0x440d45 VMOVSD %XMM0,(%R14,%RCX,8) |
(281) 0x440d4b VMOVSD (%R13,%RDI,8),%XMM5 |
(281) 0x440d52 VMOVSD %XMM5,(%R12,%R8,8) |
(281) 0x440d58 MOV 0x78(%RSP),%R9D |
(281) 0x440d5d INC %RBX |
(281) 0x440d60 LEA (%RBX),%R15D |
(281) 0x440d63 CMP %R15D,0x50(%RSP) |
(281) 0x440d68 JLE 440d88 |
(281) 0x440d6a MOV 0x48(%RSP),%R12D |
(281) 0x440d6f MOV 0x4c(%RSP),%R11D |
(281) 0x440d74 MOV 0x54(%RSP),%EDX |
(281) 0x440d78 MOV %R11D,0x7c(%RSP) |
(281) 0x440d7d SUB %R9D,%R12D |
(281) 0x440d80 JMP 440948 |
0x440d85 NOPL (%RAX) |
0x440d88 VZEROUPPER |
0x440d8b LEA -0x28(%RBP),%RSP |
0x440d8f POP %RBX |
0x440d90 POP %R12 |
0x440d92 POP %R13 |
0x440d94 POP %R14 |
0x440d96 POP %R15 |
0x440d98 POP %RBP |
0x440d99 RET |
0x440d9a NOPW (%RAX,%RAX,1) |
(281) 0x440da0 MOV 0x7c(%RSP),%ESI |
(281) 0x440da4 XOR %R8D,%R8D |
(281) 0x440da7 JMP 440c4d |
0x440dac INC %R12D |
0x440daf XOR %EDX,%EDX |
0x440db1 JMP 4408e2 |
0x440db6 NOPW %CS:(%RAX,%RAX,1) |
Path / |
Source file and lines | reset_field.cpp:34-38 |
Module | exec |
nb instructions | 80 |
nb uops | 90 |
loop length | 279 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 10 |
micro-operation queue | 15.00 cycles |
front end | 15.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 5.70 | 8.00 | 6.00 | 6.00 | 8.50 | 5.87 | 5.70 | 8.50 | 8.50 | 8.50 | 5.73 | 6.00 |
cycles | 5.70 | 11.73 | 6.00 | 6.00 | 8.50 | 5.87 | 5.70 | 8.50 | 8.50 | 8.50 | 5.73 | 6.00 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.24-14.34 |
Stall cycles | 0.00 |
Front-end | 15.00 |
Dispatch | 11.73 |
DIV/SQRT | 12.00 |
Overall L1 | 15.00 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 20% |
all | 9% |
load | 10% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 10% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD $-0x80,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x28(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RDI),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x24(%RDI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x2,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA 0x1(%RBX),%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ESI,0x4c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 440d8b <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x52b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x2(%RCX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 440d8b <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x52b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R14D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %ESI,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EDI,0x54(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 404650 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 404540 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x54(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 440dac <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x54c> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %R12D,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%R12,%R9,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R10D,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R10D,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 440d8b <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x52b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R9D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x4c(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R13),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x54(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x10(%R13),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R15D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x8(%R13),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%R13),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R11D,0x7c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R11D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %EAX,%RBX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R15,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 4408e2 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x82> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | reset_field.cpp:34-38 |
Module | exec |
nb instructions | 80 |
nb uops | 90 |
loop length | 279 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 10 |
micro-operation queue | 15.00 cycles |
front end | 15.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 5.70 | 8.00 | 6.00 | 6.00 | 8.50 | 5.87 | 5.70 | 8.50 | 8.50 | 8.50 | 5.73 | 6.00 |
cycles | 5.70 | 11.73 | 6.00 | 6.00 | 8.50 | 5.87 | 5.70 | 8.50 | 8.50 | 8.50 | 5.73 | 6.00 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.24-14.34 |
Stall cycles | 0.00 |
Front-end | 15.00 |
Dispatch | 11.73 |
DIV/SQRT | 12.00 |
Overall L1 | 15.00 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 20% |
all | 9% |
load | 10% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 10% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD $-0x80,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x28(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RDI),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x24(%RDI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x2,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA 0x1(%RBX),%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ESI,0x4c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 440d8b <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x52b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x2(%RCX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 440d8b <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x52b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R14D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %ESI,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EDI,0x54(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 404650 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 404540 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x54(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 440dac <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x54c> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %R12D,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%R12,%R9,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R10D,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R10D,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 440d8b <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x52b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R9D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x4c(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R13),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x54(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x10(%R13),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R15D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x8(%R13),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%R13),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R11D,0x7c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R11D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %EAX,%RBX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R15,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 4408e2 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x82> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0– | 1.71 | 0.57 |
▼Loop 281 - reset_field.cpp:36-38 - exec– | 0 | 0.01 |
○Loop 282 - reset_field.cpp:37-38 - exec | 1.7 | 0.57 |