Function: _Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buf ... | Module: exec | Source: advec_mom.cpp:53-57 [...] | Coverage: 2.88% |
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Function: _Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buf ... | Module: exec | Source: advec_mom.cpp:53-57 [...] | Coverage: 2.88% |
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/home/eoseret/qaas_runs_CPU_9468/171-112-9712/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69 |
-------------------------------------------------------------------------------- |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
/home/eoseret/qaas_runs_CPU_9468/171-112-9712/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp: 53 - 57 |
-------------------------------------------------------------------------------- |
53: #pragma omp parallel for simd collapse(2) |
54: for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) { |
55: for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) { |
56: post_vol(i, j) = volume(i, j) + vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j); |
57: pre_vol(i, j) = post_vol(i, j) + vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j); |
0x42b2c0 PUSH %RBP |
0x42b2c1 MOV %RSP,%RBP |
0x42b2c4 PUSH %R15 |
0x42b2c6 PUSH %R14 |
0x42b2c8 PUSH %R13 |
0x42b2ca PUSH %R12 |
0x42b2cc PUSH %RBX |
0x42b2cd AND $-0x40,%RSP |
0x42b2d1 SUB $0xc0,%RSP |
0x42b2d8 MOV 0x30(%RDI),%EAX |
0x42b2db MOV 0x34(%RDI),%EDX |
0x42b2de MOV 0x28(%RDI),%ECX |
0x42b2e1 MOV 0x2c(%RDI),%EBX |
0x42b2e4 ADD $0x4,%EDX |
0x42b2e7 LEA -0x1(%RAX),%R15D |
0x42b2eb LEA -0x1(%RCX),%ESI |
0x42b2ee MOV %EDX,0x5c(%RSP) |
0x42b2f2 MOV %ESI,0x58(%RSP) |
0x42b2f6 CMP %EDX,%R15D |
0x42b2f9 JGE 42b973 |
0x42b2ff LEA 0x4(%RBX),%R14D |
0x42b303 MOV %EDX,%EBX |
0x42b305 SUB %R15D,%EBX |
0x42b308 CMP %R14D,%ESI |
0x42b30b JGE 42b973 |
0x42b311 MOV %RDI,%R12 |
0x42b314 MOV %R14D,%EDI |
0x42b317 SUB %ESI,%EDI |
0x42b319 MOV %EDI,0x90(%RSP) |
0x42b320 CALL 404650 <omp_get_num_threads@plt> |
0x42b325 MOV %EAX,%R13D |
0x42b328 CALL 404540 <omp_get_thread_num@plt> |
0x42b32d XOR %EDX,%EDX |
0x42b32f MOV %EAX,%R8D |
0x42b332 MOV 0x90(%RSP),%EAX |
0x42b339 IMUL %EBX,%EAX |
0x42b33c DIV %R13D |
0x42b33f MOV %EAX,%EDI |
0x42b341 CMP %EDX,%R8D |
0x42b344 JB 42b9a7 |
0x42b34a IMUL %EDI,%R8D |
0x42b34e LEA (%R8,%RDX,1),%R8D |
0x42b352 LEA (%RDI,%R8,1),%R9D |
0x42b356 MOV %R9D,0x54(%RSP) |
0x42b35b CMP %R9D,%R8D |
0x42b35e JAE 42b973 |
0x42b364 MOV %R8D,%EAX |
0x42b367 XOR %EDX,%EDX |
0x42b369 MOV 0x58(%RSP),%R10D |
0x42b36e MOV (%R12),%RSI |
0x42b372 DIVL 0x90(%RSP) |
0x42b379 MOV 0x8(%R12),%RBX |
0x42b37e MOV %RSI,0x40(%RSP) |
0x42b383 MOV %RBX,0x30(%RSP) |
0x42b388 ADD %EDX,%R10D |
0x42b38b LEA (%RAX,%R15,1),%R11D |
0x42b38f MOV %R14D,%EDX |
0x42b392 MOV 0x10(%R12),%R15 |
0x42b397 MOV 0x20(%R12),%R14 |
0x42b39c MOV 0x18(%R12),%R12 |
0x42b3a1 MOV %R10D,0xb0(%RSP) |
0x42b3a9 SUB %R10D,%EDX |
0x42b3ac MOV %R15,0x48(%RSP) |
0x42b3b1 MOVSXD %R11D,%R9 |
0x42b3b4 MOV %R14,0x38(%RSP) |
0x42b3b9 MOV %R12,0x28(%RSP) |
0x42b3be XCHG %AX,%AX |
(180) 0x42b3c0 CMP %EDX,%EDI |
(180) 0x42b3c2 CMOVBE %EDI,%EDX |
(180) 0x42b3c5 LEA (%R8,%RDX,1),%ECX |
(180) 0x42b3c9 MOV %ECX,0x94(%RSP) |
(180) 0x42b3d0 CMP %ECX,%R8D |
(180) 0x42b3d3 JAE 42b988 |
(180) 0x42b3d9 MOV 0x48(%RSP),%R13 |
(180) 0x42b3de MOV 0x30(%RSP),%R11 |
(180) 0x42b3e3 LEA 0x1(%R9),%RBX |
(180) 0x42b3e7 MOV 0x40(%RSP),%RAX |
(180) 0x42b3ec MOV 0x38(%RSP),%R10 |
(180) 0x42b3f1 MOV %RBX,0x60(%RSP) |
(180) 0x42b3f6 MOV 0x10(%R13),%R14 |
(180) 0x42b3fa MOV (%R13),%RDI |
(180) 0x42b3fe MOV (%R11),%R13 |
(180) 0x42b401 MOV (%RAX),%R15 |
(180) 0x42b404 MOV 0x10(%R10),%R12 |
(180) 0x42b408 MOV 0x10(%RAX),%RSI |
(180) 0x42b40c IMUL %R9,%RDI |
(180) 0x42b410 MOV %R14,0xa0(%RSP) |
(180) 0x42b418 IMUL %R13,%RBX |
(180) 0x42b41c MOV 0x28(%RSP),%RAX |
(180) 0x42b421 MOV (%R10),%R10 |
(180) 0x42b424 IMUL %R9,%R15 |
(180) 0x42b428 MOV 0x10(%R11),%RCX |
(180) 0x42b42c MOV %R12,0xa8(%RSP) |
(180) 0x42b434 IMUL %R9,%R10 |
(180) 0x42b438 MOV %RDI,0x68(%RSP) |
(180) 0x42b43d IMUL (%RAX),%R9 |
(180) 0x42b441 MOV %RBX,%R11 |
(180) 0x42b444 MOV %RBX,0x80(%RSP) |
(180) 0x42b44c SUB %R13,%R11 |
(180) 0x42b44f MOV 0x10(%RAX),%R13 |
(180) 0x42b453 LEA -0x1(%RDX),%EAX |
(180) 0x42b456 MOV %R15,0x70(%RSP) |
(180) 0x42b45b MOV %R10,0x78(%RSP) |
(180) 0x42b460 MOV %R11,0x98(%RSP) |
(180) 0x42b468 MOV %R13,0xb8(%RSP) |
(180) 0x42b470 MOV %R9,0x88(%RSP) |
(180) 0x42b478 CMP $0x6,%EAX |
(180) 0x42b47b JBE 42b998 |
(180) 0x42b481 MOVSXD 0xb0(%RSP),%RAX |
(180) 0x42b489 ADD %RAX,%RDI |
(180) 0x42b48c LEA (%R10,%RAX,1),%R10 |
(180) 0x42b490 LEA (%RBX,%RAX,1),%RBX |
(180) 0x42b494 LEA (%R11,%RAX,1),%R11 |
(180) 0x42b498 LEA (%R14,%RDI,8),%R14 |
(180) 0x42b49c LEA 0x1(%R15,%RAX,1),%RDI |
(180) 0x42b4a1 ADD %R9,%RAX |
(180) 0x42b4a4 MOV 0xb8(%RSP),%R9 |
(180) 0x42b4ac LEA (%R12,%R10,8),%R12 |
(180) 0x42b4b0 SAL $0x3,%RDI |
(180) 0x42b4b4 LEA (%RCX,%RBX,8),%RBX |
(180) 0x42b4b8 LEA (%RCX,%R11,8),%R11 |
(180) 0x42b4bc LEA (%R9,%RAX,8),%R10 |
(180) 0x42b4c0 MOV %EDX,%R9D |
(180) 0x42b4c3 LEA (%RSI,%RDI,1),%R15 |
(180) 0x42b4c7 XOR %EAX,%EAX |
(180) 0x42b4c9 SHR $0x3,%R9D |
(180) 0x42b4cd LEA -0x8(%RSI,%RDI,1),%R13 |
(180) 0x42b4d2 SAL $0x6,%R9 |
(180) 0x42b4d6 LEA -0x40(%R9),%RDI |
(180) 0x42b4da SHR $0x6,%RDI |
(180) 0x42b4de INC %RDI |
(180) 0x42b4e1 AND $0x3,%EDI |
(180) 0x42b4e4 JE 42b5ae |
(180) 0x42b4ea CMP $0x1,%RDI |
(180) 0x42b4ee JE 42b569 |
(180) 0x42b4f0 CMP $0x2,%RDI |
(180) 0x42b4f4 JE 42b52d |
(180) 0x42b4f6 VMOVUPD (%R14),%ZMM7 |
(180) 0x42b4fc MOV $0x40,%EAX |
(180) 0x42b501 VADDPD (%R15),%ZMM7,%ZMM0 |
(180) 0x42b507 VSUBPD (%R13),%ZMM0,%ZMM2 |
(180) 0x42b50e VMOVUPD %ZMM2,(%R12) |
(180) 0x42b515 VMOVUPD (%RBX),%ZMM1 |
(180) 0x42b51b VSUBPD (%R11),%ZMM1,%ZMM3 |
(180) 0x42b521 VADDPD %ZMM2,%ZMM3,%ZMM4 |
(180) 0x42b527 VMOVUPD %ZMM4,(%R10) |
(180) 0x42b52d VMOVUPD (%R14,%RAX,1),%ZMM5 |
(180) 0x42b534 VADDPD (%R15,%RAX,1),%ZMM5,%ZMM6 |
(180) 0x42b53b VSUBPD (%R13,%RAX,1),%ZMM6,%ZMM8 |
(180) 0x42b543 VMOVUPD %ZMM8,(%R12,%RAX,1) |
(180) 0x42b54a VMOVUPD (%RBX,%RAX,1),%ZMM9 |
(180) 0x42b551 VSUBPD (%R11,%RAX,1),%ZMM9,%ZMM10 |
(180) 0x42b558 VADDPD %ZMM8,%ZMM10,%ZMM11 |
(180) 0x42b55e VMOVUPD %ZMM11,(%R10,%RAX,1) |
(180) 0x42b565 ADD $0x40,%RAX |
(180) 0x42b569 VMOVUPD (%R14,%RAX,1),%ZMM12 |
(180) 0x42b570 VADDPD (%R15,%RAX,1),%ZMM12,%ZMM13 |
(180) 0x42b577 VSUBPD (%R13,%RAX,1),%ZMM13,%ZMM14 |
(180) 0x42b57f VMOVUPD %ZMM14,(%R12,%RAX,1) |
(180) 0x42b586 VMOVUPD (%RBX,%RAX,1),%ZMM15 |
(180) 0x42b58d VSUBPD (%R11,%RAX,1),%ZMM15,%ZMM7 |
(180) 0x42b594 VADDPD %ZMM14,%ZMM7,%ZMM0 |
(180) 0x42b59a VMOVUPD %ZMM0,(%R10,%RAX,1) |
(180) 0x42b5a1 ADD $0x40,%RAX |
(180) 0x42b5a5 CMP %RAX,%R9 |
(180) 0x42b5a8 JE 42b6af |
(181) 0x42b5ae VMOVUPD (%R14,%RAX,1),%ZMM2 |
(181) 0x42b5b5 VADDPD (%R15,%RAX,1),%ZMM2,%ZMM1 |
(181) 0x42b5bc VSUBPD (%R13,%RAX,1),%ZMM1,%ZMM3 |
(181) 0x42b5c4 VMOVUPD %ZMM3,(%R12,%RAX,1) |
(181) 0x42b5cb VMOVUPD (%RBX,%RAX,1),%ZMM4 |
(181) 0x42b5d2 VSUBPD (%R11,%RAX,1),%ZMM4,%ZMM5 |
(181) 0x42b5d9 VADDPD %ZMM3,%ZMM5,%ZMM6 |
(181) 0x42b5df VMOVUPD %ZMM6,(%R10,%RAX,1) |
(181) 0x42b5e6 VMOVUPD 0x40(%R14,%RAX,1),%ZMM8 |
(181) 0x42b5ee VADDPD 0x40(%R15,%RAX,1),%ZMM8,%ZMM9 |
(181) 0x42b5f6 VSUBPD 0x40(%R13,%RAX,1),%ZMM9,%ZMM10 |
(181) 0x42b5fe VMOVUPD %ZMM10,0x40(%R12,%RAX,1) |
(181) 0x42b606 VMOVUPD 0x40(%RBX,%RAX,1),%ZMM11 |
(181) 0x42b60e VSUBPD 0x40(%R11,%RAX,1),%ZMM11,%ZMM12 |
(181) 0x42b616 VADDPD %ZMM10,%ZMM12,%ZMM13 |
(181) 0x42b61c VMOVUPD %ZMM13,0x40(%R10,%RAX,1) |
(181) 0x42b624 VMOVUPD 0x80(%R14,%RAX,1),%ZMM14 |
(181) 0x42b62c VADDPD 0x80(%R15,%RAX,1),%ZMM14,%ZMM15 |
(181) 0x42b634 VSUBPD 0x80(%R13,%RAX,1),%ZMM15,%ZMM7 |
(181) 0x42b63c VMOVUPD %ZMM7,0x80(%R12,%RAX,1) |
(181) 0x42b644 VMOVUPD 0x80(%RBX,%RAX,1),%ZMM0 |
(181) 0x42b64c VSUBPD 0x80(%R11,%RAX,1),%ZMM0,%ZMM2 |
(181) 0x42b654 VADDPD %ZMM7,%ZMM2,%ZMM1 |
(181) 0x42b65a VMOVUPD %ZMM1,0x80(%R10,%RAX,1) |
(181) 0x42b662 VMOVUPD 0xc0(%R14,%RAX,1),%ZMM3 |
(181) 0x42b66a VADDPD 0xc0(%R15,%RAX,1),%ZMM3,%ZMM4 |
(181) 0x42b672 VSUBPD 0xc0(%R13,%RAX,1),%ZMM4,%ZMM6 |
(181) 0x42b67a VMOVUPD %ZMM6,0xc0(%R12,%RAX,1) |
(181) 0x42b682 VMOVUPD 0xc0(%RBX,%RAX,1),%ZMM5 |
(181) 0x42b68a VSUBPD 0xc0(%R11,%RAX,1),%ZMM5,%ZMM8 |
(181) 0x42b692 VADDPD %ZMM6,%ZMM8,%ZMM9 |
(181) 0x42b698 VMOVUPD %ZMM9,0xc0(%R10,%RAX,1) |
(181) 0x42b6a0 ADD $0x100,%RAX |
(181) 0x42b6a6 CMP %RAX,%R9 |
(181) 0x42b6a9 JNE 42b5ae |
(180) 0x42b6af MOV 0xb0(%RSP),%EAX |
(180) 0x42b6b6 MOV %EDX,%R9D |
(180) 0x42b6b9 AND $-0x8,%R9D |
(180) 0x42b6bd ADD %R9D,%R8D |
(180) 0x42b6c0 ADD %R9D,%EAX |
(180) 0x42b6c3 TEST $0x7,%DL |
(180) 0x42b6c6 JE 42b935 |
(180) 0x42b6cc SUB %R9D,%EDX |
(180) 0x42b6cf LEA -0x1(%RDX),%R14D |
(180) 0x42b6d3 CMP $0x2,%R14D |
(180) 0x42b6d7 JBE 42b78e |
(180) 0x42b6dd MOVSXD 0xb0(%RSP),%R15 |
(180) 0x42b6e5 MOV 0x70(%RSP),%R13 |
(180) 0x42b6ea MOV 0x68(%RSP),%R11 |
(180) 0x42b6ef MOV 0xa0(%RSP),%RDI |
(180) 0x42b6f7 LEA (%R13,%R15,1),%R12 |
(180) 0x42b6fc MOV 0x78(%RSP),%R14 |
(180) 0x42b701 LEA 0x1(%R9,%R12,1),%RBX |
(180) 0x42b706 LEA (%R11,%R15,1),%R10 |
(180) 0x42b70a MOV 0xa8(%RSP),%R12 |
(180) 0x42b712 VMOVUPD (%RSI,%RBX,8),%YMM10 |
(180) 0x42b717 ADD %R9,%R10 |
(180) 0x42b71a LEA (%R14,%R15,1),%R13 |
(180) 0x42b71e MOV 0x88(%RSP),%R14 |
(180) 0x42b726 ADD %R9,%R13 |
(180) 0x42b729 VSUBPD -0x8(%RSI,%RBX,8),%YMM10,%YMM11 |
(180) 0x42b72f MOV 0x80(%RSP),%RBX |
(180) 0x42b737 LEA (%RBX,%R15,1),%R11 |
(180) 0x42b73b VADDPD (%RDI,%R10,8),%YMM11,%YMM12 |
(180) 0x42b741 MOV 0x98(%RSP),%R10 |
(180) 0x42b749 ADD %R9,%R11 |
(180) 0x42b74c LEA (%R10,%R15,1),%RDI |
(180) 0x42b750 ADD %R14,%R15 |
(180) 0x42b753 VMOVUPD %YMM12,(%R12,%R13,8) |
(180) 0x42b759 ADD %R9,%RDI |
(180) 0x42b75c ADD %R9,%R15 |
(180) 0x42b75f MOV 0xb8(%RSP),%R9 |
(180) 0x42b767 VMOVUPD (%RCX,%R11,8),%YMM13 |
(180) 0x42b76d VSUBPD (%RCX,%RDI,8),%YMM13,%YMM14 |
(180) 0x42b772 VADDPD %YMM12,%YMM14,%YMM15 |
(180) 0x42b777 VMOVUPD %YMM15,(%R9,%R15,8) |
(180) 0x42b77d TEST $0x3,%DL |
(180) 0x42b780 JE 42b935 |
(180) 0x42b786 AND $-0x4,%EDX |
(180) 0x42b789 ADD %EDX,%R8D |
(180) 0x42b78c ADD %EDX,%EAX |
(180) 0x42b78e MOV 0x70(%RSP),%RBX |
(180) 0x42b793 LEA 0x1(%RAX),%R15D |
(180) 0x42b797 MOVSXD %EAX,%RDX |
(180) 0x42b79a MOV 0x68(%RSP),%R14 |
(180) 0x42b79f MOVSXD %R15D,%RDI |
(180) 0x42b7a2 MOV 0xa0(%RSP),%R9 |
(180) 0x42b7aa MOV 0x78(%RSP),%R15 |
(180) 0x42b7af LEA (%RBX,%RDI,1),%R13 |
(180) 0x42b7b3 LEA (%RBX,%RDX,1),%R11 |
(180) 0x42b7b7 LEA (%RSI,%R13,8),%R12 |
(180) 0x42b7bb LEA (%R14,%RDX,1),%R10 |
(180) 0x42b7bf MOV 0xa8(%RSP),%R13 |
(180) 0x42b7c7 VMOVSD (%R12),%XMM7 |
(180) 0x42b7cd MOV %R12,0xb0(%RSP) |
(180) 0x42b7d5 LEA (%R15,%RDX,1),%R12 |
(180) 0x42b7d9 VSUBSD (%RSI,%R11,8),%XMM7,%XMM0 |
(180) 0x42b7df VADDSD (%R9,%R10,8),%XMM0,%XMM2 |
(180) 0x42b7e5 MOV 0x98(%RSP),%R9 |
(180) 0x42b7ed VMOVSD %XMM2,(%R13,%R12,8) |
(180) 0x42b7f4 MOV 0x80(%RSP),%R12 |
(180) 0x42b7fc MOV 0x88(%RSP),%R13 |
(180) 0x42b804 LEA (%R12,%RDX,1),%R11 |
(180) 0x42b808 LEA (%R13,%RDX,1),%R10 |
(180) 0x42b80d ADD %R9,%RDX |
(180) 0x42b810 VMOVSD (%RCX,%R11,8),%XMM1 |
(180) 0x42b816 LEA 0x1(%R8),%R11D |
(180) 0x42b81a VSUBSD (%RCX,%RDX,8),%XMM1,%XMM3 |
(180) 0x42b81f MOV 0xb8(%RSP),%RDX |
(180) 0x42b827 VADDSD %XMM2,%XMM3,%XMM4 |
(180) 0x42b82b VMOVSD %XMM4,(%RDX,%R10,8) |
(180) 0x42b831 MOV 0x94(%RSP),%R10D |
(180) 0x42b839 CMP %R10D,%R11D |
(180) 0x42b83c JAE 42b935 |
(180) 0x42b842 LEA 0x2(%RAX),%R9D |
(180) 0x42b846 ADD $0x2,%R8D |
(180) 0x42b84a MOVSXD %R9D,%RDX |
(180) 0x42b84d MOV 0xa0(%RSP),%R9 |
(180) 0x42b855 LEA (%RBX,%RDX,1),%R11 |
(180) 0x42b859 LEA (%RSI,%R11,8),%R10 |
(180) 0x42b85d LEA (%RDI,%R14,1),%R11 |
(180) 0x42b861 VMOVSD (%R9,%R11,8),%XMM6 |
(180) 0x42b867 MOV 0xb0(%RSP),%R11 |
(180) 0x42b86f LEA (%R15,%RDI,1),%R9 |
(180) 0x42b873 VADDSD (%R10),%XMM6,%XMM5 |
(180) 0x42b878 VSUBSD (%R11),%XMM5,%XMM8 |
(180) 0x42b87d MOV 0xa8(%RSP),%R11 |
(180) 0x42b885 VMOVSD %XMM8,(%R11,%R9,8) |
(180) 0x42b88b LEA (%R13,%RDI,1),%R9 |
(180) 0x42b890 LEA (%R12,%RDI,1),%R11 |
(180) 0x42b894 MOV %R9,0xb0(%RSP) |
(180) 0x42b89c MOV 0x98(%RSP),%R9 |
(180) 0x42b8a4 VMOVSD (%RCX,%R11,8),%XMM9 |
(180) 0x42b8aa ADD %R9,%RDI |
(180) 0x42b8ad VSUBSD (%RCX,%RDI,8),%XMM9,%XMM10 |
(180) 0x42b8b2 MOV 0xb0(%RSP),%R11 |
(180) 0x42b8ba MOV 0xb8(%RSP),%RDI |
(180) 0x42b8c2 VADDSD %XMM8,%XMM10,%XMM11 |
(180) 0x42b8c7 VMOVSD %XMM11,(%RDI,%R11,8) |
(180) 0x42b8cd MOV 0x94(%RSP),%EDI |
(180) 0x42b8d4 CMP %EDI,%R8D |
(180) 0x42b8d7 JAE 42b935 |
(180) 0x42b8d9 ADD $0x3,%EAX |
(180) 0x42b8dc MOV 0xa0(%RSP),%R8 |
(180) 0x42b8e4 ADD %RDX,%R14 |
(180) 0x42b8e7 ADD %RDX,%R15 |
(180) 0x42b8ea CLTQ |
(180) 0x42b8ec ADD %RDX,%R12 |
(180) 0x42b8ef ADD %RDX,%R9 |
(180) 0x42b8f2 ADD %RDX,%R13 |
(180) 0x42b8f5 ADD %RBX,%RAX |
(180) 0x42b8f8 VMOVSD (%RSI,%RAX,8),%XMM12 |
(180) 0x42b8fd MOV 0xa8(%RSP),%RSI |
(180) 0x42b905 VADDSD (%R8,%R14,8),%XMM12,%XMM13 |
(180) 0x42b90b VSUBSD (%R10),%XMM13,%XMM14 |
(180) 0x42b910 VMOVSD %XMM14,(%RSI,%R15,8) |
(180) 0x42b916 VMOVSD (%RCX,%R12,8),%XMM15 |
(180) 0x42b91c VSUBSD (%RCX,%R9,8),%XMM15,%XMM7 |
(180) 0x42b922 MOV 0xb8(%RSP),%RCX |
(180) 0x42b92a VADDSD %XMM14,%XMM7,%XMM0 |
(180) 0x42b92f VMOVSD %XMM0,(%RCX,%R13,8) |
(180) 0x42b935 MOV 0x94(%RSP),%R8D |
(180) 0x42b93d MOV 0x60(%RSP),%R9 |
(180) 0x42b942 LEA (%R9),%EAX |
(180) 0x42b945 CMP %EAX,0x5c(%RSP) |
(180) 0x42b949 JLE 42b970 |
(180) 0x42b94b MOV 0x54(%RSP),%EDI |
(180) 0x42b94f MOV 0x58(%RSP),%EBX |
(180) 0x42b953 MOV 0x90(%RSP),%EDX |
(180) 0x42b95a MOV %EBX,0xb0(%RSP) |
(180) 0x42b961 SUB %R8D,%EDI |
(180) 0x42b964 JMP 42b3c0 |
0x42b969 NOPL (%RAX) |
0x42b970 VZEROUPPER |
0x42b973 LEA -0x28(%RBP),%RSP |
0x42b977 POP %RBX |
0x42b978 POP %R12 |
0x42b97a POP %R13 |
0x42b97c POP %R14 |
0x42b97e POP %R15 |
0x42b980 POP %RBP |
0x42b981 RET |
0x42b982 NOPW (%RAX,%RAX,1) |
(180) 0x42b988 LEA 0x1(%R9),%RDI |
(180) 0x42b98c MOV %RDI,0x60(%RSP) |
(180) 0x42b991 JMP 42b93d |
0x42b993 NOPL (%RAX,%RAX,1) |
(180) 0x42b998 MOV 0xb0(%RSP),%EAX |
(180) 0x42b99f XOR %R9D,%R9D |
(180) 0x42b9a2 JMP 42b6cc |
0x42b9a7 INC %EDI |
0x42b9a9 XOR %EDX,%EDX |
0x42b9ab JMP 42b34a |
Path / |
Source file and lines | advec_mom.cpp:53-57 |
Module | exec |
nb instructions | 82 |
nb uops | 92 |
loop length | 301 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 11 |
micro-operation queue | 15.33 cycles |
front end | 15.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.10 | 8.00 | 6.33 | 6.33 | 9.00 | 6.07 | 5.90 | 9.00 | 9.00 | 9.00 | 5.93 | 6.33 |
cycles | 6.10 | 11.93 | 6.33 | 6.33 | 9.00 | 6.07 | 5.90 | 9.00 | 9.00 | 9.00 | 5.93 | 6.33 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.60-14.66 |
Stall cycles | 0.00 |
Front-end | 15.33 |
Dispatch | 11.93 |
DIV/SQRT | 12.00 |
Overall L1 | 15.33 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 14% |
all | 9% |
load | 9% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 9% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0xc0,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x30(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x34(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RDI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%RDI),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x4,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA -0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA -0x1(%RCX),%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x5c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ESI,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 42b973 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x6b3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA 0x4(%RBX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 42b973 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x6b3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R14D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %ESI,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EDI,0x90(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 404650 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 404540 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x90(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R13D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 42b9a7 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x6e7> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %EDI,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RDI,%R8,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R9D,0x54(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R9D,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 42b973 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x6b3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R8D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x58(%RSP),%R10D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R12),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x90(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x8(%R12),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%RAX,%R15,1),%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R14D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x10(%R12),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%R12),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%R12),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10D,0xb0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R10D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R15,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVSXD %R11D,%R9 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R14,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 42b34a <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x8a> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
Source file and lines | advec_mom.cpp:53-57 |
Module | exec |
nb instructions | 82 |
nb uops | 92 |
loop length | 301 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 11 |
micro-operation queue | 15.33 cycles |
front end | 15.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.10 | 8.00 | 6.33 | 6.33 | 9.00 | 6.07 | 5.90 | 9.00 | 9.00 | 9.00 | 5.93 | 6.33 |
cycles | 6.10 | 11.93 | 6.33 | 6.33 | 9.00 | 6.07 | 5.90 | 9.00 | 9.00 | 9.00 | 5.93 | 6.33 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.60-14.66 |
Stall cycles | 0.00 |
Front-end | 15.33 |
Dispatch | 11.93 |
DIV/SQRT | 12.00 |
Overall L1 | 15.33 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 14% |
all | 9% |
load | 9% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 9% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0xc0,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x30(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x34(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RDI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%RDI),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x4,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA -0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA -0x1(%RCX),%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x5c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ESI,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 42b973 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x6b3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA 0x4(%RBX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 42b973 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x6b3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R14D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %ESI,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EDI,0x90(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 404650 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 404540 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x90(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R13D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 42b9a7 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x6e7> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %EDI,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RDI,%R8,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R9D,0x54(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R9D,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 42b973 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x6b3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R8D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x58(%RSP),%R10D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R12),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x90(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x8(%R12),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%RAX,%R15,1),%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R14D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x10(%R12),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%R12),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%R12),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10D,0xb0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R10D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R15,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVSXD %R11D,%R9 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R14,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 42b34a <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x8a> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1– | 2.88 | 0.96 |
▼Loop 180 - advec_mom.cpp:53-57 - exec– | 0.01 | 0 |
○Loop 181 - advec_mom.cpp:56-57 - exec | 2.87 | 0.96 |