Function: _Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buf ... | Module: exec | Source: advec_mom.cpp:62-66 [...] | Coverage: 2.19% |
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Function: _Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buf ... | Module: exec | Source: advec_mom.cpp:62-66 [...] | Coverage: 2.19% |
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/home/eoseret/qaas_runs_CPU_9468/171-112-9712/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69 |
-------------------------------------------------------------------------------- |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
/home/eoseret/qaas_runs_CPU_9468/171-112-9712/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp: 62 - 66 |
-------------------------------------------------------------------------------- |
62: #pragma omp parallel for simd collapse(2) |
63: for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) { |
64: for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) { |
65: post_vol(i, j) = volume(i, j); |
66: pre_vol(i, j) = post_vol(i, j) + vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j); |
0x42b9b0 PUSH %RBP |
0x42b9b1 MOV %RSP,%RBP |
0x42b9b4 PUSH %R15 |
0x42b9b6 PUSH %R14 |
0x42b9b8 PUSH %R13 |
0x42b9ba MOV %RDI,%R13 |
0x42b9bd PUSH %R12 |
0x42b9bf PUSH %RBX |
0x42b9c0 AND $-0x40,%RSP |
0x42b9c4 ADD $-0x80,%RSP |
0x42b9c8 MOV 0x28(%RDI),%EAX |
0x42b9cb MOV 0x2c(%RDI),%EDX |
0x42b9ce MOV 0x20(%RDI),%EBX |
0x42b9d1 MOV 0x24(%R13),%ECX |
0x42b9d5 ADD $0x4,%EDX |
0x42b9d8 LEA -0x1(%RAX),%R15D |
0x42b9dc LEA -0x1(%RBX),%EDI |
0x42b9df MOV %EDX,0x40(%RSP) |
0x42b9e3 MOV %EDI,0x3c(%RSP) |
0x42b9e7 CMP %EDX,%R15D |
0x42b9ea JGE 42bf9b |
0x42b9f0 MOV %EDX,%EBX |
0x42b9f2 LEA 0x4(%RCX),%R14D |
0x42b9f6 SUB %R15D,%EBX |
0x42b9f9 CMP %R14D,%EDI |
0x42b9fc JGE 42bf9b |
0x42ba02 MOV %R14D,%ESI |
0x42ba05 SUB %EDI,%ESI |
0x42ba07 MOV %ESI,0x44(%RSP) |
0x42ba0b CALL 404650 <omp_get_num_threads@plt> |
0x42ba10 MOV %EAX,%R12D |
0x42ba13 CALL 404540 <omp_get_thread_num@plt> |
0x42ba18 XOR %EDX,%EDX |
0x42ba1a MOV %EAX,%R8D |
0x42ba1d MOV 0x44(%RSP),%EAX |
0x42ba21 IMUL %EBX,%EAX |
0x42ba24 DIV %R12D |
0x42ba27 MOV %EAX,%R12D |
0x42ba2a CMP %EDX,%R8D |
0x42ba2d JB 42bfcc |
0x42ba33 IMUL %R12D,%R8D |
0x42ba37 LEA (%R8,%RDX,1),%EBX |
0x42ba3b LEA (%R12,%RBX,1),%R9D |
0x42ba3f MOV %R9D,0x38(%RSP) |
0x42ba44 CMP %R9D,%EBX |
0x42ba47 JAE 42bf9b |
0x42ba4d MOV %EBX,%EAX |
0x42ba4f XOR %EDX,%EDX |
0x42ba51 MOV 0x3c(%RSP),%R10D |
0x42ba56 MOV 0x18(%R13),%RDI |
0x42ba5a DIVL 0x44(%RSP) |
0x42ba5e MOV %RDI,0x28(%RSP) |
0x42ba63 ADD %EDX,%R10D |
0x42ba66 LEA (%RAX,%R15,1),%R11D |
0x42ba6a MOV %R14D,%EDX |
0x42ba6d MOV 0x8(%R13),%R15 |
0x42ba71 MOV (%R13),%R14 |
0x42ba75 MOV 0x10(%R13),%R13 |
0x42ba79 MOV %R10D,0x7c(%RSP) |
0x42ba7e SUB %R10D,%EDX |
0x42ba81 MOV %R15,0x30(%RSP) |
0x42ba86 MOVSXD %R11D,%RSI |
0x42ba89 MOV %R14,0x20(%RSP) |
0x42ba8e MOV %R13,0x18(%RSP) |
0x42ba93 NOPL (%RAX,%RAX,1) |
(182) 0x42ba98 CMP %EDX,%R12D |
(182) 0x42ba9b CMOVBE %R12D,%EDX |
(182) 0x42ba9f LEA (%RBX,%RDX,1),%ECX |
(182) 0x42baa2 MOV %ECX,0x78(%RSP) |
(182) 0x42baa6 CMP %ECX,%EBX |
(182) 0x42baa8 JAE 42bfb0 |
(182) 0x42baae MOV 0x20(%RSP),%RAX |
(182) 0x42bab3 MOV 0x30(%RSP),%R12 |
(182) 0x42bab8 MOV 0x28(%RSP),%R8 |
(182) 0x42babd MOV 0x18(%RSP),%RCX |
(182) 0x42bac2 MOV (%RAX),%R11 |
(182) 0x42bac5 MOV (%R12),%R9 |
(182) 0x42bac9 MOV 0x10(%R12),%R15 |
(182) 0x42bace LEA 0x1(%RSI),%R12 |
(182) 0x42bad2 MOV (%R8),%R10 |
(182) 0x42bad5 IMUL %RSI,%R9 |
(182) 0x42bad9 MOV 0x10(%R8),%R14 |
(182) 0x42badd MOV 0x10(%RCX),%R13 |
(182) 0x42bae1 MOV %R12,0x48(%RSP) |
(182) 0x42bae6 IMUL %R11,%R12 |
(182) 0x42baea MOV 0x10(%RAX),%RDI |
(182) 0x42baee LEA -0x1(%RDX),%EAX |
(182) 0x42baf1 IMUL %RSI,%R10 |
(182) 0x42baf5 MOV %R13,0x68(%RSP) |
(182) 0x42bafa IMUL (%RCX),%RSI |
(182) 0x42bafe MOV %R9,0x50(%RSP) |
(182) 0x42bb03 MOV %R12,%R8 |
(182) 0x42bb06 SUB %R11,%R8 |
(182) 0x42bb09 MOV %R10,0x58(%RSP) |
(182) 0x42bb0e MOV %R8,0x60(%RSP) |
(182) 0x42bb13 MOV %RSI,0x70(%RSP) |
(182) 0x42bb18 CMP $0x6,%EAX |
(182) 0x42bb1b JBE 42bfc0 |
(182) 0x42bb21 MOVSXD 0x7c(%RSP),%RAX |
(182) 0x42bb26 LEA (%R9,%RAX,1),%R9 |
(182) 0x42bb2a LEA (%R10,%RAX,1),%RCX |
(182) 0x42bb2e LEA (%R8,%RAX,1),%R8 |
(182) 0x42bb32 LEA (%R15,%R9,8),%R11 |
(182) 0x42bb36 LEA (%R12,%RAX,1),%R9 |
(182) 0x42bb3a ADD %RSI,%RAX |
(182) 0x42bb3d LEA (%R14,%RCX,8),%R10 |
(182) 0x42bb41 LEA (%R13,%RAX,8),%RSI |
(182) 0x42bb46 MOV %EDX,%R13D |
(182) 0x42bb49 LEA (%RDI,%R9,8),%R9 |
(182) 0x42bb4d XOR %EAX,%EAX |
(182) 0x42bb4f SHR $0x3,%R13D |
(182) 0x42bb53 LEA (%RDI,%R8,8),%R8 |
(182) 0x42bb57 SAL $0x6,%R13 |
(182) 0x42bb5b LEA -0x40(%R13),%RCX |
(182) 0x42bb5f SHR $0x6,%RCX |
(182) 0x42bb63 INC %RCX |
(182) 0x42bb66 AND $0x7,%ECX |
(182) 0x42bb69 JE 42bcb5 |
(182) 0x42bb6f CMP $0x1,%RCX |
(182) 0x42bb73 JE 42bc85 |
(182) 0x42bb79 CMP $0x2,%RCX |
(182) 0x42bb7d JE 42bc5e |
(182) 0x42bb83 CMP $0x3,%RCX |
(182) 0x42bb87 JE 42bc37 |
(182) 0x42bb8d CMP $0x4,%RCX |
(182) 0x42bb91 JE 42bc10 |
(182) 0x42bb93 CMP $0x5,%RCX |
(182) 0x42bb97 JE 42bbe9 |
(182) 0x42bb99 CMP $0x6,%RCX |
(182) 0x42bb9d JE 42bbc2 |
(182) 0x42bb9f VMOVUPD (%R11),%ZMM0 |
(182) 0x42bba5 MOV $0x40,%EAX |
(182) 0x42bbaa VMOVUPD %ZMM0,(%R10) |
(182) 0x42bbb0 VADDPD (%R9),%ZMM0,%ZMM1 |
(182) 0x42bbb6 VSUBPD (%R8),%ZMM1,%ZMM2 |
(182) 0x42bbbc VMOVUPD %ZMM2,(%RSI) |
(182) 0x42bbc2 VMOVUPD (%R11,%RAX,1),%ZMM3 |
(182) 0x42bbc9 VMOVUPD %ZMM3,(%R10,%RAX,1) |
(182) 0x42bbd0 VADDPD (%R9,%RAX,1),%ZMM3,%ZMM4 |
(182) 0x42bbd7 VSUBPD (%R8,%RAX,1),%ZMM4,%ZMM5 |
(182) 0x42bbde VMOVUPD %ZMM5,(%RSI,%RAX,1) |
(182) 0x42bbe5 ADD $0x40,%RAX |
(182) 0x42bbe9 VMOVUPD (%R11,%RAX,1),%ZMM6 |
(182) 0x42bbf0 VMOVUPD %ZMM6,(%R10,%RAX,1) |
(182) 0x42bbf7 VADDPD (%R9,%RAX,1),%ZMM6,%ZMM7 |
(182) 0x42bbfe VSUBPD (%R8,%RAX,1),%ZMM7,%ZMM8 |
(182) 0x42bc05 VMOVUPD %ZMM8,(%RSI,%RAX,1) |
(182) 0x42bc0c ADD $0x40,%RAX |
(182) 0x42bc10 VMOVUPD (%R11,%RAX,1),%ZMM9 |
(182) 0x42bc17 VMOVUPD %ZMM9,(%R10,%RAX,1) |
(182) 0x42bc1e VADDPD (%R9,%RAX,1),%ZMM9,%ZMM10 |
(182) 0x42bc25 VSUBPD (%R8,%RAX,1),%ZMM10,%ZMM11 |
(182) 0x42bc2c VMOVUPD %ZMM11,(%RSI,%RAX,1) |
(182) 0x42bc33 ADD $0x40,%RAX |
(182) 0x42bc37 VMOVUPD (%R11,%RAX,1),%ZMM12 |
(182) 0x42bc3e VMOVUPD %ZMM12,(%R10,%RAX,1) |
(182) 0x42bc45 VADDPD (%R9,%RAX,1),%ZMM12,%ZMM13 |
(182) 0x42bc4c VSUBPD (%R8,%RAX,1),%ZMM13,%ZMM14 |
(182) 0x42bc53 VMOVUPD %ZMM14,(%RSI,%RAX,1) |
(182) 0x42bc5a ADD $0x40,%RAX |
(182) 0x42bc5e VMOVUPD (%R11,%RAX,1),%ZMM15 |
(182) 0x42bc65 VMOVUPD %ZMM15,(%R10,%RAX,1) |
(182) 0x42bc6c VADDPD (%R9,%RAX,1),%ZMM15,%ZMM0 |
(182) 0x42bc73 VSUBPD (%R8,%RAX,1),%ZMM0,%ZMM1 |
(182) 0x42bc7a VMOVUPD %ZMM1,(%RSI,%RAX,1) |
(182) 0x42bc81 ADD $0x40,%RAX |
(182) 0x42bc85 VMOVUPD (%R11,%RAX,1),%ZMM2 |
(182) 0x42bc8c VMOVUPD %ZMM2,(%R10,%RAX,1) |
(182) 0x42bc93 VADDPD (%R9,%RAX,1),%ZMM2,%ZMM3 |
(182) 0x42bc9a VSUBPD (%R8,%RAX,1),%ZMM3,%ZMM4 |
(182) 0x42bca1 VMOVUPD %ZMM4,(%RSI,%RAX,1) |
(182) 0x42bca8 ADD $0x40,%RAX |
(182) 0x42bcac CMP %R13,%RAX |
(182) 0x42bcaf JE 42bdff |
(183) 0x42bcb5 VMOVUPD (%R11,%RAX,1),%ZMM5 |
(183) 0x42bcbc VMOVUPD %ZMM5,(%R10,%RAX,1) |
(183) 0x42bcc3 VADDPD (%R9,%RAX,1),%ZMM5,%ZMM6 |
(183) 0x42bcca VSUBPD (%R8,%RAX,1),%ZMM6,%ZMM7 |
(183) 0x42bcd1 VMOVUPD %ZMM7,(%RSI,%RAX,1) |
(183) 0x42bcd8 VMOVUPD 0x40(%R11,%RAX,1),%ZMM8 |
(183) 0x42bce0 VMOVUPD %ZMM8,0x40(%R10,%RAX,1) |
(183) 0x42bce8 VADDPD 0x40(%R9,%RAX,1),%ZMM8,%ZMM9 |
(183) 0x42bcf0 VSUBPD 0x40(%R8,%RAX,1),%ZMM9,%ZMM10 |
(183) 0x42bcf8 VMOVUPD %ZMM10,0x40(%RSI,%RAX,1) |
(183) 0x42bd00 VMOVUPD 0x80(%R11,%RAX,1),%ZMM11 |
(183) 0x42bd08 VMOVUPD %ZMM11,0x80(%R10,%RAX,1) |
(183) 0x42bd10 VADDPD 0x80(%R9,%RAX,1),%ZMM11,%ZMM12 |
(183) 0x42bd18 VSUBPD 0x80(%R8,%RAX,1),%ZMM12,%ZMM13 |
(183) 0x42bd20 VMOVUPD %ZMM13,0x80(%RSI,%RAX,1) |
(183) 0x42bd28 VMOVUPD 0xc0(%R11,%RAX,1),%ZMM14 |
(183) 0x42bd30 VMOVUPD %ZMM14,0xc0(%R10,%RAX,1) |
(183) 0x42bd38 VADDPD 0xc0(%R9,%RAX,1),%ZMM14,%ZMM15 |
(183) 0x42bd40 VSUBPD 0xc0(%R8,%RAX,1),%ZMM15,%ZMM0 |
(183) 0x42bd48 VMOVUPD %ZMM0,0xc0(%RSI,%RAX,1) |
(183) 0x42bd50 VMOVUPD 0x100(%R11,%RAX,1),%ZMM1 |
(183) 0x42bd58 VMOVUPD %ZMM1,0x100(%R10,%RAX,1) |
(183) 0x42bd60 VADDPD 0x100(%R9,%RAX,1),%ZMM1,%ZMM2 |
(183) 0x42bd68 VSUBPD 0x100(%R8,%RAX,1),%ZMM2,%ZMM3 |
(183) 0x42bd70 VMOVUPD %ZMM3,0x100(%RSI,%RAX,1) |
(183) 0x42bd78 VMOVUPD 0x140(%R11,%RAX,1),%ZMM4 |
(183) 0x42bd80 VMOVUPD %ZMM4,0x140(%R10,%RAX,1) |
(183) 0x42bd88 VADDPD 0x140(%R9,%RAX,1),%ZMM4,%ZMM5 |
(183) 0x42bd90 VSUBPD 0x140(%R8,%RAX,1),%ZMM5,%ZMM6 |
(183) 0x42bd98 VMOVUPD %ZMM6,0x140(%RSI,%RAX,1) |
(183) 0x42bda0 VMOVUPD 0x180(%R11,%RAX,1),%ZMM7 |
(183) 0x42bda8 VMOVUPD %ZMM7,0x180(%R10,%RAX,1) |
(183) 0x42bdb0 VADDPD 0x180(%R9,%RAX,1),%ZMM7,%ZMM8 |
(183) 0x42bdb8 VSUBPD 0x180(%R8,%RAX,1),%ZMM8,%ZMM9 |
(183) 0x42bdc0 VMOVUPD %ZMM9,0x180(%RSI,%RAX,1) |
(183) 0x42bdc8 VMOVUPD 0x1c0(%R11,%RAX,1),%ZMM10 |
(183) 0x42bdd0 VMOVUPD %ZMM10,0x1c0(%R10,%RAX,1) |
(183) 0x42bdd8 VADDPD 0x1c0(%R9,%RAX,1),%ZMM10,%ZMM11 |
(183) 0x42bde0 VSUBPD 0x1c0(%R8,%RAX,1),%ZMM11,%ZMM12 |
(183) 0x42bde8 VMOVUPD %ZMM12,0x1c0(%RSI,%RAX,1) |
(183) 0x42bdf0 ADD $0x200,%RAX |
(183) 0x42bdf6 CMP %R13,%RAX |
(183) 0x42bdf9 JNE 42bcb5 |
(182) 0x42bdff MOV 0x7c(%RSP),%R11D |
(182) 0x42be04 MOV %EDX,%R10D |
(182) 0x42be07 AND $-0x8,%R10D |
(182) 0x42be0b ADD %R10D,%EBX |
(182) 0x42be0e LEA (%R10,%R11,1),%ESI |
(182) 0x42be12 TEST $0x7,%DL |
(182) 0x42be15 JE 42bf66 |
(182) 0x42be1b SUB %R10D,%EDX |
(182) 0x42be1e LEA -0x1(%RDX),%R9D |
(182) 0x42be22 CMP $0x2,%R9D |
(182) 0x42be26 JBE 42be95 |
(182) 0x42be28 MOVSXD 0x7c(%RSP),%R13 |
(182) 0x42be2d MOV 0x50(%RSP),%R8 |
(182) 0x42be32 MOV 0x58(%RSP),%RAX |
(182) 0x42be37 LEA (%R8,%R13,1),%RCX |
(182) 0x42be3b LEA (%R12,%R13,1),%R9 |
(182) 0x42be3f MOV 0x60(%RSP),%R8 |
(182) 0x42be44 ADD %R10,%RCX |
(182) 0x42be47 LEA (%RAX,%R13,1),%R11 |
(182) 0x42be4b ADD %R10,%R9 |
(182) 0x42be4e MOV 0x70(%RSP),%RAX |
(182) 0x42be53 VMOVUPD (%R15,%RCX,8),%YMM13 |
(182) 0x42be59 ADD %R10,%R11 |
(182) 0x42be5c LEA (%R8,%R13,1),%RCX |
(182) 0x42be60 ADD %R10,%RCX |
(182) 0x42be63 ADD %RAX,%R13 |
(182) 0x42be66 VMOVUPD %YMM13,(%R14,%R11,8) |
(182) 0x42be6c ADD %R10,%R13 |
(182) 0x42be6f MOV 0x68(%RSP),%R10 |
(182) 0x42be74 VADDPD (%RDI,%R9,8),%YMM13,%YMM14 |
(182) 0x42be7a VSUBPD (%RDI,%RCX,8),%YMM14,%YMM15 |
(182) 0x42be7f VMOVUPD %YMM15,(%R10,%R13,8) |
(182) 0x42be85 TEST $0x3,%DL |
(182) 0x42be88 JE 42bf66 |
(182) 0x42be8e AND $-0x4,%EDX |
(182) 0x42be91 ADD %EDX,%EBX |
(182) 0x42be93 ADD %EDX,%ESI |
(182) 0x42be95 MOV 0x50(%RSP),%R10 |
(182) 0x42be9a MOVSXD %ESI,%R13 |
(182) 0x42be9d MOV 0x58(%RSP),%R11 |
(182) 0x42bea2 LEA (%R12,%R13,1),%R8 |
(182) 0x42bea6 MOV 0x78(%RSP),%ECX |
(182) 0x42beaa LEA (%R10,%R13,1),%RDX |
(182) 0x42beae LEA (%R11,%R13,1),%R9 |
(182) 0x42beb2 VMOVSD (%R15,%RDX,8),%XMM0 |
(182) 0x42beb8 LEA 0x1(%RBX),%EDX |
(182) 0x42bebb VMOVSD %XMM0,(%R14,%R9,8) |
(182) 0x42bec1 MOV 0x70(%RSP),%R9 |
(182) 0x42bec6 VADDSD (%RDI,%R8,8),%XMM0,%XMM1 |
(182) 0x42becc MOV 0x60(%RSP),%R8 |
(182) 0x42bed1 LEA (%R9,%R13,1),%RAX |
(182) 0x42bed5 ADD %R8,%R13 |
(182) 0x42bed8 VSUBSD (%RDI,%R13,8),%XMM1,%XMM2 |
(182) 0x42bede MOV 0x68(%RSP),%R13 |
(182) 0x42bee3 VMOVSD %XMM2,(%R13,%RAX,8) |
(182) 0x42beea LEA 0x1(%RSI),%EAX |
(182) 0x42beed CMP %ECX,%EDX |
(182) 0x42beef JAE 42bf66 |
(182) 0x42bef1 CLTQ |
(182) 0x42bef3 ADD $0x2,%EBX |
(182) 0x42bef6 ADD $0x2,%ESI |
(182) 0x42bef9 LEA (%R10,%RAX,1),%RDX |
(182) 0x42befd LEA (%R11,%RAX,1),%RCX |
(182) 0x42bf01 VMOVSD (%R15,%RDX,8),%XMM3 |
(182) 0x42bf07 LEA (%R9,%RAX,1),%RDX |
(182) 0x42bf0b VMOVSD %XMM3,(%R14,%RCX,8) |
(182) 0x42bf11 LEA (%R12,%RAX,1),%RCX |
(182) 0x42bf15 ADD %R8,%RAX |
(182) 0x42bf18 VADDSD (%RDI,%RCX,8),%XMM3,%XMM4 |
(182) 0x42bf1d MOV %R8,%RCX |
(182) 0x42bf20 MOV 0x78(%RSP),%R8D |
(182) 0x42bf25 VSUBSD (%RDI,%RAX,8),%XMM4,%XMM5 |
(182) 0x42bf2a VMOVSD %XMM5,(%R13,%RDX,8) |
(182) 0x42bf31 CMP %R8D,%EBX |
(182) 0x42bf34 JAE 42bf66 |
(182) 0x42bf36 MOVSXD %ESI,%RBX |
(182) 0x42bf39 ADD %RBX,%R10 |
(182) 0x42bf3c ADD %RBX,%R11 |
(182) 0x42bf3f ADD %RBX,%R12 |
(182) 0x42bf42 ADD %RBX,%RCX |
(182) 0x42bf45 VMOVSD (%R15,%R10,8),%XMM6 |
(182) 0x42bf4b ADD %RBX,%R9 |
(182) 0x42bf4e VMOVSD %XMM6,(%R14,%R11,8) |
(182) 0x42bf54 VADDSD (%RDI,%R12,8),%XMM6,%XMM7 |
(182) 0x42bf5a VSUBSD (%RDI,%RCX,8),%XMM7,%XMM8 |
(182) 0x42bf5f VMOVSD %XMM8,(%R13,%R9,8) |
(182) 0x42bf66 MOV 0x78(%RSP),%EBX |
(182) 0x42bf6a MOV 0x48(%RSP),%RSI |
(182) 0x42bf6f LEA (%RSI),%R15D |
(182) 0x42bf72 CMP %R15D,0x40(%RSP) |
(182) 0x42bf77 JLE 42bf98 |
(182) 0x42bf79 MOV 0x38(%RSP),%R12D |
(182) 0x42bf7e MOV 0x3c(%RSP),%R14D |
(182) 0x42bf83 MOV 0x44(%RSP),%EDX |
(182) 0x42bf87 MOV %R14D,0x7c(%RSP) |
(182) 0x42bf8c SUB %EBX,%R12D |
(182) 0x42bf8f JMP 42ba98 |
0x42bf94 NOPL (%RAX) |
0x42bf98 VZEROUPPER |
0x42bf9b LEA -0x28(%RBP),%RSP |
0x42bf9f POP %RBX |
0x42bfa0 POP %R12 |
0x42bfa2 POP %R13 |
0x42bfa4 POP %R14 |
0x42bfa6 POP %R15 |
0x42bfa8 POP %RBP |
0x42bfa9 RET |
0x42bfaa NOPW (%RAX,%RAX,1) |
(182) 0x42bfb0 LEA 0x1(%RSI),%RSI |
(182) 0x42bfb4 MOV %RSI,0x48(%RSP) |
(182) 0x42bfb9 JMP 42bf6a |
0x42bfbb NOPL (%RAX,%RAX,1) |
(182) 0x42bfc0 MOV 0x7c(%RSP),%ESI |
(182) 0x42bfc4 XOR %R10D,%R10D |
(182) 0x42bfc7 JMP 42be1b |
0x42bfcc INC %R12D |
0x42bfcf XOR %EDX,%EDX |
0x42bfd1 JMP 42ba33 |
0x42bfd6 NOPW %CS:(%RAX,%RAX,1) |
Path / |
Source file and lines | advec_mom.cpp:62-66 |
Module | exec |
nb instructions | 81 |
nb uops | 91 |
loop length | 285 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 10 |
micro-operation queue | 15.17 cycles |
front end | 15.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 5.70 | 8.00 | 6.00 | 6.00 | 8.50 | 5.87 | 5.70 | 8.50 | 8.50 | 8.50 | 5.73 | 6.00 |
cycles | 5.70 | 11.73 | 6.00 | 6.00 | 8.50 | 5.87 | 5.70 | 8.50 | 8.50 | 8.50 | 5.73 | 6.00 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.41-14.53 |
Stall cycles | 0.00 |
Front-end | 15.17 |
Dispatch | 11.73 |
DIV/SQRT | 12.00 |
Overall L1 | 15.17 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 14% |
all | 8% |
load | 8% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 9% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD $-0x80,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x28(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RDI),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x24(%R13),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x4,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA -0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA -0x1(%RBX),%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EDI,0x3c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 42bf9b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.2+0x5eb> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x4(%RCX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 42bf9b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.2+0x5eb> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R14D,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %EDI,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ESI,0x44(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 404650 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 404540 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x44(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 42bfcc <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.2+0x61c> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %R12D,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%R12,%RBX,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R9D,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R9D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 42bf9b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.2+0x5eb> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EBX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x3c(%RSP),%R10D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%R13),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x44(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV %RDI,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%RAX,%R15,1),%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R14D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x8(%R13),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R13),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%R13),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10D,0x7c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R10D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R15,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVSXD %R11D,%RSI | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R14,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R13,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 42ba33 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.2+0x83> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | advec_mom.cpp:62-66 |
Module | exec |
nb instructions | 81 |
nb uops | 91 |
loop length | 285 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 10 |
micro-operation queue | 15.17 cycles |
front end | 15.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 5.70 | 8.00 | 6.00 | 6.00 | 8.50 | 5.87 | 5.70 | 8.50 | 8.50 | 8.50 | 5.73 | 6.00 |
cycles | 5.70 | 11.73 | 6.00 | 6.00 | 8.50 | 5.87 | 5.70 | 8.50 | 8.50 | 8.50 | 5.73 | 6.00 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.41-14.53 |
Stall cycles | 0.00 |
Front-end | 15.17 |
Dispatch | 11.73 |
DIV/SQRT | 12.00 |
Overall L1 | 15.17 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 14% |
all | 8% |
load | 8% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 9% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD $-0x80,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x28(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RDI),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x24(%R13),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x4,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA -0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA -0x1(%RBX),%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EDI,0x3c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 42bf9b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.2+0x5eb> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x4(%RCX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 42bf9b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.2+0x5eb> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R14D,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %EDI,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ESI,0x44(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 404650 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 404540 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x44(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 42bfcc <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.2+0x61c> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %R12D,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%R12,%RBX,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R9D,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R9D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 42bf9b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.2+0x5eb> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EBX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x3c(%RSP),%R10D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%R13),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x44(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV %RDI,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%RAX,%R15,1),%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R14D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x8(%R13),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R13),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%R13),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10D,0x7c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R10D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R15,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVSXD %R11D,%RSI | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R14,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R13,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 42ba33 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.2+0x83> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.2– | 2.19 | 0.73 |
▼Loop 182 - advec_mom.cpp:62-66 - exec– | 0.01 | 0 |
○Loop 183 - advec_mom.cpp:65-66 - exec | 2.18 | 0.73 |