Function: _Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buf ... | Module: exec | Source: advec_mom.cpp:157-160 [...] | Coverage: 0.75% |
---|
Function: _Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buf ... | Module: exec | Source: advec_mom.cpp:157-160 [...] | Coverage: 0.75% |
---|
/home/eoseret/qaas_runs_CPU_9468/171-112-9712/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69 |
-------------------------------------------------------------------------------- |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
/home/eoseret/qaas_runs_CPU_9468/171-112-9712/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp: 157 - 160 |
-------------------------------------------------------------------------------- |
157: #pragma omp parallel for simd collapse(2) |
158: for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) { |
159: for (int i = (x_min + 1); i < (x_max + 1 + 2); i++) { |
160: node_flux(i, j) = 0.25 * (mass_flux_y(i - 1, j + 0) + mass_flux_y(i, j) + mass_flux_y(i - 1, j + 1) + mass_flux_y(i + 0, j + 1)); |
0x42e1a0 PUSH %RBP |
0x42e1a1 MOV %RSP,%RBP |
0x42e1a4 PUSH %R15 |
0x42e1a6 PUSH %R14 |
0x42e1a8 PUSH %R13 |
0x42e1aa PUSH %R12 |
0x42e1ac PUSH %RBX |
0x42e1ad AND $-0x40,%RSP |
0x42e1b1 SUB $0x40,%RSP |
0x42e1b5 MOV 0x18(%RDI),%EAX |
0x42e1b8 MOV 0x1c(%RDI),%EDX |
0x42e1bb MOV 0x10(%RDI),%ESI |
0x42e1be MOV 0x14(%RDI),%EBX |
0x42e1c1 ADD $0x4,%EDX |
0x42e1c4 LEA -0x1(%RAX),%R15D |
0x42e1c8 LEA 0x1(%RSI),%ECX |
0x42e1cb MOV %EDX,0x20(%RSP) |
0x42e1cf MOV %ECX,0x1c(%RSP) |
0x42e1d3 CMP %EDX,%R15D |
0x42e1d6 JGE 42e63b |
0x42e1dc LEA 0x3(%RBX),%R13D |
0x42e1e0 MOV %EDX,%EBX |
0x42e1e2 SUB %R15D,%EBX |
0x42e1e5 CMP %R13D,%ECX |
0x42e1e8 JGE 42e63b |
0x42e1ee MOV %RDI,%R14 |
0x42e1f1 MOV %R13D,%EDI |
0x42e1f4 SUB %ECX,%EDI |
0x42e1f6 MOV %EDI,0x24(%RSP) |
0x42e1fa CALL 404650 <omp_get_num_threads@plt> |
0x42e1ff MOV %EAX,%R12D |
0x42e202 CALL 404540 <omp_get_thread_num@plt> |
0x42e207 MOV 0x24(%RSP),%R9D |
0x42e20c XOR %EDX,%EDX |
0x42e20e MOV %EAX,%R8D |
0x42e211 IMUL %R9D,%EBX |
0x42e215 MOV %EBX,%EAX |
0x42e217 DIV %R12D |
0x42e21a MOV %EAX,%EDI |
0x42e21c CMP %EDX,%R8D |
0x42e21f JB 42e65b |
0x42e225 IMUL %EDI,%R8D |
0x42e229 LEA (%R8,%RDX,1),%R12D |
0x42e22d LEA (%RDI,%R12,1),%R10D |
0x42e231 MOV %R10D,0x18(%RSP) |
0x42e236 CMP %R10D,%R12D |
0x42e239 JAE 42e63b |
0x42e23f MOV %R12D,%EAX |
0x42e242 XOR %EDX,%EDX |
0x42e244 MOV 0x1c(%RSP),%R11D |
0x42e249 MOV 0x8(%R14),%RCX |
0x42e24d DIVL 0x24(%RSP) |
0x42e251 VMOVSD 0x305a7(%RIP),%XMM3 |
0x42e259 MOV %RCX,0x8(%RSP) |
0x42e25e VBROADCASTSD %XMM3,%YMM4 |
0x42e263 VBROADCASTSD %XMM3,%ZMM2 |
0x42e269 ADD %R15D,%EAX |
0x42e26c MOV (%R14),%R15 |
0x42e26f LEA (%RDX,%R11,1),%ESI |
0x42e273 MOV %R13D,%EDX |
0x42e276 CLTQ |
0x42e278 MOV %ESI,0x3c(%RSP) |
0x42e27c SUB %ESI,%EDX |
0x42e27e MOV %R15,0x10(%RSP) |
0x42e283 MOV %RAX,0x30(%RSP) |
0x42e288 NOPL (%RAX,%RAX,1) |
(194) 0x42e290 CMP %EDX,%EDI |
(194) 0x42e292 CMOVBE %EDI,%EDX |
(194) 0x42e295 LEA (%R12,%RDX,1),%R13D |
(194) 0x42e299 MOV %R13D,0x38(%RSP) |
(194) 0x42e29e CMP %R13D,%R12D |
(194) 0x42e2a1 JAE 42e604 |
(194) 0x42e2a7 MOV 0x10(%RSP),%RBX |
(194) 0x42e2ac MOV 0x30(%RSP),%R9 |
(194) 0x42e2b1 LEA -0x1(%RDX),%EDI |
(194) 0x42e2b4 MOV 0x8(%RSP),%R14 |
(194) 0x42e2b9 MOV (%RBX),%R8 |
(194) 0x42e2bc MOV %R9,%R10 |
(194) 0x42e2bf MOV 0x10(%RBX),%RCX |
(194) 0x42e2c3 IMUL (%R14),%R9 |
(194) 0x42e2c7 MOV 0x10(%R14),%R15 |
(194) 0x42e2cb IMUL %R8,%R10 |
(194) 0x42e2cf MOV %R9,0x28(%RSP) |
(194) 0x42e2d4 ADD %R10,%R8 |
(194) 0x42e2d7 CMP $0x6,%EDI |
(194) 0x42e2da JBE 42e650 |
(194) 0x42e2e0 MOVSXD 0x3c(%RSP),%R11 |
(194) 0x42e2e5 XOR %EAX,%EAX |
(194) 0x42e2e7 LEA (%R11,%R10,1),%RDI |
(194) 0x42e2eb LEA (%R11,%R8,1),%RSI |
(194) 0x42e2ef ADD %R9,%R11 |
(194) 0x42e2f2 LEA (%R15,%R11,8),%RBX |
(194) 0x42e2f6 SAL $0x3,%RDI |
(194) 0x42e2fa MOV %EDX,%R11D |
(194) 0x42e2fd SAL $0x3,%RSI |
(194) 0x42e301 SHR $0x3,%R11D |
(194) 0x42e305 LEA -0x8(%RCX,%RDI,1),%R14 |
(194) 0x42e30a LEA -0x8(%RCX,%RSI,1),%R13 |
(194) 0x42e30f ADD %RCX,%RDI |
(194) 0x42e312 SAL $0x6,%R11 |
(194) 0x42e316 ADD %RCX,%RSI |
(194) 0x42e319 LEA -0x40(%R11),%R9 |
(194) 0x42e31d SHR $0x6,%R9 |
(194) 0x42e321 INC %R9 |
(194) 0x42e324 AND $0x3,%R9D |
(194) 0x42e328 JE 42e3db |
(194) 0x42e32e CMP $0x1,%R9 |
(194) 0x42e332 JE 42e39e |
(194) 0x42e334 CMP $0x2,%R9 |
(194) 0x42e338 JE 42e36a |
(194) 0x42e33a VMOVUPD (%R14),%ZMM7 |
(194) 0x42e340 VMOVUPD (%R13),%ZMM1 |
(194) 0x42e347 MOV $0x40,%EAX |
(194) 0x42e34c VADDPD (%RDI),%ZMM7,%ZMM0 |
(194) 0x42e352 VADDPD (%RSI),%ZMM1,%ZMM5 |
(194) 0x42e358 VADDPD %ZMM5,%ZMM0,%ZMM6 |
(194) 0x42e35e VMULPD %ZMM2,%ZMM6,%ZMM8 |
(194) 0x42e364 VMOVUPD %ZMM8,(%RBX) |
(194) 0x42e36a VMOVUPD (%R14,%RAX,1),%ZMM9 |
(194) 0x42e371 VMOVUPD (%R13,%RAX,1),%ZMM11 |
(194) 0x42e379 VADDPD (%RDI,%RAX,1),%ZMM9,%ZMM10 |
(194) 0x42e380 VADDPD (%RSI,%RAX,1),%ZMM11,%ZMM12 |
(194) 0x42e387 VADDPD %ZMM12,%ZMM10,%ZMM13 |
(194) 0x42e38d VMULPD %ZMM2,%ZMM13,%ZMM14 |
(194) 0x42e393 VMOVUPD %ZMM14,(%RBX,%RAX,1) |
(194) 0x42e39a ADD $0x40,%RAX |
(194) 0x42e39e VMOVUPD (%R14,%RAX,1),%ZMM15 |
(194) 0x42e3a5 VMOVUPD (%R13,%RAX,1),%ZMM7 |
(194) 0x42e3ad VADDPD (%RDI,%RAX,1),%ZMM15,%ZMM0 |
(194) 0x42e3b4 VADDPD (%RSI,%RAX,1),%ZMM7,%ZMM1 |
(194) 0x42e3bb VADDPD %ZMM1,%ZMM0,%ZMM5 |
(194) 0x42e3c1 VMULPD %ZMM2,%ZMM5,%ZMM6 |
(194) 0x42e3c7 VMOVUPD %ZMM6,(%RBX,%RAX,1) |
(194) 0x42e3ce ADD $0x40,%RAX |
(194) 0x42e3d2 CMP %RAX,%R11 |
(194) 0x42e3d5 JE 42e4b6 |
(195) 0x42e3db VMOVUPD (%R14,%RAX,1),%ZMM8 |
(195) 0x42e3e2 VMOVUPD (%R13,%RAX,1),%ZMM10 |
(195) 0x42e3ea VADDPD (%RDI,%RAX,1),%ZMM8,%ZMM9 |
(195) 0x42e3f1 VADDPD (%RSI,%RAX,1),%ZMM10,%ZMM11 |
(195) 0x42e3f8 VADDPD %ZMM11,%ZMM9,%ZMM12 |
(195) 0x42e3fe VMULPD %ZMM2,%ZMM12,%ZMM13 |
(195) 0x42e404 VMOVUPD %ZMM13,(%RBX,%RAX,1) |
(195) 0x42e40b VMOVUPD 0x40(%R14,%RAX,1),%ZMM14 |
(195) 0x42e413 VMOVUPD 0x40(%R13,%RAX,1),%ZMM0 |
(195) 0x42e41b VADDPD 0x40(%RDI,%RAX,1),%ZMM14,%ZMM15 |
(195) 0x42e423 VADDPD 0x40(%RSI,%RAX,1),%ZMM0,%ZMM7 |
(195) 0x42e42b VADDPD %ZMM7,%ZMM15,%ZMM1 |
(195) 0x42e431 VMULPD %ZMM2,%ZMM1,%ZMM5 |
(195) 0x42e437 VMOVUPD %ZMM5,0x40(%RBX,%RAX,1) |
(195) 0x42e43f VMOVUPD 0x80(%R14,%RAX,1),%ZMM6 |
(195) 0x42e447 VMOVUPD 0x80(%R13,%RAX,1),%ZMM9 |
(195) 0x42e44f VADDPD 0x80(%RDI,%RAX,1),%ZMM6,%ZMM8 |
(195) 0x42e457 VADDPD 0x80(%RSI,%RAX,1),%ZMM9,%ZMM10 |
(195) 0x42e45f VADDPD %ZMM10,%ZMM8,%ZMM11 |
(195) 0x42e465 VMULPD %ZMM2,%ZMM11,%ZMM12 |
(195) 0x42e46b VMOVUPD %ZMM12,0x80(%RBX,%RAX,1) |
(195) 0x42e473 VMOVUPD 0xc0(%R14,%RAX,1),%ZMM13 |
(195) 0x42e47b VMOVUPD 0xc0(%R13,%RAX,1),%ZMM15 |
(195) 0x42e483 VADDPD 0xc0(%RDI,%RAX,1),%ZMM13,%ZMM14 |
(195) 0x42e48b VADDPD 0xc0(%RSI,%RAX,1),%ZMM15,%ZMM0 |
(195) 0x42e493 VADDPD %ZMM0,%ZMM14,%ZMM7 |
(195) 0x42e499 VMULPD %ZMM2,%ZMM7,%ZMM1 |
(195) 0x42e49f VMOVUPD %ZMM1,0xc0(%RBX,%RAX,1) |
(195) 0x42e4a7 ADD $0x100,%RAX |
(195) 0x42e4ad CMP %RAX,%R11 |
(195) 0x42e4b0 JNE 42e3db |
(194) 0x42e4b6 MOV 0x3c(%RSP),%ESI |
(194) 0x42e4ba MOV %EDX,%EAX |
(194) 0x42e4bc AND $-0x8,%EAX |
(194) 0x42e4bf ADD %EAX,%R12D |
(194) 0x42e4c2 ADD %EAX,%ESI |
(194) 0x42e4c4 TEST $0x7,%DL |
(194) 0x42e4c7 JE 42e5ff |
(194) 0x42e4cd SUB %EAX,%EDX |
(194) 0x42e4cf LEA -0x1(%RDX),%EDI |
(194) 0x42e4d2 CMP $0x2,%EDI |
(194) 0x42e4d5 JBE 42e52d |
(194) 0x42e4d7 MOVSXD 0x3c(%RSP),%R14 |
(194) 0x42e4dc MOV 0x28(%RSP),%R11 |
(194) 0x42e4e1 LEA (%R10,%R14,1),%R13 |
(194) 0x42e4e5 LEA (%R8,%R14,1),%RBX |
(194) 0x42e4e9 ADD %RAX,%R13 |
(194) 0x42e4ec ADD %RAX,%RBX |
(194) 0x42e4ef ADD %R11,%RAX |
(194) 0x42e4f2 VMOVUPD -0x8(%RCX,%R13,8),%YMM5 |
(194) 0x42e4f9 VMOVUPD (%RCX,%RBX,8),%YMM8 |
(194) 0x42e4fe ADD %R14,%RAX |
(194) 0x42e501 VADDPD -0x8(%RCX,%RBX,8),%YMM5,%YMM6 |
(194) 0x42e507 VADDPD (%RCX,%R13,8),%YMM8,%YMM9 |
(194) 0x42e50d VADDPD %YMM9,%YMM6,%YMM10 |
(194) 0x42e512 VMULPD %YMM4,%YMM10,%YMM11 |
(194) 0x42e516 VMOVUPD %YMM11,(%R15,%RAX,8) |
(194) 0x42e51c TEST $0x3,%DL |
(194) 0x42e51f JE 42e5ff |
(194) 0x42e525 AND $-0x4,%EDX |
(194) 0x42e528 ADD %EDX,%R12D |
(194) 0x42e52b ADD %EDX,%ESI |
(194) 0x42e52d MOVSXD %ESI,%RDX |
(194) 0x42e530 LEA -0x1(%RSI),%EAX |
(194) 0x42e533 MOV 0x28(%RSP),%RBX |
(194) 0x42e538 CLTQ |
(194) 0x42e53a LEA (%R8,%RDX,1),%R14 |
(194) 0x42e53e LEA (%RDX,%R10,1),%R9 |
(194) 0x42e542 LEA (%R10,%RAX,1),%R11 |
(194) 0x42e546 LEA (%RCX,%R14,8),%R13 |
(194) 0x42e54a ADD %R8,%RAX |
(194) 0x42e54d ADD %RBX,%RDX |
(194) 0x42e550 VMOVSD (%RCX,%R11,8),%XMM12 |
(194) 0x42e556 VMOVSD (%R13),%XMM14 |
(194) 0x42e55c LEA (%RCX,%R9,8),%RDI |
(194) 0x42e560 MOV 0x38(%RSP),%R9D |
(194) 0x42e565 VADDSD (%RCX,%RAX,8),%XMM12,%XMM13 |
(194) 0x42e56a VADDSD (%RDI),%XMM14,%XMM15 |
(194) 0x42e56e LEA 0x1(%RSI),%EAX |
(194) 0x42e571 VADDSD %XMM15,%XMM13,%XMM0 |
(194) 0x42e576 VMULSD %XMM3,%XMM0,%XMM7 |
(194) 0x42e57a VMOVSD %XMM7,(%R15,%RDX,8) |
(194) 0x42e580 LEA 0x1(%R12),%EDX |
(194) 0x42e585 CMP %R9D,%EDX |
(194) 0x42e588 JAE 42e5ff |
(194) 0x42e58a CLTQ |
(194) 0x42e58c VMOVSD (%R13),%XMM1 |
(194) 0x42e592 ADD $0x2,%R12D |
(194) 0x42e596 ADD $0x2,%ESI |
(194) 0x42e599 LEA (%R10,%RAX,1),%R14 |
(194) 0x42e59d LEA (%R8,%RAX,1),%RDX |
(194) 0x42e5a1 ADD %RBX,%RAX |
(194) 0x42e5a4 LEA (%RCX,%R14,8),%R11 |
(194) 0x42e5a8 LEA (%RCX,%RDX,8),%R14 |
(194) 0x42e5ac VMOVSD (%R14),%XMM6 |
(194) 0x42e5b1 VADDSD (%RDI),%XMM1,%XMM5 |
(194) 0x42e5b5 VADDSD (%R11),%XMM6,%XMM8 |
(194) 0x42e5ba VADDSD %XMM8,%XMM5,%XMM9 |
(194) 0x42e5bf VMULSD %XMM3,%XMM9,%XMM10 |
(194) 0x42e5c3 VMOVSD %XMM10,(%R15,%RAX,8) |
(194) 0x42e5c9 CMP %R9D,%R12D |
(194) 0x42e5cc JAE 42e5ff |
(194) 0x42e5ce MOVSXD %ESI,%R12 |
(194) 0x42e5d1 ADD %R12,%RBX |
(194) 0x42e5d4 ADD %R12,%R10 |
(194) 0x42e5d7 ADD %R8,%R12 |
(194) 0x42e5da VMOVSD (%RCX,%R10,8),%XMM11 |
(194) 0x42e5e0 VMOVSD (%RCX,%R12,8),%XMM13 |
(194) 0x42e5e6 VADDSD (%R11),%XMM11,%XMM12 |
(194) 0x42e5eb VADDSD (%R14),%XMM13,%XMM14 |
(194) 0x42e5f0 VADDSD %XMM14,%XMM12,%XMM15 |
(194) 0x42e5f5 VMULSD %XMM3,%XMM15,%XMM0 |
(194) 0x42e5f9 VMOVSD %XMM0,(%R15,%RBX,8) |
(194) 0x42e5ff MOV 0x38(%RSP),%R12D |
(194) 0x42e604 INCQ 0x30(%RSP) |
(194) 0x42e609 MOV 0x30(%RSP),%RCX |
(194) 0x42e60e ADD $0,%ECX |
(194) 0x42e611 CMP %ECX,0x20(%RSP) |
(194) 0x42e615 JLE 42e638 |
(194) 0x42e617 MOV 0x18(%RSP),%EDI |
(194) 0x42e61b MOV 0x1c(%RSP),%R8D |
(194) 0x42e620 MOV 0x24(%RSP),%EDX |
(194) 0x42e624 MOV %R8D,0x3c(%RSP) |
(194) 0x42e629 SUB %R12D,%EDI |
(194) 0x42e62c JMP 42e290 |
0x42e631 NOPL (%RAX) |
0x42e638 VZEROUPPER |
0x42e63b LEA -0x28(%RBP),%RSP |
0x42e63f POP %RBX |
0x42e640 POP %R12 |
0x42e642 POP %R13 |
0x42e644 POP %R14 |
0x42e646 POP %R15 |
0x42e648 POP %RBP |
0x42e649 RET |
0x42e64a NOPW (%RAX,%RAX,1) |
(194) 0x42e650 MOV 0x3c(%RSP),%ESI |
(194) 0x42e654 XOR %EAX,%EAX |
(194) 0x42e656 JMP 42e4cd |
0x42e65b INC %EDI |
0x42e65d XOR %EDX,%EDX |
0x42e65f JMP 42e225 |
0x42e664 NOPW %CS:(%RAX,%RAX,1) |
0x42e66f NOP |
Path / |
Source file and lines | advec_mom.cpp:157-160 |
Module | exec |
nb instructions | 82 |
nb uops | 92 |
loop length | 292 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 1 |
used ymm registers | 1 |
used zmm registers | 1 |
nb stack references | 9 |
micro-operation queue | 15.33 cycles |
front end | 15.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.30 | 8.00 | 5.67 | 5.67 | 8.00 | 6.20 | 6.30 | 8.00 | 8.00 | 8.00 | 6.20 | 5.67 |
cycles | 6.30 | 11.90 | 5.67 | 5.67 | 8.00 | 6.20 | 6.30 | 8.00 | 8.00 | 8.00 | 6.20 | 5.67 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.57-14.70 |
Stall cycles | 0.00 |
Front-end | 15.33 |
Dispatch | 11.90 |
DIV/SQRT | 12.00 |
Overall L1 | 15.33 |
all | 5% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 12% |
all | 9% |
load | 9% |
store | 8% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 9% |
all | 12% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
all | 9% |
load | 10% |
store | 8% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 10% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0x40,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x18(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x1c(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x14(%RDI),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x4,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA -0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA 0x1(%RSI),%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ECX,0x1c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 42e63b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.8+0x49b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA 0x3(%RBX),%R13D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R13D,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 42e63b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.8+0x49b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R13D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %ECX,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EDI,0x24(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 404650 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 404540 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x24(%RSP),%R9D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %R9D,%EBX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %EBX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 42e65b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.8+0x4bb> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %EDI,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RDI,%R12,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R10D,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R10D,%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 42e63b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.8+0x49b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R12D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x1c(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%R14),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x24(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
VMOVSD 0x305a7(%RIP),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VBROADCASTSD %XMM3,%YMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VBROADCASTSD %XMM3,%ZMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %R15D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV (%R14),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%RDX,%R11,1),%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R13D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CLTQ | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
MOV %ESI,0x3c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %ESI,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R15,0x10(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 42e225 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.8+0x85> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | advec_mom.cpp:157-160 |
Module | exec |
nb instructions | 82 |
nb uops | 92 |
loop length | 292 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 1 |
used ymm registers | 1 |
used zmm registers | 1 |
nb stack references | 9 |
micro-operation queue | 15.33 cycles |
front end | 15.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.30 | 8.00 | 5.67 | 5.67 | 8.00 | 6.20 | 6.30 | 8.00 | 8.00 | 8.00 | 6.20 | 5.67 |
cycles | 6.30 | 11.90 | 5.67 | 5.67 | 8.00 | 6.20 | 6.30 | 8.00 | 8.00 | 8.00 | 6.20 | 5.67 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.57-14.70 |
Stall cycles | 0.00 |
Front-end | 15.33 |
Dispatch | 11.90 |
DIV/SQRT | 12.00 |
Overall L1 | 15.33 |
all | 5% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 12% |
all | 9% |
load | 9% |
store | 8% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 9% |
all | 12% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
all | 9% |
load | 10% |
store | 8% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 10% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0x40,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x18(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x1c(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x14(%RDI),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x4,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA -0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA 0x1(%RSI),%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ECX,0x1c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 42e63b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.8+0x49b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA 0x3(%RBX),%R13D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R13D,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 42e63b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.8+0x49b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R13D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %ECX,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EDI,0x24(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 404650 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 404540 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x24(%RSP),%R9D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %R9D,%EBX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %EBX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 42e65b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.8+0x4bb> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %EDI,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RDI,%R12,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R10D,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R10D,%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 42e63b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.8+0x49b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R12D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x1c(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%R14),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x24(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
VMOVSD 0x305a7(%RIP),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VBROADCASTSD %XMM3,%YMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VBROADCASTSD %XMM3,%ZMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %R15D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV (%R14),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%RDX,%R11,1),%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R13D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CLTQ | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
MOV %ESI,0x3c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %ESI,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R15,0x10(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 42e225 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.8+0x85> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.8– | 0.75 | 0.25 |
▼Loop 194 - advec_mom.cpp:159-160 - exec– | 0.01 | 0 |
○Loop 195 - advec_mom.cpp:160-160 - exec | 0.74 | 0.25 |