Function: __svml_idiv4_e9 | Module: exec | Source: :0-0 | Coverage: 0.01% |
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Function: __svml_idiv4_e9 | Module: exec | Source: :0-0 | Coverage: 0.01% |
---|
*** This Panel is Intentionally Left Blank. *** It is due to a lack of debug symbols in the given object |
0x4525a0 ENDBR64 |
0x4525a4 VPXOR %XMM2,%XMM2,%XMM2 |
0x4525a8 VPCMPEQD %XMM2,%XMM1,%XMM2 |
0x4525ac VTESTPS %XMM2,%XMM2 |
0x4525b1 JE 4525ba |
0x4525b3 MOV $0,%EAX |
0x4525b8 DIV %AL |
0x4525ba VCVTDQ2PS %XMM1,%XMM2 |
0x4525be VRCPPS %XMM2,%XMM2 |
0x4525c2 VCVTPS2PD %XMM2,%YMM2 |
0x4525c6 VCVTDQ2PD %XMM1,%YMM1 |
0x4525ca VMULPD %YMM2,%YMM1,%YMM3 |
0x4525ce VBROADCASTSD 0x120d1(%RIP),%YMM4 |
0x4525d7 VSUBPD %YMM3,%YMM4,%YMM3 |
0x4525db VMULPD %YMM2,%YMM3,%YMM2 |
0x4525df VCVTDQ2PD %XMM0,%YMM0 |
0x4525e3 VMULPD %YMM0,%YMM2,%YMM0 |
0x4525e7 VMULPD %YMM1,%YMM2,%YMM1 |
0x4525eb VBROADCASTSD 0x2398c(%RIP),%YMM2 |
0x4525f4 VSUBPD %YMM1,%YMM2,%YMM1 |
0x4525f8 VMULPD %YMM1,%YMM0,%YMM0 |
0x4525fc VCVTTPD2DQ %YMM0,%XMM0 |
0x452600 VZEROUPPER |
0x452603 RET |
0x452604 NOPW %CS:(%RAX,%RAX,1) |
0x45260e XCHG %AX,%AX |
Path / |
Source file and lines | |
Module | exec |
nb instructions | 23 |
nb uops | 28.50 |
loop length | 96.50 |
used x86 registers | 0.50 |
used mmx registers | 0 |
used xmm registers | 3 |
used ymm registers | 5 |
used zmm registers | 0 |
nb stack references | 0 |
ADD-SUB / MUL ratio | 0.40 |
micro-operation queue | 4.75 cycles |
front end | 4.75 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 7.50 | 7.50 | 1.00 | 1.00 | 0.00 | 5.50 | 2.00 | 0.00 | 0.00 | 0.00 | 0.50 | 1.00 |
cycles | 7.50 | 7.50 | 1.00 | 1.00 | 0.00 | 5.50 | 2.00 | 0.00 | 0.00 | 0.00 | 0.50 | 1.00 |
Cycles executing div or sqrt instructions | 3.00 |
FE+BE cycles | 41.71-41.82 |
Stall cycles | 36.71-36.82 |
RS full (events) | 41.20-41.31 |
Front-end | 4.75 |
Dispatch | 7.50 |
DIV/SQRT | 3.00 |
Overall L1 | 7.50 |
all | 92% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 92% |
all | 84% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 100% |
other | 60% |
all | 87% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 100% |
other | 78% |
all | 23% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 23% |
all | 38% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 50% |
add-sub | 50% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 25% |
other | 25% |
all | 33% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 50% |
add-sub | 50% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 25% |
other | 24% |
Source file and lines | |
Module | exec |
nb instructions | 24 |
nb uops | 31 |
loop length | 100 |
used x86 registers | 1 |
used mmx registers | 0 |
used xmm registers | 3 |
used ymm registers | 5 |
used zmm registers | 0 |
nb stack references | 0 |
ADD-SUB / MUL ratio | 0.40 |
micro-operation queue | 5.17 cycles |
front end | 5.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 8.00 | 8.00 | 1.00 | 1.00 | 0.00 | 6.00 | 2.00 | 0.00 | 0.00 | 0.00 | 1.00 | 1.00 |
cycles | 8.00 | 8.00 | 1.00 | 1.00 | 0.00 | 6.00 | 2.00 | 0.00 | 0.00 | 0.00 | 1.00 | 1.00 |
Cycles executing div or sqrt instructions | 6.00 |
FE+BE cycles | 41.73-41.95 |
Stall cycles | 36.36-36.58 |
RS full (events) | 41.19-41.41 |
Front-end | 5.17 |
Dispatch | 8.00 |
DIV/SQRT | 6.00 |
Overall L1 | 8.00 |
all | 85% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 85% |
all | 84% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 100% |
other | 60% |
all | 85% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 100% |
other | 75% |
all | 22% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 22% |
all | 38% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 50% |
add-sub | 50% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 25% |
other | 25% |
all | 32% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 50% |
add-sub | 50% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 25% |
other | 23% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ENDBR64 | |||||||||||||||
VPXOR %XMM2,%XMM2,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VPCMPEQD %XMM2,%XMM1,%XMM2 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VTESTPS %XMM2,%XMM2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
JE 4525ba <__svml_idiv4_e9+0x1a> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV $0,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
DIV %AL | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
VCVTDQ2PS %XMM1,%XMM2 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VRCPPS %XMM2,%XMM2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 1 |
VCVTPS2PD %XMM2,%YMM2 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 7 | 1 |
VCVTDQ2PD %XMM1,%YMM1 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 7 | 1 |
VMULPD %YMM2,%YMM1,%YMM3 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VBROADCASTSD 0x120d1(%RIP),%YMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
VSUBPD %YMM3,%YMM4,%YMM3 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMULPD %YMM2,%YMM3,%YMM2 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VCVTDQ2PD %XMM0,%YMM0 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 7 | 1 |
VMULPD %YMM0,%YMM2,%YMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULPD %YMM1,%YMM2,%YMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VBROADCASTSD 0x2398c(%RIP),%YMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
VSUBPD %YMM1,%YMM2,%YMM1 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMULPD %YMM1,%YMM0,%YMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VCVTTPD2DQ %YMM0,%XMM0 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 7 | 1 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
Source file and lines | |
Module | exec |
nb instructions | 22 |
nb uops | 26 |
loop length | 93 |
used x86 registers | 0 |
used mmx registers | 0 |
used xmm registers | 3 |
used ymm registers | 5 |
used zmm registers | 0 |
nb stack references | 0 |
ADD-SUB / MUL ratio | 0.40 |
micro-operation queue | 4.33 cycles |
front end | 4.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 7.00 | 7.00 | 1.00 | 1.00 | 0.00 | 5.00 | 2.00 | 0.00 | 0.00 | 0.00 | 0.00 | 1.00 |
cycles | 7.00 | 7.00 | 1.00 | 1.00 | 0.00 | 5.00 | 2.00 | 0.00 | 0.00 | 0.00 | 0.00 | 1.00 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 41.69 |
Stall cycles | 37.06 |
RS full (events) | 41.21 |
Front-end | 4.33 |
Dispatch | 7.00 |
Overall L1 | 7.00 |
all | 100% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 100% |
all | 84% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 100% |
other | 60% |
all | 89% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 100% |
other | 81% |
all | 25% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 25% |
all | 38% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 50% |
add-sub | 50% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 25% |
other | 25% |
all | 34% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 50% |
add-sub | 50% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 25% |
other | 25% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ENDBR64 | |||||||||||||||
VPXOR %XMM2,%XMM2,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VPCMPEQD %XMM2,%XMM1,%XMM2 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VTESTPS %XMM2,%XMM2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
JE 4525ba <__svml_idiv4_e9+0x1a> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VCVTDQ2PS %XMM1,%XMM2 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VRCPPS %XMM2,%XMM2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 1 |
VCVTPS2PD %XMM2,%YMM2 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 7 | 1 |
VCVTDQ2PD %XMM1,%YMM1 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 7 | 1 |
VMULPD %YMM2,%YMM1,%YMM3 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VBROADCASTSD 0x120d1(%RIP),%YMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
VSUBPD %YMM3,%YMM4,%YMM3 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMULPD %YMM2,%YMM3,%YMM2 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VCVTDQ2PD %XMM0,%YMM0 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 7 | 1 |
VMULPD %YMM0,%YMM2,%YMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULPD %YMM1,%YMM2,%YMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VBROADCASTSD 0x2398c(%RIP),%YMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
VSUBPD %YMM1,%YMM2,%YMM1 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMULPD %YMM1,%YMM0,%YMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VCVTTPD2DQ %YMM0,%XMM0 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 7 | 1 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
Name | Coverage (%) | Time (s) |
---|---|---|
○__svml_idiv4_e9 | 0.01 | 0.01 |