Function: _Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buf ... | Module: exec | Source: advec_mom.cpp:146-149 [...] | Coverage: 3.56% |
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Function: _Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buf ... | Module: exec | Source: advec_mom.cpp:146-149 [...] | Coverage: 3.56% |
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/home/eoseret/qaas_runs_CPU_9468/171-112-9712/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69 |
-------------------------------------------------------------------------------- |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
/home/eoseret/qaas_runs_CPU_9468/171-112-9712/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp: 146 - 149 |
-------------------------------------------------------------------------------- |
146: #pragma omp parallel for simd collapse(2) |
147: for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) { |
148: for (int i = (x_min + 1); i < (x_max + 1 + 2); i++) { |
149: vel1(i, j) = (vel1(i, j) * node_mass_pre(i, j) + mom_flux(i - 1, j + 0) - mom_flux(i, j)) / node_mass_post(i, j); |
0x42d3a0 PUSH %RBP |
0x42d3a1 MOV %RSP,%RBP |
0x42d3a4 PUSH %R15 |
0x42d3a6 PUSH %R14 |
0x42d3a8 PUSH %R13 |
0x42d3aa PUSH %R12 |
0x42d3ac PUSH %RBX |
0x42d3ad AND $-0x40,%RSP |
0x42d3b1 ADD $-0x80,%RSP |
0x42d3b5 MOV 0x28(%RDI),%EAX |
0x42d3b8 MOV 0x2c(%RDI),%EDX |
0x42d3bb MOV 0x20(%RDI),%EBX |
0x42d3be MOV 0x24(%RDI),%ECX |
0x42d3c1 ADD $0x3,%EDX |
0x42d3c4 LEA 0x1(%RAX),%R15D |
0x42d3c8 LEA 0x1(%RBX),%ESI |
0x42d3cb MOV %EDX,0x44(%RSP) |
0x42d3cf MOV %ESI,0x40(%RSP) |
0x42d3d3 CMP %EDX,%R15D |
0x42d3d6 JGE 42d883 |
0x42d3dc MOV %EDX,%EBX |
0x42d3de LEA 0x3(%RCX),%R14D |
0x42d3e2 SUB %R15D,%EBX |
0x42d3e5 CMP %R14D,%ESI |
0x42d3e8 JGE 42d883 |
0x42d3ee MOV %RDI,%R13 |
0x42d3f1 MOV %R14D,%EDI |
0x42d3f4 SUB %ESI,%EDI |
0x42d3f6 MOV %EDI,0x68(%RSP) |
0x42d3fa CALL 404650 <omp_get_num_threads@plt> |
0x42d3ff MOV %EAX,%R12D |
0x42d402 CALL 404540 <omp_get_thread_num@plt> |
0x42d407 XOR %EDX,%EDX |
0x42d409 MOV %EAX,%R8D |
0x42d40c MOV 0x68(%RSP),%EAX |
0x42d410 IMUL %EBX,%EAX |
0x42d413 DIV %R12D |
0x42d416 MOV %EAX,%ECX |
0x42d418 CMP %EDX,%R8D |
0x42d41b JB 42d8a2 |
0x42d421 IMUL %ECX,%R8D |
0x42d425 LEA (%R8,%RDX,1),%EBX |
0x42d429 LEA (%RCX,%RBX,1),%R9D |
0x42d42d MOV %R9D,0x3c(%RSP) |
0x42d432 CMP %R9D,%EBX |
0x42d435 JAE 42d883 |
0x42d43b MOV %EBX,%EAX |
0x42d43d XOR %EDX,%EDX |
0x42d43f MOV 0x40(%RSP),%ESI |
0x42d443 MOV (%R13),%R10 |
0x42d447 DIVL 0x68(%RSP) |
0x42d44b MOV 0x10(%R13),%R11 |
0x42d44f MOV %R10,0x30(%RSP) |
0x42d454 MOV %R11,0x28(%RSP) |
0x42d459 ADD %EDX,%ESI |
0x42d45b ADD %R15D,%EAX |
0x42d45e MOV %R14D,%EDX |
0x42d461 MOV 0x18(%R13),%R15 |
0x42d465 MOV 0x8(%R13),%R14 |
0x42d469 SUB %ESI,%EDX |
0x42d46b MOVSXD %EAX,%R12 |
0x42d46e MOV %R15,0x20(%RSP) |
0x42d473 MOV %R14,0x18(%RSP) |
0x42d478 NOPL (%RAX,%RAX,1) |
(190) 0x42d480 CMP %EDX,%ECX |
(190) 0x42d482 CMOVBE %ECX,%EDX |
(190) 0x42d485 LEA (%RBX,%RDX,1),%ECX |
(190) 0x42d488 MOV %ECX,0x6c(%RSP) |
(190) 0x42d48c CMP %ECX,%EBX |
(190) 0x42d48e JAE 42d85b |
(190) 0x42d494 MOV 0x30(%RSP),%R13 |
(190) 0x42d499 MOV 0x28(%RSP),%RDI |
(190) 0x42d49e MOV 0x18(%RSP),%RAX |
(190) 0x42d4a3 MOV 0x20(%RSP),%R9 |
(190) 0x42d4a8 MOV 0x10(%R13),%R14 |
(190) 0x42d4ac MOV (%R13),%RCX |
(190) 0x42d4b0 MOV (%RAX),%R10 |
(190) 0x42d4b3 MOV (%RDI),%R13 |
(190) 0x42d4b6 IMUL %R12,%RCX |
(190) 0x42d4ba MOV 0x10(%RDI),%R15 |
(190) 0x42d4be MOV (%R9),%R11 |
(190) 0x42d4c1 LEA -0x1(%RDX),%EDI |
(190) 0x42d4c4 IMUL %R12,%R13 |
(190) 0x42d4c8 MOV 0x10(%R9),%R8 |
(190) 0x42d4cc MOV 0x10(%RAX),%R9 |
(190) 0x42d4d0 MOV %R14,0x50(%RSP) |
(190) 0x42d4d5 IMUL %R12,%R10 |
(190) 0x42d4d9 MOV %R15,0x70(%RSP) |
(190) 0x42d4de MOV %RCX,0x48(%RSP) |
(190) 0x42d4e3 IMUL %R12,%R11 |
(190) 0x42d4e7 MOV %R13,0x58(%RSP) |
(190) 0x42d4ec MOV %R9,0x78(%RSP) |
(190) 0x42d4f1 MOV %R10,0x60(%RSP) |
(190) 0x42d4f6 CMP $0x6,%EDI |
(190) 0x42d4f9 JBE 42d898 |
(190) 0x42d4ff MOVSXD %ESI,%RAX |
(190) 0x42d502 ADD %RAX,%R13 |
(190) 0x42d505 ADD %RAX,%RCX |
(190) 0x42d508 LEA (%R11,%RAX,1),%RDI |
(190) 0x42d50c ADD %R10,%RAX |
(190) 0x42d50f MOV %EDX,%R10D |
(190) 0x42d512 LEA (%R15,%R13,8),%R15 |
(190) 0x42d516 LEA (%R9,%RAX,8),%R13 |
(190) 0x42d51a SAL $0x3,%RDI |
(190) 0x42d51e SHR $0x3,%R10D |
(190) 0x42d522 LEA (%R14,%RCX,8),%RCX |
(190) 0x42d526 LEA -0x8(%R8,%RDI,1),%R14 |
(190) 0x42d52b XOR %EAX,%EAX |
(190) 0x42d52d SAL $0x6,%R10 |
(190) 0x42d531 ADD %R8,%RDI |
(190) 0x42d534 LEA -0x40(%R10),%R9 |
(190) 0x42d538 SHR $0x6,%R9 |
(190) 0x42d53c INC %R9 |
(190) 0x42d53f AND $0x3,%R9D |
(190) 0x42d543 JE 42d5e6 |
(190) 0x42d549 CMP $0x1,%R9 |
(190) 0x42d54d JE 42d5ae |
(190) 0x42d54f CMP $0x2,%R9 |
(190) 0x42d553 JE 42d57f |
(190) 0x42d555 VMOVUPD (%RCX),%ZMM0 |
(190) 0x42d55b VMOVUPD (%RDI),%ZMM3 |
(190) 0x42d561 MOV $0x40,%EAX |
(190) 0x42d566 VFMSUB132PD (%R15),%ZMM3,%ZMM0 |
(190) 0x42d56c VADDPD (%R14),%ZMM0,%ZMM1 |
(190) 0x42d572 VDIVPD (%R13),%ZMM1,%ZMM2 |
(190) 0x42d579 VMOVUPD %ZMM2,(%RCX) |
(190) 0x42d57f VMOVUPD (%RCX,%RAX,1),%ZMM4 |
(190) 0x42d586 VMOVUPD (%RDI,%RAX,1),%ZMM5 |
(190) 0x42d58d VFMSUB132PD (%R15,%RAX,1),%ZMM5,%ZMM4 |
(190) 0x42d594 VADDPD (%R14,%RAX,1),%ZMM4,%ZMM6 |
(190) 0x42d59b VDIVPD (%R13,%RAX,1),%ZMM6,%ZMM7 |
(190) 0x42d5a3 VMOVUPD %ZMM7,(%RCX,%RAX,1) |
(190) 0x42d5aa ADD $0x40,%RAX |
(190) 0x42d5ae VMOVUPD (%RCX,%RAX,1),%ZMM8 |
(190) 0x42d5b5 VMOVUPD (%RDI,%RAX,1),%ZMM9 |
(190) 0x42d5bc VFMSUB132PD (%R15,%RAX,1),%ZMM9,%ZMM8 |
(190) 0x42d5c3 VADDPD (%R14,%RAX,1),%ZMM8,%ZMM10 |
(190) 0x42d5ca VDIVPD (%R13,%RAX,1),%ZMM10,%ZMM11 |
(190) 0x42d5d2 VMOVUPD %ZMM11,(%RCX,%RAX,1) |
(190) 0x42d5d9 ADD $0x40,%RAX |
(190) 0x42d5dd CMP %RAX,%R10 |
(190) 0x42d5e0 JE 42d6b0 |
(191) 0x42d5e6 VMOVUPD (%RDI,%RAX,1),%ZMM13 |
(191) 0x42d5ed VMOVUPD (%RCX,%RAX,1),%ZMM12 |
(191) 0x42d5f4 VMOVUPD 0x40(%RCX,%RAX,1),%ZMM0 |
(191) 0x42d5fc VMOVUPD 0x80(%RCX,%RAX,1),%ZMM5 |
(191) 0x42d604 VFMSUB132PD (%R15,%RAX,1),%ZMM13,%ZMM12 |
(191) 0x42d60b VMOVUPD 0xc0(%RCX,%RAX,1),%ZMM8 |
(191) 0x42d613 VADDPD (%R14,%RAX,1),%ZMM12,%ZMM14 |
(191) 0x42d61a VDIVPD (%R13,%RAX,1),%ZMM14,%ZMM15 |
(191) 0x42d622 VMOVUPD %ZMM15,(%RCX,%RAX,1) |
(191) 0x42d629 VMOVUPD 0x40(%RDI,%RAX,1),%ZMM3 |
(191) 0x42d631 VFMSUB132PD 0x40(%R15,%RAX,1),%ZMM3,%ZMM0 |
(191) 0x42d639 VADDPD 0x40(%R14,%RAX,1),%ZMM0,%ZMM1 |
(191) 0x42d641 VDIVPD 0x40(%R13,%RAX,1),%ZMM1,%ZMM2 |
(191) 0x42d649 VMOVUPD %ZMM2,0x40(%RCX,%RAX,1) |
(191) 0x42d651 VMOVUPD 0x80(%RDI,%RAX,1),%ZMM4 |
(191) 0x42d659 VFMSUB132PD 0x80(%R15,%RAX,1),%ZMM4,%ZMM5 |
(191) 0x42d661 VADDPD 0x80(%R14,%RAX,1),%ZMM5,%ZMM6 |
(191) 0x42d669 VDIVPD 0x80(%R13,%RAX,1),%ZMM6,%ZMM7 |
(191) 0x42d671 VMOVUPD %ZMM7,0x80(%RCX,%RAX,1) |
(191) 0x42d679 VMOVUPD 0xc0(%RDI,%RAX,1),%ZMM9 |
(191) 0x42d681 VFMSUB132PD 0xc0(%R15,%RAX,1),%ZMM9,%ZMM8 |
(191) 0x42d689 VADDPD 0xc0(%R14,%RAX,1),%ZMM8,%ZMM10 |
(191) 0x42d691 VDIVPD 0xc0(%R13,%RAX,1),%ZMM10,%ZMM11 |
(191) 0x42d699 VMOVUPD %ZMM11,0xc0(%RCX,%RAX,1) |
(191) 0x42d6a1 ADD $0x100,%RAX |
(191) 0x42d6a7 CMP %RAX,%R10 |
(191) 0x42d6aa JNE 42d5e6 |
(190) 0x42d6b0 MOV %EDX,%R13D |
(190) 0x42d6b3 AND $-0x8,%R13D |
(190) 0x42d6b7 ADD %R13D,%EBX |
(190) 0x42d6ba LEA (%R13,%RSI,1),%ECX |
(190) 0x42d6bf TEST $0x7,%DL |
(190) 0x42d6c2 JE 42d857 |
(190) 0x42d6c8 SUB %R13D,%EDX |
(190) 0x42d6cb LEA -0x1(%RDX),%R15D |
(190) 0x42d6cf CMP $0x2,%R15D |
(190) 0x42d6d3 JBE 42d748 |
(190) 0x42d6d5 MOV 0x48(%RSP),%RDI |
(190) 0x42d6da MOVSXD %ESI,%RSI |
(190) 0x42d6dd MOV 0x50(%RSP),%R14 |
(190) 0x42d6e2 MOV 0x60(%RSP),%R9 |
(190) 0x42d6e7 MOV 0x58(%RSP),%RAX |
(190) 0x42d6ec ADD %RSI,%RDI |
(190) 0x42d6ef ADD %R13,%RDI |
(190) 0x42d6f2 LEA (%R9,%RSI,1),%R15 |
(190) 0x42d6f6 LEA (%R14,%RDI,8),%R10 |
(190) 0x42d6fa LEA (%R11,%RSI,1),%RDI |
(190) 0x42d6fe ADD %RAX,%RSI |
(190) 0x42d701 ADD %R13,%R15 |
(190) 0x42d704 ADD %R13,%RDI |
(190) 0x42d707 ADD %R13,%RSI |
(190) 0x42d70a VMOVUPD (%R10),%YMM12 |
(190) 0x42d70f MOV 0x70(%RSP),%R13 |
(190) 0x42d714 VMOVUPD -0x8(%R8,%RDI,8),%YMM13 |
(190) 0x42d71b VFMADD132PD (%R13,%RSI,8),%YMM13,%YMM12 |
(190) 0x42d722 MOV 0x78(%RSP),%RSI |
(190) 0x42d727 VSUBPD (%R8,%RDI,8),%YMM12,%YMM14 |
(190) 0x42d72d VDIVPD (%RSI,%R15,8),%YMM14,%YMM15 |
(190) 0x42d733 VMOVUPD %YMM15,(%R10) |
(190) 0x42d738 TEST $0x3,%DL |
(190) 0x42d73b JE 42d857 |
(190) 0x42d741 AND $-0x4,%EDX |
(190) 0x42d744 ADD %EDX,%EBX |
(190) 0x42d746 ADD %EDX,%ECX |
(190) 0x42d748 MOV 0x48(%RSP),%R15 |
(190) 0x42d74d MOVSXD %ECX,%RAX |
(190) 0x42d750 MOV 0x50(%RSP),%R14 |
(190) 0x42d755 LEA -0x1(%RCX),%R10D |
(190) 0x42d759 MOV 0x58(%RSP),%R9 |
(190) 0x42d75e MOVSXD %R10D,%RSI |
(190) 0x42d761 MOV 0x60(%RSP),%R10 |
(190) 0x42d766 LEA (%R15,%RAX,1),%RDX |
(190) 0x42d76a ADD %R11,%RSI |
(190) 0x42d76d LEA (%R14,%RDX,8),%R13 |
(190) 0x42d771 MOV 0x70(%RSP),%RDX |
(190) 0x42d776 LEA (%R9,%RAX,1),%RDI |
(190) 0x42d77a VMOVSD (%R8,%RSI,8),%XMM3 |
(190) 0x42d780 MOV 0x78(%RSP),%RSI |
(190) 0x42d785 VMOVSD (%RDX,%RDI,8),%XMM0 |
(190) 0x42d78a LEA (%R11,%RAX,1),%RDI |
(190) 0x42d78e ADD %R10,%RAX |
(190) 0x42d791 LEA (%R8,%RDI,8),%RDX |
(190) 0x42d795 LEA 0x1(%RBX),%EDI |
(190) 0x42d798 VFMADD132SD (%R13),%XMM3,%XMM0 |
(190) 0x42d79e VSUBSD (%RDX),%XMM0,%XMM1 |
(190) 0x42d7a2 VDIVSD (%RSI,%RAX,8),%XMM1,%XMM2 |
(190) 0x42d7a7 VMOVSD %XMM2,(%R13) |
(190) 0x42d7ad MOV 0x6c(%RSP),%R13D |
(190) 0x42d7b2 LEA 0x1(%RCX),%EAX |
(190) 0x42d7b5 CMP %R13D,%EDI |
(190) 0x42d7b8 JAE 42d857 |
(190) 0x42d7be CLTQ |
(190) 0x42d7c0 MOV %R14,%R13 |
(190) 0x42d7c3 ADD $0x2,%EBX |
(190) 0x42d7c6 ADD $0x2,%ECX |
(190) 0x42d7c9 LEA (%R15,%RAX,1),%RSI |
(190) 0x42d7cd LEA (%R14,%RSI,8),%RSI |
(190) 0x42d7d1 LEA (%R11,%RAX,1),%R14 |
(190) 0x42d7d5 LEA (%R8,%R14,8),%RDI |
(190) 0x42d7d9 MOV %R9,%R14 |
(190) 0x42d7dc LEA (%R9,%RAX,1),%R9 |
(190) 0x42d7e0 ADD %R10,%RAX |
(190) 0x42d7e3 MOV %RDI,0x60(%RSP) |
(190) 0x42d7e8 MOV 0x70(%RSP),%RDI |
(190) 0x42d7ed VMOVSD (%RDI,%R9,8),%XMM5 |
(190) 0x42d7f3 MOV 0x60(%RSP),%R9 |
(190) 0x42d7f8 VMOVSD (%R9),%XMM4 |
(190) 0x42d7fd MOV %R10,%R9 |
(190) 0x42d800 MOV 0x78(%RSP),%R10 |
(190) 0x42d805 VFMSUB132SD (%RSI),%XMM4,%XMM5 |
(190) 0x42d80a VADDSD (%RDX),%XMM5,%XMM6 |
(190) 0x42d80e MOV 0x6c(%RSP),%EDX |
(190) 0x42d812 VDIVSD (%R10,%RAX,8),%XMM6,%XMM7 |
(190) 0x42d818 VMOVSD %XMM7,(%RSI) |
(190) 0x42d81c CMP %EDX,%EBX |
(190) 0x42d81e JAE 42d857 |
(190) 0x42d820 MOVSXD %ECX,%RCX |
(190) 0x42d823 MOV 0x60(%RSP),%RBX |
(190) 0x42d828 ADD %RCX,%R15 |
(190) 0x42d82b ADD %RCX,%R11 |
(190) 0x42d82e ADD %RCX,%R14 |
(190) 0x42d831 ADD %RCX,%R9 |
(190) 0x42d834 LEA (%R13,%R15,8),%RAX |
(190) 0x42d839 VMOVSD (%R8,%R11,8),%XMM9 |
(190) 0x42d83f VMOVSD (%RAX),%XMM8 |
(190) 0x42d843 VFMSUB132SD (%RDI,%R14,8),%XMM9,%XMM8 |
(190) 0x42d849 VADDSD (%RBX),%XMM8,%XMM10 |
(190) 0x42d84d VDIVSD (%R10,%R9,8),%XMM10,%XMM11 |
(190) 0x42d853 VMOVSD %XMM11,(%RAX) |
(190) 0x42d857 MOV 0x6c(%RSP),%EBX |
(190) 0x42d85b INC %R12 |
(190) 0x42d85e LEA (%R12),%R8D |
(190) 0x42d862 CMP %R8D,0x44(%RSP) |
(190) 0x42d867 JLE 42d880 |
(190) 0x42d869 MOV 0x3c(%RSP),%ECX |
(190) 0x42d86d MOV 0x68(%RSP),%EDX |
(190) 0x42d871 MOV 0x40(%RSP),%ESI |
(190) 0x42d875 SUB %EBX,%ECX |
(190) 0x42d877 JMP 42d480 |
0x42d87c NOPL (%RAX) |
0x42d880 VZEROUPPER |
0x42d883 LEA -0x28(%RBP),%RSP |
0x42d887 POP %RBX |
0x42d888 POP %R12 |
0x42d88a POP %R13 |
0x42d88c POP %R14 |
0x42d88e POP %R15 |
0x42d890 POP %RBP |
0x42d891 RET |
0x42d892 NOPW (%RAX,%RAX,1) |
(190) 0x42d898 MOV %ESI,%ECX |
(190) 0x42d89a XOR %R13D,%R13D |
(190) 0x42d89d JMP 42d6c8 |
0x42d8a2 INC %ECX |
0x42d8a4 XOR %EDX,%EDX |
0x42d8a6 JMP 42d421 |
0x42d8ab NOPL (%RAX,%RAX,1) |
Path / |
Source file and lines | advec_mom.cpp:146-149 |
Module | exec |
nb instructions | 79 |
nb uops | 89 |
loop length | 266 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 9 |
micro-operation queue | 14.83 cycles |
front end | 14.83 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 5.70 | 8.00 | 6.00 | 6.00 | 8.00 | 5.87 | 5.70 | 8.00 | 8.00 | 8.00 | 5.73 | 6.00 |
cycles | 5.70 | 11.73 | 6.00 | 6.00 | 8.00 | 5.87 | 5.70 | 8.00 | 8.00 | 8.00 | 5.73 | 6.00 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.07-14.16 |
Stall cycles | 0.00 |
Front-end | 14.83 |
Dispatch | 11.73 |
DIV/SQRT | 12.00 |
Overall L1 | 14.83 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 14% |
all | 9% |
load | 10% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 9% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD $-0x80,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x28(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RDI),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x24(%RDI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x3,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA 0x1(%RBX),%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x44(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ESI,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 42d883 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x4e3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x3(%RCX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 42d883 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x4e3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R14D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %ESI,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EDI,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 404650 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 404540 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x68(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 42d8a2 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x502> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %ECX,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RCX,%RBX,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R9D,0x3c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R9D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 42d883 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x4e3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EBX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x40(%RSP),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R13),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x68(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x10(%R13),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R15D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x18(%R13),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%R13),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %ESI,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %EAX,%R12 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R15,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 42d421 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x81> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | advec_mom.cpp:146-149 |
Module | exec |
nb instructions | 79 |
nb uops | 89 |
loop length | 266 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 9 |
micro-operation queue | 14.83 cycles |
front end | 14.83 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 5.70 | 8.00 | 6.00 | 6.00 | 8.00 | 5.87 | 5.70 | 8.00 | 8.00 | 8.00 | 5.73 | 6.00 |
cycles | 5.70 | 11.73 | 6.00 | 6.00 | 8.00 | 5.87 | 5.70 | 8.00 | 8.00 | 8.00 | 5.73 | 6.00 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.07-14.16 |
Stall cycles | 0.00 |
Front-end | 14.83 |
Dispatch | 11.73 |
DIV/SQRT | 12.00 |
Overall L1 | 14.83 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 14% |
all | 9% |
load | 10% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 9% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD $-0x80,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x28(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RDI),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x24(%RDI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x3,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA 0x1(%RBX),%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x44(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ESI,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 42d883 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x4e3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x3(%RCX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 42d883 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x4e3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R14D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %ESI,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EDI,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 404650 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 404540 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x68(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 42d8a2 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x502> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %ECX,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RCX,%RBX,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R9D,0x3c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R9D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 42d883 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x4e3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EBX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x40(%RSP),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R13),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x68(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x10(%R13),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R15D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x18(%R13),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%R13),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %ESI,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %EAX,%R12 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R15,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 42d421 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x81> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7– | 3.56 | 1.19 |
▼Loop 190 - advec_mom.cpp:148-149 - exec– | 0.01 | 0 |
○Loop 191 - advec_mom.cpp:149-149 - exec | 3.55 | 1.18 |