Function: _Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_ ... | Module: exec | Source: advec_cell.cpp:117-125 [...] | Coverage: 2.73% |
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Function: _Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_ ... | Module: exec | Source: advec_cell.cpp:117-125 [...] | Coverage: 2.73% |
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/home/eoseret/qaas_runs_CPU_9468/171-112-9712/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69 |
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69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
/home/eoseret/qaas_runs_CPU_9468/171-112-9712/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp: 117 - 125 |
-------------------------------------------------------------------------------- |
117: #pragma omp parallel for simd collapse(2) |
118: for (int j = (y_min + 1); j < (y_max + 2); j++) { |
119: for (int i = (x_min + 1); i < (x_max + 2); i++) { |
120: double pre_mass_s = density1(i, j) * pre_vol(i, j); |
121: double post_mass_s = pre_mass_s + mass_flux_x(i, j) - mass_flux_x(i + 1, j + 0); |
122: double post_ener_s = (energy1(i, j) * pre_mass_s + ener_flux(i, j) - ener_flux(i + 1, j + 0)) / post_mass_s; |
123: double advec_vol_s = pre_vol(i, j) + vol_flux_x(i, j) - vol_flux_x(i + 1, j + 0); |
124: density1(i, j) = post_mass_s / advec_vol_s; |
125: energy1(i, j) = post_ener_s; |
0x427600 PUSH %RBP |
0x427601 MOV %RSP,%RBP |
0x427604 PUSH %R15 |
0x427606 PUSH %R14 |
0x427608 PUSH %R13 |
0x42760a PUSH %R12 |
0x42760c PUSH %RBX |
0x42760d AND $-0x40,%RSP |
0x427611 SUB $0xc0,%RSP |
0x427618 MOV 0x38(%RDI),%EAX |
0x42761b MOV 0x3c(%RDI),%ECX |
0x42761e MOV 0x30(%RDI),%ESI |
0x427621 MOV 0x34(%RDI),%EDX |
0x427624 ADD $0x2,%ECX |
0x427627 LEA 0x1(%RAX),%R15D |
0x42762b INC %ESI |
0x42762d MOV %ECX,0x48(%RSP) |
0x427631 MOV %ESI,0x44(%RSP) |
0x427635 CMP %ECX,%R15D |
0x427638 JGE 427d3b |
0x42763e MOV %ECX,%R13D |
0x427641 LEA 0x2(%RDX),%R14D |
0x427645 SUB %R15D,%R13D |
0x427648 CMP %R14D,%ESI |
0x42764b JGE 427d3b |
0x427651 MOV %RDI,%RBX |
0x427654 MOV %R14D,%EDI |
0x427657 SUB %ESI,%EDI |
0x427659 MOV %EDI,0x4c(%RSP) |
0x42765d CALL 404650 <omp_get_num_threads@plt> |
0x427662 MOV %EAX,%R12D |
0x427665 CALL 404540 <omp_get_thread_num@plt> |
0x42766a XOR %EDX,%EDX |
0x42766c MOV %EAX,%R8D |
0x42766f MOV 0x4c(%RSP),%EAX |
0x427673 IMUL %R13D,%EAX |
0x427677 DIV %R12D |
0x42767a MOV %EAX,%ECX |
0x42767c CMP %EDX,%R8D |
0x42767f JB 427d5f |
0x427685 IMUL %ECX,%R8D |
0x427689 LEA (%R8,%RDX,1),%R10D |
0x42768d LEA (%RCX,%R10,1),%R9D |
0x427691 MOV %R9D,0x40(%RSP) |
0x427696 CMP %R9D,%R10D |
0x427699 JAE 427d3b |
0x42769f MOV %R10D,%EAX |
0x4276a2 XOR %EDX,%EDX |
0x4276a4 MOV 0x44(%RSP),%R11D |
0x4276a9 MOV (%RBX),%RSI |
0x4276ac DIVL 0x4c(%RSP) |
0x4276b0 MOV 0x10(%RBX),%R13 |
0x4276b4 MOV 0x8(%RBX),%RDI |
0x4276b8 MOV 0x28(%RBX),%R12 |
0x4276bc MOV %RSI,0x30(%RSP) |
0x4276c1 MOV %R13,0x20(%RSP) |
0x4276c6 MOV %RDI,0x18(%RSP) |
0x4276cb MOV %R12,0x10(%RSP) |
0x4276d0 MOV %R14D,%R9D |
0x4276d3 MOV 0x20(%RBX),%R14 |
0x4276d7 MOV 0x18(%RBX),%RBX |
0x4276db MOV %R14,0x28(%RSP) |
0x4276e0 MOV %RBX,0x8(%RSP) |
0x4276e5 LEA (%RAX,%R15,1),%R15D |
0x4276e9 ADD %EDX,%R11D |
0x4276ec MOVSXD %R15D,%R8 |
0x4276ef MOV %R11D,0x9c(%RSP) |
0x4276f7 SUB %R11D,%R9D |
0x4276fa MOV %R8,0xb8(%RSP) |
0x427702 NOPW (%RAX,%RAX,1) |
(163) 0x427708 CMP %R9D,%ECX |
(163) 0x42770b CMOVBE %ECX,%R9D |
(163) 0x42770f LEA (%R10,%R9,1),%ECX |
(163) 0x427713 MOV %R9D,%EDX |
(163) 0x427716 MOV %ECX,0x98(%RSP) |
(163) 0x42771d CMP %ECX,%R10D |
(163) 0x427720 JAE 427cfb |
(163) 0x427726 MOV 0x20(%RSP),%RSI |
(163) 0x42772b MOV 0x30(%RSP),%R9 |
(163) 0x427730 MOV 0x18(%RSP),%R14 |
(163) 0x427735 MOV 0x28(%RSP),%RAX |
(163) 0x42773a MOV 0x10(%RSI),%R11 |
(163) 0x42773e MOV 0x10(%R9),%R15 |
(163) 0x427742 MOV 0x10(%R14),%R12 |
(163) 0x427746 MOV (%R9),%RBX |
(163) 0x427749 MOV 0x10(%RSP),%R9 |
(163) 0x42774e MOV 0xb8(%RSP),%RCX |
(163) 0x427756 MOV %R11,0xb0(%RSP) |
(163) 0x42775e MOV (%RSI),%R11 |
(163) 0x427761 MOV 0x8(%RSP),%RSI |
(163) 0x427766 MOV %R12,0xa0(%RSP) |
(163) 0x42776e MOV 0x10(%RAX),%R13 |
(163) 0x427772 MOV (%RAX),%RDI |
(163) 0x427775 IMUL %RCX,%RBX |
(163) 0x427779 MOV %R15,0x78(%RSP) |
(163) 0x42777e MOV (%R14),%R8 |
(163) 0x427781 MOV 0x10(%R9),%R12 |
(163) 0x427785 IMUL %RCX,%R11 |
(163) 0x427789 MOV (%R9),%R9 |
(163) 0x42778c MOV (%RSI),%RAX |
(163) 0x42778f IMUL %RCX,%RDI |
(163) 0x427793 MOV %R13,0x88(%RSP) |
(163) 0x42779b IMUL %RCX,%R8 |
(163) 0x42779f MOV %RBX,0x70(%RSP) |
(163) 0x4277a4 MOV 0x10(%RSI),%R14 |
(163) 0x4277a8 IMUL %RCX,%R9 |
(163) 0x4277ac MOV %R11,0x58(%RSP) |
(163) 0x4277b1 IMUL %RCX,%RAX |
(163) 0x4277b5 LEA -0x1(%RDX),%ECX |
(163) 0x4277b8 MOV %RDI,0x80(%RSP) |
(163) 0x4277c0 MOV %R8,0x90(%RSP) |
(163) 0x4277c8 MOV %R9,0x60(%RSP) |
(163) 0x4277cd MOV %RAX,0xa8(%RSP) |
(163) 0x4277d5 CMP $0x6,%ECX |
(163) 0x4277d8 JBE 427d50 |
(163) 0x4277de MOVSXD 0x9c(%RSP),%RAX |
(163) 0x4277e6 LEA (%RBX,%RAX,1),%RBX |
(163) 0x4277ea LEA (%R9,%RAX,1),%R9 |
(163) 0x4277ee LEA (%R15,%RBX,8),%RSI |
(163) 0x4277f2 LEA (%RDI,%RAX,1),%R15 |
(163) 0x4277f6 SAL $0x3,%R9 |
(163) 0x4277fa LEA (%R11,%RAX,1),%RDI |
(163) 0x4277fe MOV 0xb0(%RSP),%R11 |
(163) 0x427806 LEA (%R13,%R15,8),%R13 |
(163) 0x42780b SAL $0x3,%RDI |
(163) 0x42780f LEA (%R8,%RAX,1),%R15 |
(163) 0x427813 MOV 0xa0(%RSP),%R8 |
(163) 0x42781b LEA 0x8(%R11,%RDI,1),%RCX |
(163) 0x427820 LEA (%R11,%RDI,1),%RBX |
(163) 0x427824 MOV 0xa8(%RSP),%RDI |
(163) 0x42782c MOV %RCX,0x50(%RSP) |
(163) 0x427831 LEA (%R8,%R15,8),%RCX |
(163) 0x427835 LEA (%R12,%R9,1),%R11 |
(163) 0x427839 ADD %RDI,%RAX |
(163) 0x42783c LEA 0x8(%R12,%R9,1),%R9 |
(163) 0x427841 SAL $0x3,%RAX |
(163) 0x427845 LEA (%R14,%RAX,1),%R8 |
(163) 0x427849 LEA 0x8(%R14,%RAX,1),%RDI |
(163) 0x42784e MOV %EDX,%EAX |
(163) 0x427850 SHR $0x3,%EAX |
(163) 0x427853 MOV %EAX,%R15D |
(163) 0x427856 MOV %R15,%RAX |
(163) 0x427859 SAL $0x6,%RAX |
(163) 0x42785d MOV %RAX,0x68(%RSP) |
(163) 0x427862 XOR %EAX,%EAX |
(163) 0x427864 AND $0x1,%R15D |
(163) 0x427868 JE 4278cf |
(163) 0x42786a VMOVUPD (%R13),%ZMM0 |
(163) 0x427871 VMOVUPD (%R11),%ZMM7 |
(163) 0x427877 MOV $0x40,%EAX |
(163) 0x42787c MOV 0x50(%RSP),%R15 |
(163) 0x427881 CMPQ $0x40,0x68(%RSP) |
(163) 0x427887 VMULPD (%RSI),%ZMM0,%ZMM1 |
(163) 0x42788d VSUBPD (%R9),%ZMM7,%ZMM3 |
(163) 0x427893 VADDPD (%R8),%ZMM0,%ZMM5 |
(163) 0x427899 VSUBPD (%RDI),%ZMM5,%ZMM6 |
(163) 0x42789f VSUBPD (%R15),%ZMM1,%ZMM2 |
(163) 0x4278a5 VFMADD132PD (%RCX),%ZMM3,%ZMM1 |
(163) 0x4278ab VADDPD (%RBX),%ZMM2,%ZMM4 |
(163) 0x4278b1 VDIVPD %ZMM6,%ZMM4,%ZMM8 |
(163) 0x4278b7 VDIVPD %ZMM4,%ZMM1,%ZMM9 |
(163) 0x4278bd VMOVUPD %ZMM8,(%RSI) |
(163) 0x4278c3 VMOVUPD %ZMM9,(%RCX) |
(163) 0x4278c9 JE 4279bb |
(163) 0x4278cf MOV %R10D,0x3c(%RSP) |
(163) 0x4278d4 MOV 0xb8(%RSP),%R15 |
(163) 0x4278dc MOV 0x50(%RSP),%R10 |
(164) 0x4278e1 VMOVUPD (%R13,%RAX,1),%ZMM10 |
(164) 0x4278e9 VMOVUPD (%R11,%RAX,1),%ZMM14 |
(164) 0x4278f0 VMULPD (%RSI,%RAX,1),%ZMM10,%ZMM11 |
(164) 0x4278f7 VSUBPD (%R9,%RAX,1),%ZMM14,%ZMM15 |
(164) 0x4278fe VADDPD (%R8,%RAX,1),%ZMM10,%ZMM0 |
(164) 0x427905 VSUBPD (%RDI,%RAX,1),%ZMM0,%ZMM1 |
(164) 0x42790c VSUBPD (%R10,%RAX,1),%ZMM11,%ZMM12 |
(164) 0x427913 VFMADD132PD (%RCX,%RAX,1),%ZMM15,%ZMM11 |
(164) 0x42791a VADDPD (%RBX,%RAX,1),%ZMM12,%ZMM13 |
(164) 0x427921 VDIVPD %ZMM13,%ZMM11,%ZMM4 |
(164) 0x427927 VDIVPD %ZMM1,%ZMM13,%ZMM2 |
(164) 0x42792d VMOVUPD %ZMM2,(%RSI,%RAX,1) |
(164) 0x427934 VMOVUPD %ZMM4,(%RCX,%RAX,1) |
(164) 0x42793b VMOVUPD 0x40(%R13,%RAX,1),%ZMM7 |
(164) 0x427943 VMOVUPD 0x40(%R11,%RAX,1),%ZMM5 |
(164) 0x42794b VMULPD 0x40(%RSI,%RAX,1),%ZMM7,%ZMM6 |
(164) 0x427953 VSUBPD 0x40(%R9,%RAX,1),%ZMM5,%ZMM9 |
(164) 0x42795b VADDPD 0x40(%R8,%RAX,1),%ZMM7,%ZMM10 |
(164) 0x427963 VSUBPD 0x40(%RDI,%RAX,1),%ZMM10,%ZMM11 |
(164) 0x42796b VSUBPD 0x40(%R10,%RAX,1),%ZMM6,%ZMM3 |
(164) 0x427973 VFMADD132PD 0x40(%RCX,%RAX,1),%ZMM9,%ZMM6 |
(164) 0x42797b VADDPD 0x40(%RBX,%RAX,1),%ZMM3,%ZMM8 |
(164) 0x427983 VDIVPD %ZMM11,%ZMM8,%ZMM12 |
(164) 0x427989 VDIVPD %ZMM8,%ZMM6,%ZMM13 |
(164) 0x42798f VMOVUPD %ZMM12,0x40(%RSI,%RAX,1) |
(164) 0x427997 VMOVUPD %ZMM13,0x40(%RCX,%RAX,1) |
(164) 0x42799f SUB $-0x80,%RAX |
(164) 0x4279a3 CMP %RAX,0x68(%RSP) |
(164) 0x4279a8 JNE 4278e1 |
(163) 0x4279ae MOV %R15,0xb8(%RSP) |
(163) 0x4279b6 MOV 0x3c(%RSP),%R10D |
(163) 0x4279bb MOV 0x9c(%RSP),%ESI |
(163) 0x4279c2 MOV %EDX,%R13D |
(163) 0x4279c5 AND $-0x8,%R13D |
(163) 0x4279c9 ADD %R13D,%R10D |
(163) 0x4279cc LEA (%R13,%RSI,1),%ESI |
(163) 0x4279d1 TEST $0x7,%DL |
(163) 0x4279d4 JE 427cf3 |
(163) 0x4279da SUB %R13D,%EDX |
(163) 0x4279dd LEA -0x1(%RDX),%EBX |
(163) 0x4279e0 CMP $0x2,%EBX |
(163) 0x4279e3 JBE 427ac2 |
(163) 0x4279e9 MOVSXD 0x9c(%RSP),%RAX |
(163) 0x4279f1 MOV 0x70(%RSP),%RCX |
(163) 0x4279f6 MOV 0x90(%RSP),%RDI |
(163) 0x4279fe MOV 0x78(%RSP),%R9 |
(163) 0x427a03 LEA (%RCX,%RAX,1),%R11 |
(163) 0x427a07 MOV 0xa0(%RSP),%R15 |
(163) 0x427a0f MOV 0x58(%RSP),%R8 |
(163) 0x427a14 ADD %RAX,%RDI |
(163) 0x427a17 ADD %R13,%R11 |
(163) 0x427a1a MOV 0x60(%RSP),%RCX |
(163) 0x427a1f ADD %R13,%RDI |
(163) 0x427a22 LEA (%R9,%R11,8),%RBX |
(163) 0x427a26 LEA (%R8,%RAX,1),%R9 |
(163) 0x427a2a LEA (%R15,%RDI,8),%R11 |
(163) 0x427a2e MOV 0xa8(%RSP),%RDI |
(163) 0x427a36 MOV 0x80(%RSP),%R15 |
(163) 0x427a3e LEA (%RCX,%RAX,1),%R8 |
(163) 0x427a42 ADD %R13,%R9 |
(163) 0x427a45 ADD %R13,%R8 |
(163) 0x427a48 ADD %RAX,%RDI |
(163) 0x427a4b ADD %R15,%RAX |
(163) 0x427a4e VMOVUPD 0x8(%R12,%R8,8),%YMM4 |
(163) 0x427a55 VMOVUPD (%R12,%R8,8),%YMM1 |
(163) 0x427a5b ADD %R13,%RDI |
(163) 0x427a5e ADD %R13,%RAX |
(163) 0x427a61 MOV 0x88(%RSP),%R13 |
(163) 0x427a69 VMOVUPD (%R13,%RAX,8),%YMM14 |
(163) 0x427a70 MOV 0xb0(%RSP),%RAX |
(163) 0x427a78 VMULPD (%RBX),%YMM14,%YMM15 |
(163) 0x427a7c VADDPD (%R14,%RDI,8),%YMM14,%YMM7 |
(163) 0x427a82 VSUBPD 0x8(%R14,%RDI,8),%YMM7,%YMM6 |
(163) 0x427a89 VADDPD (%RAX,%R9,8),%YMM15,%YMM0 |
(163) 0x427a8f VFMSUB132PD (%R11),%YMM4,%YMM15 |
(163) 0x427a94 VSUBPD 0x8(%RAX,%R9,8),%YMM0,%YMM2 |
(163) 0x427a9b VADDPD %YMM15,%YMM1,%YMM8 |
(163) 0x427aa0 VDIVPD %YMM6,%YMM2,%YMM3 |
(163) 0x427aa4 VDIVPD %YMM2,%YMM8,%YMM5 |
(163) 0x427aa8 VMOVUPD %YMM3,(%RBX) |
(163) 0x427aac VMOVUPD %YMM5,(%R11) |
(163) 0x427ab1 TEST $0x3,%DL |
(163) 0x427ab4 JE 427cf3 |
(163) 0x427aba AND $-0x4,%EDX |
(163) 0x427abd ADD %EDX,%R10D |
(163) 0x427ac0 ADD %EDX,%ESI |
(163) 0x427ac2 MOV 0x80(%RSP),%RCX |
(163) 0x427aca MOVSXD %ESI,%RDX |
(163) 0x427acd MOV 0x88(%RSP),%RDI |
(163) 0x427ad5 LEA 0x1(%RSI),%EAX |
(163) 0x427ad8 MOV 0x70(%RSP),%R9 |
(163) 0x427add MOV 0x78(%RSP),%RBX |
(163) 0x427ae2 CLTQ |
(163) 0x427ae4 LEA (%RCX,%RDX,1),%R8 |
(163) 0x427ae8 MOV 0xb0(%RSP),%R13 |
(163) 0x427af0 VMOVSD (%RDI,%R8,8),%XMM9 |
(163) 0x427af6 ADD %RDX,%R9 |
(163) 0x427af9 MOV 0x90(%RSP),%RDI |
(163) 0x427b01 LEA (%RBX,%R9,8),%R11 |
(163) 0x427b05 MOV 0x58(%RSP),%RBX |
(163) 0x427b0a MOV 0xa0(%RSP),%R8 |
(163) 0x427b12 VMULSD (%R11),%XMM9,%XMM10 |
(163) 0x427b17 ADD %RDX,%RDI |
(163) 0x427b1a LEA (%RBX,%RDX,1),%RCX |
(163) 0x427b1e LEA (%RAX,%RBX,1),%R15 |
(163) 0x427b22 LEA (%R13,%R15,8),%R9 |
(163) 0x427b27 VADDSD (%R13,%RCX,8),%XMM10,%XMM11 |
(163) 0x427b2e MOV 0x60(%RSP),%R13 |
(163) 0x427b33 LEA (%R8,%RDI,8),%RCX |
(163) 0x427b37 LEA (%R13,%RDX,1),%R15 |
(163) 0x427b3c LEA (%R13,%RAX,1),%RDI |
(163) 0x427b41 VMOVSD (%R12,%R15,8),%XMM13 |
(163) 0x427b47 LEA (%R12,%RDI,8),%R8 |
(163) 0x427b4b MOV 0xa8(%RSP),%R15 |
(163) 0x427b53 VMOVSD (%R8),%XMM14 |
(163) 0x427b58 VSUBSD (%R9),%XMM11,%XMM12 |
(163) 0x427b5d ADD %R15,%RDX |
(163) 0x427b60 MOV %R15,%RDI |
(163) 0x427b63 VADDSD (%R14,%RDX,8),%XMM9,%XMM15 |
(163) 0x427b69 VFMSUB132SD (%RCX),%XMM14,%XMM10 |
(163) 0x427b6e LEA 0x1(%R10),%EDX |
(163) 0x427b72 ADD %RAX,%RDI |
(163) 0x427b75 LEA (%R14,%RDI,8),%RDI |
(163) 0x427b79 VSUBSD (%RDI),%XMM15,%XMM0 |
(163) 0x427b7d VADDSD %XMM13,%XMM10,%XMM1 |
(163) 0x427b82 VDIVSD %XMM0,%XMM12,%XMM2 |
(163) 0x427b86 VDIVSD %XMM12,%XMM1,%XMM4 |
(163) 0x427b8b VMOVSD %XMM2,(%R11) |
(163) 0x427b90 MOV 0x98(%RSP),%R11D |
(163) 0x427b98 VMOVSD %XMM4,(%RCX) |
(163) 0x427b9c CMP %R11D,%EDX |
(163) 0x427b9f JAE 427cf3 |
(163) 0x427ba5 MOV 0x70(%RSP),%RCX |
(163) 0x427baa MOV 0x78(%RSP),%R15 |
(163) 0x427baf ADD $0x2,%R10D |
(163) 0x427bb3 MOV 0x80(%RSP),%RDX |
(163) 0x427bbb MOV 0x88(%RSP),%R11 |
(163) 0x427bc3 ADD %RAX,%RCX |
(163) 0x427bc6 VMOVSD (%R8),%XMM5 |
(163) 0x427bcb LEA (%R15,%RCX,8),%RCX |
(163) 0x427bcf LEA (%RAX,%RDX,1),%R15 |
(163) 0x427bd3 VMOVSD (%R11,%R15,8),%XMM7 |
(163) 0x427bd9 LEA 0x2(%RSI),%EDX |
(163) 0x427bdc MOV 0xb0(%RSP),%R15 |
(163) 0x427be4 MOVSXD %EDX,%RDX |
(163) 0x427be7 VMULSD (%RCX),%XMM7,%XMM6 |
(163) 0x427beb LEA (%RBX,%RDX,1),%R11 |
(163) 0x427bef VADDSD (%RDI),%XMM7,%XMM10 |
(163) 0x427bf3 LEA (%R15,%R11,8),%R11 |
(163) 0x427bf7 MOV 0xa0(%RSP),%R15 |
(163) 0x427bff MOV 0x98(%RSP),%EDI |
(163) 0x427c06 VSUBSD (%R11),%XMM6,%XMM3 |
(163) 0x427c0b VADDSD (%R9),%XMM3,%XMM8 |
(163) 0x427c10 MOV 0x90(%RSP),%R9 |
(163) 0x427c18 ADD %R9,%RAX |
(163) 0x427c1b LEA (%R13,%RDX,1),%R9 |
(163) 0x427c20 LEA (%R12,%R9,8),%R9 |
(163) 0x427c24 LEA (%R15,%RAX,8),%RAX |
(163) 0x427c28 MOV 0xa8(%RSP),%R15 |
(163) 0x427c30 VSUBSD (%R9),%XMM5,%XMM9 |
(163) 0x427c35 LEA (%R15,%RDX,1),%R8 |
(163) 0x427c39 LEA (%R14,%R8,8),%R8 |
(163) 0x427c3d VFMADD132SD (%RAX),%XMM9,%XMM6 |
(163) 0x427c42 VSUBSD (%R8),%XMM10,%XMM11 |
(163) 0x427c47 VDIVSD %XMM11,%XMM8,%XMM12 |
(163) 0x427c4c VDIVSD %XMM8,%XMM6,%XMM13 |
(163) 0x427c51 VMOVSD %XMM12,(%RCX) |
(163) 0x427c55 VMOVSD %XMM13,(%RAX) |
(163) 0x427c59 CMP %EDI,%R10D |
(163) 0x427c5c JAE 427cf3 |
(163) 0x427c62 MOV 0x70(%RSP),%RCX |
(163) 0x427c67 MOV 0x78(%RSP),%R10 |
(163) 0x427c6c ADD $0x3,%ESI |
(163) 0x427c6f MOV 0x80(%RSP),%RDI |
(163) 0x427c77 MOVSXD %ESI,%RSI |
(163) 0x427c7a VMOVSD (%R9),%XMM1 |
(163) 0x427c7f ADD %RDX,%RCX |
(163) 0x427c82 ADD %RSI,%RBX |
(163) 0x427c85 ADD %RSI,%R13 |
(163) 0x427c88 ADD %RSI,%R15 |
(163) 0x427c8b LEA (%R10,%RCX,8),%RAX |
(163) 0x427c8f MOV 0x88(%RSP),%RCX |
(163) 0x427c97 ADD %RDX,%RDI |
(163) 0x427c9a MOV 0xb0(%RSP),%R10 |
(163) 0x427ca2 VSUBSD (%R12,%R13,8),%XMM1,%XMM4 |
(163) 0x427ca8 VMOVSD (%RCX,%RDI,8),%XMM14 |
(163) 0x427cad MOV 0xa0(%RSP),%RDI |
(163) 0x427cb5 VMULSD (%RAX),%XMM14,%XMM15 |
(163) 0x427cb9 VADDSD (%R8),%XMM14,%XMM7 |
(163) 0x427cbe VSUBSD (%R14,%R15,8),%XMM7,%XMM6 |
(163) 0x427cc4 VSUBSD (%R10,%RBX,8),%XMM15,%XMM0 |
(163) 0x427cca VADDSD (%R11),%XMM0,%XMM2 |
(163) 0x427ccf MOV 0x90(%RSP),%R11 |
(163) 0x427cd7 ADD %RDX,%R11 |
(163) 0x427cda LEA (%RDI,%R11,8),%RBX |
(163) 0x427cde VDIVSD %XMM6,%XMM2,%XMM3 |
(163) 0x427ce2 VFMADD132SD (%RBX),%XMM4,%XMM15 |
(163) 0x427ce7 VDIVSD %XMM2,%XMM15,%XMM8 |
(163) 0x427ceb VMOVSD %XMM3,(%RAX) |
(163) 0x427cef VMOVSD %XMM8,(%RBX) |
(163) 0x427cf3 MOV 0x98(%RSP),%R10D |
(163) 0x427cfb INCQ 0xb8(%RSP) |
(163) 0x427d03 MOV 0xb8(%RSP),%R12 |
(163) 0x427d0b ADD $0,%R12D |
(163) 0x427d0f CMP %R12D,0x48(%RSP) |
(163) 0x427d14 JLE 427d38 |
(163) 0x427d16 MOV 0x40(%RSP),%ECX |
(163) 0x427d1a MOV 0x44(%RSP),%R14D |
(163) 0x427d1f MOV 0x4c(%RSP),%R9D |
(163) 0x427d24 MOV %R14D,0x9c(%RSP) |
(163) 0x427d2c SUB %R10D,%ECX |
(163) 0x427d2f JMP 427708 |
0x427d34 NOPL (%RAX) |
0x427d38 VZEROUPPER |
0x427d3b LEA -0x28(%RBP),%RSP |
0x427d3f POP %RBX |
0x427d40 POP %R12 |
0x427d42 POP %R13 |
0x427d44 POP %R14 |
0x427d46 POP %R15 |
0x427d48 POP %RBP |
0x427d49 RET |
0x427d4a NOPW (%RAX,%RAX,1) |
(163) 0x427d50 MOV 0x9c(%RSP),%ESI |
(163) 0x427d57 XOR %R13D,%R13D |
(163) 0x427d5a JMP 4279da |
0x427d5f INC %ECX |
0x427d61 XOR %EDX,%EDX |
0x427d63 JMP 427685 |
0x427d68 NOPL (%RAX,%RAX,1) |
Path / |
Source file and lines | advec_cell.cpp:117-125 |
Module | exec |
nb instructions | 85 |
nb uops | 95 |
loop length | 309 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 13 |
micro-operation queue | 15.83 cycles |
front end | 15.83 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.10 | 8.00 | 6.67 | 6.67 | 10.00 | 6.07 | 5.90 | 10.00 | 10.00 | 10.00 | 5.93 | 6.67 |
cycles | 6.10 | 11.93 | 6.67 | 6.67 | 10.00 | 6.07 | 5.90 | 10.00 | 10.00 | 10.00 | 5.93 | 6.67 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 15.08-15.21 |
Stall cycles | 0.00 |
Front-end | 15.83 |
Dispatch | 11.93 |
DIV/SQRT | 12.00 |
Overall L1 | 15.83 |
all | 3% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 12% |
all | 8% |
load | 9% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 8% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0xc0,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x38(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x3c(%RDI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x30(%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x34(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x2,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
INC %ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ECX,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ESI,0x44(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %ECX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 427d3b <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x73b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %ECX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x2(%RDX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%R13D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 427d3b <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x73b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R14D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %ESI,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EDI,0x4c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 404650 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 404540 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x4c(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %R13D,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 427d5f <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x75f> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %ECX,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RCX,%R10,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R9D,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R9D,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 427d3b <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x73b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R10D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x44(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RBX),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x4c(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x10(%RBX),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RBX),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RBX),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R13,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDI,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,0x10(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14D,%R9D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x20(%RBX),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RBX),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R14,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%RAX,%R15,1),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD %EDX,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %R15D,%R8 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R11D,0x9c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R11D,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R8,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 427685 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x85> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | advec_cell.cpp:117-125 |
Module | exec |
nb instructions | 85 |
nb uops | 95 |
loop length | 309 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 13 |
micro-operation queue | 15.83 cycles |
front end | 15.83 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.10 | 8.00 | 6.67 | 6.67 | 10.00 | 6.07 | 5.90 | 10.00 | 10.00 | 10.00 | 5.93 | 6.67 |
cycles | 6.10 | 11.93 | 6.67 | 6.67 | 10.00 | 6.07 | 5.90 | 10.00 | 10.00 | 10.00 | 5.93 | 6.67 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 15.08-15.21 |
Stall cycles | 0.00 |
Front-end | 15.83 |
Dispatch | 11.93 |
DIV/SQRT | 12.00 |
Overall L1 | 15.83 |
all | 3% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 12% |
all | 8% |
load | 9% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 8% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0xc0,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x38(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x3c(%RDI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x30(%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x34(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x2,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
INC %ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ECX,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ESI,0x44(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %ECX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 427d3b <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x73b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %ECX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x2(%RDX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%R13D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 427d3b <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x73b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R14D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %ESI,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EDI,0x4c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 404650 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 404540 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x4c(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %R13D,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 427d5f <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x75f> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %ECX,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RCX,%R10,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R9D,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R9D,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 427d3b <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x73b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R10D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x44(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RBX),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x4c(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x10(%RBX),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RBX),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RBX),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R13,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDI,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,0x10(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14D,%R9D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x20(%RBX),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RBX),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R14,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%RAX,%R15,1),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD %EDX,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %R15D,%R8 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R11D,0x9c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R11D,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R8,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 427685 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x85> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3– | 2.73 | 0.91 |
▼Loop 163 - advec_cell.cpp:119-125 - exec– | 0.01 | 0.01 |
○Loop 164 - advec_cell.cpp:120-125 - exec | 2.73 | 0.91 |