Function: _Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1 | Module: exec | Source: reset_field.cpp:44-48 [...] | Coverage: 1.96% |
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Function: _Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1 | Module: exec | Source: reset_field.cpp:44-48 [...] | Coverage: 1.96% |
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/home/eoseret/qaas_runs_CPU_9468/171-112-9712/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/reset_field.cpp: 44 - 48 |
-------------------------------------------------------------------------------- |
44: #pragma omp parallel for simd collapse(2) |
45: for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) { |
46: for (int i = (x_min + 1); i < (x_max + 1 + 2); i++) { |
47: xvel0(i, j) = xvel1(i, j); |
48: yvel0(i, j) = yvel1(i, j); |
/home/eoseret/qaas_runs_CPU_9468/171-112-9712/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69 |
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69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
0x440300 PUSH %RBP |
0x440301 MOV %RSP,%RBP |
0x440304 PUSH %R15 |
0x440306 PUSH %R14 |
0x440308 PUSH %R13 |
0x44030a PUSH %R12 |
0x44030c PUSH %RBX |
0x44030d AND $-0x40,%RSP |
0x440311 ADD $-0x80,%RSP |
0x440315 MOV 0x28(%RDI),%EAX |
0x440318 MOV 0x2c(%RDI),%EDX |
0x44031b MOV 0x20(%RDI),%EBX |
0x44031e MOV 0x24(%RDI),%ECX |
0x440321 ADD $0x3,%EDX |
0x440324 LEA 0x1(%RAX),%R15D |
0x440328 LEA 0x1(%RBX),%ESI |
0x44032b MOV %EDX,0x50(%RSP) |
0x44032f MOV %ESI,0x4c(%RSP) |
0x440333 CMP %EDX,%R15D |
0x440336 JGE 44082b |
0x44033c MOV %EDX,%EBX |
0x44033e LEA 0x3(%RCX),%R14D |
0x440342 SUB %R15D,%EBX |
0x440345 CMP %R14D,%ESI |
0x440348 JGE 44082b |
0x44034e MOV %RDI,%R13 |
0x440351 MOV %R14D,%EDI |
0x440354 SUB %ESI,%EDI |
0x440356 MOV %EDI,0x54(%RSP) |
0x44035a CALL 404650 <omp_get_num_threads@plt> |
0x44035f MOV %EAX,%R12D |
0x440362 CALL 404540 <omp_get_thread_num@plt> |
0x440367 XOR %EDX,%EDX |
0x440369 MOV %EAX,%R8D |
0x44036c MOV 0x54(%RSP),%EAX |
0x440370 IMUL %EBX,%EAX |
0x440373 DIV %R12D |
0x440376 MOV %EAX,%R12D |
0x440379 CMP %EDX,%R8D |
0x44037c JB 44084c |
0x440382 IMUL %R12D,%R8D |
0x440386 LEA (%R8,%RDX,1),%R9D |
0x44038a LEA (%R12,%R9,1),%R10D |
0x44038e MOV %R10D,0x48(%RSP) |
0x440393 CMP %R10D,%R9D |
0x440396 JAE 44082b |
0x44039c MOV %R9D,%EAX |
0x44039f XOR %EDX,%EDX |
0x4403a1 MOV 0x4c(%RSP),%R11D |
0x4403a6 MOV (%R13),%RSI |
0x4403aa DIVL 0x54(%RSP) |
0x4403ae MOV 0x10(%R13),%RBX |
0x4403b2 MOV %RSI,0x38(%RSP) |
0x4403b7 MOV %RBX,0x28(%RSP) |
0x4403bc ADD %EDX,%R11D |
0x4403bf ADD %R15D,%EAX |
0x4403c2 MOV %R14D,%EDX |
0x4403c5 MOV 0x8(%R13),%R15 |
0x4403c9 MOV 0x18(%R13),%R14 |
0x4403cd MOV %R11D,0x7c(%RSP) |
0x4403d2 SUB %R11D,%EDX |
0x4403d5 MOVSXD %EAX,%RBX |
0x4403d8 MOV %R15,0x40(%RSP) |
0x4403dd MOV %R14,0x30(%RSP) |
0x4403e2 NOPW (%RAX,%RAX,1) |
(279) 0x4403e8 CMP %EDX,%R12D |
(279) 0x4403eb CMOVBE %R12D,%EDX |
(279) 0x4403ef LEA (%R9,%RDX,1),%ECX |
(279) 0x4403f3 MOV %ECX,0x78(%RSP) |
(279) 0x4403f7 CMP %ECX,%R9D |
(279) 0x4403fa JAE 4407fd |
(279) 0x440400 MOV 0x30(%RSP),%R12 |
(279) 0x440405 MOV 0x38(%RSP),%RDI |
(279) 0x44040a LEA -0x1(%RDX),%EAX |
(279) 0x44040d MOV 0x28(%RSP),%RCX |
(279) 0x440412 MOV 0x40(%RSP),%R13 |
(279) 0x440417 MOV (%R12),%RSI |
(279) 0x44041b MOV (%RDI),%R8 |
(279) 0x44041e MOV (%RCX),%R10 |
(279) 0x440421 MOV (%R13),%R11 |
(279) 0x440425 IMUL %RBX,%R8 |
(279) 0x440429 MOV 0x10(%R13),%R15 |
(279) 0x44042d MOV 0x10(%RDI),%R14 |
(279) 0x440431 IMUL %RBX,%RSI |
(279) 0x440435 MOV 0x10(%R12),%R13 |
(279) 0x44043a MOV 0x10(%RCX),%R12 |
(279) 0x44043e IMUL %RBX,%R10 |
(279) 0x440442 IMUL %RBX,%R11 |
(279) 0x440446 MOV %R8,0x60(%RSP) |
(279) 0x44044b MOV %RSI,0x68(%RSP) |
(279) 0x440450 MOV %R10,0x70(%RSP) |
(279) 0x440455 CMP $0x6,%EAX |
(279) 0x440458 JBE 440840 |
(279) 0x44045e MOVSXD 0x7c(%RSP),%RAX |
(279) 0x440463 LEA (%R8,%RAX,1),%RCX |
(279) 0x440467 LEA (%R11,%RAX,1),%RDI |
(279) 0x44046b LEA (%R14,%RCX,8),%R8 |
(279) 0x44046f MOV 0x70(%RSP),%RCX |
(279) 0x440474 LEA (%RSI,%RAX,1),%RSI |
(279) 0x440478 LEA (%R15,%RDI,8),%R10 |
(279) 0x44047c LEA (%R13,%RSI,8),%RDI |
(279) 0x440481 ADD %RCX,%RAX |
(279) 0x440484 MOV %EDX,%ECX |
(279) 0x440486 SHR $0x3,%ECX |
(279) 0x440489 LEA (%R12,%RAX,8),%RSI |
(279) 0x44048d XOR %EAX,%EAX |
(279) 0x44048f SAL $0x6,%RCX |
(279) 0x440493 MOV %RCX,0x58(%RSP) |
(279) 0x440498 SUB $0x40,%RCX |
(279) 0x44049c SHR $0x6,%RCX |
(279) 0x4404a0 INC %RCX |
(279) 0x4404a3 AND $0x7,%ECX |
(279) 0x4404a6 JE 4405c4 |
(279) 0x4404ac CMP $0x1,%RCX |
(279) 0x4404b0 JE 440599 |
(279) 0x4404b6 CMP $0x2,%RCX |
(279) 0x4404ba JE 440579 |
(279) 0x4404c0 CMP $0x3,%RCX |
(279) 0x4404c4 JE 440559 |
(279) 0x4404ca CMP $0x4,%RCX |
(279) 0x4404ce JE 440539 |
(279) 0x4404d0 CMP $0x5,%RCX |
(279) 0x4404d4 JE 440519 |
(279) 0x4404d6 CMP $0x6,%RCX |
(279) 0x4404da JE 4404f9 |
(279) 0x4404dc VMOVUPD (%R10),%ZMM3 |
(279) 0x4404e2 MOV $0x40,%EAX |
(279) 0x4404e7 VMOVUPD %ZMM3,(%R8) |
(279) 0x4404ed VMOVUPD (%RDI),%ZMM4 |
(279) 0x4404f3 VMOVUPD %ZMM4,(%RSI) |
(279) 0x4404f9 VMOVUPD (%R10,%RAX,1),%ZMM1 |
(279) 0x440500 VMOVUPD %ZMM1,(%R8,%RAX,1) |
(279) 0x440507 VMOVUPD (%RDI,%RAX,1),%ZMM2 |
(279) 0x44050e VMOVUPD %ZMM2,(%RSI,%RAX,1) |
(279) 0x440515 ADD $0x40,%RAX |
(279) 0x440519 VMOVUPD (%R10,%RAX,1),%ZMM0 |
(279) 0x440520 VMOVUPD %ZMM0,(%R8,%RAX,1) |
(279) 0x440527 VMOVUPD (%RDI,%RAX,1),%ZMM5 |
(279) 0x44052e VMOVUPD %ZMM5,(%RSI,%RAX,1) |
(279) 0x440535 ADD $0x40,%RAX |
(279) 0x440539 VMOVUPD (%R10,%RAX,1),%ZMM6 |
(279) 0x440540 VMOVUPD %ZMM6,(%R8,%RAX,1) |
(279) 0x440547 VMOVUPD (%RDI,%RAX,1),%ZMM7 |
(279) 0x44054e VMOVUPD %ZMM7,(%RSI,%RAX,1) |
(279) 0x440555 ADD $0x40,%RAX |
(279) 0x440559 VMOVUPD (%R10,%RAX,1),%ZMM8 |
(279) 0x440560 VMOVUPD %ZMM8,(%R8,%RAX,1) |
(279) 0x440567 VMOVUPD (%RDI,%RAX,1),%ZMM9 |
(279) 0x44056e VMOVUPD %ZMM9,(%RSI,%RAX,1) |
(279) 0x440575 ADD $0x40,%RAX |
(279) 0x440579 VMOVUPD (%R10,%RAX,1),%ZMM10 |
(279) 0x440580 VMOVUPD %ZMM10,(%R8,%RAX,1) |
(279) 0x440587 VMOVUPD (%RDI,%RAX,1),%ZMM11 |
(279) 0x44058e VMOVUPD %ZMM11,(%RSI,%RAX,1) |
(279) 0x440595 ADD $0x40,%RAX |
(279) 0x440599 VMOVUPD (%R10,%RAX,1),%ZMM12 |
(279) 0x4405a0 VMOVUPD %ZMM12,(%R8,%RAX,1) |
(279) 0x4405a7 VMOVUPD (%RDI,%RAX,1),%ZMM13 |
(279) 0x4405ae VMOVUPD %ZMM13,(%RSI,%RAX,1) |
(279) 0x4405b5 ADD $0x40,%RAX |
(279) 0x4405b9 CMP %RAX,0x58(%RSP) |
(279) 0x4405be JE 4406d1 |
(280) 0x4405c4 VMOVUPD (%R10,%RAX,1),%ZMM14 |
(280) 0x4405cb VMOVUPD %ZMM14,(%R8,%RAX,1) |
(280) 0x4405d2 VMOVUPD (%RDI,%RAX,1),%ZMM15 |
(280) 0x4405d9 VMOVUPD %ZMM15,(%RSI,%RAX,1) |
(280) 0x4405e0 VMOVUPD 0x40(%R10,%RAX,1),%ZMM3 |
(280) 0x4405e8 VMOVUPD %ZMM3,0x40(%R8,%RAX,1) |
(280) 0x4405f0 VMOVUPD 0x40(%RDI,%RAX,1),%ZMM4 |
(280) 0x4405f8 VMOVUPD %ZMM4,0x40(%RSI,%RAX,1) |
(280) 0x440600 VMOVUPD 0x80(%R10,%RAX,1),%ZMM1 |
(280) 0x440608 VMOVUPD %ZMM1,0x80(%R8,%RAX,1) |
(280) 0x440610 VMOVUPD 0x80(%RDI,%RAX,1),%ZMM2 |
(280) 0x440618 VMOVUPD %ZMM2,0x80(%RSI,%RAX,1) |
(280) 0x440620 VMOVUPD 0xc0(%R10,%RAX,1),%ZMM0 |
(280) 0x440628 VMOVUPD %ZMM0,0xc0(%R8,%RAX,1) |
(280) 0x440630 VMOVUPD 0xc0(%RDI,%RAX,1),%ZMM5 |
(280) 0x440638 VMOVUPD %ZMM5,0xc0(%RSI,%RAX,1) |
(280) 0x440640 VMOVUPD 0x100(%R10,%RAX,1),%ZMM6 |
(280) 0x440648 VMOVUPD %ZMM6,0x100(%R8,%RAX,1) |
(280) 0x440650 VMOVUPD 0x100(%RDI,%RAX,1),%ZMM7 |
(280) 0x440658 VMOVUPD %ZMM7,0x100(%RSI,%RAX,1) |
(280) 0x440660 VMOVUPD 0x140(%R10,%RAX,1),%ZMM8 |
(280) 0x440668 VMOVUPD %ZMM8,0x140(%R8,%RAX,1) |
(280) 0x440670 VMOVUPD 0x140(%RDI,%RAX,1),%ZMM9 |
(280) 0x440678 VMOVUPD %ZMM9,0x140(%RSI,%RAX,1) |
(280) 0x440680 VMOVUPD 0x180(%R10,%RAX,1),%ZMM10 |
(280) 0x440688 VMOVUPD %ZMM10,0x180(%R8,%RAX,1) |
(280) 0x440690 VMOVUPD 0x180(%RDI,%RAX,1),%ZMM11 |
(280) 0x440698 VMOVUPD %ZMM11,0x180(%RSI,%RAX,1) |
(280) 0x4406a0 VMOVUPD 0x1c0(%R10,%RAX,1),%ZMM12 |
(280) 0x4406a8 VMOVUPD %ZMM12,0x1c0(%R8,%RAX,1) |
(280) 0x4406b0 VMOVUPD 0x1c0(%RDI,%RAX,1),%ZMM13 |
(280) 0x4406b8 VMOVUPD %ZMM13,0x1c0(%RSI,%RAX,1) |
(280) 0x4406c0 ADD $0x200,%RAX |
(280) 0x4406c6 CMP %RAX,0x58(%RSP) |
(280) 0x4406cb JNE 4405c4 |
(279) 0x4406d1 MOV 0x7c(%RSP),%R10D |
(279) 0x4406d6 MOV %EDX,%R8D |
(279) 0x4406d9 AND $-0x8,%R8D |
(279) 0x4406dd ADD %R8D,%R9D |
(279) 0x4406e0 LEA (%R8,%R10,1),%ESI |
(279) 0x4406e4 TEST $0x7,%DL |
(279) 0x4406e7 JE 4407f8 |
(279) 0x4406ed SUB %R8D,%EDX |
(279) 0x4406f0 LEA -0x1(%RDX),%EDI |
(279) 0x4406f3 CMP $0x2,%EDI |
(279) 0x4406f6 JBE 44074f |
(279) 0x4406f8 MOVSXD 0x7c(%RSP),%RCX |
(279) 0x4406fd MOV 0x60(%RSP),%R10 |
(279) 0x440702 MOV 0x68(%RSP),%RDI |
(279) 0x440707 LEA (%R11,%RCX,1),%RAX |
(279) 0x44070b ADD %RCX,%R10 |
(279) 0x44070e ADD %R8,%RAX |
(279) 0x440711 ADD %RCX,%RDI |
(279) 0x440714 ADD %R8,%R10 |
(279) 0x440717 VMOVUPD (%R15,%RAX,8),%YMM14 |
(279) 0x44071d MOV 0x70(%RSP),%RAX |
(279) 0x440722 ADD %R8,%RDI |
(279) 0x440725 VMOVUPD %YMM14,(%R14,%R10,8) |
(279) 0x44072b ADD %RAX,%RCX |
(279) 0x44072e VMOVUPD (%R13,%RDI,8),%YMM15 |
(279) 0x440735 ADD %R8,%RCX |
(279) 0x440738 VMOVUPD %YMM15,(%R12,%RCX,8) |
(279) 0x44073e TEST $0x3,%DL |
(279) 0x440741 JE 4407f8 |
(279) 0x440747 AND $-0x4,%EDX |
(279) 0x44074a ADD %EDX,%R9D |
(279) 0x44074d ADD %EDX,%ESI |
(279) 0x44074f MOVSXD %ESI,%R10 |
(279) 0x440752 MOV 0x60(%RSP),%RCX |
(279) 0x440757 MOV 0x68(%RSP),%RDI |
(279) 0x44075c LEA (%R11,%R10,1),%RDX |
(279) 0x440760 VMOVSD (%R15,%RDX,8),%XMM3 |
(279) 0x440766 LEA (%RCX,%R10,1),%R8 |
(279) 0x44076a LEA (%RDI,%R10,1),%RAX |
(279) 0x44076e LEA 0x1(%R9),%EDX |
(279) 0x440772 VMOVSD %XMM3,(%R14,%R8,8) |
(279) 0x440778 MOV 0x70(%RSP),%R8 |
(279) 0x44077d VMOVSD (%R13,%RAX,8),%XMM4 |
(279) 0x440784 LEA 0x1(%RSI),%EAX |
(279) 0x440787 ADD %R8,%R10 |
(279) 0x44078a VMOVSD %XMM4,(%R12,%R10,8) |
(279) 0x440790 MOV 0x78(%RSP),%R10D |
(279) 0x440795 CMP %R10D,%EDX |
(279) 0x440798 JAE 4407f8 |
(279) 0x44079a CLTQ |
(279) 0x44079c ADD $0x2,%R9D |
(279) 0x4407a0 ADD $0x2,%ESI |
(279) 0x4407a3 LEA (%R11,%RAX,1),%RDX |
(279) 0x4407a7 VMOVSD (%R15,%RDX,8),%XMM1 |
(279) 0x4407ad LEA (%RCX,%RAX,1),%RDX |
(279) 0x4407b1 VMOVSD %XMM1,(%R14,%RDX,8) |
(279) 0x4407b7 LEA (%RDI,%RAX,1),%RDX |
(279) 0x4407bb ADD %R8,%RAX |
(279) 0x4407be VMOVSD (%R13,%RDX,8),%XMM2 |
(279) 0x4407c5 VMOVSD %XMM2,(%R12,%RAX,8) |
(279) 0x4407cb CMP %R10D,%R9D |
(279) 0x4407ce JAE 4407f8 |
(279) 0x4407d0 MOVSXD %ESI,%R9 |
(279) 0x4407d3 ADD %R9,%R11 |
(279) 0x4407d6 ADD %R9,%RCX |
(279) 0x4407d9 ADD %R9,%RDI |
(279) 0x4407dc ADD %R9,%R8 |
(279) 0x4407df VMOVSD (%R15,%R11,8),%XMM0 |
(279) 0x4407e5 VMOVSD %XMM0,(%R14,%RCX,8) |
(279) 0x4407eb VMOVSD (%R13,%RDI,8),%XMM5 |
(279) 0x4407f2 VMOVSD %XMM5,(%R12,%R8,8) |
(279) 0x4407f8 MOV 0x78(%RSP),%R9D |
(279) 0x4407fd INC %RBX |
(279) 0x440800 LEA (%RBX),%R15D |
(279) 0x440803 CMP %R15D,0x50(%RSP) |
(279) 0x440808 JLE 440828 |
(279) 0x44080a MOV 0x48(%RSP),%R12D |
(279) 0x44080f MOV 0x4c(%RSP),%R11D |
(279) 0x440814 MOV 0x54(%RSP),%EDX |
(279) 0x440818 MOV %R11D,0x7c(%RSP) |
(279) 0x44081d SUB %R9D,%R12D |
(279) 0x440820 JMP 4403e8 |
0x440825 NOPL (%RAX) |
0x440828 VZEROUPPER |
0x44082b LEA -0x28(%RBP),%RSP |
0x44082f POP %RBX |
0x440830 POP %R12 |
0x440832 POP %R13 |
0x440834 POP %R14 |
0x440836 POP %R15 |
0x440838 POP %RBP |
0x440839 RET |
0x44083a NOPW (%RAX,%RAX,1) |
(279) 0x440840 MOV 0x7c(%RSP),%ESI |
(279) 0x440844 XOR %R8D,%R8D |
(279) 0x440847 JMP 4406ed |
0x44084c INC %R12D |
0x44084f XOR %EDX,%EDX |
0x440851 JMP 440382 |
0x440856 NOPW %CS:(%RAX,%RAX,1) |
Path / |
Source file and lines | reset_field.cpp:44-48 |
Module | exec |
nb instructions | 80 |
nb uops | 90 |
loop length | 279 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 10 |
micro-operation queue | 15.00 cycles |
front end | 15.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 5.70 | 8.00 | 6.00 | 6.00 | 8.50 | 5.87 | 5.70 | 8.50 | 8.50 | 8.50 | 5.73 | 6.00 |
cycles | 5.70 | 11.73 | 6.00 | 6.00 | 8.50 | 5.87 | 5.70 | 8.50 | 8.50 | 8.50 | 5.73 | 6.00 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.24-14.34 |
Stall cycles | 0.00 |
Front-end | 15.00 |
Dispatch | 11.73 |
DIV/SQRT | 12.00 |
Overall L1 | 15.00 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 20% |
all | 9% |
load | 10% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 10% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD $-0x80,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x28(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RDI),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x24(%RDI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x3,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA 0x1(%RBX),%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ESI,0x4c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 44082b <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x52b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x3(%RCX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 44082b <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x52b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R14D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %ESI,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EDI,0x54(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 404650 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 404540 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x54(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 44084c <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x54c> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %R12D,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%R12,%R9,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R10D,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R10D,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 44082b <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x52b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R9D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x4c(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R13),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x54(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x10(%R13),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R15D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x8(%R13),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%R13),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R11D,0x7c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R11D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %EAX,%RBX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R15,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 440382 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x82> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | reset_field.cpp:44-48 |
Module | exec |
nb instructions | 80 |
nb uops | 90 |
loop length | 279 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 10 |
micro-operation queue | 15.00 cycles |
front end | 15.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 5.70 | 8.00 | 6.00 | 6.00 | 8.50 | 5.87 | 5.70 | 8.50 | 8.50 | 8.50 | 5.73 | 6.00 |
cycles | 5.70 | 11.73 | 6.00 | 6.00 | 8.50 | 5.87 | 5.70 | 8.50 | 8.50 | 8.50 | 5.73 | 6.00 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.24-14.34 |
Stall cycles | 0.00 |
Front-end | 15.00 |
Dispatch | 11.73 |
DIV/SQRT | 12.00 |
Overall L1 | 15.00 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 20% |
all | 9% |
load | 10% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 10% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD $-0x80,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x28(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RDI),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x24(%RDI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x3,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA 0x1(%RBX),%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ESI,0x4c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 44082b <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x52b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x3(%RCX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 44082b <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x52b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R14D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %ESI,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EDI,0x54(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 404650 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 404540 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x54(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 44084c <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x54c> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %R12D,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%R12,%R9,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R10D,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R10D,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 44082b <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x52b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R9D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x4c(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R13),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x54(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x10(%R13),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R15D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x8(%R13),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%R13),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R11D,0x7c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R11D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %EAX,%RBX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R15,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 440382 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x82> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1– | 1.96 | 0.66 |
▼Loop 279 - reset_field.cpp:46-48 - exec– | 0 | 0.01 |
○Loop 280 - reset_field.cpp:47-48 - exec | 1.96 | 0.65 |