Function: _Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0 | Module: exec | Source: revert.cpp:34-38 [...] | Coverage: 1.63% |
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Function: _Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0 | Module: exec | Source: revert.cpp:34-38 [...] | Coverage: 1.63% |
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/home/eoseret/qaas_runs_CPU_9468/171-112-9712/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69 |
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69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
/home/eoseret/qaas_runs_CPU_9468/171-112-9712/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/revert.cpp: 34 - 38 |
-------------------------------------------------------------------------------- |
34: #pragma omp parallel for simd collapse(2) |
35: for (int j = (y_min + 1); j < (y_max + 2); j++) { |
36: for (int i = (x_min + 1); i < (x_max + 2); i++) { |
37: density1(i, j) = density0(i, j); |
38: energy1(i, j) = energy0(i, j); |
0x441010 PUSH %RBP |
0x441011 MOV %RSP,%RBP |
0x441014 PUSH %R15 |
0x441016 PUSH %R14 |
0x441018 PUSH %R13 |
0x44101a PUSH %R12 |
0x44101c PUSH %RBX |
0x44101d AND $-0x40,%RSP |
0x441021 ADD $-0x80,%RSP |
0x441025 MOV 0x28(%RDI),%EAX |
0x441028 MOV 0x2c(%RDI),%EDX |
0x44102b MOV 0x20(%RDI),%EBX |
0x44102e MOV 0x24(%RDI),%ECX |
0x441031 ADD $0x2,%EDX |
0x441034 LEA 0x1(%RAX),%R15D |
0x441038 LEA 0x1(%RBX),%ESI |
0x44103b MOV %EDX,0x50(%RSP) |
0x44103f MOV %ESI,0x4c(%RSP) |
0x441043 CMP %EDX,%R15D |
0x441046 JGE 44153b |
0x44104c MOV %EDX,%EBX |
0x44104e LEA 0x2(%RCX),%R14D |
0x441052 SUB %R15D,%EBX |
0x441055 CMP %R14D,%ESI |
0x441058 JGE 44153b |
0x44105e MOV %RDI,%R13 |
0x441061 MOV %R14D,%EDI |
0x441064 SUB %ESI,%EDI |
0x441066 MOV %EDI,0x54(%RSP) |
0x44106a CALL 404650 <omp_get_num_threads@plt> |
0x44106f MOV %EAX,%R12D |
0x441072 CALL 404540 <omp_get_thread_num@plt> |
0x441077 XOR %EDX,%EDX |
0x441079 MOV %EAX,%R8D |
0x44107c MOV 0x54(%RSP),%EAX |
0x441080 IMUL %EBX,%EAX |
0x441083 DIV %R12D |
0x441086 MOV %EAX,%R12D |
0x441089 CMP %EDX,%R8D |
0x44108c JB 44155c |
0x441092 IMUL %R12D,%R8D |
0x441096 LEA (%R8,%RDX,1),%R9D |
0x44109a LEA (%R12,%R9,1),%R10D |
0x44109e MOV %R10D,0x48(%RSP) |
0x4410a3 CMP %R10D,%R9D |
0x4410a6 JAE 44153b |
0x4410ac MOV %R9D,%EAX |
0x4410af XOR %EDX,%EDX |
0x4410b1 MOV 0x4c(%RSP),%R11D |
0x4410b6 MOV 0x8(%R13),%RSI |
0x4410ba DIVL 0x54(%RSP) |
0x4410be MOV 0x18(%R13),%RBX |
0x4410c2 MOV %RSI,0x38(%RSP) |
0x4410c7 MOV %RBX,0x28(%RSP) |
0x4410cc ADD %EDX,%R11D |
0x4410cf ADD %R15D,%EAX |
0x4410d2 MOV %R14D,%EDX |
0x4410d5 MOV (%R13),%R15 |
0x4410d9 MOV 0x10(%R13),%R14 |
0x4410dd MOV %R11D,0x7c(%RSP) |
0x4410e2 SUB %R11D,%EDX |
0x4410e5 MOVSXD %EAX,%RBX |
0x4410e8 MOV %R15,0x40(%RSP) |
0x4410ed MOV %R14,0x30(%RSP) |
0x4410f2 NOPW (%RAX,%RAX,1) |
(284) 0x4410f8 CMP %EDX,%R12D |
(284) 0x4410fb CMOVBE %R12D,%EDX |
(284) 0x4410ff LEA (%R9,%RDX,1),%ECX |
(284) 0x441103 MOV %ECX,0x78(%RSP) |
(284) 0x441107 CMP %ECX,%R9D |
(284) 0x44110a JAE 44150d |
(284) 0x441110 MOV 0x30(%RSP),%R12 |
(284) 0x441115 MOV 0x38(%RSP),%RDI |
(284) 0x44111a LEA -0x1(%RDX),%EAX |
(284) 0x44111d MOV 0x28(%RSP),%RCX |
(284) 0x441122 MOV 0x40(%RSP),%R13 |
(284) 0x441127 MOV (%R12),%RSI |
(284) 0x44112b MOV (%RDI),%R8 |
(284) 0x44112e MOV (%RCX),%R10 |
(284) 0x441131 MOV (%R13),%R11 |
(284) 0x441135 IMUL %RBX,%R8 |
(284) 0x441139 MOV 0x10(%R13),%R15 |
(284) 0x44113d MOV 0x10(%RDI),%R14 |
(284) 0x441141 IMUL %RBX,%RSI |
(284) 0x441145 MOV 0x10(%R12),%R13 |
(284) 0x44114a MOV 0x10(%RCX),%R12 |
(284) 0x44114e IMUL %RBX,%R10 |
(284) 0x441152 IMUL %RBX,%R11 |
(284) 0x441156 MOV %R8,0x60(%RSP) |
(284) 0x44115b MOV %RSI,0x68(%RSP) |
(284) 0x441160 MOV %R10,0x70(%RSP) |
(284) 0x441165 CMP $0x6,%EAX |
(284) 0x441168 JBE 441550 |
(284) 0x44116e MOVSXD 0x7c(%RSP),%RAX |
(284) 0x441173 LEA (%R8,%RAX,1),%RCX |
(284) 0x441177 LEA (%R11,%RAX,1),%RDI |
(284) 0x44117b LEA (%R14,%RCX,8),%R8 |
(284) 0x44117f MOV 0x70(%RSP),%RCX |
(284) 0x441184 LEA (%RSI,%RAX,1),%RSI |
(284) 0x441188 LEA (%R15,%RDI,8),%R10 |
(284) 0x44118c LEA (%R13,%RSI,8),%RDI |
(284) 0x441191 ADD %RCX,%RAX |
(284) 0x441194 MOV %EDX,%ECX |
(284) 0x441196 SHR $0x3,%ECX |
(284) 0x441199 LEA (%R12,%RAX,8),%RSI |
(284) 0x44119d XOR %EAX,%EAX |
(284) 0x44119f SAL $0x6,%RCX |
(284) 0x4411a3 MOV %RCX,0x58(%RSP) |
(284) 0x4411a8 SUB $0x40,%RCX |
(284) 0x4411ac SHR $0x6,%RCX |
(284) 0x4411b0 INC %RCX |
(284) 0x4411b3 AND $0x7,%ECX |
(284) 0x4411b6 JE 4412d4 |
(284) 0x4411bc CMP $0x1,%RCX |
(284) 0x4411c0 JE 4412a9 |
(284) 0x4411c6 CMP $0x2,%RCX |
(284) 0x4411ca JE 441289 |
(284) 0x4411d0 CMP $0x3,%RCX |
(284) 0x4411d4 JE 441269 |
(284) 0x4411da CMP $0x4,%RCX |
(284) 0x4411de JE 441249 |
(284) 0x4411e0 CMP $0x5,%RCX |
(284) 0x4411e4 JE 441229 |
(284) 0x4411e6 CMP $0x6,%RCX |
(284) 0x4411ea JE 441209 |
(284) 0x4411ec VMOVUPD (%R10),%ZMM3 |
(284) 0x4411f2 MOV $0x40,%EAX |
(284) 0x4411f7 VMOVUPD %ZMM3,(%R8) |
(284) 0x4411fd VMOVUPD (%RDI),%ZMM4 |
(284) 0x441203 VMOVUPD %ZMM4,(%RSI) |
(284) 0x441209 VMOVUPD (%R10,%RAX,1),%ZMM1 |
(284) 0x441210 VMOVUPD %ZMM1,(%R8,%RAX,1) |
(284) 0x441217 VMOVUPD (%RDI,%RAX,1),%ZMM2 |
(284) 0x44121e VMOVUPD %ZMM2,(%RSI,%RAX,1) |
(284) 0x441225 ADD $0x40,%RAX |
(284) 0x441229 VMOVUPD (%R10,%RAX,1),%ZMM0 |
(284) 0x441230 VMOVUPD %ZMM0,(%R8,%RAX,1) |
(284) 0x441237 VMOVUPD (%RDI,%RAX,1),%ZMM5 |
(284) 0x44123e VMOVUPD %ZMM5,(%RSI,%RAX,1) |
(284) 0x441245 ADD $0x40,%RAX |
(284) 0x441249 VMOVUPD (%R10,%RAX,1),%ZMM6 |
(284) 0x441250 VMOVUPD %ZMM6,(%R8,%RAX,1) |
(284) 0x441257 VMOVUPD (%RDI,%RAX,1),%ZMM7 |
(284) 0x44125e VMOVUPD %ZMM7,(%RSI,%RAX,1) |
(284) 0x441265 ADD $0x40,%RAX |
(284) 0x441269 VMOVUPD (%R10,%RAX,1),%ZMM8 |
(284) 0x441270 VMOVUPD %ZMM8,(%R8,%RAX,1) |
(284) 0x441277 VMOVUPD (%RDI,%RAX,1),%ZMM9 |
(284) 0x44127e VMOVUPD %ZMM9,(%RSI,%RAX,1) |
(284) 0x441285 ADD $0x40,%RAX |
(284) 0x441289 VMOVUPD (%R10,%RAX,1),%ZMM10 |
(284) 0x441290 VMOVUPD %ZMM10,(%R8,%RAX,1) |
(284) 0x441297 VMOVUPD (%RDI,%RAX,1),%ZMM11 |
(284) 0x44129e VMOVUPD %ZMM11,(%RSI,%RAX,1) |
(284) 0x4412a5 ADD $0x40,%RAX |
(284) 0x4412a9 VMOVUPD (%R10,%RAX,1),%ZMM12 |
(284) 0x4412b0 VMOVUPD %ZMM12,(%R8,%RAX,1) |
(284) 0x4412b7 VMOVUPD (%RDI,%RAX,1),%ZMM13 |
(284) 0x4412be VMOVUPD %ZMM13,(%RSI,%RAX,1) |
(284) 0x4412c5 ADD $0x40,%RAX |
(284) 0x4412c9 CMP %RAX,0x58(%RSP) |
(284) 0x4412ce JE 4413e1 |
(285) 0x4412d4 VMOVUPD (%R10,%RAX,1),%ZMM14 |
(285) 0x4412db VMOVUPD %ZMM14,(%R8,%RAX,1) |
(285) 0x4412e2 VMOVUPD (%RDI,%RAX,1),%ZMM15 |
(285) 0x4412e9 VMOVUPD %ZMM15,(%RSI,%RAX,1) |
(285) 0x4412f0 VMOVUPD 0x40(%R10,%RAX,1),%ZMM3 |
(285) 0x4412f8 VMOVUPD %ZMM3,0x40(%R8,%RAX,1) |
(285) 0x441300 VMOVUPD 0x40(%RDI,%RAX,1),%ZMM4 |
(285) 0x441308 VMOVUPD %ZMM4,0x40(%RSI,%RAX,1) |
(285) 0x441310 VMOVUPD 0x80(%R10,%RAX,1),%ZMM1 |
(285) 0x441318 VMOVUPD %ZMM1,0x80(%R8,%RAX,1) |
(285) 0x441320 VMOVUPD 0x80(%RDI,%RAX,1),%ZMM2 |
(285) 0x441328 VMOVUPD %ZMM2,0x80(%RSI,%RAX,1) |
(285) 0x441330 VMOVUPD 0xc0(%R10,%RAX,1),%ZMM0 |
(285) 0x441338 VMOVUPD %ZMM0,0xc0(%R8,%RAX,1) |
(285) 0x441340 VMOVUPD 0xc0(%RDI,%RAX,1),%ZMM5 |
(285) 0x441348 VMOVUPD %ZMM5,0xc0(%RSI,%RAX,1) |
(285) 0x441350 VMOVUPD 0x100(%R10,%RAX,1),%ZMM6 |
(285) 0x441358 VMOVUPD %ZMM6,0x100(%R8,%RAX,1) |
(285) 0x441360 VMOVUPD 0x100(%RDI,%RAX,1),%ZMM7 |
(285) 0x441368 VMOVUPD %ZMM7,0x100(%RSI,%RAX,1) |
(285) 0x441370 VMOVUPD 0x140(%R10,%RAX,1),%ZMM8 |
(285) 0x441378 VMOVUPD %ZMM8,0x140(%R8,%RAX,1) |
(285) 0x441380 VMOVUPD 0x140(%RDI,%RAX,1),%ZMM9 |
(285) 0x441388 VMOVUPD %ZMM9,0x140(%RSI,%RAX,1) |
(285) 0x441390 VMOVUPD 0x180(%R10,%RAX,1),%ZMM10 |
(285) 0x441398 VMOVUPD %ZMM10,0x180(%R8,%RAX,1) |
(285) 0x4413a0 VMOVUPD 0x180(%RDI,%RAX,1),%ZMM11 |
(285) 0x4413a8 VMOVUPD %ZMM11,0x180(%RSI,%RAX,1) |
(285) 0x4413b0 VMOVUPD 0x1c0(%R10,%RAX,1),%ZMM12 |
(285) 0x4413b8 VMOVUPD %ZMM12,0x1c0(%R8,%RAX,1) |
(285) 0x4413c0 VMOVUPD 0x1c0(%RDI,%RAX,1),%ZMM13 |
(285) 0x4413c8 VMOVUPD %ZMM13,0x1c0(%RSI,%RAX,1) |
(285) 0x4413d0 ADD $0x200,%RAX |
(285) 0x4413d6 CMP %RAX,0x58(%RSP) |
(285) 0x4413db JNE 4412d4 |
(284) 0x4413e1 MOV 0x7c(%RSP),%R10D |
(284) 0x4413e6 MOV %EDX,%R8D |
(284) 0x4413e9 AND $-0x8,%R8D |
(284) 0x4413ed ADD %R8D,%R9D |
(284) 0x4413f0 LEA (%R8,%R10,1),%ESI |
(284) 0x4413f4 TEST $0x7,%DL |
(284) 0x4413f7 JE 441508 |
(284) 0x4413fd SUB %R8D,%EDX |
(284) 0x441400 LEA -0x1(%RDX),%EDI |
(284) 0x441403 CMP $0x2,%EDI |
(284) 0x441406 JBE 44145f |
(284) 0x441408 MOVSXD 0x7c(%RSP),%RCX |
(284) 0x44140d MOV 0x60(%RSP),%R10 |
(284) 0x441412 MOV 0x68(%RSP),%RDI |
(284) 0x441417 LEA (%R11,%RCX,1),%RAX |
(284) 0x44141b ADD %RCX,%R10 |
(284) 0x44141e ADD %R8,%RAX |
(284) 0x441421 ADD %RCX,%RDI |
(284) 0x441424 ADD %R8,%R10 |
(284) 0x441427 VMOVUPD (%R15,%RAX,8),%YMM14 |
(284) 0x44142d MOV 0x70(%RSP),%RAX |
(284) 0x441432 ADD %R8,%RDI |
(284) 0x441435 VMOVUPD %YMM14,(%R14,%R10,8) |
(284) 0x44143b ADD %RAX,%RCX |
(284) 0x44143e VMOVUPD (%R13,%RDI,8),%YMM15 |
(284) 0x441445 ADD %R8,%RCX |
(284) 0x441448 VMOVUPD %YMM15,(%R12,%RCX,8) |
(284) 0x44144e TEST $0x3,%DL |
(284) 0x441451 JE 441508 |
(284) 0x441457 AND $-0x4,%EDX |
(284) 0x44145a ADD %EDX,%R9D |
(284) 0x44145d ADD %EDX,%ESI |
(284) 0x44145f MOVSXD %ESI,%R10 |
(284) 0x441462 MOV 0x60(%RSP),%RCX |
(284) 0x441467 MOV 0x68(%RSP),%RDI |
(284) 0x44146c LEA (%R11,%R10,1),%RDX |
(284) 0x441470 VMOVSD (%R15,%RDX,8),%XMM3 |
(284) 0x441476 LEA (%RCX,%R10,1),%R8 |
(284) 0x44147a LEA (%RDI,%R10,1),%RAX |
(284) 0x44147e LEA 0x1(%R9),%EDX |
(284) 0x441482 VMOVSD %XMM3,(%R14,%R8,8) |
(284) 0x441488 MOV 0x70(%RSP),%R8 |
(284) 0x44148d VMOVSD (%R13,%RAX,8),%XMM4 |
(284) 0x441494 LEA 0x1(%RSI),%EAX |
(284) 0x441497 ADD %R8,%R10 |
(284) 0x44149a VMOVSD %XMM4,(%R12,%R10,8) |
(284) 0x4414a0 MOV 0x78(%RSP),%R10D |
(284) 0x4414a5 CMP %R10D,%EDX |
(284) 0x4414a8 JAE 441508 |
(284) 0x4414aa CLTQ |
(284) 0x4414ac ADD $0x2,%R9D |
(284) 0x4414b0 ADD $0x2,%ESI |
(284) 0x4414b3 LEA (%R11,%RAX,1),%RDX |
(284) 0x4414b7 VMOVSD (%R15,%RDX,8),%XMM1 |
(284) 0x4414bd LEA (%RCX,%RAX,1),%RDX |
(284) 0x4414c1 VMOVSD %XMM1,(%R14,%RDX,8) |
(284) 0x4414c7 LEA (%RDI,%RAX,1),%RDX |
(284) 0x4414cb ADD %R8,%RAX |
(284) 0x4414ce VMOVSD (%R13,%RDX,8),%XMM2 |
(284) 0x4414d5 VMOVSD %XMM2,(%R12,%RAX,8) |
(284) 0x4414db CMP %R10D,%R9D |
(284) 0x4414de JAE 441508 |
(284) 0x4414e0 MOVSXD %ESI,%R9 |
(284) 0x4414e3 ADD %R9,%R11 |
(284) 0x4414e6 ADD %R9,%RCX |
(284) 0x4414e9 ADD %R9,%RDI |
(284) 0x4414ec ADD %R9,%R8 |
(284) 0x4414ef VMOVSD (%R15,%R11,8),%XMM0 |
(284) 0x4414f5 VMOVSD %XMM0,(%R14,%RCX,8) |
(284) 0x4414fb VMOVSD (%R13,%RDI,8),%XMM5 |
(284) 0x441502 VMOVSD %XMM5,(%R12,%R8,8) |
(284) 0x441508 MOV 0x78(%RSP),%R9D |
(284) 0x44150d INC %RBX |
(284) 0x441510 LEA (%RBX),%R15D |
(284) 0x441513 CMP %R15D,0x50(%RSP) |
(284) 0x441518 JLE 441538 |
(284) 0x44151a MOV 0x48(%RSP),%R12D |
(284) 0x44151f MOV 0x4c(%RSP),%R11D |
(284) 0x441524 MOV 0x54(%RSP),%EDX |
(284) 0x441528 MOV %R11D,0x7c(%RSP) |
(284) 0x44152d SUB %R9D,%R12D |
(284) 0x441530 JMP 4410f8 |
0x441535 NOPL (%RAX) |
0x441538 VZEROUPPER |
0x44153b LEA -0x28(%RBP),%RSP |
0x44153f POP %RBX |
0x441540 POP %R12 |
0x441542 POP %R13 |
0x441544 POP %R14 |
0x441546 POP %R15 |
0x441548 POP %RBP |
0x441549 RET |
0x44154a NOPW (%RAX,%RAX,1) |
(284) 0x441550 MOV 0x7c(%RSP),%ESI |
(284) 0x441554 XOR %R8D,%R8D |
(284) 0x441557 JMP 4413fd |
0x44155c INC %R12D |
0x44155f XOR %EDX,%EDX |
0x441561 JMP 441092 |
0x441566 NOPW %CS:(%RAX,%RAX,1) |
Path / |
Source file and lines | revert.cpp:34-38 |
Module | exec |
nb instructions | 80 |
nb uops | 90 |
loop length | 279 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 10 |
micro-operation queue | 15.00 cycles |
front end | 15.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 5.70 | 8.00 | 6.00 | 6.00 | 8.50 | 5.87 | 5.70 | 8.50 | 8.50 | 8.50 | 5.73 | 6.00 |
cycles | 5.70 | 11.73 | 6.00 | 6.00 | 8.50 | 5.87 | 5.70 | 8.50 | 8.50 | 8.50 | 5.73 | 6.00 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.24-14.34 |
Stall cycles | 0.00 |
Front-end | 15.00 |
Dispatch | 11.73 |
DIV/SQRT | 12.00 |
Overall L1 | 15.00 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 20% |
all | 9% |
load | 10% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 10% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD $-0x80,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x28(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RDI),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x24(%RDI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x2,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA 0x1(%RBX),%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ESI,0x4c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 44153b <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x52b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x2(%RCX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 44153b <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x52b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R14D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %ESI,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EDI,0x54(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 404650 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 404540 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x54(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 44155c <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x54c> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %R12D,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%R12,%R9,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R10D,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R10D,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 44153b <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x52b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R9D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x4c(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%R13),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x54(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x18(%R13),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R15D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV (%R13),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%R13),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R11D,0x7c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R11D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %EAX,%RBX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R15,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 441092 <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x82> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | revert.cpp:34-38 |
Module | exec |
nb instructions | 80 |
nb uops | 90 |
loop length | 279 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 10 |
micro-operation queue | 15.00 cycles |
front end | 15.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 5.70 | 8.00 | 6.00 | 6.00 | 8.50 | 5.87 | 5.70 | 8.50 | 8.50 | 8.50 | 5.73 | 6.00 |
cycles | 5.70 | 11.73 | 6.00 | 6.00 | 8.50 | 5.87 | 5.70 | 8.50 | 8.50 | 8.50 | 5.73 | 6.00 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.24-14.34 |
Stall cycles | 0.00 |
Front-end | 15.00 |
Dispatch | 11.73 |
DIV/SQRT | 12.00 |
Overall L1 | 15.00 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 20% |
all | 9% |
load | 10% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 10% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD $-0x80,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x28(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RDI),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x24(%RDI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x2,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA 0x1(%RBX),%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ESI,0x4c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 44153b <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x52b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x2(%RCX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 44153b <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x52b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R14D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %ESI,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EDI,0x54(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 404650 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 404540 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x54(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 44155c <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x54c> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %R12D,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%R12,%R9,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R10D,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R10D,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 44153b <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x52b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R9D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x4c(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%R13),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x54(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x18(%R13),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R15D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV (%R13),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%R13),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R11D,0x7c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R11D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %EAX,%RBX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R15,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 441092 <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x82> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0– | 1.63 | 0.54 |
▼Loop 284 - revert.cpp:36-38 - exec– | 0 | 0.01 |
○Loop 285 - revert.cpp:37-38 - exec | 1.62 | 0.54 |