Function: _Z14generate_chunkiR16global_variables._omp_fn.0 | Module: exec | Source: generate_chunk.cpp:74-80 [...] | Coverage: 0.03% |
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Function: _Z14generate_chunkiR16global_variables._omp_fn.0 | Module: exec | Source: generate_chunk.cpp:74-80 [...] | Coverage: 0.03% |
---|
/home/eoseret/qaas_runs_CPU_9468/171-112-9712/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 46 - 69 |
-------------------------------------------------------------------------------- |
46: T &operator[](size_t i) const { return data[i]; } |
[...] |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
/home/eoseret/qaas_runs_CPU_9468/171-112-9712/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/generate_chunk.cpp: 74 - 80 |
-------------------------------------------------------------------------------- |
74: #pragma omp parallel for simd collapse(2) |
75: for (int j = (0); j < (yrange); j++) { |
76: for (int i = (0); i < (xrange); i++) { |
77: field.energy0(i, j) = state_energy[0]; |
78: field.density0(i, j) = state_density[0]; |
79: field.xvel0(i, j) = state_xvel[0]; |
80: field.yvel0(i, j) = state_yvel[0]; |
0x436aa0 PUSH %RBP |
0x436aa1 MOV %RSP,%RBP |
0x436aa4 PUSH %R15 |
0x436aa6 PUSH %R14 |
0x436aa8 PUSH %R13 |
0x436aaa PUSH %R12 |
0x436aac PUSH %RBX |
0x436aad AND $-0x40,%RSP |
0x436ab1 ADD $-0x80,%RSP |
0x436ab5 MOV 0x2c(%RDI),%R14D |
0x436ab9 MOV 0x28(%RDI),%R15D |
0x436abd MOV %R14D,0x48(%RSP) |
0x436ac2 MOV %R15D,0x2c(%RSP) |
0x436ac7 TEST %R14D,%R14D |
0x436aca JLE 43703b |
0x436ad0 TEST %R15D,%R15D |
0x436ad3 JLE 43703b |
0x436ad9 MOV %RDI,%RBX |
0x436adc CALL 404650 <omp_get_num_threads@plt> |
0x436ae1 MOV %EAX,%R12D |
0x436ae4 CALL 404540 <omp_get_thread_num@plt> |
0x436ae9 XOR %EDX,%EDX |
0x436aeb MOV %EAX,%ESI |
0x436aed MOV %R14D,%EAX |
0x436af0 IMUL %R15D,%EAX |
0x436af4 DIV %R12D |
0x436af7 MOV %EAX,%R12D |
0x436afa CMP %EDX,%ESI |
0x436afc JB 43705d |
0x436b02 IMUL %R12D,%ESI |
0x436b06 LEA (%RSI,%RDX,1),%R14D |
0x436b0a LEA (%R12,%R14,1),%EDI |
0x436b0e MOV %EDI,0x28(%RSP) |
0x436b12 CMP %EDI,%R14D |
0x436b15 JAE 43703b |
0x436b1b MOV 0x2c(%RSP),%R8D |
0x436b20 MOV %R14D,%EAX |
0x436b23 XOR %EDX,%EDX |
0x436b25 MOV 0x8(%RBX),%R9 |
0x436b29 MOV (%RBX),%R10 |
0x436b2c MOV 0x10(%RBX),%R11 |
0x436b30 DIV %R8D |
0x436b33 MOV 0x18(%RBX),%R15 |
0x436b37 MOV 0x20(%RBX),%R13 |
0x436b3b MOV %R9,0x20(%RSP) |
0x436b40 MOV %R10,0x18(%RSP) |
0x436b45 MOV %R11,0x10(%RSP) |
0x436b4a MOV %R15,0x8(%RSP) |
0x436b4f MOV %EDX,0x60(%RSP) |
0x436b53 SUB %EDX,%R8D |
0x436b56 MOVSXD %EAX,%RBX |
0x436b59 NOPL (%RAX) |
(235) 0x436b60 CMP %R8D,%R12D |
(235) 0x436b63 CMOVBE %R12D,%R8D |
(235) 0x436b67 LEA (%R14,%R8,1),%ECX |
(235) 0x436b6b MOV %R8D,0x64(%RSP) |
(235) 0x436b70 MOV %ECX,0x4c(%RSP) |
(235) 0x436b74 CMP %ECX,%R14D |
(235) 0x436b77 JAE 43700f |
(235) 0x436b7d MOV 0x18(%RSP),%RSI |
(235) 0x436b82 MOV 0x10(%RSP),%R9 |
(235) 0x436b87 MOV 0xb8(%R13),%R11 |
(235) 0x436b8e MOV 0x10(%R13),%RAX |
(235) 0x436b92 MOV 0x8(%RSP),%R15 |
(235) 0x436b97 MOV 0x30(%R13),%RDX |
(235) 0x436b9b MOV 0x8(%RSI),%RDI |
(235) 0x436b9f MOV (%R13),%R10 |
(235) 0x436ba3 MOV %R11,0x70(%RSP) |
(235) 0x436ba8 MOV 0x8(%R9),%RSI |
(235) 0x436bac MOV 0xa8(%R13),%R11 |
(235) 0x436bb3 IMUL %RBX,%RDX |
(235) 0x436bb7 MOV %RAX,0x68(%RSP) |
(235) 0x436bbc MOV 0xd8(%R13),%R9 |
(235) 0x436bc3 MOV 0x20(%RSP),%R12 |
(235) 0x436bc8 IMUL %RBX,%R10 |
(235) 0x436bcc MOV 0xe8(%R13),%RAX |
(235) 0x436bd3 IMUL %RBX,%R11 |
(235) 0x436bd7 MOV 0x8(%R15),%RCX |
(235) 0x436bdb IMUL %RBX,%R9 |
(235) 0x436bdf MOV 0x64(%RSP),%R15D |
(235) 0x436be4 MOV 0x8(%R12),%R8 |
(235) 0x436be9 MOV %RDX,0x30(%RSP) |
(235) 0x436bee MOV 0x40(%R13),%R12 |
(235) 0x436bf2 MOV %RAX,0x78(%RSP) |
(235) 0x436bf7 LEA -0x1(%R15),%EAX |
(235) 0x436bfb MOV %R10,0x38(%RSP) |
(235) 0x436c00 MOV %R12,0x50(%RSP) |
(235) 0x436c05 MOV %R11,0x40(%RSP) |
(235) 0x436c0a MOV %R9,0x58(%RSP) |
(235) 0x436c0f CMP $0x6,%EAX |
(235) 0x436c12 JBE 437050 |
(235) 0x436c18 MOVSXD 0x60(%RSP),%RAX |
(235) 0x436c1d LEA (%R10,%RAX,1),%R9 |
(235) 0x436c21 MOV 0x68(%RSP),%R10 |
(235) 0x436c26 LEA (%RDX,%RAX,1),%RDX |
(235) 0x436c2a LEA (%R12,%RDX,8),%R15 |
(235) 0x436c2e MOV 0x70(%RSP),%RDX |
(235) 0x436c33 LEA (%R11,%RAX,1),%R11 |
(235) 0x436c37 LEA (%R10,%R9,8),%R12 |
(235) 0x436c3b MOV 0x58(%RSP),%R9 |
(235) 0x436c40 MOV 0x78(%RSP),%R10 |
(235) 0x436c45 LEA (%RDX,%R11,8),%RDX |
(235) 0x436c49 ADD %R9,%RAX |
(235) 0x436c4c LEA (%R10,%RAX,8),%R11 |
(235) 0x436c50 MOV 0x64(%RSP),%R10D |
(235) 0x436c55 XOR %EAX,%EAX |
(235) 0x436c57 SHR $0x3,%R10D |
(235) 0x436c5b SAL $0x6,%R10 |
(235) 0x436c5f LEA -0x40(%R10),%R9 |
(235) 0x436c63 SHR $0x6,%R9 |
(235) 0x436c67 INC %R9 |
(235) 0x436c6a AND $0x3,%R9D |
(235) 0x436c6e JE 436d2f |
(235) 0x436c74 CMP $0x1,%R9 |
(235) 0x436c78 JE 436cee |
(235) 0x436c7a CMP $0x2,%R9 |
(235) 0x436c7e JE 436cb6 |
(235) 0x436c80 VBROADCASTSD (%R8),%ZMM0 |
(235) 0x436c86 MOV $0x40,%EAX |
(235) 0x436c8b VMOVUPD %ZMM0,(%R15) |
(235) 0x436c91 VBROADCASTSD (%RDI),%ZMM1 |
(235) 0x436c97 VMOVUPD %ZMM1,(%R12) |
(235) 0x436c9e VBROADCASTSD (%RSI),%ZMM2 |
(235) 0x436ca4 VMOVUPD %ZMM2,(%RDX) |
(235) 0x436caa VBROADCASTSD (%RCX),%ZMM3 |
(235) 0x436cb0 VMOVUPD %ZMM3,(%R11) |
(235) 0x436cb6 VBROADCASTSD (%R8),%ZMM4 |
(235) 0x436cbc VMOVUPD %ZMM4,(%R15,%RAX,1) |
(235) 0x436cc3 VBROADCASTSD (%RDI),%ZMM5 |
(235) 0x436cc9 VMOVUPD %ZMM5,(%R12,%RAX,1) |
(235) 0x436cd0 VBROADCASTSD (%RSI),%ZMM6 |
(235) 0x436cd6 VMOVUPD %ZMM6,(%RDX,%RAX,1) |
(235) 0x436cdd VBROADCASTSD (%RCX),%ZMM7 |
(235) 0x436ce3 VMOVUPD %ZMM7,(%R11,%RAX,1) |
(235) 0x436cea ADD $0x40,%RAX |
(235) 0x436cee VBROADCASTSD (%R8),%ZMM8 |
(235) 0x436cf4 VMOVUPD %ZMM8,(%R15,%RAX,1) |
(235) 0x436cfb VBROADCASTSD (%RDI),%ZMM9 |
(235) 0x436d01 VMOVUPD %ZMM9,(%R12,%RAX,1) |
(235) 0x436d08 VBROADCASTSD (%RSI),%ZMM10 |
(235) 0x436d0e VMOVUPD %ZMM10,(%RDX,%RAX,1) |
(235) 0x436d15 VBROADCASTSD (%RCX),%ZMM11 |
(235) 0x436d1b VMOVUPD %ZMM11,(%R11,%RAX,1) |
(235) 0x436d22 ADD $0x40,%RAX |
(235) 0x436d26 CMP %RAX,%R10 |
(235) 0x436d29 JE 436e1a |
(236) 0x436d2f VBROADCASTSD (%R8),%ZMM12 |
(236) 0x436d35 VMOVUPD %ZMM12,(%R15,%RAX,1) |
(236) 0x436d3c VBROADCASTSD (%RDI),%ZMM13 |
(236) 0x436d42 VMOVUPD %ZMM13,(%R12,%RAX,1) |
(236) 0x436d49 VBROADCASTSD (%RSI),%ZMM14 |
(236) 0x436d4f VMOVUPD %ZMM14,(%RDX,%RAX,1) |
(236) 0x436d56 VBROADCASTSD (%RCX),%ZMM15 |
(236) 0x436d5c VMOVUPD %ZMM15,(%R11,%RAX,1) |
(236) 0x436d63 VBROADCASTSD (%R8),%ZMM0 |
(236) 0x436d69 VMOVUPD %ZMM0,0x40(%R15,%RAX,1) |
(236) 0x436d71 VBROADCASTSD (%RDI),%ZMM1 |
(236) 0x436d77 VMOVUPD %ZMM1,0x40(%R12,%RAX,1) |
(236) 0x436d7f VBROADCASTSD (%RSI),%ZMM2 |
(236) 0x436d85 VMOVUPD %ZMM2,0x40(%RDX,%RAX,1) |
(236) 0x436d8d VBROADCASTSD (%RCX),%ZMM3 |
(236) 0x436d93 VMOVUPD %ZMM3,0x40(%R11,%RAX,1) |
(236) 0x436d9b VBROADCASTSD (%R8),%ZMM4 |
(236) 0x436da1 VMOVUPD %ZMM4,0x80(%R15,%RAX,1) |
(236) 0x436da9 VBROADCASTSD (%RDI),%ZMM5 |
(236) 0x436daf VMOVUPD %ZMM5,0x80(%R12,%RAX,1) |
(236) 0x436db7 VBROADCASTSD (%RSI),%ZMM6 |
(236) 0x436dbd VMOVUPD %ZMM6,0x80(%RDX,%RAX,1) |
(236) 0x436dc5 VBROADCASTSD (%RCX),%ZMM7 |
(236) 0x436dcb VMOVUPD %ZMM7,0x80(%R11,%RAX,1) |
(236) 0x436dd3 VBROADCASTSD (%R8),%ZMM8 |
(236) 0x436dd9 VMOVUPD %ZMM8,0xc0(%R15,%RAX,1) |
(236) 0x436de1 VBROADCASTSD (%RDI),%ZMM9 |
(236) 0x436de7 VMOVUPD %ZMM9,0xc0(%R12,%RAX,1) |
(236) 0x436def VBROADCASTSD (%RSI),%ZMM10 |
(236) 0x436df5 VMOVUPD %ZMM10,0xc0(%RDX,%RAX,1) |
(236) 0x436dfd VBROADCASTSD (%RCX),%ZMM11 |
(236) 0x436e03 VMOVUPD %ZMM11,0xc0(%R11,%RAX,1) |
(236) 0x436e0b ADD $0x100,%RAX |
(236) 0x436e11 CMP %RAX,%R10 |
(236) 0x436e14 JNE 436d2f |
(235) 0x436e1a MOV 0x64(%RSP),%R15D |
(235) 0x436e1f MOV 0x60(%RSP),%EDX |
(235) 0x436e23 MOV %R15D,%R12D |
(235) 0x436e26 AND $-0x8,%R12D |
(235) 0x436e2a ADD %R12D,%R14D |
(235) 0x436e2d LEA (%R12,%RDX,1),%R10D |
(235) 0x436e31 TEST $0x7,%R15B |
(235) 0x436e35 JE 43700a |
(235) 0x436e3b MOV 0x64(%RSP),%EDX |
(235) 0x436e3f SUB %R12D,%EDX |
(235) 0x436e42 LEA -0x1(%RDX),%R11D |
(235) 0x436e46 CMP $0x2,%R11D |
(235) 0x436e4a JBE 436ee2 |
(235) 0x436e50 MOVSXD 0x60(%RSP),%RAX |
(235) 0x436e55 MOV 0x30(%RSP),%R9 |
(235) 0x436e5a VBROADCASTSD (%R8),%YMM15 |
(235) 0x436e5f MOV 0x50(%RSP),%R15 |
(235) 0x436e64 LEA (%R9,%RAX,1),%R11 |
(235) 0x436e68 MOV 0x38(%RSP),%R9 |
(235) 0x436e6d VMOVSD (%RDI),%XMM12 |
(235) 0x436e71 ADD %R12,%R11 |
(235) 0x436e74 VMOVSD (%RSI),%XMM13 |
(235) 0x436e78 VMOVSD (%RCX),%XMM14 |
(235) 0x436e7c VMOVUPD %YMM15,(%R15,%R11,8) |
(235) 0x436e82 LEA (%R9,%RAX,1),%R11 |
(235) 0x436e86 MOV 0x68(%RSP),%R15 |
(235) 0x436e8b MOV 0x40(%RSP),%R9 |
(235) 0x436e90 VBROADCASTSD %XMM12,%YMM0 |
(235) 0x436e95 VBROADCASTSD %XMM13,%YMM1 |
(235) 0x436e9a VBROADCASTSD %XMM14,%YMM2 |
(235) 0x436e9f ADD %R12,%R11 |
(235) 0x436ea2 VMOVUPD %YMM0,(%R15,%R11,8) |
(235) 0x436ea8 LEA (%R9,%RAX,1),%R11 |
(235) 0x436eac MOV 0x58(%RSP),%R9 |
(235) 0x436eb1 MOV 0x70(%RSP),%R15 |
(235) 0x436eb6 ADD %R12,%R11 |
(235) 0x436eb9 ADD %R9,%RAX |
(235) 0x436ebc VMOVUPD %YMM1,(%R15,%R11,8) |
(235) 0x436ec2 ADD %R12,%RAX |
(235) 0x436ec5 MOV 0x78(%RSP),%R12 |
(235) 0x436eca VMOVUPD %YMM2,(%R12,%RAX,8) |
(235) 0x436ed0 TEST $0x3,%DL |
(235) 0x436ed3 JE 43700a |
(235) 0x436ed9 AND $-0x4,%EDX |
(235) 0x436edc ADD %EDX,%R14D |
(235) 0x436edf ADD %EDX,%R10D |
(235) 0x436ee2 MOV 0x30(%RSP),%R9 |
(235) 0x436ee7 VMOVSD (%R8),%XMM3 |
(235) 0x436eec MOVSXD %R10D,%RAX |
(235) 0x436eef MOV 0x50(%RSP),%R11 |
(235) 0x436ef4 MOV 0x38(%RSP),%R15 |
(235) 0x436ef9 LEA (%R9,%RAX,1),%RDX |
(235) 0x436efd VMOVSD %XMM3,(%R11,%RDX,8) |
(235) 0x436f03 MOV 0x68(%RSP),%RDX |
(235) 0x436f08 LEA (%R15,%RAX,1),%R12 |
(235) 0x436f0c MOV 0x40(%RSP),%R11 |
(235) 0x436f11 VMOVSD (%RDI),%XMM4 |
(235) 0x436f15 VMOVSD %XMM4,(%RDX,%R12,8) |
(235) 0x436f1b MOV 0x70(%RSP),%R12 |
(235) 0x436f20 LEA (%R11,%RAX,1),%RDX |
(235) 0x436f24 VMOVSD (%RSI),%XMM5 |
(235) 0x436f28 VMOVSD %XMM5,(%R12,%RDX,8) |
(235) 0x436f2e MOV 0x58(%RSP),%RDX |
(235) 0x436f33 MOV 0x78(%RSP),%R12 |
(235) 0x436f38 VMOVSD (%RCX),%XMM6 |
(235) 0x436f3c ADD %RDX,%RAX |
(235) 0x436f3f LEA 0x1(%R14),%EDX |
(235) 0x436f43 VMOVSD %XMM6,(%R12,%RAX,8) |
(235) 0x436f49 MOV 0x4c(%RSP),%R12D |
(235) 0x436f4e LEA 0x1(%R10),%EAX |
(235) 0x436f52 CMP %R12D,%EDX |
(235) 0x436f55 JAE 43700a |
(235) 0x436f5b VMOVSD (%R8),%XMM7 |
(235) 0x436f60 CLTQ |
(235) 0x436f62 MOV 0x50(%RSP),%R12 |
(235) 0x436f67 ADD $0x2,%R14D |
(235) 0x436f6b LEA (%RAX,%R9,1),%RDX |
(235) 0x436f6f ADD $0x2,%R10D |
(235) 0x436f73 VMOVSD %XMM7,(%R12,%RDX,8) |
(235) 0x436f79 MOV 0x68(%RSP),%R12 |
(235) 0x436f7e LEA (%RAX,%R15,1),%RDX |
(235) 0x436f82 VMOVSD (%RDI),%XMM8 |
(235) 0x436f86 VMOVSD %XMM8,(%R12,%RDX,8) |
(235) 0x436f8c MOV 0x70(%RSP),%R12 |
(235) 0x436f91 LEA (%RAX,%R11,1),%RDX |
(235) 0x436f95 VMOVSD (%RSI),%XMM9 |
(235) 0x436f99 VMOVSD %XMM9,(%R12,%RDX,8) |
(235) 0x436f9f MOV 0x58(%RSP),%RDX |
(235) 0x436fa4 MOV 0x78(%RSP),%R12 |
(235) 0x436fa9 VMOVSD (%RCX),%XMM10 |
(235) 0x436fad ADD %RDX,%RAX |
(235) 0x436fb0 VMOVSD %XMM10,(%R12,%RAX,8) |
(235) 0x436fb6 MOV 0x4c(%RSP),%EAX |
(235) 0x436fba CMP %EAX,%R14D |
(235) 0x436fbd JAE 43700a |
(235) 0x436fbf VMOVSD (%R8),%XMM11 |
(235) 0x436fc4 MOVSXD %R10D,%R14 |
(235) 0x436fc7 MOV 0x50(%RSP),%R8 |
(235) 0x436fcc ADD %R14,%R9 |
(235) 0x436fcf ADD %R14,%R15 |
(235) 0x436fd2 ADD %R14,%R11 |
(235) 0x436fd5 ADD %R14,%RDX |
(235) 0x436fd8 VMOVSD %XMM11,(%R8,%R9,8) |
(235) 0x436fde VMOVSD (%RDI),%XMM12 |
(235) 0x436fe2 MOV 0x68(%RSP),%RDI |
(235) 0x436fe7 VMOVSD %XMM12,(%RDI,%R15,8) |
(235) 0x436fed VMOVSD (%RSI),%XMM13 |
(235) 0x436ff1 MOV 0x70(%RSP),%RSI |
(235) 0x436ff6 VMOVSD %XMM13,(%RSI,%R11,8) |
(235) 0x436ffc VMOVSD (%RCX),%XMM14 |
(235) 0x437000 MOV 0x78(%RSP),%RCX |
(235) 0x437005 VMOVSD %XMM14,(%RCX,%RDX,8) |
(235) 0x43700a MOV 0x4c(%RSP),%R14D |
(235) 0x43700f INC %RBX |
(235) 0x437012 CMP %EBX,0x48(%RSP) |
(235) 0x437016 JLE 437038 |
(235) 0x437018 MOV 0x28(%RSP),%R12D |
(235) 0x43701d MOV 0x2c(%RSP),%R8D |
(235) 0x437022 MOVL $0,0x60(%RSP) |
(235) 0x43702a SUB %R14D,%R12D |
(235) 0x43702d JMP 436b60 |
0x437032 NOPW (%RAX,%RAX,1) |
0x437038 VZEROUPPER |
0x43703b LEA -0x28(%RBP),%RSP |
0x43703f POP %RBX |
0x437040 POP %R12 |
0x437042 POP %R13 |
0x437044 POP %R14 |
0x437046 POP %R15 |
0x437048 POP %RBP |
0x437049 RET |
0x43704a NOPW (%RAX,%RAX,1) |
(235) 0x437050 MOV 0x60(%RSP),%R10D |
(235) 0x437055 XOR %R12D,%R12D |
(235) 0x437058 JMP 436e3b |
0x43705d INC %R12D |
0x437060 XOR %EDX,%EDX |
0x437062 JMP 436b02 |
0x437067 NOPW (%RAX,%RAX,1) |
Path / |
Source file and lines | generate_chunk.cpp:74-80 |
Module | exec |
nb instructions | 67 |
nb uops | 76 |
loop length | 241 |
used x86 registers | 15 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 9 |
micro-operation queue | 12.67 cycles |
front end | 12.67 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 3.70 | 8.00 | 5.00 | 5.00 | 8.00 | 3.87 | 3.70 | 8.00 | 8.00 | 8.00 | 3.73 | 5.00 |
cycles | 3.70 | 10.13 | 5.00 | 5.00 | 8.00 | 3.87 | 3.70 | 8.00 | 8.00 | 8.00 | 3.73 | 5.00 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 12.20-12.27 |
Stall cycles | 0.00 |
Front-end | 12.67 |
Dispatch | 10.13 |
DIV/SQRT | 12.00 |
Overall L1 | 12.67 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 20% |
all | 9% |
load | 10% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 10% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD $-0x80,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x2c(%RDI),%R14D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RDI),%R15D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R14D,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15D,0x2c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %R14D,%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 43703b <_Z14generate_chunkiR16global_variables._omp_fn.0+0x59b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
TEST %R15D,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 43703b <_Z14generate_chunkiR16global_variables._omp_fn.0+0x59b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 404650 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 404540 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R14D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %R15D,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 43705d <_Z14generate_chunkiR16global_variables._omp_fn.0+0x5bd> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %R12D,%ESI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%RSI,%RDX,1),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%R12,%R14,1),%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDI,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDI,%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 43703b <_Z14generate_chunkiR16global_variables._omp_fn.0+0x59b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x2c(%RSP),%R8D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R14D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x8(%RBX),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RBX),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%RBX),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIV %R8D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV 0x18(%RBX),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RBX),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R9,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0x10(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15,0x8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EDX,0x60(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %EAX,%RBX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 436b02 <_Z14generate_chunkiR16global_variables._omp_fn.0+0x62> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | generate_chunk.cpp:74-80 |
Module | exec |
nb instructions | 67 |
nb uops | 76 |
loop length | 241 |
used x86 registers | 15 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 9 |
micro-operation queue | 12.67 cycles |
front end | 12.67 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 3.70 | 8.00 | 5.00 | 5.00 | 8.00 | 3.87 | 3.70 | 8.00 | 8.00 | 8.00 | 3.73 | 5.00 |
cycles | 3.70 | 10.13 | 5.00 | 5.00 | 8.00 | 3.87 | 3.70 | 8.00 | 8.00 | 8.00 | 3.73 | 5.00 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 12.20-12.27 |
Stall cycles | 0.00 |
Front-end | 12.67 |
Dispatch | 10.13 |
DIV/SQRT | 12.00 |
Overall L1 | 12.67 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 20% |
all | 9% |
load | 10% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 10% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD $-0x80,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x2c(%RDI),%R14D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RDI),%R15D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R14D,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15D,0x2c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %R14D,%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 43703b <_Z14generate_chunkiR16global_variables._omp_fn.0+0x59b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
TEST %R15D,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 43703b <_Z14generate_chunkiR16global_variables._omp_fn.0+0x59b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 404650 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 404540 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R14D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %R15D,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 43705d <_Z14generate_chunkiR16global_variables._omp_fn.0+0x5bd> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %R12D,%ESI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%RSI,%RDX,1),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%R12,%R14,1),%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDI,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDI,%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 43703b <_Z14generate_chunkiR16global_variables._omp_fn.0+0x59b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x2c(%RSP),%R8D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R14D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x8(%RBX),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RBX),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%RBX),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIV %R8D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV 0x18(%RBX),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RBX),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R9,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0x10(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15,0x8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EDX,0x60(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %EAX,%RBX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 436b02 <_Z14generate_chunkiR16global_variables._omp_fn.0+0x62> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼_Z14generate_chunkiR16global_variables._omp_fn.0– | 0.03 | 0.01 |
▼Loop 235 - generate_chunk.cpp:74-80 - exec– | 0 | 0 |
○Loop 236 - generate_chunk.cpp:77-80 - exec | 0.03 | 0.01 |