Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ... | Module: exec | Source: advec_mom.cpp:157-160 [...] | Coverage: 0.9% |
---|
Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ... | Module: exec | Source: advec_mom.cpp:157-160 [...] | Coverage: 0.9% |
---|
/scratch_na/users/xoserete/qaas_runs/171-415-4969/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp: 157 - 160 |
-------------------------------------------------------------------------------- |
157: #pragma omp parallel for simd collapse(2) |
158: for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) { |
159: for (int i = (x_min + 1); i < (x_max + 1 + 2); i++) { |
160: node_flux(i, j) = 0.25 * (mass_flux_y(i - 1, j + 0) + mass_flux_y(i, j) + mass_flux_y(i - 1, j + 1) + mass_flux_y(i + 0, j + 1)); |
/scratch_na/users/xoserete/qaas_runs/171-415-4969/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69 |
-------------------------------------------------------------------------------- |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
0x42c4c0 PUSH %RBP |
0x42c4c1 MOV %RSP,%RBP |
0x42c4c4 PUSH %R15 |
0x42c4c6 PUSH %R14 |
0x42c4c8 PUSH %R13 |
0x42c4ca PUSH %R12 |
0x42c4cc PUSH %RBX |
0x42c4cd AND $-0x40,%RSP |
0x42c4d1 SUB $0x40,%RSP |
0x42c4d5 MOV 0x18(%RDI),%EAX |
0x42c4d8 MOV 0x1c(%RDI),%EDX |
0x42c4db MOV 0x10(%RDI),%ESI |
0x42c4de MOV 0x14(%RDI),%EBX |
0x42c4e1 ADD $0x4,%EDX |
0x42c4e4 LEA -0x1(%RAX),%R15D |
0x42c4e8 LEA 0x1(%RSI),%ECX |
0x42c4eb MOV %EDX,0x20(%RSP) |
0x42c4ef MOV %ECX,0x1c(%RSP) |
0x42c4f3 CMP %EDX,%R15D |
0x42c4f6 JGE 42c95b |
0x42c4fc LEA 0x3(%RBX),%R13D |
0x42c500 MOV %EDX,%EBX |
0x42c502 SUB %R15D,%EBX |
0x42c505 CMP %R13D,%ECX |
0x42c508 JGE 42c95b |
0x42c50e MOV %RDI,%R14 |
0x42c511 MOV %R13D,%EDI |
0x42c514 SUB %ECX,%EDI |
0x42c516 MOV %EDI,0x24(%RSP) |
0x42c51a CALL 4046c0 <omp_get_num_threads@plt> |
0x42c51f MOV %EAX,%R12D |
0x42c522 CALL 4045b0 <omp_get_thread_num@plt> |
0x42c527 MOV 0x24(%RSP),%R9D |
0x42c52c XOR %EDX,%EDX |
0x42c52e MOV %EAX,%R8D |
0x42c531 IMUL %R9D,%EBX |
0x42c535 MOV %EBX,%EAX |
0x42c537 DIV %R12D |
0x42c53a MOV %EAX,%EDI |
0x42c53c CMP %EDX,%R8D |
0x42c53f JB 42c97b |
0x42c545 IMUL %EDI,%R8D |
0x42c549 LEA (%R8,%RDX,1),%R12D |
0x42c54d LEA (%RDI,%R12,1),%R10D |
0x42c551 MOV %R10D,0x18(%RSP) |
0x42c556 CMP %R10D,%R12D |
0x42c559 JAE 42c95b |
0x42c55f MOV %R12D,%EAX |
0x42c562 XOR %EDX,%EDX |
0x42c564 MOV 0x1c(%RSP),%R11D |
0x42c569 MOV 0x8(%R14),%RCX |
0x42c56d DIVL 0x24(%RSP) |
0x42c571 VMOVSD 0x3634f(%RIP),%XMM3 |
0x42c579 MOV %RCX,0x8(%RSP) |
0x42c57e VBROADCASTSD %XMM3,%YMM4 |
0x42c583 VBROADCASTSD %XMM3,%ZMM2 |
0x42c589 ADD %R15D,%EAX |
0x42c58c MOV (%R14),%R15 |
0x42c58f LEA (%RDX,%R11,1),%ESI |
0x42c593 MOV %R13D,%EDX |
0x42c596 CLTQ |
0x42c598 MOV %ESI,0x3c(%RSP) |
0x42c59c SUB %ESI,%EDX |
0x42c59e MOV %R15,0x10(%RSP) |
0x42c5a3 MOV %RAX,0x30(%RSP) |
0x42c5a8 NOPL (%RAX,%RAX,1) |
(141) 0x42c5b0 CMP %EDX,%EDI |
(141) 0x42c5b2 CMOVBE %EDI,%EDX |
(141) 0x42c5b5 LEA (%R12,%RDX,1),%R13D |
(141) 0x42c5b9 MOV %R13D,0x38(%RSP) |
(141) 0x42c5be CMP %R13D,%R12D |
(141) 0x42c5c1 JAE 42c924 |
(141) 0x42c5c7 MOV 0x10(%RSP),%RBX |
(141) 0x42c5cc MOV 0x30(%RSP),%R9 |
(141) 0x42c5d1 LEA -0x1(%RDX),%EDI |
(141) 0x42c5d4 MOV 0x8(%RSP),%R14 |
(141) 0x42c5d9 MOV (%RBX),%R8 |
(141) 0x42c5dc MOV %R9,%R10 |
(141) 0x42c5df MOV 0x10(%RBX),%RCX |
(141) 0x42c5e3 IMUL (%R14),%R9 |
(141) 0x42c5e7 MOV 0x10(%R14),%R15 |
(141) 0x42c5eb IMUL %R8,%R10 |
(141) 0x42c5ef MOV %R9,0x28(%RSP) |
(141) 0x42c5f4 ADD %R10,%R8 |
(141) 0x42c5f7 CMP $0x6,%EDI |
(141) 0x42c5fa JBE 42c970 |
(141) 0x42c600 MOVSXD 0x3c(%RSP),%R11 |
(141) 0x42c605 XOR %EAX,%EAX |
(141) 0x42c607 LEA (%R10,%R11,1),%RSI |
(141) 0x42c60b LEA (%R8,%R11,1),%RDI |
(141) 0x42c60f ADD %R9,%R11 |
(141) 0x42c612 LEA (%R15,%R11,8),%RBX |
(141) 0x42c616 SAL $0x3,%RSI |
(141) 0x42c61a MOV %EDX,%R11D |
(141) 0x42c61d SAL $0x3,%RDI |
(141) 0x42c621 SHR $0x3,%R11D |
(141) 0x42c625 LEA -0x8(%RCX,%RSI,1),%R13 |
(141) 0x42c62a LEA -0x8(%RCX,%RDI,1),%R14 |
(141) 0x42c62f ADD %RCX,%RSI |
(141) 0x42c632 SAL $0x6,%R11 |
(141) 0x42c636 ADD %RCX,%RDI |
(141) 0x42c639 LEA -0x40(%R11),%R9 |
(141) 0x42c63d SHR $0x6,%R9 |
(141) 0x42c641 INC %R9 |
(141) 0x42c644 AND $0x3,%R9D |
(141) 0x42c648 JE 42c6fb |
(141) 0x42c64e CMP $0x1,%R9 |
(141) 0x42c652 JE 42c6be |
(141) 0x42c654 CMP $0x2,%R9 |
(141) 0x42c658 JE 42c68a |
(141) 0x42c65a VMOVUPD (%RDI),%ZMM7 |
(141) 0x42c660 VMOVUPD (%RSI),%ZMM1 |
(141) 0x42c666 MOV $0x40,%EAX |
(141) 0x42c66b VADDPD (%R14),%ZMM7,%ZMM0 |
(141) 0x42c671 VADDPD (%R13),%ZMM1,%ZMM5 |
(141) 0x42c678 VADDPD %ZMM5,%ZMM0,%ZMM6 |
(141) 0x42c67e VMULPD %ZMM2,%ZMM6,%ZMM8 |
(141) 0x42c684 VMOVUPD %ZMM8,(%RBX) |
(141) 0x42c68a VMOVUPD (%RDI,%RAX,1),%ZMM9 |
(141) 0x42c691 VMOVUPD (%RSI,%RAX,1),%ZMM11 |
(141) 0x42c698 VADDPD (%R14,%RAX,1),%ZMM9,%ZMM10 |
(141) 0x42c69f VADDPD (%R13,%RAX,1),%ZMM11,%ZMM12 |
(141) 0x42c6a7 VADDPD %ZMM12,%ZMM10,%ZMM13 |
(141) 0x42c6ad VMULPD %ZMM2,%ZMM13,%ZMM14 |
(141) 0x42c6b3 VMOVUPD %ZMM14,(%RBX,%RAX,1) |
(141) 0x42c6ba ADD $0x40,%RAX |
(141) 0x42c6be VMOVUPD (%RDI,%RAX,1),%ZMM15 |
(141) 0x42c6c5 VMOVUPD (%RSI,%RAX,1),%ZMM7 |
(141) 0x42c6cc VADDPD (%R14,%RAX,1),%ZMM15,%ZMM0 |
(141) 0x42c6d3 VADDPD (%R13,%RAX,1),%ZMM7,%ZMM1 |
(141) 0x42c6db VADDPD %ZMM1,%ZMM0,%ZMM5 |
(141) 0x42c6e1 VMULPD %ZMM2,%ZMM5,%ZMM6 |
(141) 0x42c6e7 VMOVUPD %ZMM6,(%RBX,%RAX,1) |
(141) 0x42c6ee ADD $0x40,%RAX |
(141) 0x42c6f2 CMP %R11,%RAX |
(141) 0x42c6f5 JE 42c7d6 |
(142) 0x42c6fb VMOVUPD (%RDI,%RAX,1),%ZMM8 |
(142) 0x42c702 VMOVUPD (%RSI,%RAX,1),%ZMM10 |
(142) 0x42c709 VADDPD (%R14,%RAX,1),%ZMM8,%ZMM9 |
(142) 0x42c710 VADDPD (%R13,%RAX,1),%ZMM10,%ZMM11 |
(142) 0x42c718 VADDPD %ZMM11,%ZMM9,%ZMM12 |
(142) 0x42c71e VMULPD %ZMM2,%ZMM12,%ZMM13 |
(142) 0x42c724 VMOVUPD %ZMM13,(%RBX,%RAX,1) |
(142) 0x42c72b VMOVUPD 0x40(%RDI,%RAX,1),%ZMM14 |
(142) 0x42c733 VMOVUPD 0x40(%RSI,%RAX,1),%ZMM0 |
(142) 0x42c73b VADDPD 0x40(%R14,%RAX,1),%ZMM14,%ZMM15 |
(142) 0x42c743 VADDPD 0x40(%R13,%RAX,1),%ZMM0,%ZMM7 |
(142) 0x42c74b VADDPD %ZMM7,%ZMM15,%ZMM1 |
(142) 0x42c751 VMULPD %ZMM2,%ZMM1,%ZMM5 |
(142) 0x42c757 VMOVUPD %ZMM5,0x40(%RBX,%RAX,1) |
(142) 0x42c75f VMOVUPD 0x80(%RDI,%RAX,1),%ZMM6 |
(142) 0x42c767 VMOVUPD 0x80(%RSI,%RAX,1),%ZMM9 |
(142) 0x42c76f VADDPD 0x80(%R14,%RAX,1),%ZMM6,%ZMM8 |
(142) 0x42c777 VADDPD 0x80(%R13,%RAX,1),%ZMM9,%ZMM10 |
(142) 0x42c77f VADDPD %ZMM10,%ZMM8,%ZMM11 |
(142) 0x42c785 VMULPD %ZMM2,%ZMM11,%ZMM12 |
(142) 0x42c78b VMOVUPD %ZMM12,0x80(%RBX,%RAX,1) |
(142) 0x42c793 VMOVUPD 0xc0(%RDI,%RAX,1),%ZMM13 |
(142) 0x42c79b VMOVUPD 0xc0(%RSI,%RAX,1),%ZMM15 |
(142) 0x42c7a3 VADDPD 0xc0(%R14,%RAX,1),%ZMM13,%ZMM14 |
(142) 0x42c7ab VADDPD 0xc0(%R13,%RAX,1),%ZMM15,%ZMM0 |
(142) 0x42c7b3 VADDPD %ZMM0,%ZMM14,%ZMM7 |
(142) 0x42c7b9 VMULPD %ZMM2,%ZMM7,%ZMM1 |
(142) 0x42c7bf VMOVUPD %ZMM1,0xc0(%RBX,%RAX,1) |
(142) 0x42c7c7 ADD $0x100,%RAX |
(142) 0x42c7cd CMP %R11,%RAX |
(142) 0x42c7d0 JNE 42c6fb |
(141) 0x42c7d6 MOV 0x3c(%RSP),%ESI |
(141) 0x42c7da MOV %EDX,%EAX |
(141) 0x42c7dc AND $-0x8,%EAX |
(141) 0x42c7df ADD %EAX,%R12D |
(141) 0x42c7e2 ADD %EAX,%ESI |
(141) 0x42c7e4 TEST $0x7,%DL |
(141) 0x42c7e7 JE 42c91f |
(141) 0x42c7ed SUB %EAX,%EDX |
(141) 0x42c7ef LEA -0x1(%RDX),%R13D |
(141) 0x42c7f3 CMP $0x2,%R13D |
(141) 0x42c7f7 JBE 42c84d |
(141) 0x42c7f9 MOVSXD 0x3c(%RSP),%R14 |
(141) 0x42c7fe MOV 0x28(%RSP),%R11 |
(141) 0x42c803 LEA (%R10,%R14,1),%RDI |
(141) 0x42c807 LEA (%R8,%R14,1),%RBX |
(141) 0x42c80b ADD %RAX,%RDI |
(141) 0x42c80e ADD %RAX,%RBX |
(141) 0x42c811 ADD %R11,%RAX |
(141) 0x42c814 VMOVUPD -0x8(%RCX,%RDI,8),%YMM5 |
(141) 0x42c81a VMOVUPD (%RCX,%RBX,8),%YMM8 |
(141) 0x42c81f ADD %R14,%RAX |
(141) 0x42c822 VADDPD -0x8(%RCX,%RBX,8),%YMM5,%YMM6 |
(141) 0x42c828 VADDPD (%RCX,%RDI,8),%YMM8,%YMM9 |
(141) 0x42c82d VADDPD %YMM9,%YMM6,%YMM10 |
(141) 0x42c832 VMULPD %YMM4,%YMM10,%YMM11 |
(141) 0x42c836 VMOVUPD %YMM11,(%R15,%RAX,8) |
(141) 0x42c83c TEST $0x3,%DL |
(141) 0x42c83f JE 42c91f |
(141) 0x42c845 AND $-0x4,%EDX |
(141) 0x42c848 ADD %EDX,%R12D |
(141) 0x42c84b ADD %EDX,%ESI |
(141) 0x42c84d MOVSXD %ESI,%RDX |
(141) 0x42c850 LEA -0x1(%RSI),%EAX |
(141) 0x42c853 MOV 0x28(%RSP),%RBX |
(141) 0x42c858 LEA (%RDX,%R10,1),%R9 |
(141) 0x42c85c CLTQ |
(141) 0x42c85e LEA (%R8,%RDX,1),%R14 |
(141) 0x42c862 LEA (%RCX,%R9,8),%R13 |
(141) 0x42c866 LEA (%R10,%RAX,1),%R11 |
(141) 0x42c86a ADD %R8,%RAX |
(141) 0x42c86d ADD %RBX,%RDX |
(141) 0x42c870 VMOVSD (%RCX,%R11,8),%XMM12 |
(141) 0x42c876 VMOVSD (%R13),%XMM14 |
(141) 0x42c87c LEA (%RCX,%R14,8),%RDI |
(141) 0x42c880 MOV 0x38(%RSP),%R9D |
(141) 0x42c885 VADDSD (%RCX,%RAX,8),%XMM12,%XMM13 |
(141) 0x42c88a VADDSD (%RDI),%XMM14,%XMM15 |
(141) 0x42c88e LEA 0x1(%RSI),%EAX |
(141) 0x42c891 VADDSD %XMM15,%XMM13,%XMM0 |
(141) 0x42c896 VMULSD %XMM3,%XMM0,%XMM7 |
(141) 0x42c89a VMOVSD %XMM7,(%R15,%RDX,8) |
(141) 0x42c8a0 LEA 0x1(%R12),%EDX |
(141) 0x42c8a5 CMP %R9D,%EDX |
(141) 0x42c8a8 JAE 42c91f |
(141) 0x42c8aa CLTQ |
(141) 0x42c8ac VMOVSD (%RDI),%XMM1 |
(141) 0x42c8b0 ADD $0x2,%R12D |
(141) 0x42c8b4 ADD $0x2,%ESI |
(141) 0x42c8b7 LEA (%R10,%RAX,1),%R14 |
(141) 0x42c8bb LEA (%R8,%RAX,1),%RDX |
(141) 0x42c8bf ADD %RBX,%RAX |
(141) 0x42c8c2 LEA (%RCX,%R14,8),%R11 |
(141) 0x42c8c6 LEA (%RCX,%RDX,8),%R14 |
(141) 0x42c8ca VMOVSD (%R14),%XMM6 |
(141) 0x42c8cf VADDSD (%R13),%XMM1,%XMM5 |
(141) 0x42c8d5 VADDSD (%R11),%XMM6,%XMM8 |
(141) 0x42c8da VADDSD %XMM8,%XMM5,%XMM9 |
(141) 0x42c8df VMULSD %XMM3,%XMM9,%XMM10 |
(141) 0x42c8e3 VMOVSD %XMM10,(%R15,%RAX,8) |
(141) 0x42c8e9 CMP %R9D,%R12D |
(141) 0x42c8ec JAE 42c91f |
(141) 0x42c8ee MOVSXD %ESI,%R12 |
(141) 0x42c8f1 ADD %R12,%RBX |
(141) 0x42c8f4 ADD %R12,%R10 |
(141) 0x42c8f7 ADD %R8,%R12 |
(141) 0x42c8fa VMOVSD (%RCX,%R10,8),%XMM11 |
(141) 0x42c900 VMOVSD (%RCX,%R12,8),%XMM13 |
(141) 0x42c906 VADDSD (%R11),%XMM11,%XMM12 |
(141) 0x42c90b VADDSD (%R14),%XMM13,%XMM14 |
(141) 0x42c910 VADDSD %XMM14,%XMM12,%XMM15 |
(141) 0x42c915 VMULSD %XMM3,%XMM15,%XMM0 |
(141) 0x42c919 VMOVSD %XMM0,(%R15,%RBX,8) |
(141) 0x42c91f MOV 0x38(%RSP),%R12D |
(141) 0x42c924 INCQ 0x30(%RSP) |
(141) 0x42c929 MOV 0x30(%RSP),%RCX |
(141) 0x42c92e ADD $0,%ECX |
(141) 0x42c931 CMP %ECX,0x20(%RSP) |
(141) 0x42c935 JLE 42c958 |
(141) 0x42c937 MOV 0x18(%RSP),%EDI |
(141) 0x42c93b MOV 0x1c(%RSP),%R8D |
(141) 0x42c940 MOV 0x24(%RSP),%EDX |
(141) 0x42c944 MOV %R8D,0x3c(%RSP) |
(141) 0x42c949 SUB %R12D,%EDI |
(141) 0x42c94c JMP 42c5b0 |
0x42c951 NOPL (%RAX) |
0x42c958 VZEROUPPER |
0x42c95b LEA -0x28(%RBP),%RSP |
0x42c95f POP %RBX |
0x42c960 POP %R12 |
0x42c962 POP %R13 |
0x42c964 POP %R14 |
0x42c966 POP %R15 |
0x42c968 POP %RBP |
0x42c969 RET |
0x42c96a NOPW (%RAX,%RAX,1) |
(141) 0x42c970 MOV 0x3c(%RSP),%ESI |
(141) 0x42c974 XOR %EAX,%EAX |
(141) 0x42c976 JMP 42c7ed |
0x42c97b INC %EDI |
0x42c97d XOR %EDX,%EDX |
0x42c97f JMP 42c545 |
0x42c984 NOPW %CS:(%RAX,%RAX,1) |
0x42c98f NOP |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
○98.09 | gomp_thread_start | team.c:130 | libgomp.so.1.0.0 |
○1.85 | GOMP_parallel | libgomp.h:985 | libgomp.so.1.0.0 |
Path / |
Source file and lines | advec_mom.cpp:157-160 |
Module | exec |
nb instructions | 82 |
nb uops | 92 |
loop length | 292 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 1 |
used ymm registers | 1 |
used zmm registers | 1 |
nb stack references | 9 |
micro-operation queue | 15.33 cycles |
front end | 15.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.30 | 8.00 | 5.67 | 5.67 | 8.00 | 6.20 | 6.30 | 8.00 | 8.00 | 8.00 | 6.20 | 5.67 |
cycles | 6.30 | 11.90 | 5.67 | 5.67 | 8.00 | 6.20 | 6.30 | 8.00 | 8.00 | 8.00 | 6.20 | 5.67 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.57-14.66 |
Stall cycles | 0.00 |
Front-end | 15.33 |
Dispatch | 11.90 |
DIV/SQRT | 12.00 |
Overall L1 | 15.33 |
all | 5% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 12% |
all | 9% |
load | 9% |
store | 8% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 9% |
all | 12% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
all | 9% |
load | 10% |
store | 8% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 10% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0x40,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x18(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x1c(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x14(%RDI),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x4,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA -0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA 0x1(%RSI),%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ECX,0x1c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 42c95b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.8+0x49b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA 0x3(%RBX),%R13D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R13D,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 42c95b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.8+0x49b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R13D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %ECX,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EDI,0x24(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x24(%RSP),%R9D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %R9D,%EBX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %EBX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 42c97b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.8+0x4bb> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %EDI,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RDI,%R12,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R10D,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R10D,%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 42c95b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.8+0x49b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R12D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x1c(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%R14),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x24(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
VMOVSD 0x3634f(%RIP),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VBROADCASTSD %XMM3,%YMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VBROADCASTSD %XMM3,%ZMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %R15D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV (%R14),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%RDX,%R11,1),%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R13D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CLTQ | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
MOV %ESI,0x3c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %ESI,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R15,0x10(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 42c545 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.8+0x85> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | advec_mom.cpp:157-160 |
Module | exec |
nb instructions | 82 |
nb uops | 92 |
loop length | 292 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 1 |
used ymm registers | 1 |
used zmm registers | 1 |
nb stack references | 9 |
micro-operation queue | 15.33 cycles |
front end | 15.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.30 | 8.00 | 5.67 | 5.67 | 8.00 | 6.20 | 6.30 | 8.00 | 8.00 | 8.00 | 6.20 | 5.67 |
cycles | 6.30 | 11.90 | 5.67 | 5.67 | 8.00 | 6.20 | 6.30 | 8.00 | 8.00 | 8.00 | 6.20 | 5.67 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.57-14.66 |
Stall cycles | 0.00 |
Front-end | 15.33 |
Dispatch | 11.90 |
DIV/SQRT | 12.00 |
Overall L1 | 15.33 |
all | 5% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 12% |
all | 9% |
load | 9% |
store | 8% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 9% |
all | 12% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
all | 9% |
load | 10% |
store | 8% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 10% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0x40,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x18(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x1c(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x14(%RDI),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x4,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA -0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA 0x1(%RSI),%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ECX,0x1c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 42c95b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.8+0x49b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA 0x3(%RBX),%R13D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R13D,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 42c95b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.8+0x49b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R13D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %ECX,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EDI,0x24(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x24(%RSP),%R9D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %R9D,%EBX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %EBX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 42c97b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.8+0x4bb> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %EDI,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RDI,%R12,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R10D,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R10D,%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 42c95b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.8+0x49b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R12D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x1c(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%R14),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x24(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
VMOVSD 0x3634f(%RIP),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VBROADCASTSD %XMM3,%YMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VBROADCASTSD %XMM3,%ZMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %R15D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV (%R14),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%RDX,%R11,1),%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R13D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CLTQ | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
MOV %ESI,0x3c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %ESI,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R15,0x10(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 42c545 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.8+0x85> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D | 0.9 | 0.3 |
▼Loop 141 - advec_mom.cpp:160-160 - exec– | 0.01 | 0 |
○Loop 142 - advec_mom.cpp:160-160 - exec | 0.89 | 0.29 |