Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ... | Module: exec | Source: advec_cell.cpp:54-58 [...] | Coverage: 1.09% |
---|
Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ... | Module: exec | Source: advec_cell.cpp:54-58 [...] | Coverage: 1.09% |
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/scratch_na/users/xoserete/qaas_runs/171-415-4969/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp: 54 - 58 |
-------------------------------------------------------------------------------- |
54: #pragma omp parallel for simd collapse(2) |
55: for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) { |
56: for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) { |
57: pre_vol(i, j) = volume(i, j) + vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j); |
58: post_vol(i, j) = volume(i, j); |
/scratch_na/users/xoserete/qaas_runs/171-415-4969/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69 |
-------------------------------------------------------------------------------- |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
0x4256f0 PUSH %RBP |
0x4256f1 MOV %RSP,%RBP |
0x4256f4 PUSH %R15 |
0x4256f6 PUSH %R14 |
0x4256f8 PUSH %R13 |
0x4256fa PUSH %R12 |
0x4256fc PUSH %RBX |
0x4256fd AND $-0x40,%RSP |
0x425701 ADD $-0x80,%RSP |
0x425705 MOV 0x28(%RDI),%EAX |
0x425708 MOV 0x2c(%RDI),%ECX |
0x42570b MOV 0x20(%RDI),%ESI |
0x42570e MOV 0x24(%RDI),%EDX |
0x425711 ADD $0x4,%ECX |
0x425714 LEA -0x1(%RAX),%R15D |
0x425718 DEC %ESI |
0x42571a MOV %ECX,0x48(%RSP) |
0x42571e MOV %ESI,0x44(%RSP) |
0x425722 CMP %ECX,%R15D |
0x425725 JGE 425bd3 |
0x42572b MOV %ECX,%EBX |
0x42572d LEA 0x4(%RDX),%R14D |
0x425731 SUB %R15D,%EBX |
0x425734 CMP %R14D,%ESI |
0x425737 JGE 425bd3 |
0x42573d MOV %RDI,%R13 |
0x425740 MOV %R14D,%EDI |
0x425743 SUB %ESI,%EDI |
0x425745 MOV %EDI,0x4c(%RSP) |
0x425749 CALL 4046c0 <omp_get_num_threads@plt> |
0x42574e MOV %EAX,%R12D |
0x425751 CALL 4045b0 <omp_get_thread_num@plt> |
0x425756 XOR %EDX,%EDX |
0x425758 MOV %EAX,%R8D |
0x42575b MOV 0x4c(%RSP),%EAX |
0x42575f IMUL %EBX,%EAX |
0x425762 DIV %R12D |
0x425765 MOV %EAX,%ECX |
0x425767 CMP %EDX,%R8D |
0x42576a JB 425bf3 |
0x425770 IMUL %ECX,%R8D |
0x425774 LEA (%R8,%RDX,1),%R11D |
0x425778 LEA (%RCX,%R11,1),%R9D |
0x42577c MOV %R9D,0x40(%RSP) |
0x425781 CMP %R9D,%R11D |
0x425784 JAE 425bd3 |
0x42578a MOV %R11D,%EAX |
0x42578d XOR %EDX,%EDX |
0x42578f MOV 0x44(%RSP),%R10D |
0x425794 MOV 0x8(%R13),%RSI |
0x425798 DIVL 0x4c(%RSP) |
0x42579c MOV 0x18(%R13),%RBX |
0x4257a0 MOV %RSI,0x30(%RSP) |
0x4257a5 MOV %RBX,0x20(%RSP) |
0x4257aa ADD %EDX,%R10D |
0x4257ad ADD %R15D,%EAX |
0x4257b0 MOV %R14D,%EDX |
0x4257b3 MOV (%R13),%R15 |
0x4257b7 MOV 0x10(%R13),%R14 |
0x4257bb MOV %R10D,0x74(%RSP) |
0x4257c0 SUB %R10D,%EDX |
0x4257c3 MOVSXD %EAX,%R12 |
0x4257c6 MOV %R15,0x38(%RSP) |
0x4257cb MOV %R14,0x28(%RSP) |
(107) 0x4257d0 CMP %EDX,%ECX |
(107) 0x4257d2 CMOVBE %ECX,%EDX |
(107) 0x4257d5 LEA (%R11,%RDX,1),%ECX |
(107) 0x4257d9 MOV %ECX,0x70(%RSP) |
(107) 0x4257dd CMP %ECX,%R11D |
(107) 0x4257e0 JAE 425ba2 |
(107) 0x4257e6 MOV 0x38(%RSP),%R13 |
(107) 0x4257eb MOV 0x28(%RSP),%R9 |
(107) 0x4257f0 MOV 0x20(%RSP),%RAX |
(107) 0x4257f5 MOV 0x30(%RSP),%RDI |
(107) 0x4257fa MOV (%R13),%RBX |
(107) 0x4257fe MOV 0x10(%R9),%R8 |
(107) 0x425802 MOV (%R9),%R10 |
(107) 0x425805 MOV (%RAX),%R9 |
(107) 0x425808 IMUL %R12,%RBX |
(107) 0x42580c MOV (%RDI),%R14 |
(107) 0x42580f MOV 0x10(%RAX),%RCX |
(107) 0x425813 MOV %R8,0x60(%RSP) |
(107) 0x425818 IMUL %R12,%R10 |
(107) 0x42581c MOV 0x10(%R13),%R15 |
(107) 0x425820 LEA -0x1(%RDX),%R13D |
(107) 0x425824 MOV 0x10(%RDI),%RSI |
(107) 0x425828 IMUL %R12,%R9 |
(107) 0x42582c MOV %RCX,0x78(%RSP) |
(107) 0x425831 MOV %RBX,0x50(%RSP) |
(107) 0x425836 IMUL %R12,%R14 |
(107) 0x42583a MOV %R10,0x58(%RSP) |
(107) 0x42583f MOV %R9,0x68(%RSP) |
(107) 0x425844 CMP $0x6,%R13D |
(107) 0x425848 JBE 425be8 |
(107) 0x42584e MOVSXD 0x74(%RSP),%RAX |
(107) 0x425853 LEA (%R10,%RAX,1),%R10 |
(107) 0x425857 LEA (%RBX,%RAX,1),%RBX |
(107) 0x42585b LEA (%R8,%R10,8),%R10 |
(107) 0x42585f MOV 0x78(%RSP),%R8 |
(107) 0x425864 LEA 0x1(%R14,%RAX,1),%RDI |
(107) 0x425869 ADD %R9,%RAX |
(107) 0x42586c SAL $0x3,%RDI |
(107) 0x425870 LEA (%R15,%RBX,8),%RCX |
(107) 0x425874 LEA (%R8,%RAX,8),%R9 |
(107) 0x425878 MOV %EDX,%R8D |
(107) 0x42587b LEA (%RSI,%RDI,1),%R13 |
(107) 0x42587f XOR %EAX,%EAX |
(107) 0x425881 SHR $0x3,%R8D |
(107) 0x425885 LEA -0x8(%RSI,%RDI,1),%RBX |
(107) 0x42588a SAL $0x6,%R8 |
(107) 0x42588e LEA -0x40(%R8),%RDI |
(107) 0x425892 SHR $0x6,%RDI |
(107) 0x425896 INC %RDI |
(107) 0x425899 AND $0x3,%EDI |
(107) 0x42589c JE 42593f |
(107) 0x4258a2 CMP $0x1,%RDI |
(107) 0x4258a6 JE 425907 |
(107) 0x4258a8 CMP $0x2,%RDI |
(107) 0x4258ac JE 4258d8 |
(107) 0x4258ae VMOVUPD (%R13),%ZMM6 |
(107) 0x4258b5 MOV $0x40,%EAX |
(107) 0x4258ba VADDPD (%RCX),%ZMM6,%ZMM0 |
(107) 0x4258c0 VSUBPD (%RBX),%ZMM0,%ZMM1 |
(107) 0x4258c6 VMOVUPD %ZMM1,(%R10) |
(107) 0x4258cc VMOVUPD (%RCX),%ZMM7 |
(107) 0x4258d2 VMOVUPD %ZMM7,(%R9) |
(107) 0x4258d8 VMOVUPD (%R13,%RAX,1),%ZMM2 |
(107) 0x4258e0 VADDPD (%RCX,%RAX,1),%ZMM2,%ZMM3 |
(107) 0x4258e7 VSUBPD (%RBX,%RAX,1),%ZMM3,%ZMM4 |
(107) 0x4258ee VMOVUPD %ZMM4,(%R10,%RAX,1) |
(107) 0x4258f5 VMOVUPD (%RCX,%RAX,1),%ZMM5 |
(107) 0x4258fc VMOVUPD %ZMM5,(%R9,%RAX,1) |
(107) 0x425903 ADD $0x40,%RAX |
(107) 0x425907 VMOVUPD (%R13,%RAX,1),%ZMM8 |
(107) 0x42590f VADDPD (%RCX,%RAX,1),%ZMM8,%ZMM9 |
(107) 0x425916 VSUBPD (%RBX,%RAX,1),%ZMM9,%ZMM10 |
(107) 0x42591d VMOVUPD %ZMM10,(%R10,%RAX,1) |
(107) 0x425924 VMOVUPD (%RCX,%RAX,1),%ZMM11 |
(107) 0x42592b VMOVUPD %ZMM11,(%R9,%RAX,1) |
(107) 0x425932 ADD $0x40,%RAX |
(107) 0x425936 CMP %RAX,%R8 |
(107) 0x425939 JE 425a09 |
(108) 0x42593f VMOVUPD (%R13,%RAX,1),%ZMM12 |
(108) 0x425947 VADDPD (%RCX,%RAX,1),%ZMM12,%ZMM13 |
(108) 0x42594e VSUBPD (%RBX,%RAX,1),%ZMM13,%ZMM14 |
(108) 0x425955 VMOVUPD %ZMM14,(%R10,%RAX,1) |
(108) 0x42595c VMOVUPD (%RCX,%RAX,1),%ZMM15 |
(108) 0x425963 VMOVUPD %ZMM15,(%R9,%RAX,1) |
(108) 0x42596a VMOVUPD 0x40(%R13,%RAX,1),%ZMM6 |
(108) 0x425972 VADDPD 0x40(%RCX,%RAX,1),%ZMM6,%ZMM0 |
(108) 0x42597a VSUBPD 0x40(%RBX,%RAX,1),%ZMM0,%ZMM1 |
(108) 0x425982 VMOVUPD %ZMM1,0x40(%R10,%RAX,1) |
(108) 0x42598a VMOVUPD 0x40(%RCX,%RAX,1),%ZMM7 |
(108) 0x425992 VMOVUPD %ZMM7,0x40(%R9,%RAX,1) |
(108) 0x42599a VMOVUPD 0x80(%R13,%RAX,1),%ZMM2 |
(108) 0x4259a2 VADDPD 0x80(%RCX,%RAX,1),%ZMM2,%ZMM3 |
(108) 0x4259aa VSUBPD 0x80(%RBX,%RAX,1),%ZMM3,%ZMM4 |
(108) 0x4259b2 VMOVUPD %ZMM4,0x80(%R10,%RAX,1) |
(108) 0x4259ba VMOVUPD 0x80(%RCX,%RAX,1),%ZMM5 |
(108) 0x4259c2 VMOVUPD %ZMM5,0x80(%R9,%RAX,1) |
(108) 0x4259ca VMOVUPD 0xc0(%R13,%RAX,1),%ZMM8 |
(108) 0x4259d2 VADDPD 0xc0(%RCX,%RAX,1),%ZMM8,%ZMM9 |
(108) 0x4259da VSUBPD 0xc0(%RBX,%RAX,1),%ZMM9,%ZMM10 |
(108) 0x4259e2 VMOVUPD %ZMM10,0xc0(%R10,%RAX,1) |
(108) 0x4259ea VMOVUPD 0xc0(%RCX,%RAX,1),%ZMM11 |
(108) 0x4259f2 VMOVUPD %ZMM11,0xc0(%R9,%RAX,1) |
(108) 0x4259fa ADD $0x100,%RAX |
(108) 0x425a00 CMP %RAX,%R8 |
(108) 0x425a03 JNE 42593f |
(107) 0x425a09 MOV 0x74(%RSP),%EAX |
(107) 0x425a0d MOV %EDX,%EDI |
(107) 0x425a0f AND $-0x8,%EDI |
(107) 0x425a12 ADD %EDI,%R11D |
(107) 0x425a15 ADD %EDI,%EAX |
(107) 0x425a17 TEST $0x7,%DL |
(107) 0x425a1a JE 425b9d |
(107) 0x425a20 SUB %EDI,%EDX |
(107) 0x425a22 LEA -0x1(%RDX),%ECX |
(107) 0x425a25 CMP $0x2,%ECX |
(107) 0x425a28 JBE 425a9b |
(107) 0x425a2a MOVSXD 0x74(%RSP),%R13 |
(107) 0x425a2f MOV 0x50(%RSP),%RBX |
(107) 0x425a34 LEA (%R14,%R13,1),%R8 |
(107) 0x425a38 LEA (%RBX,%R13,1),%R10 |
(107) 0x425a3c MOV 0x58(%RSP),%RBX |
(107) 0x425a41 LEA 0x1(%RDI,%R8,1),%RCX |
(107) 0x425a46 ADD %RDI,%R10 |
(107) 0x425a49 MOV 0x60(%RSP),%R8 |
(107) 0x425a4e VMOVUPD (%RSI,%RCX,8),%YMM12 |
(107) 0x425a53 LEA (%R15,%R10,8),%R9 |
(107) 0x425a57 LEA (%RBX,%R13,1),%R10 |
(107) 0x425a5b ADD %RDI,%R10 |
(107) 0x425a5e VSUBPD -0x8(%RSI,%RCX,8),%YMM12,%YMM13 |
(107) 0x425a64 VADDPD (%R9),%YMM13,%YMM14 |
(107) 0x425a69 VMOVUPD %YMM14,(%R8,%R10,8) |
(107) 0x425a6f VMOVUPD (%R9),%YMM15 |
(107) 0x425a74 MOV 0x68(%RSP),%R9 |
(107) 0x425a79 ADD %R9,%R13 |
(107) 0x425a7c ADD %RDI,%R13 |
(107) 0x425a7f MOV 0x78(%RSP),%RDI |
(107) 0x425a84 VMOVUPD %YMM15,(%RDI,%R13,8) |
(107) 0x425a8a TEST $0x3,%DL |
(107) 0x425a8d JE 425b9d |
(107) 0x425a93 AND $-0x4,%EDX |
(107) 0x425a96 ADD %EDX,%R11D |
(107) 0x425a99 ADD %EDX,%EAX |
(107) 0x425a9b MOV 0x50(%RSP),%RBX |
(107) 0x425aa0 MOVSXD %EAX,%RCX |
(107) 0x425aa3 LEA 0x1(%RAX),%R13D |
(107) 0x425aa7 LEA (%RBX,%RCX,1),%RDX |
(107) 0x425aab LEA (%R15,%RDX,8),%RDI |
(107) 0x425aaf MOVSXD %R13D,%RDX |
(107) 0x425ab2 MOV 0x58(%RSP),%R13 |
(107) 0x425ab7 LEA (%R14,%RDX,1),%R10 |
(107) 0x425abb LEA (%RSI,%R10,8),%R8 |
(107) 0x425abf LEA (%R14,%RCX,1),%R10 |
(107) 0x425ac3 VMOVSD (%R8),%XMM6 |
(107) 0x425ac8 LEA (%R13,%RCX,1),%R9 |
(107) 0x425acd VSUBSD (%RSI,%R10,8),%XMM6,%XMM0 |
(107) 0x425ad3 MOV 0x60(%RSP),%R10 |
(107) 0x425ad8 VADDSD (%RDI),%XMM0,%XMM1 |
(107) 0x425adc VMOVSD %XMM1,(%R10,%R9,8) |
(107) 0x425ae2 MOV 0x78(%RSP),%R9 |
(107) 0x425ae7 MOV 0x70(%RSP),%R10D |
(107) 0x425aec VMOVSD (%RDI),%XMM7 |
(107) 0x425af0 MOV 0x68(%RSP),%RDI |
(107) 0x425af5 ADD %RDI,%RCX |
(107) 0x425af8 VMOVSD %XMM7,(%R9,%RCX,8) |
(107) 0x425afe LEA 0x1(%R11),%ECX |
(107) 0x425b02 CMP %R10D,%ECX |
(107) 0x425b05 JAE 425b9d |
(107) 0x425b0b LEA 0x2(%RAX),%R9D |
(107) 0x425b0f LEA (%RDX,%RBX,1),%RDI |
(107) 0x425b13 ADD $0x2,%R11D |
(107) 0x425b17 MOVSXD %R9D,%RCX |
(107) 0x425b1a LEA (%R15,%RDI,8),%RDI |
(107) 0x425b1e LEA (%R14,%RCX,1),%R10 |
(107) 0x425b22 LEA (%RSI,%R10,8),%R9 |
(107) 0x425b26 LEA (%R13,%RDX,1),%R10 |
(107) 0x425b2b VMOVSD (%R9),%XMM2 |
(107) 0x425b30 VADDSD (%RDI),%XMM2,%XMM3 |
(107) 0x425b34 VSUBSD (%R8),%XMM3,%XMM4 |
(107) 0x425b39 MOV 0x60(%RSP),%R8 |
(107) 0x425b3e VMOVSD %XMM4,(%R8,%R10,8) |
(107) 0x425b44 MOV 0x68(%RSP),%R10 |
(107) 0x425b49 VMOVSD (%RDI),%XMM5 |
(107) 0x425b4d MOV 0x78(%RSP),%RDI |
(107) 0x425b52 ADD %R10,%RDX |
(107) 0x425b55 VMOVSD %XMM5,(%RDI,%RDX,8) |
(107) 0x425b5a MOV 0x70(%RSP),%EDX |
(107) 0x425b5e CMP %EDX,%R11D |
(107) 0x425b61 JAE 425b9d |
(107) 0x425b63 ADD $0x3,%EAX |
(107) 0x425b66 ADD %RCX,%RBX |
(107) 0x425b69 ADD %RCX,%R13 |
(107) 0x425b6c ADD %RCX,%R10 |
(107) 0x425b6f CLTQ |
(107) 0x425b71 LEA (%R15,%RBX,8),%R11 |
(107) 0x425b75 MOV 0x78(%RSP),%R15 |
(107) 0x425b7a ADD %R14,%RAX |
(107) 0x425b7d VMOVSD (%RSI,%RAX,8),%XMM8 |
(107) 0x425b82 VADDSD (%R11),%XMM8,%XMM9 |
(107) 0x425b87 VSUBSD (%R9),%XMM9,%XMM10 |
(107) 0x425b8c VMOVSD %XMM10,(%R8,%R13,8) |
(107) 0x425b92 VMOVSD (%R11),%XMM11 |
(107) 0x425b97 VMOVSD %XMM11,(%R15,%R10,8) |
(107) 0x425b9d MOV 0x70(%RSP),%R11D |
(107) 0x425ba2 INC %R12 |
(107) 0x425ba5 LEA (%R12),%ESI |
(107) 0x425ba9 CMP %ESI,0x48(%RSP) |
(107) 0x425bad JLE 425bd0 |
(107) 0x425baf MOV 0x40(%RSP),%ECX |
(107) 0x425bb3 MOV 0x44(%RSP),%R14D |
(107) 0x425bb8 MOV 0x4c(%RSP),%EDX |
(107) 0x425bbc MOV %R14D,0x74(%RSP) |
(107) 0x425bc1 SUB %R11D,%ECX |
(107) 0x425bc4 JMP 4257d0 |
0x425bc9 NOPL (%RAX) |
0x425bd0 VZEROUPPER |
0x425bd3 LEA -0x28(%RBP),%RSP |
0x425bd7 POP %RBX |
0x425bd8 POP %R12 |
0x425bda POP %R13 |
0x425bdc POP %R14 |
0x425bde POP %R15 |
0x425be0 POP %RBP |
0x425be1 RET |
0x425be2 NOPW (%RAX,%RAX,1) |
(107) 0x425be8 MOV 0x74(%RSP),%EAX |
(107) 0x425bec XOR %EDI,%EDI |
(107) 0x425bee JMP 425a20 |
0x425bf3 INC %ECX |
0x425bf5 XOR %EDX,%EDX |
0x425bf7 JMP 425770 |
0x425bfc NOPL (%RAX) |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
○98.10 | gomp_thread_start | team.c:130 | libgomp.so.1.0.0 |
○1.89 | GOMP_parallel | libgomp.h:985 | libgomp.so.1.0.0 |
Path / |
Source file and lines | advec_cell.cpp:54-58 |
Module | exec |
nb instructions | 79 |
nb uops | 89 |
loop length | 268 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 10 |
micro-operation queue | 14.83 cycles |
front end | 14.83 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 5.70 | 8.00 | 6.00 | 6.00 | 8.50 | 5.87 | 5.70 | 8.50 | 8.50 | 8.50 | 5.73 | 6.00 |
cycles | 5.70 | 11.73 | 6.00 | 6.00 | 8.50 | 5.87 | 5.70 | 8.50 | 8.50 | 8.50 | 5.73 | 6.00 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.07-14.16 |
Stall cycles | 0.00 |
Front-end | 14.83 |
Dispatch | 11.73 |
DIV/SQRT | 12.00 |
Overall L1 | 14.83 |
all | 3% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 12% |
all | 8% |
load | 9% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 9% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD $-0x80,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x28(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%RDI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x24(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x4,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA -0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
DEC %ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ECX,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ESI,0x44(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %ECX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 425bd3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.1.lto_priv.0+0x4e3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %ECX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x4(%RDX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 425bd3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.1.lto_priv.0+0x4e3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R14D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %ESI,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EDI,0x4c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x4c(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 425bf3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.1.lto_priv.0+0x503> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %ECX,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RCX,%R11,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R9D,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R9D,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 425bd3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.1.lto_priv.0+0x4e3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R11D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x44(%RSP),%R10D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%R13),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x4c(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x18(%R13),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R15D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV (%R13),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%R13),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10D,0x74(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R10D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %EAX,%R12 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R15,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 425770 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.1.lto_priv.0+0x80> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | advec_cell.cpp:54-58 |
Module | exec |
nb instructions | 79 |
nb uops | 89 |
loop length | 268 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 10 |
micro-operation queue | 14.83 cycles |
front end | 14.83 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 5.70 | 8.00 | 6.00 | 6.00 | 8.50 | 5.87 | 5.70 | 8.50 | 8.50 | 8.50 | 5.73 | 6.00 |
cycles | 5.70 | 11.73 | 6.00 | 6.00 | 8.50 | 5.87 | 5.70 | 8.50 | 8.50 | 8.50 | 5.73 | 6.00 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.07-14.16 |
Stall cycles | 0.00 |
Front-end | 14.83 |
Dispatch | 11.73 |
DIV/SQRT | 12.00 |
Overall L1 | 14.83 |
all | 3% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 12% |
all | 8% |
load | 9% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 9% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD $-0x80,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x28(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%RDI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x24(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x4,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA -0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
DEC %ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ECX,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ESI,0x44(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %ECX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 425bd3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.1.lto_priv.0+0x4e3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %ECX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x4(%RDX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 425bd3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.1.lto_priv.0+0x4e3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R14D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %ESI,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EDI,0x4c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x4c(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 425bf3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.1.lto_priv.0+0x503> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %ECX,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RCX,%R11,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R9D,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R9D,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 425bd3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.1.lto_priv.0+0x4e3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R11D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x44(%RSP),%R10D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%R13),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x4c(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x18(%R13),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R15D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV (%R13),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%R13),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10D,0x74(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R10D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %EAX,%R12 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R15,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 425770 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.1.lto_priv.0+0x80> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D | 1.09 | 0.36 |
▼Loop 107 - advec_cell.cpp:57-58 - exec– | 0 | 0 |
○Loop 108 - advec_cell.cpp:57-58 - exec | 1.09 | 0.36 |