Function: __svml_i64rem8_z0 | Module: exec | Source: :0-0 | Coverage: 19.02% |
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Function: __svml_i64rem8_z0 | Module: exec | Source: :0-0 | Coverage: 19.02% |
---|
*** This Panel is Intentionally Left Blank. *** It is due to a lack of debug symbols in the given object |
0x4664a0 ENDBR64 |
0x4664a4 VMOVDQU64 0x25352(%RIP),%ZMM2 |
0x4664ae VPCMPGTQ %ZMM1,%ZMM2,%K1 |
0x4664b4 VPSUBQ %ZMM1,%ZMM2,%ZMM1{%K1} |
0x4664ba VMOVDQU64 0x2547c(%RIP),%ZMM5 |
0x4664c4 VMOVUPD 0x253b2(%RIP),%ZMM3 |
0x4664ce VMOVUPD 0x254e8(%RIP),%ZMM6 |
0x4664d8 VMOVUPD 0x253de(%RIP),%ZMM4 |
0x4664e2 VPCMPEQQ %ZMM2,%ZMM1,%K0 |
0x4664e8 KORTESTB %K0,%K0 |
0x4664ec JE 4664f5 |
0x4664ee MOV $0,%EAX |
0x4664f3 DIV %AL |
0x4664f5 VPANDQ %ZMM5,%ZMM1,%ZMM7 |
0x4664fb VCVTUQQ2PD {rn-sae},%ZMM7,%ZMM7 |
0x466501 VPANDNQ %ZMM1,%ZMM5,%ZMM8 |
0x466507 VCVTUQQ2PD {rn-sae},%ZMM8,%ZMM8 |
0x46650d VCVTUQQ2PD {rn-sae},%ZMM1,%ZMM9 |
0x466513 VANDPD %ZMM9,%ZMM6,%ZMM6 |
0x466519 VSUBPD {rn-sae},%ZMM6,%ZMM8,%ZMM8 |
0x46651f VADDPD {rn-sae},%ZMM8,%ZMM7,%ZMM7 |
0x466525 VPCMPGTQ %ZMM0,%ZMM2,%K1 |
0x46652b VPSUBQ %ZMM0,%ZMM2,%ZMM0{%K1} |
0x466531 VCVTUQQ2PD {rn-sae},%ZMM0,%ZMM8 |
0x466537 VRCP14PD %ZMM9,%ZMM10 |
0x46653d VFNMADD231PD {rn-sae},%ZMM9,%ZMM10,%ZMM3 |
0x466543 VFMADD132PD {rn-sae},%ZMM10,%ZMM10,%ZMM3 |
0x466549 VMULPD {rn-sae},%ZMM3,%ZMM8,%ZMM8 |
0x46654f VRNDSCALEPD $0x3,{sae},%ZMM8,%ZMM8 |
0x466556 VANDPD %ZMM8,%ZMM4,%ZMM8 |
0x46655c VPANDNQ %ZMM0,%ZMM5,%ZMM9 |
0x466562 VCVTUQQ2PD {rn-sae},%ZMM9,%ZMM9 |
0x466568 VFNMADD231PD {rn-sae},%ZMM8,%ZMM6,%ZMM9 |
0x46656e VPANDQ %ZMM5,%ZMM0,%ZMM5 |
0x466574 VCVTUQQ2PD {rn-sae},%ZMM5,%ZMM5 |
0x46657a VFNMADD231PD {rn-sae},%ZMM8,%ZMM7,%ZMM5 |
0x466580 VADDPD {rn-sae},%ZMM5,%ZMM9,%ZMM5 |
0x466586 VMULPD {rn-sae},%ZMM3,%ZMM5,%ZMM9 |
0x46658c VRNDSCALEPD $0x3,{sae},%ZMM9,%ZMM9 |
0x466593 VANDPD %ZMM9,%ZMM4,%ZMM9 |
0x466599 VFNMADD231PD {rn-sae},%ZMM9,%ZMM6,%ZMM5 |
0x46659f VFNMADD231PD {rn-sae},%ZMM9,%ZMM7,%ZMM5 |
0x4665a5 VMULPD {rn-sae},%ZMM3,%ZMM5,%ZMM10 |
0x4665ab VRNDSCALEPD $0x3,{sae},%ZMM10,%ZMM10 |
0x4665b2 VANDPD %ZMM10,%ZMM4,%ZMM4 |
0x4665b8 VFNMADD231PD {rn-sae},%ZMM6,%ZMM4,%ZMM5 |
0x4665be VFNMADD231PD {rn-sae},%ZMM7,%ZMM4,%ZMM5 |
0x4665c4 VMULPD {rn-sae},%ZMM3,%ZMM5,%ZMM3 |
0x4665ca VCVTPD2UQQ {rz-sae},%ZMM4,%ZMM4 |
0x4665d0 VCVTPD2UQQ {rz-sae},%ZMM9,%ZMM5 |
0x4665d6 VCVTPD2UQQ {rz-sae},%ZMM8,%ZMM6 |
0x4665dc VPADDQ %ZMM5,%ZMM6,%ZMM5 |
0x4665e2 VCVTPD2UQQ {rz-sae},%ZMM3,%ZMM3 |
0x4665e8 VPADDD %ZMM4,%ZMM3,%ZMM3 |
0x4665ee VPADDQ %ZMM3,%ZMM5,%ZMM3 |
0x4665f4 VPMULLQ %ZMM1,%ZMM3,%ZMM3 |
0x4665fa VPSUBQ %ZMM3,%ZMM0,%ZMM0 |
0x466600 VPCMPNLTUQ %ZMM1,%ZMM0,%K2 |
0x466607 VPSUBQ %ZMM1,%ZMM0,%ZMM0{%K2} |
0x46660d VPSUBQ %ZMM0,%ZMM2,%ZMM0{%K1} |
0x466613 RET |
0x466614 NOPW %CS:(%RAX,%RAX,1) |
0x46661e XCHG %AX,%AX |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
►100.00+ | __kmp_invoke_microtask | libiomp5.so | |
○ | __kmp_invoke_task_func | libiomp5.so |
Path / |
Source file and lines | |
Module | exec |
nb instructions | 60 |
nb uops | 68.50 |
loop length | 368.50 |
used x86 registers | 0.50 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 11 |
nb stack references | 0 |
ADD-SUB / MUL ratio | 0.75 |
micro-operation queue | 11.42 cycles |
front end | 11.42 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 28.50 | 1.50 | 2.00 | 2.00 | 0.00 | 28.50 | 2.00 | 0.00 | 0.00 | 0.00 | 0.50 | 2.00 |
cycles | 28.50 | 7.50 | 2.00 | 2.00 | 0.00 | 28.50 | 2.00 | 0.00 | 0.00 | 0.00 | 0.50 | 2.00 |
Cycles executing div or sqrt instructions | 3.00 |
FE+BE cycles | 149.63-149.73 |
Stall cycles | 138.06-138.16 |
RS full (events) | 149.11-149.20 |
Front-end | 11.42 |
Dispatch | 28.50 |
DIV/SQRT | 3.00 |
Overall L1 | 28.50 |
all | 98% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 96% |
all | 100% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | 100% |
fma | 100% |
div/sqrt | 100% |
other | 100% |
all | 99% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | 100% |
fma | 100% |
div/sqrt | 100% |
other | 98% |
all | 98% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 96% |
all | 100% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | 100% |
fma | 100% |
div/sqrt | 100% |
other | 100% |
all | 99% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | 100% |
fma | 100% |
div/sqrt | 100% |
other | 98% |
Source file and lines | |
Module | exec |
nb instructions | 61 |
nb uops | 71 |
loop length | 372 |
used x86 registers | 1 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 11 |
nb stack references | 0 |
ADD-SUB / MUL ratio | 0.75 |
micro-operation queue | 11.83 cycles |
front end | 11.83 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 28.50 | 3.00 | 2.00 | 2.00 | 0.00 | 28.50 | 2.00 | 0.00 | 0.00 | 0.00 | 1.00 | 2.00 |
cycles | 28.50 | 7.50 | 2.00 | 2.00 | 0.00 | 28.50 | 2.00 | 0.00 | 0.00 | 0.00 | 1.00 | 2.00 |
Cycles executing div or sqrt instructions | 6.00 |
FE+BE cycles | 149.67-149.86 |
Stall cycles | 137.75-137.94 |
RS full (events) | 149.13-149.32 |
Front-end | 11.83 |
Dispatch | 28.50 |
DIV/SQRT | 6.00 |
Overall L1 | 28.50 |
all | 96% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 93% |
all | 100% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | 100% |
fma | 100% |
div/sqrt | 100% |
other | 100% |
all | 98% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | 100% |
fma | 100% |
div/sqrt | 100% |
other | 96% |
all | 96% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 93% |
all | 100% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | 100% |
fma | 100% |
div/sqrt | 100% |
other | 100% |
all | 98% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | 100% |
fma | 100% |
div/sqrt | 100% |
other | 96% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ENDBR64 | |||||||||||||||
VMOVDQU64 0x25352(%RIP),%ZMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VPCMPGTQ %ZMM1,%ZMM2,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0-3 | 1 |
VPSUBQ %ZMM1,%ZMM2,%ZMM1{%K1} | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.50 |
VMOVDQU64 0x2547c(%RIP),%ZMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMOVUPD 0x253b2(%RIP),%ZMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMOVUPD 0x254e8(%RIP),%ZMM6 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMOVUPD 0x253de(%RIP),%ZMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VPCMPEQQ %ZMM2,%ZMM1,%K0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
KORTESTB %K0,%K0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
JE 4664f5 <__svml_i64rem8_z0+0x55> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV $0,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
DIV %AL | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
VPANDQ %ZMM5,%ZMM1,%ZMM7 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VCVTUQQ2PD {rn-sae},%ZMM7,%ZMM7 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VPANDNQ %ZMM1,%ZMM5,%ZMM8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VCVTUQQ2PD {rn-sae},%ZMM8,%ZMM8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VCVTUQQ2PD {rn-sae},%ZMM1,%ZMM9 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VANDPD %ZMM9,%ZMM6,%ZMM6 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VSUBPD {rn-sae},%ZMM6,%ZMM8,%ZMM8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VADDPD {rn-sae},%ZMM8,%ZMM7,%ZMM7 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VPCMPGTQ %ZMM0,%ZMM2,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0-3 | 1 |
VPSUBQ %ZMM0,%ZMM2,%ZMM0{%K1} | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.50 |
VCVTUQQ2PD {rn-sae},%ZMM0,%ZMM8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VRCP14PD %ZMM9,%ZMM10 | 3 | 2.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 7 | 2 |
VFNMADD231PD {rn-sae},%ZMM9,%ZMM10,%ZMM3 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD132PD {rn-sae},%ZMM10,%ZMM10,%ZMM3 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULPD {rn-sae},%ZMM3,%ZMM8,%ZMM8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VRNDSCALEPD $0x3,{sae},%ZMM8,%ZMM8 | 2 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 8 | 1 |
VANDPD %ZMM8,%ZMM4,%ZMM8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VPANDNQ %ZMM0,%ZMM5,%ZMM9 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VCVTUQQ2PD {rn-sae},%ZMM9,%ZMM9 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFNMADD231PD {rn-sae},%ZMM8,%ZMM6,%ZMM9 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VPANDQ %ZMM5,%ZMM0,%ZMM5 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VCVTUQQ2PD {rn-sae},%ZMM5,%ZMM5 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFNMADD231PD {rn-sae},%ZMM8,%ZMM7,%ZMM5 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VADDPD {rn-sae},%ZMM5,%ZMM9,%ZMM5 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMULPD {rn-sae},%ZMM3,%ZMM5,%ZMM9 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VRNDSCALEPD $0x3,{sae},%ZMM9,%ZMM9 | 2 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 8 | 1 |
VANDPD %ZMM9,%ZMM4,%ZMM9 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VFNMADD231PD {rn-sae},%ZMM9,%ZMM6,%ZMM5 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFNMADD231PD {rn-sae},%ZMM9,%ZMM7,%ZMM5 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULPD {rn-sae},%ZMM3,%ZMM5,%ZMM10 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VRNDSCALEPD $0x3,{sae},%ZMM10,%ZMM10 | 2 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 8 | 1 |
VANDPD %ZMM10,%ZMM4,%ZMM4 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VFNMADD231PD {rn-sae},%ZMM6,%ZMM4,%ZMM5 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFNMADD231PD {rn-sae},%ZMM7,%ZMM4,%ZMM5 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULPD {rn-sae},%ZMM3,%ZMM5,%ZMM3 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VCVTPD2UQQ {rz-sae},%ZMM4,%ZMM4 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VCVTPD2UQQ {rz-sae},%ZMM9,%ZMM5 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VCVTPD2UQQ {rz-sae},%ZMM8,%ZMM6 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VPADDQ %ZMM5,%ZMM6,%ZMM5 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VCVTPD2UQQ {rz-sae},%ZMM3,%ZMM3 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VPADDD %ZMM4,%ZMM3,%ZMM3 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VPADDQ %ZMM3,%ZMM5,%ZMM3 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VPMULLQ %ZMM1,%ZMM3,%ZMM3 | 5 | 1.50 | 0 | 0 | 0 | 0 | 1.50 | 0 | 0 | 0 | 0 | 0 | 0 | 15 | 1.50 |
VPSUBQ %ZMM3,%ZMM0,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.50 |
VPCMPNLTUQ %ZMM1,%ZMM0,%K2 | |||||||||||||||
VPSUBQ %ZMM1,%ZMM0,%ZMM0{%K2} | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.50 |
VPSUBQ %ZMM0,%ZMM2,%ZMM0{%K1} | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.50 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
Source file and lines | |
Module | exec |
nb instructions | 59 |
nb uops | 66 |
loop length | 365 |
used x86 registers | 0 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 11 |
nb stack references | 0 |
ADD-SUB / MUL ratio | 0.75 |
micro-operation queue | 11.00 cycles |
front end | 11.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 28.50 | 0.00 | 2.00 | 2.00 | 0.00 | 28.50 | 2.00 | 0.00 | 0.00 | 0.00 | 0.00 | 2.00 |
cycles | 28.50 | 7.50 | 2.00 | 2.00 | 0.00 | 28.50 | 2.00 | 0.00 | 0.00 | 0.00 | 0.00 | 2.00 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 149.60 |
Stall cycles | 138.38 |
RS full (events) | 149.09 |
Front-end | 11.00 |
Dispatch | 28.50 |
Overall L1 | 28.50 |
all | 100% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 100% |
all | 100% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | 100% |
fma | 100% |
div/sqrt | 100% |
other | 100% |
all | 100% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | 100% |
fma | 100% |
div/sqrt | 100% |
other | 100% |
all | 100% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 100% |
all | 100% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | 100% |
fma | 100% |
div/sqrt | 100% |
other | 100% |
all | 100% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | 100% |
fma | 100% |
div/sqrt | 100% |
other | 100% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ENDBR64 | |||||||||||||||
VMOVDQU64 0x25352(%RIP),%ZMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VPCMPGTQ %ZMM1,%ZMM2,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0-3 | 1 |
VPSUBQ %ZMM1,%ZMM2,%ZMM1{%K1} | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.50 |
VMOVDQU64 0x2547c(%RIP),%ZMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMOVUPD 0x253b2(%RIP),%ZMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMOVUPD 0x254e8(%RIP),%ZMM6 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMOVUPD 0x253de(%RIP),%ZMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VPCMPEQQ %ZMM2,%ZMM1,%K0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
KORTESTB %K0,%K0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
JE 4664f5 <__svml_i64rem8_z0+0x55> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VPANDQ %ZMM5,%ZMM1,%ZMM7 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VCVTUQQ2PD {rn-sae},%ZMM7,%ZMM7 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VPANDNQ %ZMM1,%ZMM5,%ZMM8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VCVTUQQ2PD {rn-sae},%ZMM8,%ZMM8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VCVTUQQ2PD {rn-sae},%ZMM1,%ZMM9 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VANDPD %ZMM9,%ZMM6,%ZMM6 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VSUBPD {rn-sae},%ZMM6,%ZMM8,%ZMM8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VADDPD {rn-sae},%ZMM8,%ZMM7,%ZMM7 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VPCMPGTQ %ZMM0,%ZMM2,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0-3 | 1 |
VPSUBQ %ZMM0,%ZMM2,%ZMM0{%K1} | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.50 |
VCVTUQQ2PD {rn-sae},%ZMM0,%ZMM8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VRCP14PD %ZMM9,%ZMM10 | 3 | 2.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 7 | 2 |
VFNMADD231PD {rn-sae},%ZMM9,%ZMM10,%ZMM3 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD132PD {rn-sae},%ZMM10,%ZMM10,%ZMM3 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULPD {rn-sae},%ZMM3,%ZMM8,%ZMM8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VRNDSCALEPD $0x3,{sae},%ZMM8,%ZMM8 | 2 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 8 | 1 |
VANDPD %ZMM8,%ZMM4,%ZMM8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VPANDNQ %ZMM0,%ZMM5,%ZMM9 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VCVTUQQ2PD {rn-sae},%ZMM9,%ZMM9 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFNMADD231PD {rn-sae},%ZMM8,%ZMM6,%ZMM9 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VPANDQ %ZMM5,%ZMM0,%ZMM5 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VCVTUQQ2PD {rn-sae},%ZMM5,%ZMM5 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFNMADD231PD {rn-sae},%ZMM8,%ZMM7,%ZMM5 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VADDPD {rn-sae},%ZMM5,%ZMM9,%ZMM5 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMULPD {rn-sae},%ZMM3,%ZMM5,%ZMM9 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VRNDSCALEPD $0x3,{sae},%ZMM9,%ZMM9 | 2 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 8 | 1 |
VANDPD %ZMM9,%ZMM4,%ZMM9 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VFNMADD231PD {rn-sae},%ZMM9,%ZMM6,%ZMM5 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFNMADD231PD {rn-sae},%ZMM9,%ZMM7,%ZMM5 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULPD {rn-sae},%ZMM3,%ZMM5,%ZMM10 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VRNDSCALEPD $0x3,{sae},%ZMM10,%ZMM10 | 2 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 8 | 1 |
VANDPD %ZMM10,%ZMM4,%ZMM4 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VFNMADD231PD {rn-sae},%ZMM6,%ZMM4,%ZMM5 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFNMADD231PD {rn-sae},%ZMM7,%ZMM4,%ZMM5 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULPD {rn-sae},%ZMM3,%ZMM5,%ZMM3 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VCVTPD2UQQ {rz-sae},%ZMM4,%ZMM4 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VCVTPD2UQQ {rz-sae},%ZMM9,%ZMM5 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VCVTPD2UQQ {rz-sae},%ZMM8,%ZMM6 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VPADDQ %ZMM5,%ZMM6,%ZMM5 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VCVTPD2UQQ {rz-sae},%ZMM3,%ZMM3 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VPADDD %ZMM4,%ZMM3,%ZMM3 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VPADDQ %ZMM3,%ZMM5,%ZMM3 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VPMULLQ %ZMM1,%ZMM3,%ZMM3 | 5 | 1.50 | 0 | 0 | 0 | 0 | 1.50 | 0 | 0 | 0 | 0 | 0 | 0 | 15 | 1.50 |
VPSUBQ %ZMM3,%ZMM0,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.50 |
VPCMPNLTUQ %ZMM1,%ZMM0,%K2 | |||||||||||||||
VPSUBQ %ZMM1,%ZMM0,%ZMM0{%K2} | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.50 |
VPSUBQ %ZMM0,%ZMM2,%ZMM0{%K1} | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.50 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
Name | Coverage (%) | Time (s) |
---|---|---|
○__svml_i64rem8_z0 | 19.02 | 12.58 |