Function: reset_field_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double> ... | Module: exec | Source: reset_field.cpp:44-48 [...] | Coverage: 2.05% |
---|
Function: reset_field_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double> ... | Module: exec | Source: reset_field.cpp:44-48 [...] | Coverage: 2.05% |
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/scratch_na/users/xoserete/qaas_runs/171-415-4969/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/reset_field.cpp: 44 - 48 |
-------------------------------------------------------------------------------- |
44: #pragma omp parallel for simd collapse(2) |
45: for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) { |
46: for (int i = (x_min + 1); i < (x_max + 1 + 2); i++) { |
47: xvel0(i, j) = xvel1(i, j); |
48: yvel0(i, j) = yvel1(i, j); |
/scratch_na/users/xoserete/qaas_runs/171-415-4969/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69 |
-------------------------------------------------------------------------------- |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
0x43ed50 PUSH %RBP |
0x43ed51 MOV %RSP,%RBP |
0x43ed54 PUSH %R15 |
0x43ed56 PUSH %R14 |
0x43ed58 PUSH %R13 |
0x43ed5a PUSH %R12 |
0x43ed5c PUSH %RBX |
0x43ed5d AND $-0x40,%RSP |
0x43ed61 ADD $-0x80,%RSP |
0x43ed65 MOV 0x28(%RDI),%EAX |
0x43ed68 MOV 0x2c(%RDI),%EDX |
0x43ed6b MOV 0x20(%RDI),%EBX |
0x43ed6e MOV 0x24(%RDI),%ECX |
0x43ed71 ADD $0x3,%EDX |
0x43ed74 LEA 0x1(%RAX),%R15D |
0x43ed78 LEA 0x1(%RBX),%ESI |
0x43ed7b MOV %EDX,0x50(%RSP) |
0x43ed7f MOV %ESI,0x4c(%RSP) |
0x43ed83 CMP %EDX,%R15D |
0x43ed86 JGE 43f283 |
0x43ed8c MOV %EDX,%EBX |
0x43ed8e LEA 0x3(%RCX),%R14D |
0x43ed92 SUB %R15D,%EBX |
0x43ed95 CMP %R14D,%ESI |
0x43ed98 JGE 43f283 |
0x43ed9e MOV %RDI,%R13 |
0x43eda1 MOV %R14D,%EDI |
0x43eda4 SUB %ESI,%EDI |
0x43eda6 MOV %EDI,0x54(%RSP) |
0x43edaa CALL 4046c0 <omp_get_num_threads@plt> |
0x43edaf MOV %EAX,%R12D |
0x43edb2 CALL 4045b0 <omp_get_thread_num@plt> |
0x43edb7 XOR %EDX,%EDX |
0x43edb9 MOV %EAX,%R8D |
0x43edbc MOV 0x54(%RSP),%EAX |
0x43edc0 IMUL %EBX,%EAX |
0x43edc3 DIV %R12D |
0x43edc6 MOV %EAX,%R12D |
0x43edc9 CMP %EDX,%R8D |
0x43edcc JB 43f2a4 |
0x43edd2 IMUL %R12D,%R8D |
0x43edd6 LEA (%R8,%RDX,1),%R9D |
0x43edda LEA (%R12,%R9,1),%R10D |
0x43edde MOV %R10D,0x48(%RSP) |
0x43ede3 CMP %R10D,%R9D |
0x43ede6 JAE 43f283 |
0x43edec MOV %R9D,%EAX |
0x43edef XOR %EDX,%EDX |
0x43edf1 MOV 0x4c(%RSP),%R11D |
0x43edf6 MOV (%R13),%RSI |
0x43edfa DIVL 0x54(%RSP) |
0x43edfe MOV 0x10(%R13),%RBX |
0x43ee02 MOV %RSI,0x38(%RSP) |
0x43ee07 MOV %RBX,0x28(%RSP) |
0x43ee0c ADD %EDX,%R11D |
0x43ee0f ADD %R15D,%EAX |
0x43ee12 MOV %R14D,%EDX |
0x43ee15 MOV 0x8(%R13),%R15 |
0x43ee19 MOV 0x18(%R13),%R14 |
0x43ee1d MOV %R11D,0x7c(%RSP) |
0x43ee22 SUB %R11D,%EDX |
0x43ee25 MOVSXD %EAX,%RBX |
0x43ee28 MOV %R15,0x40(%RSP) |
0x43ee2d MOV %R14,0x30(%RSP) |
0x43ee32 NOPW (%RAX,%RAX,1) |
(231) 0x43ee38 CMP %EDX,%R12D |
(231) 0x43ee3b CMOVBE %R12D,%EDX |
(231) 0x43ee3f LEA (%R9,%RDX,1),%ECX |
(231) 0x43ee43 MOV %ECX,0x78(%RSP) |
(231) 0x43ee47 CMP %ECX,%R9D |
(231) 0x43ee4a JAE 43f24d |
(231) 0x43ee50 MOV 0x30(%RSP),%R12 |
(231) 0x43ee55 MOV 0x38(%RSP),%RDI |
(231) 0x43ee5a LEA -0x1(%RDX),%EAX |
(231) 0x43ee5d MOV 0x28(%RSP),%RCX |
(231) 0x43ee62 MOV 0x40(%RSP),%R13 |
(231) 0x43ee67 MOV (%R12),%RSI |
(231) 0x43ee6b MOV (%RDI),%R8 |
(231) 0x43ee6e MOV (%RCX),%R10 |
(231) 0x43ee71 MOV (%R13),%R11 |
(231) 0x43ee75 IMUL %RBX,%R8 |
(231) 0x43ee79 MOV 0x10(%R13),%R15 |
(231) 0x43ee7d MOV 0x10(%RDI),%R14 |
(231) 0x43ee81 IMUL %RBX,%RSI |
(231) 0x43ee85 MOV 0x10(%R12),%R13 |
(231) 0x43ee8a MOV 0x10(%RCX),%R12 |
(231) 0x43ee8e IMUL %RBX,%R10 |
(231) 0x43ee92 IMUL %RBX,%R11 |
(231) 0x43ee96 MOV %R8,0x60(%RSP) |
(231) 0x43ee9b MOV %RSI,0x68(%RSP) |
(231) 0x43eea0 MOV %R10,0x70(%RSP) |
(231) 0x43eea5 CMP $0x6,%EAX |
(231) 0x43eea8 JBE 43f298 |
(231) 0x43eeae MOVSXD 0x7c(%RSP),%RAX |
(231) 0x43eeb3 LEA (%R8,%RAX,1),%RCX |
(231) 0x43eeb7 LEA (%R11,%RAX,1),%RDI |
(231) 0x43eebb LEA (%R14,%RCX,8),%R8 |
(231) 0x43eebf MOV 0x70(%RSP),%RCX |
(231) 0x43eec4 LEA (%RSI,%RAX,1),%RSI |
(231) 0x43eec8 LEA (%R15,%RDI,8),%R10 |
(231) 0x43eecc LEA (%R13,%RSI,8),%RDI |
(231) 0x43eed1 ADD %RCX,%RAX |
(231) 0x43eed4 MOV %EDX,%ECX |
(231) 0x43eed6 SHR $0x3,%ECX |
(231) 0x43eed9 LEA (%R12,%RAX,8),%RSI |
(231) 0x43eedd XOR %EAX,%EAX |
(231) 0x43eedf SAL $0x6,%RCX |
(231) 0x43eee3 MOV %RCX,0x58(%RSP) |
(231) 0x43eee8 SUB $0x40,%RCX |
(231) 0x43eeec SHR $0x6,%RCX |
(231) 0x43eef0 INC %RCX |
(231) 0x43eef3 AND $0x7,%ECX |
(231) 0x43eef6 JE 43f014 |
(231) 0x43eefc CMP $0x1,%RCX |
(231) 0x43ef00 JE 43efe9 |
(231) 0x43ef06 CMP $0x2,%RCX |
(231) 0x43ef0a JE 43efc9 |
(231) 0x43ef10 CMP $0x3,%RCX |
(231) 0x43ef14 JE 43efa9 |
(231) 0x43ef1a CMP $0x4,%RCX |
(231) 0x43ef1e JE 43ef89 |
(231) 0x43ef20 CMP $0x5,%RCX |
(231) 0x43ef24 JE 43ef69 |
(231) 0x43ef26 CMP $0x6,%RCX |
(231) 0x43ef2a JE 43ef49 |
(231) 0x43ef2c VMOVUPD (%R10),%ZMM3 |
(231) 0x43ef32 MOV $0x40,%EAX |
(231) 0x43ef37 VMOVUPD %ZMM3,(%R8) |
(231) 0x43ef3d VMOVUPD (%RDI),%ZMM4 |
(231) 0x43ef43 VMOVUPD %ZMM4,(%RSI) |
(231) 0x43ef49 VMOVUPD (%R10,%RAX,1),%ZMM1 |
(231) 0x43ef50 VMOVUPD %ZMM1,(%R8,%RAX,1) |
(231) 0x43ef57 VMOVUPD (%RDI,%RAX,1),%ZMM2 |
(231) 0x43ef5e VMOVUPD %ZMM2,(%RSI,%RAX,1) |
(231) 0x43ef65 ADD $0x40,%RAX |
(231) 0x43ef69 VMOVUPD (%R10,%RAX,1),%ZMM0 |
(231) 0x43ef70 VMOVUPD %ZMM0,(%R8,%RAX,1) |
(231) 0x43ef77 VMOVUPD (%RDI,%RAX,1),%ZMM5 |
(231) 0x43ef7e VMOVUPD %ZMM5,(%RSI,%RAX,1) |
(231) 0x43ef85 ADD $0x40,%RAX |
(231) 0x43ef89 VMOVUPD (%R10,%RAX,1),%ZMM6 |
(231) 0x43ef90 VMOVUPD %ZMM6,(%R8,%RAX,1) |
(231) 0x43ef97 VMOVUPD (%RDI,%RAX,1),%ZMM7 |
(231) 0x43ef9e VMOVUPD %ZMM7,(%RSI,%RAX,1) |
(231) 0x43efa5 ADD $0x40,%RAX |
(231) 0x43efa9 VMOVUPD (%R10,%RAX,1),%ZMM8 |
(231) 0x43efb0 VMOVUPD %ZMM8,(%R8,%RAX,1) |
(231) 0x43efb7 VMOVUPD (%RDI,%RAX,1),%ZMM9 |
(231) 0x43efbe VMOVUPD %ZMM9,(%RSI,%RAX,1) |
(231) 0x43efc5 ADD $0x40,%RAX |
(231) 0x43efc9 VMOVUPD (%R10,%RAX,1),%ZMM10 |
(231) 0x43efd0 VMOVUPD %ZMM10,(%R8,%RAX,1) |
(231) 0x43efd7 VMOVUPD (%RDI,%RAX,1),%ZMM11 |
(231) 0x43efde VMOVUPD %ZMM11,(%RSI,%RAX,1) |
(231) 0x43efe5 ADD $0x40,%RAX |
(231) 0x43efe9 VMOVUPD (%R10,%RAX,1),%ZMM12 |
(231) 0x43eff0 VMOVUPD %ZMM12,(%R8,%RAX,1) |
(231) 0x43eff7 VMOVUPD (%RDI,%RAX,1),%ZMM13 |
(231) 0x43effe VMOVUPD %ZMM13,(%RSI,%RAX,1) |
(231) 0x43f005 ADD $0x40,%RAX |
(231) 0x43f009 CMP %RAX,0x58(%RSP) |
(231) 0x43f00e JE 43f121 |
(232) 0x43f014 VMOVUPD (%R10,%RAX,1),%ZMM14 |
(232) 0x43f01b VMOVUPD %ZMM14,(%R8,%RAX,1) |
(232) 0x43f022 VMOVUPD (%RDI,%RAX,1),%ZMM15 |
(232) 0x43f029 VMOVUPD %ZMM15,(%RSI,%RAX,1) |
(232) 0x43f030 VMOVUPD 0x40(%R10,%RAX,1),%ZMM3 |
(232) 0x43f038 VMOVUPD %ZMM3,0x40(%R8,%RAX,1) |
(232) 0x43f040 VMOVUPD 0x40(%RDI,%RAX,1),%ZMM4 |
(232) 0x43f048 VMOVUPD %ZMM4,0x40(%RSI,%RAX,1) |
(232) 0x43f050 VMOVUPD 0x80(%R10,%RAX,1),%ZMM1 |
(232) 0x43f058 VMOVUPD %ZMM1,0x80(%R8,%RAX,1) |
(232) 0x43f060 VMOVUPD 0x80(%RDI,%RAX,1),%ZMM2 |
(232) 0x43f068 VMOVUPD %ZMM2,0x80(%RSI,%RAX,1) |
(232) 0x43f070 VMOVUPD 0xc0(%R10,%RAX,1),%ZMM0 |
(232) 0x43f078 VMOVUPD %ZMM0,0xc0(%R8,%RAX,1) |
(232) 0x43f080 VMOVUPD 0xc0(%RDI,%RAX,1),%ZMM5 |
(232) 0x43f088 VMOVUPD %ZMM5,0xc0(%RSI,%RAX,1) |
(232) 0x43f090 VMOVUPD 0x100(%R10,%RAX,1),%ZMM6 |
(232) 0x43f098 VMOVUPD %ZMM6,0x100(%R8,%RAX,1) |
(232) 0x43f0a0 VMOVUPD 0x100(%RDI,%RAX,1),%ZMM7 |
(232) 0x43f0a8 VMOVUPD %ZMM7,0x100(%RSI,%RAX,1) |
(232) 0x43f0b0 VMOVUPD 0x140(%R10,%RAX,1),%ZMM8 |
(232) 0x43f0b8 VMOVUPD %ZMM8,0x140(%R8,%RAX,1) |
(232) 0x43f0c0 VMOVUPD 0x140(%RDI,%RAX,1),%ZMM9 |
(232) 0x43f0c8 VMOVUPD %ZMM9,0x140(%RSI,%RAX,1) |
(232) 0x43f0d0 VMOVUPD 0x180(%R10,%RAX,1),%ZMM10 |
(232) 0x43f0d8 VMOVUPD %ZMM10,0x180(%R8,%RAX,1) |
(232) 0x43f0e0 VMOVUPD 0x180(%RDI,%RAX,1),%ZMM11 |
(232) 0x43f0e8 VMOVUPD %ZMM11,0x180(%RSI,%RAX,1) |
(232) 0x43f0f0 VMOVUPD 0x1c0(%R10,%RAX,1),%ZMM12 |
(232) 0x43f0f8 VMOVUPD %ZMM12,0x1c0(%R8,%RAX,1) |
(232) 0x43f100 VMOVUPD 0x1c0(%RDI,%RAX,1),%ZMM13 |
(232) 0x43f108 VMOVUPD %ZMM13,0x1c0(%RSI,%RAX,1) |
(232) 0x43f110 ADD $0x200,%RAX |
(232) 0x43f116 CMP %RAX,0x58(%RSP) |
(232) 0x43f11b JNE 43f014 |
(231) 0x43f121 MOV 0x7c(%RSP),%R10D |
(231) 0x43f126 MOV %EDX,%R8D |
(231) 0x43f129 AND $-0x8,%R8D |
(231) 0x43f12d ADD %R8D,%R9D |
(231) 0x43f130 LEA (%R8,%R10,1),%ESI |
(231) 0x43f134 TEST $0x7,%DL |
(231) 0x43f137 JE 43f248 |
(231) 0x43f13d SUB %R8D,%EDX |
(231) 0x43f140 LEA -0x1(%RDX),%EDI |
(231) 0x43f143 CMP $0x2,%EDI |
(231) 0x43f146 JBE 43f19f |
(231) 0x43f148 MOVSXD 0x7c(%RSP),%RCX |
(231) 0x43f14d MOV 0x60(%RSP),%R10 |
(231) 0x43f152 MOV 0x68(%RSP),%RDI |
(231) 0x43f157 LEA (%R11,%RCX,1),%RAX |
(231) 0x43f15b ADD %RCX,%R10 |
(231) 0x43f15e ADD %R8,%RAX |
(231) 0x43f161 ADD %RCX,%RDI |
(231) 0x43f164 ADD %R8,%R10 |
(231) 0x43f167 VMOVUPD (%R15,%RAX,8),%YMM14 |
(231) 0x43f16d MOV 0x70(%RSP),%RAX |
(231) 0x43f172 ADD %R8,%RDI |
(231) 0x43f175 VMOVUPD %YMM14,(%R14,%R10,8) |
(231) 0x43f17b ADD %RAX,%RCX |
(231) 0x43f17e VMOVUPD (%R13,%RDI,8),%YMM15 |
(231) 0x43f185 ADD %R8,%RCX |
(231) 0x43f188 VMOVUPD %YMM15,(%R12,%RCX,8) |
(231) 0x43f18e TEST $0x3,%DL |
(231) 0x43f191 JE 43f248 |
(231) 0x43f197 AND $-0x4,%EDX |
(231) 0x43f19a ADD %EDX,%R9D |
(231) 0x43f19d ADD %EDX,%ESI |
(231) 0x43f19f MOVSXD %ESI,%R10 |
(231) 0x43f1a2 MOV 0x60(%RSP),%RCX |
(231) 0x43f1a7 MOV 0x68(%RSP),%RDI |
(231) 0x43f1ac LEA (%R11,%R10,1),%RDX |
(231) 0x43f1b0 VMOVSD (%R15,%RDX,8),%XMM3 |
(231) 0x43f1b6 LEA (%RCX,%R10,1),%R8 |
(231) 0x43f1ba LEA (%RDI,%R10,1),%RAX |
(231) 0x43f1be LEA 0x1(%R9),%EDX |
(231) 0x43f1c2 VMOVSD %XMM3,(%R14,%R8,8) |
(231) 0x43f1c8 MOV 0x70(%RSP),%R8 |
(231) 0x43f1cd VMOVSD (%R13,%RAX,8),%XMM4 |
(231) 0x43f1d4 LEA 0x1(%RSI),%EAX |
(231) 0x43f1d7 ADD %R8,%R10 |
(231) 0x43f1da VMOVSD %XMM4,(%R12,%R10,8) |
(231) 0x43f1e0 MOV 0x78(%RSP),%R10D |
(231) 0x43f1e5 CMP %R10D,%EDX |
(231) 0x43f1e8 JAE 43f248 |
(231) 0x43f1ea CLTQ |
(231) 0x43f1ec ADD $0x2,%R9D |
(231) 0x43f1f0 ADD $0x2,%ESI |
(231) 0x43f1f3 LEA (%R11,%RAX,1),%RDX |
(231) 0x43f1f7 VMOVSD (%R15,%RDX,8),%XMM1 |
(231) 0x43f1fd LEA (%RCX,%RAX,1),%RDX |
(231) 0x43f201 VMOVSD %XMM1,(%R14,%RDX,8) |
(231) 0x43f207 LEA (%RDI,%RAX,1),%RDX |
(231) 0x43f20b ADD %R8,%RAX |
(231) 0x43f20e VMOVSD (%R13,%RDX,8),%XMM2 |
(231) 0x43f215 VMOVSD %XMM2,(%R12,%RAX,8) |
(231) 0x43f21b CMP %R10D,%R9D |
(231) 0x43f21e JAE 43f248 |
(231) 0x43f220 MOVSXD %ESI,%R9 |
(231) 0x43f223 ADD %R9,%R11 |
(231) 0x43f226 ADD %R9,%RCX |
(231) 0x43f229 ADD %R9,%RDI |
(231) 0x43f22c ADD %R9,%R8 |
(231) 0x43f22f VMOVSD (%R15,%R11,8),%XMM0 |
(231) 0x43f235 VMOVSD %XMM0,(%R14,%RCX,8) |
(231) 0x43f23b VMOVSD (%R13,%RDI,8),%XMM5 |
(231) 0x43f242 VMOVSD %XMM5,(%R12,%R8,8) |
(231) 0x43f248 MOV 0x78(%RSP),%R9D |
(231) 0x43f24d INC %RBX |
(231) 0x43f250 MOV 0x50(%RSP),%R11D |
(231) 0x43f255 LEA (%RBX),%R15D |
(231) 0x43f258 CMP %R11D,%R15D |
(231) 0x43f25b JGE 43f280 |
(231) 0x43f25d MOV 0x48(%RSP),%R12D |
(231) 0x43f262 MOV 0x4c(%RSP),%R14D |
(231) 0x43f267 MOV 0x54(%RSP),%EDX |
(231) 0x43f26b MOV %R14D,0x7c(%RSP) |
(231) 0x43f270 SUB %R9D,%R12D |
(231) 0x43f273 JMP 43ee38 |
0x43f278 NOPL (%RAX,%RAX,1) |
0x43f280 VZEROUPPER |
0x43f283 LEA -0x28(%RBP),%RSP |
0x43f287 POP %RBX |
0x43f288 POP %R12 |
0x43f28a POP %R13 |
0x43f28c POP %R14 |
0x43f28e POP %R15 |
0x43f290 POP %RBP |
0x43f291 RET |
0x43f292 NOPW (%RAX,%RAX,1) |
(231) 0x43f298 MOV 0x7c(%RSP),%ESI |
(231) 0x43f29c XOR %R8D,%R8D |
(231) 0x43f29f JMP 43f13d |
0x43f2a4 INC %R12D |
0x43f2a7 XOR %EDX,%EDX |
0x43f2a9 JMP 43edd2 |
0x43f2ae XCHG %AX,%AX |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
○98.24 | gomp_thread_start | team.c:130 | libgomp.so.1.0.0 |
○1.76 | GOMP_parallel | libgomp.h:985 | libgomp.so.1.0.0 |
Path / |
Source file and lines | reset_field.cpp:44-48 |
Module | exec |
nb instructions | 80 |
nb uops | 90 |
loop length | 276 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 10 |
micro-operation queue | 15.00 cycles |
front end | 15.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 5.70 | 8.00 | 6.00 | 6.00 | 8.50 | 5.87 | 5.70 | 8.50 | 8.50 | 8.50 | 5.73 | 6.00 |
cycles | 5.70 | 11.73 | 6.00 | 6.00 | 8.50 | 5.87 | 5.70 | 8.50 | 8.50 | 8.50 | 5.73 | 6.00 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.24-14.34 |
Stall cycles | 0.00 |
Front-end | 15.00 |
Dispatch | 11.73 |
DIV/SQRT | 12.00 |
Overall L1 | 15.00 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 20% |
all | 9% |
load | 10% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 10% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD $-0x80,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x28(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RDI),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x24(%RDI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x3,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA 0x1(%RBX),%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ESI,0x4c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 43f283 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1.lto_priv.0+0x533> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x3(%RCX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 43f283 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1.lto_priv.0+0x533> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R14D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %ESI,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EDI,0x54(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x54(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 43f2a4 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1.lto_priv.0+0x554> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %R12D,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%R12,%R9,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R10D,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R10D,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 43f283 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1.lto_priv.0+0x533> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R9D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x4c(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R13),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x54(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x10(%R13),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R15D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x8(%R13),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%R13),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R11D,0x7c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R11D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %EAX,%RBX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R15,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 43edd2 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1.lto_priv.0+0x82> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | reset_field.cpp:44-48 |
Module | exec |
nb instructions | 80 |
nb uops | 90 |
loop length | 276 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 10 |
micro-operation queue | 15.00 cycles |
front end | 15.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 5.70 | 8.00 | 6.00 | 6.00 | 8.50 | 5.87 | 5.70 | 8.50 | 8.50 | 8.50 | 5.73 | 6.00 |
cycles | 5.70 | 11.73 | 6.00 | 6.00 | 8.50 | 5.87 | 5.70 | 8.50 | 8.50 | 8.50 | 5.73 | 6.00 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.24-14.34 |
Stall cycles | 0.00 |
Front-end | 15.00 |
Dispatch | 11.73 |
DIV/SQRT | 12.00 |
Overall L1 | 15.00 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 20% |
all | 9% |
load | 10% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 10% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD $-0x80,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x28(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RDI),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x24(%RDI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x3,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA 0x1(%RBX),%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ESI,0x4c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 43f283 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1.lto_priv.0+0x533> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x3(%RCX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 43f283 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1.lto_priv.0+0x533> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R14D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %ESI,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EDI,0x54(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x54(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 43f2a4 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1.lto_priv.0+0x554> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %R12D,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%R12,%R9,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R10D,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R10D,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 43f283 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1.lto_priv.0+0x533> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R9D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x4c(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R13),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x54(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x10(%R13),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R15D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x8(%R13),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%R13),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R11D,0x7c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R11D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %EAX,%RBX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R15,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 43edd2 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1.lto_priv.0+0x82> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼reset_field_kernel(int, int, int, int, clover::Buffer2D | 2.05 | 0.68 |
▼Loop 231 - reset_field.cpp:47-48 - exec– | 0 | 0.01 |
○Loop 232 - reset_field.cpp:47-48 - exec | 2.05 | 0.67 |