Function: reset_field_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double> ... | Module: exec | Source: reset_field.cpp:34-38 [...] | Coverage: 1.88% |
---|
Function: reset_field_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double> ... | Module: exec | Source: reset_field.cpp:34-38 [...] | Coverage: 1.88% |
---|
/scratch_na/users/xoserete/qaas_runs/171-415-4969/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/reset_field.cpp: 34 - 38 |
-------------------------------------------------------------------------------- |
34: #pragma omp parallel for simd collapse(2) |
35: for (int j = (y_min + 1); j < (y_max + 2); j++) { |
36: for (int i = (x_min + 1); i < (x_max + 2); i++) { |
37: density0(i, j) = density1(i, j); |
38: energy0(i, j) = energy1(i, j); |
/scratch_na/users/xoserete/qaas_runs/171-415-4969/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69 |
-------------------------------------------------------------------------------- |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
0x43e7f0 PUSH %RBP |
0x43e7f1 MOV %RSP,%RBP |
0x43e7f4 PUSH %R15 |
0x43e7f6 PUSH %R14 |
0x43e7f8 PUSH %R13 |
0x43e7fa PUSH %R12 |
0x43e7fc PUSH %RBX |
0x43e7fd AND $-0x40,%RSP |
0x43e801 ADD $-0x80,%RSP |
0x43e805 MOV 0x28(%RDI),%EAX |
0x43e808 MOV 0x2c(%RDI),%EDX |
0x43e80b MOV 0x20(%RDI),%EBX |
0x43e80e MOV 0x24(%RDI),%ECX |
0x43e811 ADD $0x2,%EDX |
0x43e814 LEA 0x1(%RAX),%R15D |
0x43e818 LEA 0x1(%RBX),%ESI |
0x43e81b MOV %EDX,0x50(%RSP) |
0x43e81f MOV %ESI,0x4c(%RSP) |
0x43e823 CMP %EDX,%R15D |
0x43e826 JGE 43ed23 |
0x43e82c MOV %EDX,%EBX |
0x43e82e LEA 0x2(%RCX),%R14D |
0x43e832 SUB %R15D,%EBX |
0x43e835 CMP %R14D,%ESI |
0x43e838 JGE 43ed23 |
0x43e83e MOV %RDI,%R13 |
0x43e841 MOV %R14D,%EDI |
0x43e844 SUB %ESI,%EDI |
0x43e846 MOV %EDI,0x54(%RSP) |
0x43e84a CALL 4046c0 <omp_get_num_threads@plt> |
0x43e84f MOV %EAX,%R12D |
0x43e852 CALL 4045b0 <omp_get_thread_num@plt> |
0x43e857 XOR %EDX,%EDX |
0x43e859 MOV %EAX,%R8D |
0x43e85c MOV 0x54(%RSP),%EAX |
0x43e860 IMUL %EBX,%EAX |
0x43e863 DIV %R12D |
0x43e866 MOV %EAX,%R12D |
0x43e869 CMP %EDX,%R8D |
0x43e86c JB 43ed44 |
0x43e872 IMUL %R12D,%R8D |
0x43e876 LEA (%R8,%RDX,1),%R9D |
0x43e87a LEA (%R12,%R9,1),%R10D |
0x43e87e MOV %R10D,0x48(%RSP) |
0x43e883 CMP %R10D,%R9D |
0x43e886 JAE 43ed23 |
0x43e88c MOV %R9D,%EAX |
0x43e88f XOR %EDX,%EDX |
0x43e891 MOV 0x4c(%RSP),%R11D |
0x43e896 MOV (%R13),%RSI |
0x43e89a DIVL 0x54(%RSP) |
0x43e89e MOV 0x10(%R13),%RBX |
0x43e8a2 MOV %RSI,0x38(%RSP) |
0x43e8a7 MOV %RBX,0x28(%RSP) |
0x43e8ac ADD %EDX,%R11D |
0x43e8af ADD %R15D,%EAX |
0x43e8b2 MOV %R14D,%EDX |
0x43e8b5 MOV 0x8(%R13),%R15 |
0x43e8b9 MOV 0x18(%R13),%R14 |
0x43e8bd MOV %R11D,0x7c(%RSP) |
0x43e8c2 SUB %R11D,%EDX |
0x43e8c5 MOVSXD %EAX,%RBX |
0x43e8c8 MOV %R15,0x40(%RSP) |
0x43e8cd MOV %R14,0x30(%RSP) |
0x43e8d2 NOPW (%RAX,%RAX,1) |
(229) 0x43e8d8 CMP %EDX,%R12D |
(229) 0x43e8db CMOVBE %R12D,%EDX |
(229) 0x43e8df LEA (%R9,%RDX,1),%ECX |
(229) 0x43e8e3 MOV %ECX,0x78(%RSP) |
(229) 0x43e8e7 CMP %ECX,%R9D |
(229) 0x43e8ea JAE 43eced |
(229) 0x43e8f0 MOV 0x30(%RSP),%R12 |
(229) 0x43e8f5 MOV 0x38(%RSP),%RDI |
(229) 0x43e8fa LEA -0x1(%RDX),%EAX |
(229) 0x43e8fd MOV 0x28(%RSP),%RCX |
(229) 0x43e902 MOV 0x40(%RSP),%R13 |
(229) 0x43e907 MOV (%R12),%RSI |
(229) 0x43e90b MOV (%RDI),%R8 |
(229) 0x43e90e MOV (%RCX),%R10 |
(229) 0x43e911 MOV (%R13),%R11 |
(229) 0x43e915 IMUL %RBX,%R8 |
(229) 0x43e919 MOV 0x10(%R13),%R15 |
(229) 0x43e91d MOV 0x10(%RDI),%R14 |
(229) 0x43e921 IMUL %RBX,%RSI |
(229) 0x43e925 MOV 0x10(%R12),%R13 |
(229) 0x43e92a MOV 0x10(%RCX),%R12 |
(229) 0x43e92e IMUL %RBX,%R10 |
(229) 0x43e932 IMUL %RBX,%R11 |
(229) 0x43e936 MOV %R8,0x60(%RSP) |
(229) 0x43e93b MOV %RSI,0x68(%RSP) |
(229) 0x43e940 MOV %R10,0x70(%RSP) |
(229) 0x43e945 CMP $0x6,%EAX |
(229) 0x43e948 JBE 43ed38 |
(229) 0x43e94e MOVSXD 0x7c(%RSP),%RAX |
(229) 0x43e953 LEA (%R8,%RAX,1),%RCX |
(229) 0x43e957 LEA (%R11,%RAX,1),%RDI |
(229) 0x43e95b LEA (%R14,%RCX,8),%R8 |
(229) 0x43e95f MOV 0x70(%RSP),%RCX |
(229) 0x43e964 LEA (%RSI,%RAX,1),%RSI |
(229) 0x43e968 LEA (%R15,%RDI,8),%R10 |
(229) 0x43e96c LEA (%R13,%RSI,8),%RDI |
(229) 0x43e971 ADD %RCX,%RAX |
(229) 0x43e974 MOV %EDX,%ECX |
(229) 0x43e976 SHR $0x3,%ECX |
(229) 0x43e979 LEA (%R12,%RAX,8),%RSI |
(229) 0x43e97d XOR %EAX,%EAX |
(229) 0x43e97f SAL $0x6,%RCX |
(229) 0x43e983 MOV %RCX,0x58(%RSP) |
(229) 0x43e988 SUB $0x40,%RCX |
(229) 0x43e98c SHR $0x6,%RCX |
(229) 0x43e990 INC %RCX |
(229) 0x43e993 AND $0x7,%ECX |
(229) 0x43e996 JE 43eab4 |
(229) 0x43e99c CMP $0x1,%RCX |
(229) 0x43e9a0 JE 43ea89 |
(229) 0x43e9a6 CMP $0x2,%RCX |
(229) 0x43e9aa JE 43ea69 |
(229) 0x43e9b0 CMP $0x3,%RCX |
(229) 0x43e9b4 JE 43ea49 |
(229) 0x43e9ba CMP $0x4,%RCX |
(229) 0x43e9be JE 43ea29 |
(229) 0x43e9c0 CMP $0x5,%RCX |
(229) 0x43e9c4 JE 43ea09 |
(229) 0x43e9c6 CMP $0x6,%RCX |
(229) 0x43e9ca JE 43e9e9 |
(229) 0x43e9cc VMOVUPD (%R10),%ZMM3 |
(229) 0x43e9d2 MOV $0x40,%EAX |
(229) 0x43e9d7 VMOVUPD %ZMM3,(%R8) |
(229) 0x43e9dd VMOVUPD (%RDI),%ZMM4 |
(229) 0x43e9e3 VMOVUPD %ZMM4,(%RSI) |
(229) 0x43e9e9 VMOVUPD (%R10,%RAX,1),%ZMM1 |
(229) 0x43e9f0 VMOVUPD %ZMM1,(%R8,%RAX,1) |
(229) 0x43e9f7 VMOVUPD (%RDI,%RAX,1),%ZMM2 |
(229) 0x43e9fe VMOVUPD %ZMM2,(%RSI,%RAX,1) |
(229) 0x43ea05 ADD $0x40,%RAX |
(229) 0x43ea09 VMOVUPD (%R10,%RAX,1),%ZMM0 |
(229) 0x43ea10 VMOVUPD %ZMM0,(%R8,%RAX,1) |
(229) 0x43ea17 VMOVUPD (%RDI,%RAX,1),%ZMM5 |
(229) 0x43ea1e VMOVUPD %ZMM5,(%RSI,%RAX,1) |
(229) 0x43ea25 ADD $0x40,%RAX |
(229) 0x43ea29 VMOVUPD (%R10,%RAX,1),%ZMM6 |
(229) 0x43ea30 VMOVUPD %ZMM6,(%R8,%RAX,1) |
(229) 0x43ea37 VMOVUPD (%RDI,%RAX,1),%ZMM7 |
(229) 0x43ea3e VMOVUPD %ZMM7,(%RSI,%RAX,1) |
(229) 0x43ea45 ADD $0x40,%RAX |
(229) 0x43ea49 VMOVUPD (%R10,%RAX,1),%ZMM8 |
(229) 0x43ea50 VMOVUPD %ZMM8,(%R8,%RAX,1) |
(229) 0x43ea57 VMOVUPD (%RDI,%RAX,1),%ZMM9 |
(229) 0x43ea5e VMOVUPD %ZMM9,(%RSI,%RAX,1) |
(229) 0x43ea65 ADD $0x40,%RAX |
(229) 0x43ea69 VMOVUPD (%R10,%RAX,1),%ZMM10 |
(229) 0x43ea70 VMOVUPD %ZMM10,(%R8,%RAX,1) |
(229) 0x43ea77 VMOVUPD (%RDI,%RAX,1),%ZMM11 |
(229) 0x43ea7e VMOVUPD %ZMM11,(%RSI,%RAX,1) |
(229) 0x43ea85 ADD $0x40,%RAX |
(229) 0x43ea89 VMOVUPD (%R10,%RAX,1),%ZMM12 |
(229) 0x43ea90 VMOVUPD %ZMM12,(%R8,%RAX,1) |
(229) 0x43ea97 VMOVUPD (%RDI,%RAX,1),%ZMM13 |
(229) 0x43ea9e VMOVUPD %ZMM13,(%RSI,%RAX,1) |
(229) 0x43eaa5 ADD $0x40,%RAX |
(229) 0x43eaa9 CMP %RAX,0x58(%RSP) |
(229) 0x43eaae JE 43ebc1 |
(230) 0x43eab4 VMOVUPD (%R10,%RAX,1),%ZMM14 |
(230) 0x43eabb VMOVUPD %ZMM14,(%R8,%RAX,1) |
(230) 0x43eac2 VMOVUPD (%RDI,%RAX,1),%ZMM15 |
(230) 0x43eac9 VMOVUPD %ZMM15,(%RSI,%RAX,1) |
(230) 0x43ead0 VMOVUPD 0x40(%R10,%RAX,1),%ZMM3 |
(230) 0x43ead8 VMOVUPD %ZMM3,0x40(%R8,%RAX,1) |
(230) 0x43eae0 VMOVUPD 0x40(%RDI,%RAX,1),%ZMM4 |
(230) 0x43eae8 VMOVUPD %ZMM4,0x40(%RSI,%RAX,1) |
(230) 0x43eaf0 VMOVUPD 0x80(%R10,%RAX,1),%ZMM1 |
(230) 0x43eaf8 VMOVUPD %ZMM1,0x80(%R8,%RAX,1) |
(230) 0x43eb00 VMOVUPD 0x80(%RDI,%RAX,1),%ZMM2 |
(230) 0x43eb08 VMOVUPD %ZMM2,0x80(%RSI,%RAX,1) |
(230) 0x43eb10 VMOVUPD 0xc0(%R10,%RAX,1),%ZMM0 |
(230) 0x43eb18 VMOVUPD %ZMM0,0xc0(%R8,%RAX,1) |
(230) 0x43eb20 VMOVUPD 0xc0(%RDI,%RAX,1),%ZMM5 |
(230) 0x43eb28 VMOVUPD %ZMM5,0xc0(%RSI,%RAX,1) |
(230) 0x43eb30 VMOVUPD 0x100(%R10,%RAX,1),%ZMM6 |
(230) 0x43eb38 VMOVUPD %ZMM6,0x100(%R8,%RAX,1) |
(230) 0x43eb40 VMOVUPD 0x100(%RDI,%RAX,1),%ZMM7 |
(230) 0x43eb48 VMOVUPD %ZMM7,0x100(%RSI,%RAX,1) |
(230) 0x43eb50 VMOVUPD 0x140(%R10,%RAX,1),%ZMM8 |
(230) 0x43eb58 VMOVUPD %ZMM8,0x140(%R8,%RAX,1) |
(230) 0x43eb60 VMOVUPD 0x140(%RDI,%RAX,1),%ZMM9 |
(230) 0x43eb68 VMOVUPD %ZMM9,0x140(%RSI,%RAX,1) |
(230) 0x43eb70 VMOVUPD 0x180(%R10,%RAX,1),%ZMM10 |
(230) 0x43eb78 VMOVUPD %ZMM10,0x180(%R8,%RAX,1) |
(230) 0x43eb80 VMOVUPD 0x180(%RDI,%RAX,1),%ZMM11 |
(230) 0x43eb88 VMOVUPD %ZMM11,0x180(%RSI,%RAX,1) |
(230) 0x43eb90 VMOVUPD 0x1c0(%R10,%RAX,1),%ZMM12 |
(230) 0x43eb98 VMOVUPD %ZMM12,0x1c0(%R8,%RAX,1) |
(230) 0x43eba0 VMOVUPD 0x1c0(%RDI,%RAX,1),%ZMM13 |
(230) 0x43eba8 VMOVUPD %ZMM13,0x1c0(%RSI,%RAX,1) |
(230) 0x43ebb0 ADD $0x200,%RAX |
(230) 0x43ebb6 CMP %RAX,0x58(%RSP) |
(230) 0x43ebbb JNE 43eab4 |
(229) 0x43ebc1 MOV 0x7c(%RSP),%R10D |
(229) 0x43ebc6 MOV %EDX,%R8D |
(229) 0x43ebc9 AND $-0x8,%R8D |
(229) 0x43ebcd ADD %R8D,%R9D |
(229) 0x43ebd0 LEA (%R8,%R10,1),%ESI |
(229) 0x43ebd4 TEST $0x7,%DL |
(229) 0x43ebd7 JE 43ece8 |
(229) 0x43ebdd SUB %R8D,%EDX |
(229) 0x43ebe0 LEA -0x1(%RDX),%EDI |
(229) 0x43ebe3 CMP $0x2,%EDI |
(229) 0x43ebe6 JBE 43ec3f |
(229) 0x43ebe8 MOVSXD 0x7c(%RSP),%RCX |
(229) 0x43ebed MOV 0x60(%RSP),%R10 |
(229) 0x43ebf2 MOV 0x68(%RSP),%RDI |
(229) 0x43ebf7 LEA (%R11,%RCX,1),%RAX |
(229) 0x43ebfb ADD %RCX,%R10 |
(229) 0x43ebfe ADD %R8,%RAX |
(229) 0x43ec01 ADD %RCX,%RDI |
(229) 0x43ec04 ADD %R8,%R10 |
(229) 0x43ec07 VMOVUPD (%R15,%RAX,8),%YMM14 |
(229) 0x43ec0d MOV 0x70(%RSP),%RAX |
(229) 0x43ec12 ADD %R8,%RDI |
(229) 0x43ec15 VMOVUPD %YMM14,(%R14,%R10,8) |
(229) 0x43ec1b ADD %RAX,%RCX |
(229) 0x43ec1e VMOVUPD (%R13,%RDI,8),%YMM15 |
(229) 0x43ec25 ADD %R8,%RCX |
(229) 0x43ec28 VMOVUPD %YMM15,(%R12,%RCX,8) |
(229) 0x43ec2e TEST $0x3,%DL |
(229) 0x43ec31 JE 43ece8 |
(229) 0x43ec37 AND $-0x4,%EDX |
(229) 0x43ec3a ADD %EDX,%R9D |
(229) 0x43ec3d ADD %EDX,%ESI |
(229) 0x43ec3f MOVSXD %ESI,%R10 |
(229) 0x43ec42 MOV 0x60(%RSP),%RCX |
(229) 0x43ec47 MOV 0x68(%RSP),%RDI |
(229) 0x43ec4c LEA (%R11,%R10,1),%RDX |
(229) 0x43ec50 VMOVSD (%R15,%RDX,8),%XMM3 |
(229) 0x43ec56 LEA (%RCX,%R10,1),%R8 |
(229) 0x43ec5a LEA (%RDI,%R10,1),%RAX |
(229) 0x43ec5e LEA 0x1(%R9),%EDX |
(229) 0x43ec62 VMOVSD %XMM3,(%R14,%R8,8) |
(229) 0x43ec68 MOV 0x70(%RSP),%R8 |
(229) 0x43ec6d VMOVSD (%R13,%RAX,8),%XMM4 |
(229) 0x43ec74 LEA 0x1(%RSI),%EAX |
(229) 0x43ec77 ADD %R8,%R10 |
(229) 0x43ec7a VMOVSD %XMM4,(%R12,%R10,8) |
(229) 0x43ec80 MOV 0x78(%RSP),%R10D |
(229) 0x43ec85 CMP %R10D,%EDX |
(229) 0x43ec88 JAE 43ece8 |
(229) 0x43ec8a CLTQ |
(229) 0x43ec8c ADD $0x2,%R9D |
(229) 0x43ec90 ADD $0x2,%ESI |
(229) 0x43ec93 LEA (%R11,%RAX,1),%RDX |
(229) 0x43ec97 VMOVSD (%R15,%RDX,8),%XMM1 |
(229) 0x43ec9d LEA (%RCX,%RAX,1),%RDX |
(229) 0x43eca1 VMOVSD %XMM1,(%R14,%RDX,8) |
(229) 0x43eca7 LEA (%RDI,%RAX,1),%RDX |
(229) 0x43ecab ADD %R8,%RAX |
(229) 0x43ecae VMOVSD (%R13,%RDX,8),%XMM2 |
(229) 0x43ecb5 VMOVSD %XMM2,(%R12,%RAX,8) |
(229) 0x43ecbb CMP %R10D,%R9D |
(229) 0x43ecbe JAE 43ece8 |
(229) 0x43ecc0 MOVSXD %ESI,%R9 |
(229) 0x43ecc3 ADD %R9,%R11 |
(229) 0x43ecc6 ADD %R9,%RCX |
(229) 0x43ecc9 ADD %R9,%RDI |
(229) 0x43eccc ADD %R9,%R8 |
(229) 0x43eccf VMOVSD (%R15,%R11,8),%XMM0 |
(229) 0x43ecd5 VMOVSD %XMM0,(%R14,%RCX,8) |
(229) 0x43ecdb VMOVSD (%R13,%RDI,8),%XMM5 |
(229) 0x43ece2 VMOVSD %XMM5,(%R12,%R8,8) |
(229) 0x43ece8 MOV 0x78(%RSP),%R9D |
(229) 0x43eced INC %RBX |
(229) 0x43ecf0 MOV 0x50(%RSP),%R11D |
(229) 0x43ecf5 LEA (%RBX),%R15D |
(229) 0x43ecf8 CMP %R11D,%R15D |
(229) 0x43ecfb JGE 43ed20 |
(229) 0x43ecfd MOV 0x48(%RSP),%R12D |
(229) 0x43ed02 MOV 0x4c(%RSP),%R14D |
(229) 0x43ed07 MOV 0x54(%RSP),%EDX |
(229) 0x43ed0b MOV %R14D,0x7c(%RSP) |
(229) 0x43ed10 SUB %R9D,%R12D |
(229) 0x43ed13 JMP 43e8d8 |
0x43ed18 NOPL (%RAX,%RAX,1) |
0x43ed20 VZEROUPPER |
0x43ed23 LEA -0x28(%RBP),%RSP |
0x43ed27 POP %RBX |
0x43ed28 POP %R12 |
0x43ed2a POP %R13 |
0x43ed2c POP %R14 |
0x43ed2e POP %R15 |
0x43ed30 POP %RBP |
0x43ed31 RET |
0x43ed32 NOPW (%RAX,%RAX,1) |
(229) 0x43ed38 MOV 0x7c(%RSP),%ESI |
(229) 0x43ed3c XOR %R8D,%R8D |
(229) 0x43ed3f JMP 43ebdd |
0x43ed44 INC %R12D |
0x43ed47 XOR %EDX,%EDX |
0x43ed49 JMP 43e872 |
0x43ed4e XCHG %AX,%AX |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
○98.13 | gomp_thread_start | team.c:130 | libgomp.so.1.0.0 |
○1.84 | GOMP_parallel | libgomp.h:985 | libgomp.so.1.0.0 |
Path / |
Source file and lines | reset_field.cpp:34-38 |
Module | exec |
nb instructions | 80 |
nb uops | 90 |
loop length | 276 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 10 |
micro-operation queue | 15.00 cycles |
front end | 15.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 5.70 | 8.00 | 6.00 | 6.00 | 8.50 | 5.87 | 5.70 | 8.50 | 8.50 | 8.50 | 5.73 | 6.00 |
cycles | 5.70 | 11.73 | 6.00 | 6.00 | 8.50 | 5.87 | 5.70 | 8.50 | 8.50 | 8.50 | 5.73 | 6.00 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.24-14.34 |
Stall cycles | 0.00 |
Front-end | 15.00 |
Dispatch | 11.73 |
DIV/SQRT | 12.00 |
Overall L1 | 15.00 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 20% |
all | 9% |
load | 10% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 10% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD $-0x80,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x28(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RDI),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x24(%RDI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x2,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA 0x1(%RBX),%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ESI,0x4c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 43ed23 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0.lto_priv.0+0x533> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x2(%RCX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 43ed23 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0.lto_priv.0+0x533> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R14D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %ESI,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EDI,0x54(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x54(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 43ed44 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0.lto_priv.0+0x554> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %R12D,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%R12,%R9,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R10D,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R10D,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 43ed23 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0.lto_priv.0+0x533> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R9D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x4c(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R13),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x54(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x10(%R13),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R15D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x8(%R13),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%R13),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R11D,0x7c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R11D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %EAX,%RBX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R15,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 43e872 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0.lto_priv.0+0x82> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | reset_field.cpp:34-38 |
Module | exec |
nb instructions | 80 |
nb uops | 90 |
loop length | 276 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 10 |
micro-operation queue | 15.00 cycles |
front end | 15.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 5.70 | 8.00 | 6.00 | 6.00 | 8.50 | 5.87 | 5.70 | 8.50 | 8.50 | 8.50 | 5.73 | 6.00 |
cycles | 5.70 | 11.73 | 6.00 | 6.00 | 8.50 | 5.87 | 5.70 | 8.50 | 8.50 | 8.50 | 5.73 | 6.00 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.24-14.34 |
Stall cycles | 0.00 |
Front-end | 15.00 |
Dispatch | 11.73 |
DIV/SQRT | 12.00 |
Overall L1 | 15.00 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 20% |
all | 9% |
load | 10% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 10% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD $-0x80,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x28(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RDI),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x24(%RDI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x2,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA 0x1(%RBX),%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ESI,0x4c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 43ed23 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0.lto_priv.0+0x533> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x2(%RCX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 43ed23 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0.lto_priv.0+0x533> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R14D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %ESI,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EDI,0x54(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x54(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 43ed44 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0.lto_priv.0+0x554> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %R12D,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%R12,%R9,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R10D,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R10D,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 43ed23 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0.lto_priv.0+0x533> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R9D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x4c(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R13),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x54(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x10(%R13),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R15D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x8(%R13),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%R13),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R11D,0x7c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R11D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %EAX,%RBX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R15,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 43e872 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0.lto_priv.0+0x82> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼reset_field_kernel(int, int, int, int, clover::Buffer2D | 1.88 | 0.62 |
▼Loop 229 - reset_field.cpp:37-38 - exec– | 0.01 | 0.01 |
○Loop 230 - reset_field.cpp:37-38 - exec | 1.87 | 0.62 |