Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ... | Module: exec | Source: advec_cell.cpp:117-125 [...] | Coverage: 2.66% |
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Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ... | Module: exec | Source: advec_cell.cpp:117-125 [...] | Coverage: 2.66% |
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/scratch_na/users/xoserete/qaas_runs/171-415-4969/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp: 117 - 125 |
-------------------------------------------------------------------------------- |
117: #pragma omp parallel for simd collapse(2) |
118: for (int j = (y_min + 1); j < (y_max + 2); j++) { |
119: for (int i = (x_min + 1); i < (x_max + 2); i++) { |
120: double pre_mass_s = density1(i, j) * pre_vol(i, j); |
121: double post_mass_s = pre_mass_s + mass_flux_x(i, j) - mass_flux_x(i + 1, j + 0); |
122: double post_ener_s = (energy1(i, j) * pre_mass_s + ener_flux(i, j) - ener_flux(i + 1, j + 0)) / post_mass_s; |
123: double advec_vol_s = pre_vol(i, j) + vol_flux_x(i, j) - vol_flux_x(i + 1, j + 0); |
124: density1(i, j) = post_mass_s / advec_vol_s; |
125: energy1(i, j) = post_ener_s; |
/scratch_na/users/xoserete/qaas_runs/171-415-4969/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69 |
-------------------------------------------------------------------------------- |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
0x426630 PUSH %RBP |
0x426631 MOV %RSP,%RBP |
0x426634 PUSH %R15 |
0x426636 PUSH %R14 |
0x426638 PUSH %R13 |
0x42663a PUSH %R12 |
0x42663c PUSH %RBX |
0x42663d AND $-0x40,%RSP |
0x426641 SUB $0xc0,%RSP |
0x426648 MOV 0x38(%RDI),%EAX |
0x42664b MOV 0x3c(%RDI),%ECX |
0x42664e MOV 0x30(%RDI),%ESI |
0x426651 MOV 0x34(%RDI),%EDX |
0x426654 ADD $0x2,%ECX |
0x426657 LEA 0x1(%RAX),%R15D |
0x42665b INC %ESI |
0x42665d MOV %ECX,0x48(%RSP) |
0x426661 MOV %ESI,0x44(%RSP) |
0x426665 CMP %ECX,%R15D |
0x426668 JGE 426d6b |
0x42666e MOV %ECX,%R13D |
0x426671 LEA 0x2(%RDX),%R14D |
0x426675 SUB %R15D,%R13D |
0x426678 CMP %R14D,%ESI |
0x42667b JGE 426d6b |
0x426681 MOV %RDI,%RBX |
0x426684 MOV %R14D,%EDI |
0x426687 SUB %ESI,%EDI |
0x426689 MOV %EDI,0x4c(%RSP) |
0x42668d CALL 4046c0 <omp_get_num_threads@plt> |
0x426692 MOV %EAX,%R12D |
0x426695 CALL 4045b0 <omp_get_thread_num@plt> |
0x42669a XOR %EDX,%EDX |
0x42669c MOV %EAX,%R8D |
0x42669f MOV 0x4c(%RSP),%EAX |
0x4266a3 IMUL %R13D,%EAX |
0x4266a7 DIV %R12D |
0x4266aa MOV %EAX,%ECX |
0x4266ac CMP %EDX,%R8D |
0x4266af JB 426d8f |
0x4266b5 IMUL %ECX,%R8D |
0x4266b9 LEA (%R8,%RDX,1),%R10D |
0x4266bd LEA (%RCX,%R10,1),%R9D |
0x4266c1 MOV %R9D,0x40(%RSP) |
0x4266c6 CMP %R9D,%R10D |
0x4266c9 JAE 426d6b |
0x4266cf MOV %R10D,%EAX |
0x4266d2 XOR %EDX,%EDX |
0x4266d4 MOV 0x44(%RSP),%R11D |
0x4266d9 MOV (%RBX),%RSI |
0x4266dc DIVL 0x4c(%RSP) |
0x4266e0 MOV 0x10(%RBX),%R13 |
0x4266e4 MOV 0x8(%RBX),%RDI |
0x4266e8 MOV 0x28(%RBX),%R12 |
0x4266ec MOV %RSI,0x30(%RSP) |
0x4266f1 MOV %R13,0x20(%RSP) |
0x4266f6 MOV %RDI,0x18(%RSP) |
0x4266fb MOV %R12,0x10(%RSP) |
0x426700 MOV %R14D,%R9D |
0x426703 MOV 0x20(%RBX),%R14 |
0x426707 MOV 0x18(%RBX),%RBX |
0x42670b MOV %R14,0x28(%RSP) |
0x426710 MOV %RBX,0x8(%RSP) |
0x426715 LEA (%RAX,%R15,1),%R15D |
0x426719 ADD %EDX,%R11D |
0x42671c MOVSXD %R15D,%R8 |
0x42671f MOV %R11D,0x9c(%RSP) |
0x426727 SUB %R11D,%R9D |
0x42672a MOV %R8,0xb8(%RSP) |
0x426732 NOPW (%RAX,%RAX,1) |
(112) 0x426738 CMP %R9D,%ECX |
(112) 0x42673b CMOVBE %ECX,%R9D |
(112) 0x42673f LEA (%R10,%R9,1),%ECX |
(112) 0x426743 MOV %R9D,%EDX |
(112) 0x426746 MOV %ECX,0x98(%RSP) |
(112) 0x42674d CMP %ECX,%R10D |
(112) 0x426750 JAE 426d2b |
(112) 0x426756 MOV 0x20(%RSP),%RSI |
(112) 0x42675b MOV 0x30(%RSP),%R9 |
(112) 0x426760 MOV 0x18(%RSP),%R14 |
(112) 0x426765 MOV 0x28(%RSP),%RAX |
(112) 0x42676a MOV 0x10(%RSI),%R11 |
(112) 0x42676e MOV 0x10(%R9),%R15 |
(112) 0x426772 MOV 0x10(%R14),%R12 |
(112) 0x426776 MOV (%R9),%RBX |
(112) 0x426779 MOV 0x10(%RSP),%R9 |
(112) 0x42677e MOV 0xb8(%RSP),%RCX |
(112) 0x426786 MOV %R11,0xb0(%RSP) |
(112) 0x42678e MOV (%RSI),%R11 |
(112) 0x426791 MOV 0x8(%RSP),%RSI |
(112) 0x426796 MOV %R12,0xa0(%RSP) |
(112) 0x42679e MOV 0x10(%RAX),%R13 |
(112) 0x4267a2 MOV (%RAX),%RDI |
(112) 0x4267a5 IMUL %RCX,%RBX |
(112) 0x4267a9 MOV %R15,0x78(%RSP) |
(112) 0x4267ae MOV (%R14),%R8 |
(112) 0x4267b1 MOV 0x10(%R9),%R12 |
(112) 0x4267b5 IMUL %RCX,%R11 |
(112) 0x4267b9 MOV (%R9),%R9 |
(112) 0x4267bc MOV (%RSI),%RAX |
(112) 0x4267bf IMUL %RCX,%RDI |
(112) 0x4267c3 MOV %R13,0x88(%RSP) |
(112) 0x4267cb IMUL %RCX,%R8 |
(112) 0x4267cf MOV %RBX,0x70(%RSP) |
(112) 0x4267d4 MOV 0x10(%RSI),%R14 |
(112) 0x4267d8 IMUL %RCX,%R9 |
(112) 0x4267dc MOV %R11,0x58(%RSP) |
(112) 0x4267e1 IMUL %RCX,%RAX |
(112) 0x4267e5 LEA -0x1(%RDX),%ECX |
(112) 0x4267e8 MOV %RDI,0x80(%RSP) |
(112) 0x4267f0 MOV %R8,0x90(%RSP) |
(112) 0x4267f8 MOV %R9,0x60(%RSP) |
(112) 0x4267fd MOV %RAX,0xa8(%RSP) |
(112) 0x426805 CMP $0x6,%ECX |
(112) 0x426808 JBE 426d80 |
(112) 0x42680e MOVSXD 0x9c(%RSP),%RAX |
(112) 0x426816 LEA (%RBX,%RAX,1),%RBX |
(112) 0x42681a LEA (%R9,%RAX,1),%R9 |
(112) 0x42681e LEA (%R15,%RBX,8),%RSI |
(112) 0x426822 LEA (%RDI,%RAX,1),%R15 |
(112) 0x426826 SAL $0x3,%R9 |
(112) 0x42682a LEA (%R11,%RAX,1),%RDI |
(112) 0x42682e MOV 0xb0(%RSP),%R11 |
(112) 0x426836 LEA (%R13,%R15,8),%R13 |
(112) 0x42683b SAL $0x3,%RDI |
(112) 0x42683f LEA (%R8,%RAX,1),%R15 |
(112) 0x426843 MOV 0xa0(%RSP),%R8 |
(112) 0x42684b LEA 0x8(%R11,%RDI,1),%RCX |
(112) 0x426850 LEA (%R11,%RDI,1),%RBX |
(112) 0x426854 MOV 0xa8(%RSP),%RDI |
(112) 0x42685c MOV %RCX,0x50(%RSP) |
(112) 0x426861 LEA (%R8,%R15,8),%RCX |
(112) 0x426865 LEA (%R12,%R9,1),%R11 |
(112) 0x426869 ADD %RDI,%RAX |
(112) 0x42686c LEA 0x8(%R12,%R9,1),%R9 |
(112) 0x426871 SAL $0x3,%RAX |
(112) 0x426875 LEA (%R14,%RAX,1),%R8 |
(112) 0x426879 LEA 0x8(%R14,%RAX,1),%RDI |
(112) 0x42687e MOV %EDX,%EAX |
(112) 0x426880 SHR $0x3,%EAX |
(112) 0x426883 MOV %EAX,%R15D |
(112) 0x426886 MOV %R15,%RAX |
(112) 0x426889 SAL $0x6,%RAX |
(112) 0x42688d MOV %RAX,0x68(%RSP) |
(112) 0x426892 XOR %EAX,%EAX |
(112) 0x426894 AND $0x1,%R15D |
(112) 0x426898 JE 4268ff |
(112) 0x42689a VMOVUPD (%R13),%ZMM0 |
(112) 0x4268a1 VMOVUPD (%R11),%ZMM7 |
(112) 0x4268a7 MOV $0x40,%EAX |
(112) 0x4268ac MOV 0x50(%RSP),%R15 |
(112) 0x4268b1 CMPQ $0x40,0x68(%RSP) |
(112) 0x4268b7 VMULPD (%RSI),%ZMM0,%ZMM1 |
(112) 0x4268bd VSUBPD (%R9),%ZMM7,%ZMM3 |
(112) 0x4268c3 VADDPD (%R8),%ZMM0,%ZMM5 |
(112) 0x4268c9 VSUBPD (%RDI),%ZMM5,%ZMM6 |
(112) 0x4268cf VSUBPD (%R15),%ZMM1,%ZMM2 |
(112) 0x4268d5 VFMADD132PD (%RCX),%ZMM3,%ZMM1 |
(112) 0x4268db VADDPD (%RBX),%ZMM2,%ZMM4 |
(112) 0x4268e1 VDIVPD %ZMM6,%ZMM4,%ZMM8 |
(112) 0x4268e7 VDIVPD %ZMM4,%ZMM1,%ZMM9 |
(112) 0x4268ed VMOVUPD %ZMM8,(%RSI) |
(112) 0x4268f3 VMOVUPD %ZMM9,(%RCX) |
(112) 0x4268f9 JE 4269eb |
(112) 0x4268ff MOV %R10D,0x3c(%RSP) |
(112) 0x426904 MOV 0xb8(%RSP),%R15 |
(112) 0x42690c MOV 0x50(%RSP),%R10 |
(113) 0x426911 VMOVUPD (%R13,%RAX,1),%ZMM10 |
(113) 0x426919 VMOVUPD (%R11,%RAX,1),%ZMM14 |
(113) 0x426920 VMULPD (%RSI,%RAX,1),%ZMM10,%ZMM11 |
(113) 0x426927 VSUBPD (%R9,%RAX,1),%ZMM14,%ZMM15 |
(113) 0x42692e VADDPD (%R8,%RAX,1),%ZMM10,%ZMM0 |
(113) 0x426935 VSUBPD (%RDI,%RAX,1),%ZMM0,%ZMM1 |
(113) 0x42693c VSUBPD (%R10,%RAX,1),%ZMM11,%ZMM12 |
(113) 0x426943 VFMADD132PD (%RCX,%RAX,1),%ZMM15,%ZMM11 |
(113) 0x42694a VADDPD (%RBX,%RAX,1),%ZMM12,%ZMM13 |
(113) 0x426951 VDIVPD %ZMM13,%ZMM11,%ZMM4 |
(113) 0x426957 VDIVPD %ZMM1,%ZMM13,%ZMM2 |
(113) 0x42695d VMOVUPD %ZMM2,(%RSI,%RAX,1) |
(113) 0x426964 VMOVUPD %ZMM4,(%RCX,%RAX,1) |
(113) 0x42696b VMOVUPD 0x40(%R13,%RAX,1),%ZMM7 |
(113) 0x426973 VMOVUPD 0x40(%R11,%RAX,1),%ZMM5 |
(113) 0x42697b VMULPD 0x40(%RSI,%RAX,1),%ZMM7,%ZMM6 |
(113) 0x426983 VSUBPD 0x40(%R9,%RAX,1),%ZMM5,%ZMM9 |
(113) 0x42698b VADDPD 0x40(%R8,%RAX,1),%ZMM7,%ZMM10 |
(113) 0x426993 VSUBPD 0x40(%RDI,%RAX,1),%ZMM10,%ZMM11 |
(113) 0x42699b VSUBPD 0x40(%R10,%RAX,1),%ZMM6,%ZMM3 |
(113) 0x4269a3 VFMADD132PD 0x40(%RCX,%RAX,1),%ZMM9,%ZMM6 |
(113) 0x4269ab VADDPD 0x40(%RBX,%RAX,1),%ZMM3,%ZMM8 |
(113) 0x4269b3 VDIVPD %ZMM11,%ZMM8,%ZMM12 |
(113) 0x4269b9 VDIVPD %ZMM8,%ZMM6,%ZMM13 |
(113) 0x4269bf VMOVUPD %ZMM12,0x40(%RSI,%RAX,1) |
(113) 0x4269c7 VMOVUPD %ZMM13,0x40(%RCX,%RAX,1) |
(113) 0x4269cf SUB $-0x80,%RAX |
(113) 0x4269d3 CMP %RAX,0x68(%RSP) |
(113) 0x4269d8 JNE 426911 |
(112) 0x4269de MOV %R15,0xb8(%RSP) |
(112) 0x4269e6 MOV 0x3c(%RSP),%R10D |
(112) 0x4269eb MOV 0x9c(%RSP),%ESI |
(112) 0x4269f2 MOV %EDX,%R13D |
(112) 0x4269f5 AND $-0x8,%R13D |
(112) 0x4269f9 ADD %R13D,%R10D |
(112) 0x4269fc LEA (%R13,%RSI,1),%ESI |
(112) 0x426a01 TEST $0x7,%DL |
(112) 0x426a04 JE 426d23 |
(112) 0x426a0a SUB %R13D,%EDX |
(112) 0x426a0d LEA -0x1(%RDX),%EBX |
(112) 0x426a10 CMP $0x2,%EBX |
(112) 0x426a13 JBE 426af2 |
(112) 0x426a19 MOVSXD 0x9c(%RSP),%RAX |
(112) 0x426a21 MOV 0x70(%RSP),%RCX |
(112) 0x426a26 MOV 0x90(%RSP),%RDI |
(112) 0x426a2e MOV 0x78(%RSP),%R9 |
(112) 0x426a33 LEA (%RCX,%RAX,1),%R11 |
(112) 0x426a37 MOV 0xa0(%RSP),%R15 |
(112) 0x426a3f MOV 0x58(%RSP),%R8 |
(112) 0x426a44 ADD %RAX,%RDI |
(112) 0x426a47 ADD %R13,%R11 |
(112) 0x426a4a MOV 0x60(%RSP),%RCX |
(112) 0x426a4f ADD %R13,%RDI |
(112) 0x426a52 LEA (%R9,%R11,8),%RBX |
(112) 0x426a56 LEA (%R8,%RAX,1),%R9 |
(112) 0x426a5a LEA (%R15,%RDI,8),%R11 |
(112) 0x426a5e MOV 0xa8(%RSP),%RDI |
(112) 0x426a66 MOV 0x80(%RSP),%R15 |
(112) 0x426a6e LEA (%RCX,%RAX,1),%R8 |
(112) 0x426a72 ADD %R13,%R9 |
(112) 0x426a75 ADD %R13,%R8 |
(112) 0x426a78 ADD %RAX,%RDI |
(112) 0x426a7b ADD %R15,%RAX |
(112) 0x426a7e VMOVUPD 0x8(%R12,%R8,8),%YMM4 |
(112) 0x426a85 VMOVUPD (%R12,%R8,8),%YMM1 |
(112) 0x426a8b ADD %R13,%RDI |
(112) 0x426a8e ADD %R13,%RAX |
(112) 0x426a91 MOV 0x88(%RSP),%R13 |
(112) 0x426a99 VMOVUPD (%R13,%RAX,8),%YMM14 |
(112) 0x426aa0 MOV 0xb0(%RSP),%RAX |
(112) 0x426aa8 VMULPD (%RBX),%YMM14,%YMM15 |
(112) 0x426aac VADDPD (%R14,%RDI,8),%YMM14,%YMM7 |
(112) 0x426ab2 VSUBPD 0x8(%R14,%RDI,8),%YMM7,%YMM6 |
(112) 0x426ab9 VADDPD (%RAX,%R9,8),%YMM15,%YMM0 |
(112) 0x426abf VFMSUB132PD (%R11),%YMM4,%YMM15 |
(112) 0x426ac4 VSUBPD 0x8(%RAX,%R9,8),%YMM0,%YMM2 |
(112) 0x426acb VADDPD %YMM15,%YMM1,%YMM8 |
(112) 0x426ad0 VDIVPD %YMM6,%YMM2,%YMM3 |
(112) 0x426ad4 VDIVPD %YMM2,%YMM8,%YMM5 |
(112) 0x426ad8 VMOVUPD %YMM3,(%RBX) |
(112) 0x426adc VMOVUPD %YMM5,(%R11) |
(112) 0x426ae1 TEST $0x3,%DL |
(112) 0x426ae4 JE 426d23 |
(112) 0x426aea AND $-0x4,%EDX |
(112) 0x426aed ADD %EDX,%R10D |
(112) 0x426af0 ADD %EDX,%ESI |
(112) 0x426af2 MOV 0x80(%RSP),%RCX |
(112) 0x426afa MOVSXD %ESI,%RDX |
(112) 0x426afd MOV 0x88(%RSP),%RDI |
(112) 0x426b05 LEA 0x1(%RSI),%EAX |
(112) 0x426b08 MOV 0x70(%RSP),%R9 |
(112) 0x426b0d MOV 0x78(%RSP),%RBX |
(112) 0x426b12 CLTQ |
(112) 0x426b14 LEA (%RCX,%RDX,1),%R8 |
(112) 0x426b18 MOV 0xb0(%RSP),%R13 |
(112) 0x426b20 VMOVSD (%RDI,%R8,8),%XMM9 |
(112) 0x426b26 ADD %RDX,%R9 |
(112) 0x426b29 MOV 0x90(%RSP),%RDI |
(112) 0x426b31 LEA (%RBX,%R9,8),%R11 |
(112) 0x426b35 MOV 0x58(%RSP),%RBX |
(112) 0x426b3a MOV 0xa0(%RSP),%R8 |
(112) 0x426b42 VMULSD (%R11),%XMM9,%XMM10 |
(112) 0x426b47 ADD %RDX,%RDI |
(112) 0x426b4a LEA (%RBX,%RDX,1),%RCX |
(112) 0x426b4e LEA (%RAX,%RBX,1),%R15 |
(112) 0x426b52 LEA (%R13,%R15,8),%R9 |
(112) 0x426b57 VADDSD (%R13,%RCX,8),%XMM10,%XMM11 |
(112) 0x426b5e MOV 0x60(%RSP),%R13 |
(112) 0x426b63 LEA (%R8,%RDI,8),%RCX |
(112) 0x426b67 LEA (%R13,%RDX,1),%R15 |
(112) 0x426b6c LEA (%R13,%RAX,1),%RDI |
(112) 0x426b71 VMOVSD (%R12,%R15,8),%XMM13 |
(112) 0x426b77 LEA (%R12,%RDI,8),%R8 |
(112) 0x426b7b MOV 0xa8(%RSP),%R15 |
(112) 0x426b83 VMOVSD (%R8),%XMM14 |
(112) 0x426b88 VSUBSD (%R9),%XMM11,%XMM12 |
(112) 0x426b8d ADD %R15,%RDX |
(112) 0x426b90 MOV %R15,%RDI |
(112) 0x426b93 VADDSD (%R14,%RDX,8),%XMM9,%XMM15 |
(112) 0x426b99 VFMSUB132SD (%RCX),%XMM14,%XMM10 |
(112) 0x426b9e LEA 0x1(%R10),%EDX |
(112) 0x426ba2 ADD %RAX,%RDI |
(112) 0x426ba5 LEA (%R14,%RDI,8),%RDI |
(112) 0x426ba9 VSUBSD (%RDI),%XMM15,%XMM0 |
(112) 0x426bad VADDSD %XMM13,%XMM10,%XMM1 |
(112) 0x426bb2 VDIVSD %XMM0,%XMM12,%XMM2 |
(112) 0x426bb6 VDIVSD %XMM12,%XMM1,%XMM4 |
(112) 0x426bbb VMOVSD %XMM2,(%R11) |
(112) 0x426bc0 MOV 0x98(%RSP),%R11D |
(112) 0x426bc8 VMOVSD %XMM4,(%RCX) |
(112) 0x426bcc CMP %R11D,%EDX |
(112) 0x426bcf JAE 426d23 |
(112) 0x426bd5 MOV 0x70(%RSP),%RCX |
(112) 0x426bda MOV 0x78(%RSP),%R15 |
(112) 0x426bdf ADD $0x2,%R10D |
(112) 0x426be3 MOV 0x80(%RSP),%RDX |
(112) 0x426beb MOV 0x88(%RSP),%R11 |
(112) 0x426bf3 ADD %RAX,%RCX |
(112) 0x426bf6 VMOVSD (%R8),%XMM5 |
(112) 0x426bfb LEA (%R15,%RCX,8),%RCX |
(112) 0x426bff LEA (%RAX,%RDX,1),%R15 |
(112) 0x426c03 VMOVSD (%R11,%R15,8),%XMM7 |
(112) 0x426c09 LEA 0x2(%RSI),%EDX |
(112) 0x426c0c MOV 0xb0(%RSP),%R15 |
(112) 0x426c14 MOVSXD %EDX,%RDX |
(112) 0x426c17 VMULSD (%RCX),%XMM7,%XMM6 |
(112) 0x426c1b LEA (%RBX,%RDX,1),%R11 |
(112) 0x426c1f VADDSD (%RDI),%XMM7,%XMM10 |
(112) 0x426c23 LEA (%R15,%R11,8),%R11 |
(112) 0x426c27 MOV 0xa0(%RSP),%R15 |
(112) 0x426c2f MOV 0x98(%RSP),%EDI |
(112) 0x426c36 VSUBSD (%R11),%XMM6,%XMM3 |
(112) 0x426c3b VADDSD (%R9),%XMM3,%XMM8 |
(112) 0x426c40 MOV 0x90(%RSP),%R9 |
(112) 0x426c48 ADD %R9,%RAX |
(112) 0x426c4b LEA (%R13,%RDX,1),%R9 |
(112) 0x426c50 LEA (%R12,%R9,8),%R9 |
(112) 0x426c54 LEA (%R15,%RAX,8),%RAX |
(112) 0x426c58 MOV 0xa8(%RSP),%R15 |
(112) 0x426c60 VSUBSD (%R9),%XMM5,%XMM9 |
(112) 0x426c65 LEA (%R15,%RDX,1),%R8 |
(112) 0x426c69 LEA (%R14,%R8,8),%R8 |
(112) 0x426c6d VFMADD132SD (%RAX),%XMM9,%XMM6 |
(112) 0x426c72 VSUBSD (%R8),%XMM10,%XMM11 |
(112) 0x426c77 VDIVSD %XMM11,%XMM8,%XMM12 |
(112) 0x426c7c VDIVSD %XMM8,%XMM6,%XMM13 |
(112) 0x426c81 VMOVSD %XMM12,(%RCX) |
(112) 0x426c85 VMOVSD %XMM13,(%RAX) |
(112) 0x426c89 CMP %EDI,%R10D |
(112) 0x426c8c JAE 426d23 |
(112) 0x426c92 MOV 0x70(%RSP),%RCX |
(112) 0x426c97 MOV 0x78(%RSP),%R10 |
(112) 0x426c9c ADD $0x3,%ESI |
(112) 0x426c9f MOV 0x80(%RSP),%RDI |
(112) 0x426ca7 MOVSXD %ESI,%RSI |
(112) 0x426caa VMOVSD (%R9),%XMM1 |
(112) 0x426caf ADD %RDX,%RCX |
(112) 0x426cb2 ADD %RSI,%RBX |
(112) 0x426cb5 ADD %RSI,%R13 |
(112) 0x426cb8 ADD %RSI,%R15 |
(112) 0x426cbb LEA (%R10,%RCX,8),%RAX |
(112) 0x426cbf MOV 0x88(%RSP),%RCX |
(112) 0x426cc7 ADD %RDX,%RDI |
(112) 0x426cca MOV 0xb0(%RSP),%R10 |
(112) 0x426cd2 VSUBSD (%R12,%R13,8),%XMM1,%XMM4 |
(112) 0x426cd8 VMOVSD (%RCX,%RDI,8),%XMM14 |
(112) 0x426cdd MOV 0xa0(%RSP),%RDI |
(112) 0x426ce5 VMULSD (%RAX),%XMM14,%XMM15 |
(112) 0x426ce9 VADDSD (%R8),%XMM14,%XMM7 |
(112) 0x426cee VSUBSD (%R14,%R15,8),%XMM7,%XMM6 |
(112) 0x426cf4 VSUBSD (%R10,%RBX,8),%XMM15,%XMM0 |
(112) 0x426cfa VADDSD (%R11),%XMM0,%XMM2 |
(112) 0x426cff MOV 0x90(%RSP),%R11 |
(112) 0x426d07 ADD %RDX,%R11 |
(112) 0x426d0a LEA (%RDI,%R11,8),%RBX |
(112) 0x426d0e VDIVSD %XMM6,%XMM2,%XMM3 |
(112) 0x426d12 VFMADD132SD (%RBX),%XMM4,%XMM15 |
(112) 0x426d17 VDIVSD %XMM2,%XMM15,%XMM8 |
(112) 0x426d1b VMOVSD %XMM3,(%RAX) |
(112) 0x426d1f VMOVSD %XMM8,(%RBX) |
(112) 0x426d23 MOV 0x98(%RSP),%R10D |
(112) 0x426d2b INCQ 0xb8(%RSP) |
(112) 0x426d33 MOV 0xb8(%RSP),%R12 |
(112) 0x426d3b ADD $0,%R12D |
(112) 0x426d3f CMP %R12D,0x48(%RSP) |
(112) 0x426d44 JLE 426d68 |
(112) 0x426d46 MOV 0x40(%RSP),%ECX |
(112) 0x426d4a MOV 0x44(%RSP),%R14D |
(112) 0x426d4f MOV 0x4c(%RSP),%R9D |
(112) 0x426d54 MOV %R14D,0x9c(%RSP) |
(112) 0x426d5c SUB %R10D,%ECX |
(112) 0x426d5f JMP 426738 |
0x426d64 NOPL (%RAX) |
0x426d68 VZEROUPPER |
0x426d6b LEA -0x28(%RBP),%RSP |
0x426d6f POP %RBX |
0x426d70 POP %R12 |
0x426d72 POP %R13 |
0x426d74 POP %R14 |
0x426d76 POP %R15 |
0x426d78 POP %RBP |
0x426d79 RET |
0x426d7a NOPW (%RAX,%RAX,1) |
(112) 0x426d80 MOV 0x9c(%RSP),%ESI |
(112) 0x426d87 XOR %R13D,%R13D |
(112) 0x426d8a JMP 426a0a |
0x426d8f INC %ECX |
0x426d91 XOR %EDX,%EDX |
0x426d93 JMP 4266b5 |
0x426d98 NOPL (%RAX,%RAX,1) |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
○98.11 | gomp_thread_start | team.c:130 | libgomp.so.1.0.0 |
○1.89 | GOMP_parallel | libgomp.h:985 | libgomp.so.1.0.0 |
Path / |
Source file and lines | advec_cell.cpp:117-125 |
Module | exec |
nb instructions | 85 |
nb uops | 95 |
loop length | 309 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 13 |
micro-operation queue | 15.83 cycles |
front end | 15.83 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.10 | 8.00 | 6.67 | 6.67 | 10.00 | 6.07 | 5.90 | 10.00 | 10.00 | 10.00 | 5.93 | 6.67 |
cycles | 6.10 | 11.93 | 6.67 | 6.67 | 10.00 | 6.07 | 5.90 | 10.00 | 10.00 | 10.00 | 5.93 | 6.67 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 15.08-15.21 |
Stall cycles | 0.00 |
Front-end | 15.83 |
Dispatch | 11.93 |
DIV/SQRT | 12.00 |
Overall L1 | 15.83 |
all | 3% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 12% |
all | 8% |
load | 9% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 8% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0xc0,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x38(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x3c(%RDI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x30(%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x34(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x2,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
INC %ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ECX,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ESI,0x44(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %ECX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 426d6b <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3.lto_priv.0+0x73b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %ECX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x2(%RDX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%R13D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 426d6b <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3.lto_priv.0+0x73b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R14D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %ESI,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EDI,0x4c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x4c(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %R13D,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 426d8f <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3.lto_priv.0+0x75f> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %ECX,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RCX,%R10,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R9D,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R9D,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 426d6b <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3.lto_priv.0+0x73b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R10D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x44(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RBX),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x4c(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x10(%RBX),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RBX),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RBX),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R13,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDI,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,0x10(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14D,%R9D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x20(%RBX),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RBX),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R14,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%RAX,%R15,1),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD %EDX,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %R15D,%R8 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R11D,0x9c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R11D,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R8,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 4266b5 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3.lto_priv.0+0x85> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | advec_cell.cpp:117-125 |
Module | exec |
nb instructions | 85 |
nb uops | 95 |
loop length | 309 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 13 |
micro-operation queue | 15.83 cycles |
front end | 15.83 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.10 | 8.00 | 6.67 | 6.67 | 10.00 | 6.07 | 5.90 | 10.00 | 10.00 | 10.00 | 5.93 | 6.67 |
cycles | 6.10 | 11.93 | 6.67 | 6.67 | 10.00 | 6.07 | 5.90 | 10.00 | 10.00 | 10.00 | 5.93 | 6.67 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 15.08-15.21 |
Stall cycles | 0.00 |
Front-end | 15.83 |
Dispatch | 11.93 |
DIV/SQRT | 12.00 |
Overall L1 | 15.83 |
all | 3% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 12% |
all | 8% |
load | 9% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 8% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0xc0,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x38(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x3c(%RDI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x30(%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x34(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x2,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
INC %ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ECX,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ESI,0x44(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %ECX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 426d6b <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3.lto_priv.0+0x73b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %ECX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x2(%RDX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%R13D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 426d6b <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3.lto_priv.0+0x73b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R14D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %ESI,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EDI,0x4c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x4c(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %R13D,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 426d8f <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3.lto_priv.0+0x75f> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %ECX,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RCX,%R10,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R9D,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R9D,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 426d6b <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3.lto_priv.0+0x73b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R10D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x44(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RBX),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x4c(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x10(%RBX),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RBX),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RBX),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R13,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDI,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,0x10(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14D,%R9D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x20(%RBX),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RBX),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R14,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%RAX,%R15,1),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD %EDX,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %R15D,%R8 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R11D,0x9c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R11D,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R8,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 4266b5 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3.lto_priv.0+0x85> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D | 2.66 | 0.88 |
▼Loop 112 - advec_cell.cpp:120-125 - exec– | 0.01 | 0 |
○Loop 113 - advec_cell.cpp:120-125 - exec | 2.66 | 0.87 |