Function: revert_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, cl ... | Module: exec | Source: revert.cpp:34-38 [...] | Coverage: 1.79% |
---|
Function: revert_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, cl ... | Module: exec | Source: revert.cpp:34-38 [...] | Coverage: 1.79% |
---|
/scratch_na/users/xoserete/qaas_runs/171-415-4969/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/revert.cpp: 34 - 38 |
-------------------------------------------------------------------------------- |
34: #pragma omp parallel for simd collapse(2) |
35: for (int j = (y_min + 1); j < (y_max + 2); j++) { |
36: for (int i = (x_min + 1); i < (x_max + 2); i++) { |
37: density1(i, j) = density0(i, j); |
38: energy1(i, j) = energy0(i, j); |
/scratch_na/users/xoserete/qaas_runs/171-415-4969/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69 |
-------------------------------------------------------------------------------- |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
0x43c8c0 PUSH %RBP |
0x43c8c1 MOV %RSP,%RBP |
0x43c8c4 PUSH %R15 |
0x43c8c6 PUSH %R14 |
0x43c8c8 PUSH %R13 |
0x43c8ca PUSH %R12 |
0x43c8cc PUSH %RBX |
0x43c8cd AND $-0x40,%RSP |
0x43c8d1 ADD $-0x80,%RSP |
0x43c8d5 MOV 0x28(%RDI),%EAX |
0x43c8d8 MOV 0x2c(%RDI),%EDX |
0x43c8db MOV 0x20(%RDI),%EBX |
0x43c8de MOV 0x24(%RDI),%ECX |
0x43c8e1 ADD $0x2,%EDX |
0x43c8e4 LEA 0x1(%RAX),%R15D |
0x43c8e8 LEA 0x1(%RBX),%ESI |
0x43c8eb MOV %EDX,0x50(%RSP) |
0x43c8ef MOV %ESI,0x4c(%RSP) |
0x43c8f3 CMP %EDX,%R15D |
0x43c8f6 JGE 43cdf3 |
0x43c8fc MOV %EDX,%EBX |
0x43c8fe LEA 0x2(%RCX),%R14D |
0x43c902 SUB %R15D,%EBX |
0x43c905 CMP %R14D,%ESI |
0x43c908 JGE 43cdf3 |
0x43c90e MOV %RDI,%R13 |
0x43c911 MOV %R14D,%EDI |
0x43c914 SUB %ESI,%EDI |
0x43c916 MOV %EDI,0x54(%RSP) |
0x43c91a CALL 4046c0 <omp_get_num_threads@plt> |
0x43c91f MOV %EAX,%R12D |
0x43c922 CALL 4045b0 <omp_get_thread_num@plt> |
0x43c927 XOR %EDX,%EDX |
0x43c929 MOV %EAX,%R8D |
0x43c92c MOV 0x54(%RSP),%EAX |
0x43c930 IMUL %EBX,%EAX |
0x43c933 DIV %R12D |
0x43c936 MOV %EAX,%R12D |
0x43c939 CMP %EDX,%R8D |
0x43c93c JB 43ce14 |
0x43c942 IMUL %R12D,%R8D |
0x43c946 LEA (%R8,%RDX,1),%R9D |
0x43c94a LEA (%R12,%R9,1),%R10D |
0x43c94e MOV %R10D,0x48(%RSP) |
0x43c953 CMP %R10D,%R9D |
0x43c956 JAE 43cdf3 |
0x43c95c MOV %R9D,%EAX |
0x43c95f XOR %EDX,%EDX |
0x43c961 MOV 0x4c(%RSP),%R11D |
0x43c966 MOV 0x8(%R13),%RSI |
0x43c96a DIVL 0x54(%RSP) |
0x43c96e MOV 0x18(%R13),%RBX |
0x43c972 MOV %RSI,0x38(%RSP) |
0x43c977 MOV %RBX,0x28(%RSP) |
0x43c97c ADD %EDX,%R11D |
0x43c97f ADD %R15D,%EAX |
0x43c982 MOV %R14D,%EDX |
0x43c985 MOV (%R13),%R15 |
0x43c989 MOV 0x10(%R13),%R14 |
0x43c98d MOV %R11D,0x7c(%RSP) |
0x43c992 SUB %R11D,%EDX |
0x43c995 MOVSXD %EAX,%RBX |
0x43c998 MOV %R15,0x40(%RSP) |
0x43c99d MOV %R14,0x30(%RSP) |
0x43c9a2 NOPW (%RAX,%RAX,1) |
(221) 0x43c9a8 CMP %EDX,%R12D |
(221) 0x43c9ab CMOVBE %R12D,%EDX |
(221) 0x43c9af LEA (%R9,%RDX,1),%ECX |
(221) 0x43c9b3 MOV %ECX,0x78(%RSP) |
(221) 0x43c9b7 CMP %ECX,%R9D |
(221) 0x43c9ba JAE 43cdbd |
(221) 0x43c9c0 MOV 0x30(%RSP),%R12 |
(221) 0x43c9c5 MOV 0x38(%RSP),%RDI |
(221) 0x43c9ca LEA -0x1(%RDX),%EAX |
(221) 0x43c9cd MOV 0x28(%RSP),%RCX |
(221) 0x43c9d2 MOV 0x40(%RSP),%R13 |
(221) 0x43c9d7 MOV (%R12),%RSI |
(221) 0x43c9db MOV (%RDI),%R8 |
(221) 0x43c9de MOV (%RCX),%R10 |
(221) 0x43c9e1 MOV (%R13),%R11 |
(221) 0x43c9e5 IMUL %RBX,%R8 |
(221) 0x43c9e9 MOV 0x10(%R13),%R15 |
(221) 0x43c9ed MOV 0x10(%RDI),%R14 |
(221) 0x43c9f1 IMUL %RBX,%RSI |
(221) 0x43c9f5 MOV 0x10(%R12),%R13 |
(221) 0x43c9fa MOV 0x10(%RCX),%R12 |
(221) 0x43c9fe IMUL %RBX,%R10 |
(221) 0x43ca02 IMUL %RBX,%R11 |
(221) 0x43ca06 MOV %R8,0x60(%RSP) |
(221) 0x43ca0b MOV %RSI,0x68(%RSP) |
(221) 0x43ca10 MOV %R10,0x70(%RSP) |
(221) 0x43ca15 CMP $0x6,%EAX |
(221) 0x43ca18 JBE 43ce08 |
(221) 0x43ca1e MOVSXD 0x7c(%RSP),%RAX |
(221) 0x43ca23 LEA (%R8,%RAX,1),%RCX |
(221) 0x43ca27 LEA (%R11,%RAX,1),%RDI |
(221) 0x43ca2b LEA (%R14,%RCX,8),%R8 |
(221) 0x43ca2f MOV 0x70(%RSP),%RCX |
(221) 0x43ca34 LEA (%RSI,%RAX,1),%RSI |
(221) 0x43ca38 LEA (%R15,%RDI,8),%R10 |
(221) 0x43ca3c LEA (%R13,%RSI,8),%RDI |
(221) 0x43ca41 ADD %RCX,%RAX |
(221) 0x43ca44 MOV %EDX,%ECX |
(221) 0x43ca46 SHR $0x3,%ECX |
(221) 0x43ca49 LEA (%R12,%RAX,8),%RSI |
(221) 0x43ca4d XOR %EAX,%EAX |
(221) 0x43ca4f SAL $0x6,%RCX |
(221) 0x43ca53 MOV %RCX,0x58(%RSP) |
(221) 0x43ca58 SUB $0x40,%RCX |
(221) 0x43ca5c SHR $0x6,%RCX |
(221) 0x43ca60 INC %RCX |
(221) 0x43ca63 AND $0x7,%ECX |
(221) 0x43ca66 JE 43cb84 |
(221) 0x43ca6c CMP $0x1,%RCX |
(221) 0x43ca70 JE 43cb59 |
(221) 0x43ca76 CMP $0x2,%RCX |
(221) 0x43ca7a JE 43cb39 |
(221) 0x43ca80 CMP $0x3,%RCX |
(221) 0x43ca84 JE 43cb19 |
(221) 0x43ca8a CMP $0x4,%RCX |
(221) 0x43ca8e JE 43caf9 |
(221) 0x43ca90 CMP $0x5,%RCX |
(221) 0x43ca94 JE 43cad9 |
(221) 0x43ca96 CMP $0x6,%RCX |
(221) 0x43ca9a JE 43cab9 |
(221) 0x43ca9c VMOVUPD (%R10),%ZMM3 |
(221) 0x43caa2 MOV $0x40,%EAX |
(221) 0x43caa7 VMOVUPD %ZMM3,(%R8) |
(221) 0x43caad VMOVUPD (%RDI),%ZMM4 |
(221) 0x43cab3 VMOVUPD %ZMM4,(%RSI) |
(221) 0x43cab9 VMOVUPD (%R10,%RAX,1),%ZMM1 |
(221) 0x43cac0 VMOVUPD %ZMM1,(%R8,%RAX,1) |
(221) 0x43cac7 VMOVUPD (%RDI,%RAX,1),%ZMM2 |
(221) 0x43cace VMOVUPD %ZMM2,(%RSI,%RAX,1) |
(221) 0x43cad5 ADD $0x40,%RAX |
(221) 0x43cad9 VMOVUPD (%R10,%RAX,1),%ZMM0 |
(221) 0x43cae0 VMOVUPD %ZMM0,(%R8,%RAX,1) |
(221) 0x43cae7 VMOVUPD (%RDI,%RAX,1),%ZMM5 |
(221) 0x43caee VMOVUPD %ZMM5,(%RSI,%RAX,1) |
(221) 0x43caf5 ADD $0x40,%RAX |
(221) 0x43caf9 VMOVUPD (%R10,%RAX,1),%ZMM6 |
(221) 0x43cb00 VMOVUPD %ZMM6,(%R8,%RAX,1) |
(221) 0x43cb07 VMOVUPD (%RDI,%RAX,1),%ZMM7 |
(221) 0x43cb0e VMOVUPD %ZMM7,(%RSI,%RAX,1) |
(221) 0x43cb15 ADD $0x40,%RAX |
(221) 0x43cb19 VMOVUPD (%R10,%RAX,1),%ZMM8 |
(221) 0x43cb20 VMOVUPD %ZMM8,(%R8,%RAX,1) |
(221) 0x43cb27 VMOVUPD (%RDI,%RAX,1),%ZMM9 |
(221) 0x43cb2e VMOVUPD %ZMM9,(%RSI,%RAX,1) |
(221) 0x43cb35 ADD $0x40,%RAX |
(221) 0x43cb39 VMOVUPD (%R10,%RAX,1),%ZMM10 |
(221) 0x43cb40 VMOVUPD %ZMM10,(%R8,%RAX,1) |
(221) 0x43cb47 VMOVUPD (%RDI,%RAX,1),%ZMM11 |
(221) 0x43cb4e VMOVUPD %ZMM11,(%RSI,%RAX,1) |
(221) 0x43cb55 ADD $0x40,%RAX |
(221) 0x43cb59 VMOVUPD (%R10,%RAX,1),%ZMM12 |
(221) 0x43cb60 VMOVUPD %ZMM12,(%R8,%RAX,1) |
(221) 0x43cb67 VMOVUPD (%RDI,%RAX,1),%ZMM13 |
(221) 0x43cb6e VMOVUPD %ZMM13,(%RSI,%RAX,1) |
(221) 0x43cb75 ADD $0x40,%RAX |
(221) 0x43cb79 CMP %RAX,0x58(%RSP) |
(221) 0x43cb7e JE 43cc91 |
(222) 0x43cb84 VMOVUPD (%R10,%RAX,1),%ZMM14 |
(222) 0x43cb8b VMOVUPD %ZMM14,(%R8,%RAX,1) |
(222) 0x43cb92 VMOVUPD (%RDI,%RAX,1),%ZMM15 |
(222) 0x43cb99 VMOVUPD %ZMM15,(%RSI,%RAX,1) |
(222) 0x43cba0 VMOVUPD 0x40(%R10,%RAX,1),%ZMM3 |
(222) 0x43cba8 VMOVUPD %ZMM3,0x40(%R8,%RAX,1) |
(222) 0x43cbb0 VMOVUPD 0x40(%RDI,%RAX,1),%ZMM4 |
(222) 0x43cbb8 VMOVUPD %ZMM4,0x40(%RSI,%RAX,1) |
(222) 0x43cbc0 VMOVUPD 0x80(%R10,%RAX,1),%ZMM1 |
(222) 0x43cbc8 VMOVUPD %ZMM1,0x80(%R8,%RAX,1) |
(222) 0x43cbd0 VMOVUPD 0x80(%RDI,%RAX,1),%ZMM2 |
(222) 0x43cbd8 VMOVUPD %ZMM2,0x80(%RSI,%RAX,1) |
(222) 0x43cbe0 VMOVUPD 0xc0(%R10,%RAX,1),%ZMM0 |
(222) 0x43cbe8 VMOVUPD %ZMM0,0xc0(%R8,%RAX,1) |
(222) 0x43cbf0 VMOVUPD 0xc0(%RDI,%RAX,1),%ZMM5 |
(222) 0x43cbf8 VMOVUPD %ZMM5,0xc0(%RSI,%RAX,1) |
(222) 0x43cc00 VMOVUPD 0x100(%R10,%RAX,1),%ZMM6 |
(222) 0x43cc08 VMOVUPD %ZMM6,0x100(%R8,%RAX,1) |
(222) 0x43cc10 VMOVUPD 0x100(%RDI,%RAX,1),%ZMM7 |
(222) 0x43cc18 VMOVUPD %ZMM7,0x100(%RSI,%RAX,1) |
(222) 0x43cc20 VMOVUPD 0x140(%R10,%RAX,1),%ZMM8 |
(222) 0x43cc28 VMOVUPD %ZMM8,0x140(%R8,%RAX,1) |
(222) 0x43cc30 VMOVUPD 0x140(%RDI,%RAX,1),%ZMM9 |
(222) 0x43cc38 VMOVUPD %ZMM9,0x140(%RSI,%RAX,1) |
(222) 0x43cc40 VMOVUPD 0x180(%R10,%RAX,1),%ZMM10 |
(222) 0x43cc48 VMOVUPD %ZMM10,0x180(%R8,%RAX,1) |
(222) 0x43cc50 VMOVUPD 0x180(%RDI,%RAX,1),%ZMM11 |
(222) 0x43cc58 VMOVUPD %ZMM11,0x180(%RSI,%RAX,1) |
(222) 0x43cc60 VMOVUPD 0x1c0(%R10,%RAX,1),%ZMM12 |
(222) 0x43cc68 VMOVUPD %ZMM12,0x1c0(%R8,%RAX,1) |
(222) 0x43cc70 VMOVUPD 0x1c0(%RDI,%RAX,1),%ZMM13 |
(222) 0x43cc78 VMOVUPD %ZMM13,0x1c0(%RSI,%RAX,1) |
(222) 0x43cc80 ADD $0x200,%RAX |
(222) 0x43cc86 CMP %RAX,0x58(%RSP) |
(222) 0x43cc8b JNE 43cb84 |
(221) 0x43cc91 MOV 0x7c(%RSP),%R10D |
(221) 0x43cc96 MOV %EDX,%R8D |
(221) 0x43cc99 AND $-0x8,%R8D |
(221) 0x43cc9d ADD %R8D,%R9D |
(221) 0x43cca0 LEA (%R8,%R10,1),%ESI |
(221) 0x43cca4 TEST $0x7,%DL |
(221) 0x43cca7 JE 43cdb8 |
(221) 0x43ccad SUB %R8D,%EDX |
(221) 0x43ccb0 LEA -0x1(%RDX),%EDI |
(221) 0x43ccb3 CMP $0x2,%EDI |
(221) 0x43ccb6 JBE 43cd0f |
(221) 0x43ccb8 MOVSXD 0x7c(%RSP),%RCX |
(221) 0x43ccbd MOV 0x60(%RSP),%R10 |
(221) 0x43ccc2 MOV 0x68(%RSP),%RDI |
(221) 0x43ccc7 LEA (%R11,%RCX,1),%RAX |
(221) 0x43cccb ADD %RCX,%R10 |
(221) 0x43ccce ADD %R8,%RAX |
(221) 0x43ccd1 ADD %RCX,%RDI |
(221) 0x43ccd4 ADD %R8,%R10 |
(221) 0x43ccd7 VMOVUPD (%R15,%RAX,8),%YMM14 |
(221) 0x43ccdd MOV 0x70(%RSP),%RAX |
(221) 0x43cce2 ADD %R8,%RDI |
(221) 0x43cce5 VMOVUPD %YMM14,(%R14,%R10,8) |
(221) 0x43cceb ADD %RAX,%RCX |
(221) 0x43ccee VMOVUPD (%R13,%RDI,8),%YMM15 |
(221) 0x43ccf5 ADD %R8,%RCX |
(221) 0x43ccf8 VMOVUPD %YMM15,(%R12,%RCX,8) |
(221) 0x43ccfe TEST $0x3,%DL |
(221) 0x43cd01 JE 43cdb8 |
(221) 0x43cd07 AND $-0x4,%EDX |
(221) 0x43cd0a ADD %EDX,%R9D |
(221) 0x43cd0d ADD %EDX,%ESI |
(221) 0x43cd0f MOVSXD %ESI,%R10 |
(221) 0x43cd12 MOV 0x60(%RSP),%RCX |
(221) 0x43cd17 MOV 0x68(%RSP),%RDI |
(221) 0x43cd1c LEA (%R11,%R10,1),%RDX |
(221) 0x43cd20 VMOVSD (%R15,%RDX,8),%XMM3 |
(221) 0x43cd26 LEA (%RCX,%R10,1),%R8 |
(221) 0x43cd2a LEA (%RDI,%R10,1),%RAX |
(221) 0x43cd2e LEA 0x1(%R9),%EDX |
(221) 0x43cd32 VMOVSD %XMM3,(%R14,%R8,8) |
(221) 0x43cd38 MOV 0x70(%RSP),%R8 |
(221) 0x43cd3d VMOVSD (%R13,%RAX,8),%XMM4 |
(221) 0x43cd44 LEA 0x1(%RSI),%EAX |
(221) 0x43cd47 ADD %R8,%R10 |
(221) 0x43cd4a VMOVSD %XMM4,(%R12,%R10,8) |
(221) 0x43cd50 MOV 0x78(%RSP),%R10D |
(221) 0x43cd55 CMP %R10D,%EDX |
(221) 0x43cd58 JAE 43cdb8 |
(221) 0x43cd5a CLTQ |
(221) 0x43cd5c ADD $0x2,%R9D |
(221) 0x43cd60 ADD $0x2,%ESI |
(221) 0x43cd63 LEA (%R11,%RAX,1),%RDX |
(221) 0x43cd67 VMOVSD (%R15,%RDX,8),%XMM1 |
(221) 0x43cd6d LEA (%RCX,%RAX,1),%RDX |
(221) 0x43cd71 VMOVSD %XMM1,(%R14,%RDX,8) |
(221) 0x43cd77 LEA (%RDI,%RAX,1),%RDX |
(221) 0x43cd7b ADD %R8,%RAX |
(221) 0x43cd7e VMOVSD (%R13,%RDX,8),%XMM2 |
(221) 0x43cd85 VMOVSD %XMM2,(%R12,%RAX,8) |
(221) 0x43cd8b CMP %R10D,%R9D |
(221) 0x43cd8e JAE 43cdb8 |
(221) 0x43cd90 MOVSXD %ESI,%R9 |
(221) 0x43cd93 ADD %R9,%R11 |
(221) 0x43cd96 ADD %R9,%RCX |
(221) 0x43cd99 ADD %R9,%RDI |
(221) 0x43cd9c ADD %R9,%R8 |
(221) 0x43cd9f VMOVSD (%R15,%R11,8),%XMM0 |
(221) 0x43cda5 VMOVSD %XMM0,(%R14,%RCX,8) |
(221) 0x43cdab VMOVSD (%R13,%RDI,8),%XMM5 |
(221) 0x43cdb2 VMOVSD %XMM5,(%R12,%R8,8) |
(221) 0x43cdb8 MOV 0x78(%RSP),%R9D |
(221) 0x43cdbd INC %RBX |
(221) 0x43cdc0 MOV 0x50(%RSP),%R11D |
(221) 0x43cdc5 LEA (%RBX),%R15D |
(221) 0x43cdc8 CMP %R11D,%R15D |
(221) 0x43cdcb JGE 43cdf0 |
(221) 0x43cdcd MOV 0x48(%RSP),%R12D |
(221) 0x43cdd2 MOV 0x4c(%RSP),%R14D |
(221) 0x43cdd7 MOV 0x54(%RSP),%EDX |
(221) 0x43cddb MOV %R14D,0x7c(%RSP) |
(221) 0x43cde0 SUB %R9D,%R12D |
(221) 0x43cde3 JMP 43c9a8 |
0x43cde8 NOPL (%RAX,%RAX,1) |
0x43cdf0 VZEROUPPER |
0x43cdf3 LEA -0x28(%RBP),%RSP |
0x43cdf7 POP %RBX |
0x43cdf8 POP %R12 |
0x43cdfa POP %R13 |
0x43cdfc POP %R14 |
0x43cdfe POP %R15 |
0x43ce00 POP %RBP |
0x43ce01 RET |
0x43ce02 NOPW (%RAX,%RAX,1) |
(221) 0x43ce08 MOV 0x7c(%RSP),%ESI |
(221) 0x43ce0c XOR %R8D,%R8D |
(221) 0x43ce0f JMP 43ccad |
0x43ce14 INC %R12D |
0x43ce17 XOR %EDX,%EDX |
0x43ce19 JMP 43c942 |
0x43ce1e XCHG %AX,%AX |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
○98.18 | gomp_thread_start | team.c:130 | libgomp.so.1.0.0 |
○1.81 | GOMP_parallel | libgomp.h:985 | libgomp.so.1.0.0 |
Path / |
Source file and lines | revert.cpp:34-38 |
Module | exec |
nb instructions | 80 |
nb uops | 90 |
loop length | 276 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 10 |
micro-operation queue | 15.00 cycles |
front end | 15.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 5.70 | 8.00 | 6.00 | 6.00 | 8.50 | 5.87 | 5.70 | 8.50 | 8.50 | 8.50 | 5.73 | 6.00 |
cycles | 5.70 | 11.73 | 6.00 | 6.00 | 8.50 | 5.87 | 5.70 | 8.50 | 8.50 | 8.50 | 5.73 | 6.00 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.24-14.34 |
Stall cycles | 0.00 |
Front-end | 15.00 |
Dispatch | 11.73 |
DIV/SQRT | 12.00 |
Overall L1 | 15.00 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 20% |
all | 9% |
load | 10% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 10% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD $-0x80,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x28(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RDI),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x24(%RDI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x2,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA 0x1(%RBX),%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ESI,0x4c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 43cdf3 <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x533> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x2(%RCX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 43cdf3 <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x533> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R14D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %ESI,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EDI,0x54(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x54(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 43ce14 <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x554> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %R12D,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%R12,%R9,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R10D,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R10D,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 43cdf3 <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x533> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R9D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x4c(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%R13),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x54(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x18(%R13),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R15D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV (%R13),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%R13),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R11D,0x7c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R11D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %EAX,%RBX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R15,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 43c942 <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x82> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | revert.cpp:34-38 |
Module | exec |
nb instructions | 80 |
nb uops | 90 |
loop length | 276 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 10 |
micro-operation queue | 15.00 cycles |
front end | 15.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 5.70 | 8.00 | 6.00 | 6.00 | 8.50 | 5.87 | 5.70 | 8.50 | 8.50 | 8.50 | 5.73 | 6.00 |
cycles | 5.70 | 11.73 | 6.00 | 6.00 | 8.50 | 5.87 | 5.70 | 8.50 | 8.50 | 8.50 | 5.73 | 6.00 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.24-14.34 |
Stall cycles | 0.00 |
Front-end | 15.00 |
Dispatch | 11.73 |
DIV/SQRT | 12.00 |
Overall L1 | 15.00 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 20% |
all | 9% |
load | 10% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 10% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD $-0x80,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x28(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RDI),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x24(%RDI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x2,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA 0x1(%RBX),%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ESI,0x4c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 43cdf3 <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x533> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x2(%RCX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 43cdf3 <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x533> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R14D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %ESI,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EDI,0x54(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x54(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 43ce14 <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x554> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %R12D,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%R12,%R9,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R10D,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R10D,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 43cdf3 <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x533> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R9D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x4c(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%R13),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x54(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x18(%R13),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R15D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV (%R13),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%R13),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R11D,0x7c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R11D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %EAX,%RBX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R15,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 43c942 <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x82> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼revert_kernel(int, int, int, int, clover::Buffer2D | 1.79 | 0.59 |
▼Loop 221 - revert.cpp:37-38 - exec– | 0.01 | 0.01 |
○Loop 222 - revert.cpp:37-38 - exec | 1.79 | 0.59 |