Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ... | Module: exec | Source: advec_mom.cpp:95-100 [...] | Coverage: 3.04% |
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Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ... | Module: exec | Source: advec_mom.cpp:95-100 [...] | Coverage: 3.04% |
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/scratch_na/users/xoserete/qaas_runs/171-415-4687/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69 |
-------------------------------------------------------------------------------- |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
/scratch_na/users/xoserete/qaas_runs/171-415-4687/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp: 95 - 100 |
-------------------------------------------------------------------------------- |
95: #pragma omp parallel for simd collapse(2) |
96: for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) { |
97: for (int i = (x_min - 1 + 1); i < (x_max + 2 + 2); i++) { |
98: node_mass_post(i, j) = 0.25 * (density1(i + 0, j - 1) * post_vol(i + 0, j - 1) + density1(i, j) * post_vol(i, j) + |
99: density1(i - 1, j - 1) * post_vol(i - 1, j - 1) + density1(i - 1, j + 0) * post_vol(i - 1, j + 0)); |
100: node_mass_pre(i, j) = node_mass_post(i, j) - node_flux(i - 1, j + 0) + node_flux(i, j); |
0x42ad20 PUSH %RBP |
0x42ad21 MOV %RSP,%RBP |
0x42ad24 PUSH %R15 |
0x42ad26 PUSH %R14 |
0x42ad28 PUSH %R13 |
0x42ad2a PUSH %R12 |
0x42ad2c PUSH %RBX |
0x42ad2d MOV %RDI,%RBX |
0x42ad30 AND $-0x40,%RSP |
0x42ad34 SUB $0x100,%RSP |
0x42ad3b MOV 0x30(%RDI),%EAX |
0x42ad3e MOV 0x34(%RDI),%ECX |
0x42ad41 MOV 0x28(%RDI),%EDX |
0x42ad44 MOV 0x2c(%RDI),%EDI |
0x42ad47 ADD $0x3,%ECX |
0x42ad4a LEA 0x1(%RAX),%R12D |
0x42ad4e MOV %EDX,0x6c(%RSP) |
0x42ad52 MOV %ECX,0x70(%RSP) |
0x42ad56 CMP %ECX,%R12D |
0x42ad59 JGE 42b5bb |
0x42ad5f MOV %ECX,%R14D |
0x42ad62 LEA 0x4(%RDI),%R15D |
0x42ad66 SUB %R12D,%R14D |
0x42ad69 CMP %R15D,%EDX |
0x42ad6c JGE 42b5bb |
0x42ad72 MOV %R15D,%ESI |
0x42ad75 SUB %EDX,%ESI |
0x42ad77 MOV %ESI,0x74(%RSP) |
0x42ad7b CALL 4046c0 <omp_get_num_threads@plt> |
0x42ad80 MOV %EAX,%R13D |
0x42ad83 CALL 4045b0 <omp_get_thread_num@plt> |
0x42ad88 XOR %EDX,%EDX |
0x42ad8a MOV %EAX,%R8D |
0x42ad8d MOV 0x74(%RSP),%EAX |
0x42ad91 IMUL %R14D,%EAX |
0x42ad95 DIV %R13D |
0x42ad98 MOV %EAX,%ECX |
0x42ad9a CMP %EDX,%R8D |
0x42ad9d JB 42b5de |
0x42ada3 IMUL %ECX,%R8D |
0x42ada7 LEA (%R8,%RDX,1),%R9D |
0x42adab LEA (%RCX,%R9,1),%R10D |
0x42adaf MOV %R10D,0x68(%RSP) |
0x42adb4 CMP %R10D,%R9D |
0x42adb7 JAE 42b5bb |
0x42adbd MOV %R9D,%EAX |
0x42adc0 XOR %EDX,%EDX |
0x42adc2 MOV 0x6c(%RSP),%R11D |
0x42adc7 MOV (%RBX),%RDI |
0x42adca DIVL 0x74(%RSP) |
0x42adce MOV 0x10(%RBX),%R14 |
0x42add2 MOV 0x8(%RBX),%RSI |
0x42add6 MOV %R9D,0xfc(%RSP) |
0x42adde VMOVSD 0x37ae2(%RIP),%XMM3 |
0x42ade6 MOV %RDI,0x40(%RSP) |
0x42adeb MOV %R14,0x30(%RSP) |
0x42adf0 MOV %RSI,0x28(%RSP) |
0x42adf5 MOV %R15D,%R8D |
0x42adf8 MOV 0x20(%RBX),%R15 |
0x42adfc MOV 0x18(%RBX),%RBX |
0x42ae00 VBROADCASTSD %XMM3,%YMM4 |
0x42ae05 VBROADCASTSD %XMM3,%ZMM2 |
0x42ae0b MOV %R15,0x38(%RSP) |
0x42ae10 MOV %RBX,0x20(%RSP) |
0x42ae15 ADD %R12D,%EAX |
0x42ae18 ADD %EDX,%R11D |
0x42ae1b MOVSXD %EAX,%R12 |
0x42ae1e MOV %R11D,0xf8(%RSP) |
0x42ae26 SUB %R11D,%R8D |
0x42ae29 MOV %EAX,0xb4(%RSP) |
0x42ae30 MOV %R12,0x98(%RSP) |
0x42ae38 NOPL (%RAX,%RAX,1) |
(134) 0x42ae40 CMP %R8D,%ECX |
(134) 0x42ae43 CMOVBE %ECX,%R8D |
(134) 0x42ae47 MOV 0xfc(%RSP),%ECX |
(134) 0x42ae4e LEA (%RCX,%R8,1),%R13D |
(134) 0x42ae52 MOV %R8D,%R9D |
(134) 0x42ae55 MOV %R13D,0xb0(%RSP) |
(134) 0x42ae5d CMP %R13D,%ECX |
(134) 0x42ae60 JAE 42b56f |
(134) 0x42ae66 MOV 0xb4(%RSP),%R8D |
(134) 0x42ae6e MOV 0x40(%RSP),%RAX |
(134) 0x42ae73 MOV 0x38(%RSP),%RDI |
(134) 0x42ae78 MOV 0x98(%RSP),%R15 |
(134) 0x42ae80 LEA -0x1(%R8),%R10D |
(134) 0x42ae84 MOV 0x30(%RSP),%RSI |
(134) 0x42ae89 MOV 0x10(%RAX),%R13 |
(134) 0x42ae8d MOV (%RDI),%RCX |
(134) 0x42ae90 MOVSXD %R10D,%R11 |
(134) 0x42ae93 MOV (%RAX),%R10 |
(134) 0x42ae96 MOV %R15,%RAX |
(134) 0x42ae99 MOV %R11,%R14 |
(134) 0x42ae9c MOV 0x28(%RSP),%R8 |
(134) 0x42aea1 MOV 0x10(%RDI),%RDX |
(134) 0x42aea5 IMUL %R10,%R14 |
(134) 0x42aea9 MOV 0x10(%RSI),%RBX |
(134) 0x42aead IMUL %RCX,%R11 |
(134) 0x42aeb1 MOV (%R8),%RDI |
(134) 0x42aeb4 IMUL %R15,%R10 |
(134) 0x42aeb8 MOV %RBX,0xe0(%RSP) |
(134) 0x42aec0 LEA -0x1(%R9),%EBX |
(134) 0x42aec4 IMUL %R15,%RCX |
(134) 0x42aec8 MOV %R14,0xb8(%RSP) |
(134) 0x42aed0 IMUL (%RSI),%R15 |
(134) 0x42aed4 MOV %R11,0xc0(%RSP) |
(134) 0x42aedc IMUL %RAX,%RDI |
(134) 0x42aee0 MOV %R10,0xc8(%RSP) |
(134) 0x42aee8 MOV %RCX,0xd0(%RSP) |
(134) 0x42aef0 MOV %R15,0xd8(%RSP) |
(134) 0x42aef8 MOV 0x10(%R8),%R15 |
(134) 0x42aefc MOV 0x20(%RSP),%R8 |
(134) 0x42af01 MOV %RDI,0xf0(%RSP) |
(134) 0x42af09 MOV (%R8),%R12 |
(134) 0x42af0c MOV 0x10(%R8),%RSI |
(134) 0x42af10 IMUL %RAX,%R12 |
(134) 0x42af14 MOV %RSI,0xe8(%RSP) |
(134) 0x42af1c MOV %R12,0xa8(%RSP) |
(134) 0x42af24 CMP $0x6,%EBX |
(134) 0x42af27 JBE 42b5d0 |
(134) 0x42af2d MOVSXD 0xf8(%RSP),%RAX |
(134) 0x42af35 LEA (%R11,%RAX,1),%RDI |
(134) 0x42af39 ADD %RAX,%RCX |
(134) 0x42af3c LEA (%R14,%RAX,1),%R8 |
(134) 0x42af40 SAL $0x3,%RDI |
(134) 0x42af44 SAL $0x3,%RCX |
(134) 0x42af48 LEA (%R10,%RAX,1),%RBX |
(134) 0x42af4c LEA (%RDX,%RDI,1),%R11 |
(134) 0x42af50 SAL $0x3,%R8 |
(134) 0x42af54 LEA (%RDX,%RCX,1),%R10 |
(134) 0x42af58 SAL $0x3,%RBX |
(134) 0x42af5c MOV %R11,0x80(%RSP) |
(134) 0x42af64 LEA -0x8(%RDX,%RCX,1),%R11 |
(134) 0x42af69 MOV 0xd8(%RSP),%RCX |
(134) 0x42af71 LEA (%R13,%R8,1),%R14 |
(134) 0x42af76 LEA -0x8(%R13,%R8,1),%RSI |
(134) 0x42af7b MOV %R10,0x88(%RSP) |
(134) 0x42af83 MOV 0xe0(%RSP),%R8 |
(134) 0x42af8b LEA -0x8(%RDX,%RDI,1),%R10 |
(134) 0x42af90 MOV 0xf0(%RSP),%RDI |
(134) 0x42af98 ADD %RAX,%RCX |
(134) 0x42af9b MOV %RSI,0x90(%RSP) |
(134) 0x42afa3 MOV 0xe8(%RSP),%RSI |
(134) 0x42afab LEA (%R8,%RCX,8),%R8 |
(134) 0x42afaf MOV %R14,0x78(%RSP) |
(134) 0x42afb4 LEA (%R13,%RBX,1),%R14 |
(134) 0x42afb9 LEA (%RDI,%RAX,1),%RCX |
(134) 0x42afbd ADD %R12,%RAX |
(134) 0x42afc0 LEA -0x8(%R13,%RBX,1),%RBX |
(134) 0x42afc5 LEA (%RSI,%RAX,8),%RSI |
(134) 0x42afc9 MOV %R9D,%EAX |
(134) 0x42afcc SAL $0x3,%RCX |
(134) 0x42afd0 SHR $0x3,%EAX |
(134) 0x42afd3 LEA -0x8(%R15,%RCX,1),%RDI |
(134) 0x42afd8 ADD %R15,%RCX |
(134) 0x42afdb MOV %RAX,%R12 |
(134) 0x42afde SAL $0x6,%RAX |
(134) 0x42afe2 MOV %RAX,0xa0(%RSP) |
(134) 0x42afea XOR %EAX,%EAX |
(134) 0x42afec AND $0x1,%R12D |
(134) 0x42aff0 JE 42b084 |
(134) 0x42aff6 MOV 0x88(%RSP),%RAX |
(134) 0x42affe VMOVUPD (%R11),%ZMM5 |
(134) 0x42b004 MOV 0x80(%RSP),%R12 |
(134) 0x42b00c VMOVUPD (%R10),%ZMM8 |
(134) 0x42b012 VMOVUPD (%RAX),%ZMM7 |
(134) 0x42b018 VMULPD (%RBX),%ZMM5,%ZMM1 |
(134) 0x42b01e VMOVUPD (%R12),%ZMM6 |
(134) 0x42b025 MOV 0x78(%RSP),%RAX |
(134) 0x42b02a VMULPD (%R14),%ZMM7,%ZMM0 |
(134) 0x42b030 MOV 0xa0(%RSP),%R12 |
(134) 0x42b038 VFMADD231PD (%RAX),%ZMM6,%ZMM0 |
(134) 0x42b03e MOV 0x90(%RSP),%RAX |
(134) 0x42b046 VFMADD231PD (%RAX),%ZMM8,%ZMM1 |
(134) 0x42b04c MOV $0x40,%EAX |
(134) 0x42b051 VADDPD %ZMM1,%ZMM0,%ZMM9 |
(134) 0x42b057 VMULPD %ZMM2,%ZMM9,%ZMM10 |
(134) 0x42b05d VMOVUPD %ZMM10,(%R8) |
(134) 0x42b063 VMOVUPD (%RCX),%ZMM11 |
(134) 0x42b069 VSUBPD (%RDI),%ZMM11,%ZMM12 |
(134) 0x42b06f VADDPD %ZMM10,%ZMM12,%ZMM13 |
(134) 0x42b075 VMOVUPD %ZMM13,(%RSI) |
(134) 0x42b07b CMP %R12,%RAX |
(134) 0x42b07e JE 42b1b7 |
(134) 0x42b084 MOV %R15,0x58(%RSP) |
(134) 0x42b089 MOV 0x80(%RSP),%R12 |
(134) 0x42b091 MOV %R9D,0x64(%RSP) |
(134) 0x42b096 MOV 0x88(%RSP),%R9 |
(134) 0x42b09e MOV %RDX,0x50(%RSP) |
(134) 0x42b0a3 MOV 0x90(%RSP),%RDX |
(134) 0x42b0ab MOV %R13,0x48(%RSP) |
(134) 0x42b0b0 MOV 0x78(%RSP),%R13 |
(135) 0x42b0b5 VMOVUPD (%R9,%RAX,1),%ZMM14 |
(135) 0x42b0bc VMOVUPD (%R11,%RAX,1),%ZMM0 |
(135) 0x42b0c3 VMOVUPD (%R12,%RAX,1),%ZMM7 |
(135) 0x42b0ca VMOVUPD (%R10,%RAX,1),%ZMM5 |
(135) 0x42b0d1 VMULPD (%R14,%RAX,1),%ZMM14,%ZMM15 |
(135) 0x42b0d8 MOV 0xa0(%RSP),%R15 |
(135) 0x42b0e0 VMULPD (%RBX,%RAX,1),%ZMM0,%ZMM6 |
(135) 0x42b0e7 VFMADD231PD (%R13,%RAX,1),%ZMM7,%ZMM15 |
(135) 0x42b0ef VFMADD231PD (%RDX,%RAX,1),%ZMM5,%ZMM6 |
(135) 0x42b0f6 VADDPD %ZMM6,%ZMM15,%ZMM1 |
(135) 0x42b0fc VMULPD %ZMM2,%ZMM1,%ZMM8 |
(135) 0x42b102 VMOVUPD %ZMM8,(%R8,%RAX,1) |
(135) 0x42b109 VMOVUPD (%RCX,%RAX,1),%ZMM9 |
(135) 0x42b110 VSUBPD (%RDI,%RAX,1),%ZMM9,%ZMM10 |
(135) 0x42b117 VADDPD %ZMM8,%ZMM10,%ZMM11 |
(135) 0x42b11d VMOVUPD %ZMM11,(%RSI,%RAX,1) |
(135) 0x42b124 VMOVUPD 0x40(%R9,%RAX,1),%ZMM12 |
(135) 0x42b12c VMOVUPD 0x40(%R11,%RAX,1),%ZMM15 |
(135) 0x42b134 VMOVUPD 0x40(%R12,%RAX,1),%ZMM14 |
(135) 0x42b13c VMOVUPD 0x40(%R10,%RAX,1),%ZMM7 |
(135) 0x42b144 VMULPD 0x40(%R14,%RAX,1),%ZMM12,%ZMM13 |
(135) 0x42b14c VMULPD 0x40(%RBX,%RAX,1),%ZMM15,%ZMM0 |
(135) 0x42b154 VFMADD231PD 0x40(%R13,%RAX,1),%ZMM14,%ZMM13 |
(135) 0x42b15c VFMADD231PD 0x40(%RDX,%RAX,1),%ZMM7,%ZMM0 |
(135) 0x42b164 VADDPD %ZMM0,%ZMM13,%ZMM6 |
(135) 0x42b16a VMULPD %ZMM2,%ZMM6,%ZMM8 |
(135) 0x42b170 VMOVUPD %ZMM8,0x40(%R8,%RAX,1) |
(135) 0x42b178 VMOVUPD 0x40(%RCX,%RAX,1),%ZMM5 |
(135) 0x42b180 VSUBPD 0x40(%RDI,%RAX,1),%ZMM5,%ZMM1 |
(135) 0x42b188 VADDPD %ZMM8,%ZMM1,%ZMM9 |
(135) 0x42b18e VMOVUPD %ZMM9,0x40(%RSI,%RAX,1) |
(135) 0x42b196 SUB $-0x80,%RAX |
(135) 0x42b19a CMP %R15,%RAX |
(135) 0x42b19d JNE 42b0b5 |
(134) 0x42b1a3 MOV 0x64(%RSP),%R9D |
(134) 0x42b1a8 MOV 0x58(%RSP),%R15 |
(134) 0x42b1ad MOV 0x50(%RSP),%RDX |
(134) 0x42b1b2 MOV 0x48(%RSP),%R13 |
(134) 0x42b1b7 MOV 0xf8(%RSP),%EAX |
(134) 0x42b1be MOV %R9D,%ESI |
(134) 0x42b1c1 AND $-0x8,%ESI |
(134) 0x42b1c4 ADD %ESI,0xfc(%RSP) |
(134) 0x42b1cb ADD %ESI,%EAX |
(134) 0x42b1cd TEST $0x7,%R9B |
(134) 0x42b1d1 JE 42b55f |
(134) 0x42b1d7 MOV %R9D,%EDI |
(134) 0x42b1da SUB %ESI,%EDI |
(134) 0x42b1dc LEA -0x1(%RDI),%R14D |
(134) 0x42b1e0 CMP $0x2,%R14D |
(134) 0x42b1e4 JBE 42b2d9 |
(134) 0x42b1ea MOVSXD 0xf8(%RSP),%RCX |
(134) 0x42b1f2 MOV 0xc0(%RSP),%RBX |
(134) 0x42b1fa MOV 0xc8(%RSP),%R11 |
(134) 0x42b202 MOV 0xb8(%RSP),%R10 |
(134) 0x42b20a LEA (%RBX,%RCX,1),%R9 |
(134) 0x42b20e MOV 0xd0(%RSP),%RBX |
(134) 0x42b216 MOV 0xd8(%RSP),%R8 |
(134) 0x42b21e LEA (%R11,%RCX,1),%R11 |
(134) 0x42b222 LEA (%R10,%RCX,1),%R10 |
(134) 0x42b226 ADD %RSI,%R9 |
(134) 0x42b229 MOV 0xf0(%RSP),%R14 |
(134) 0x42b231 ADD %RCX,%RBX |
(134) 0x42b234 ADD %RSI,%R11 |
(134) 0x42b237 LEA (%R8,%RCX,1),%R12 |
(134) 0x42b23b ADD %RSI,%R10 |
(134) 0x42b23e ADD %RSI,%RBX |
(134) 0x42b241 VMOVUPD (%R13,%R11,8),%YMM10 |
(134) 0x42b248 VMOVUPD (%R13,%R10,8),%YMM12 |
(134) 0x42b24f LEA (%R14,%RCX,1),%R8 |
(134) 0x42b253 VMOVUPD -0x8(%RDX,%RBX,8),%YMM13 |
(134) 0x42b259 VMOVUPD -0x8(%R13,%R10,8),%YMM15 |
(134) 0x42b260 ADD %RSI,%R8 |
(134) 0x42b263 ADD %RSI,%R12 |
(134) 0x42b266 VMULPD (%RDX,%RBX,8),%YMM10,%YMM11 |
(134) 0x42b26b MOV 0xa8(%RSP),%R14 |
(134) 0x42b273 VMULPD -0x8(%R13,%R11,8),%YMM13,%YMM14 |
(134) 0x42b27a MOV 0xe8(%RSP),%R10 |
(134) 0x42b282 ADD %R14,%RCX |
(134) 0x42b285 ADD %RSI,%RCX |
(134) 0x42b288 MOV 0xe0(%RSP),%RSI |
(134) 0x42b290 VFMADD231PD (%RDX,%R9,8),%YMM12,%YMM11 |
(134) 0x42b296 VFMADD231PD -0x8(%RDX,%R9,8),%YMM15,%YMM14 |
(134) 0x42b29d VADDPD %YMM14,%YMM11,%YMM0 |
(134) 0x42b2a2 VMULPD %YMM4,%YMM0,%YMM6 |
(134) 0x42b2a6 VMOVUPD %YMM6,(%RSI,%R12,8) |
(134) 0x42b2ac VMOVUPD (%R15,%R8,8),%YMM7 |
(134) 0x42b2b2 VSUBPD -0x8(%R15,%R8,8),%YMM7,%YMM8 |
(134) 0x42b2b9 VADDPD %YMM6,%YMM8,%YMM5 |
(134) 0x42b2bd VMOVUPD %YMM5,(%R10,%RCX,8) |
(134) 0x42b2c3 TEST $0x3,%DIL |
(134) 0x42b2c7 JE 42b55f |
(134) 0x42b2cd AND $-0x4,%EDI |
(134) 0x42b2d0 ADD %EDI,0xfc(%RSP) |
(134) 0x42b2d7 ADD %EDI,%EAX |
(134) 0x42b2d9 MOV 0xc8(%RSP),%R12 |
(134) 0x42b2e1 MOVSXD %EAX,%RCX |
(134) 0x42b2e4 MOV 0xb8(%RSP),%RDI |
(134) 0x42b2ec MOV 0xc0(%RSP),%RBX |
(134) 0x42b2f4 LEA (%R12,%RCX,1),%R14 |
(134) 0x42b2f8 LEA (%RDI,%RCX,1),%R9 |
(134) 0x42b2fc LEA (%R13,%R14,8),%R10 |
(134) 0x42b301 MOV 0xd0(%RSP),%R14 |
(134) 0x42b309 LEA (%RBX,%RCX,1),%R11 |
(134) 0x42b30d LEA (%R13,%R9,8),%R8 |
(134) 0x42b312 LEA (%RDX,%R11,8),%R9 |
(134) 0x42b316 LEA (%R14,%RCX,1),%RSI |
(134) 0x42b31a VMOVSD (%R9),%XMM10 |
(134) 0x42b31f LEA (%RDX,%RSI,8),%R11 |
(134) 0x42b323 LEA -0x1(%RAX),%ESI |
(134) 0x42b326 MOVSXD %ESI,%RSI |
(134) 0x42b329 VMOVSD (%R11),%XMM1 |
(134) 0x42b32e ADD %RSI,%R14 |
(134) 0x42b331 ADD %RSI,%R12 |
(134) 0x42b334 ADD %RSI,%RBX |
(134) 0x42b337 ADD %RSI,%RDI |
(134) 0x42b33a VMOVSD (%RDX,%R14,8),%XMM11 |
(134) 0x42b340 VMULSD (%R10),%XMM1,%XMM9 |
(134) 0x42b345 VMOVSD (%RDX,%RBX,8),%XMM13 |
(134) 0x42b34a MOV 0xf0(%RSP),%R14 |
(134) 0x42b352 VMULSD (%R13,%R12,8),%XMM11,%XMM12 |
(134) 0x42b359 MOV 0xe0(%RSP),%RBX |
(134) 0x42b361 ADD %R14,%RSI |
(134) 0x42b364 VFMADD231SD (%R8),%XMM10,%XMM9 |
(134) 0x42b369 VFMADD231SD (%R13,%RDI,8),%XMM13,%XMM12 |
(134) 0x42b370 MOV 0xd8(%RSP),%RDI |
(134) 0x42b378 LEA (%RDI,%RCX,1),%R12 |
(134) 0x42b37c LEA (%R14,%RCX,1),%RDI |
(134) 0x42b380 MOV 0xb0(%RSP),%R14D |
(134) 0x42b388 LEA (%R15,%RDI,8),%RDI |
(134) 0x42b38c VADDSD %XMM12,%XMM9,%XMM14 |
(134) 0x42b391 VMULSD %XMM3,%XMM14,%XMM15 |
(134) 0x42b395 VMOVSD %XMM15,(%RBX,%R12,8) |
(134) 0x42b39b MOV 0xa8(%RSP),%R12 |
(134) 0x42b3a3 MOV 0xfc(%RSP),%EBX |
(134) 0x42b3aa VMOVSD (%RDI),%XMM0 |
(134) 0x42b3ae ADD %R12,%RCX |
(134) 0x42b3b1 INC %EBX |
(134) 0x42b3b3 VSUBSD (%R15,%RSI,8),%XMM0,%XMM6 |
(134) 0x42b3b9 MOV 0xe8(%RSP),%RSI |
(134) 0x42b3c1 VADDSD %XMM15,%XMM6,%XMM7 |
(134) 0x42b3c6 VMOVSD %XMM7,(%RSI,%RCX,8) |
(134) 0x42b3cb LEA 0x1(%RAX),%ECX |
(134) 0x42b3ce CMP %R14D,%EBX |
(134) 0x42b3d1 JAE 42b55f |
(134) 0x42b3d7 MOV 0xb8(%RSP),%R12 |
(134) 0x42b3df MOVSXD %ECX,%RCX |
(134) 0x42b3e2 MOV 0xc0(%RSP),%R14 |
(134) 0x42b3ea ADD $0x2,%EAX |
(134) 0x42b3ed VMOVSD (%R11),%XMM9 |
(134) 0x42b3f2 VMOVSD (%R9),%XMM11 |
(134) 0x42b3f7 LEA (%R12,%RCX,1),%RSI |
(134) 0x42b3fb MOV 0xc8(%RSP),%R12 |
(134) 0x42b403 ADD %RCX,%R14 |
(134) 0x42b406 MOV 0xf0(%RSP),%R11 |
(134) 0x42b40e LEA (%R13,%RSI,8),%RBX |
(134) 0x42b413 LEA (%RDX,%R14,8),%RSI |
(134) 0x42b417 VMULSD (%R10),%XMM9,%XMM10 |
(134) 0x42b41c MOV 0xe0(%RSP),%R10 |
(134) 0x42b424 ADD %RCX,%R12 |
(134) 0x42b427 VMOVSD (%RSI),%XMM1 |
(134) 0x42b42b LEA (%R13,%R12,8),%R14 |
(134) 0x42b430 MOV 0xd0(%RSP),%R12 |
(134) 0x42b438 ADD %RCX,%R12 |
(134) 0x42b43b LEA (%RDX,%R12,8),%R12 |
(134) 0x42b43f VFMADD231SD (%R8),%XMM11,%XMM10 |
(134) 0x42b444 MOV 0xd8(%RSP),%R8 |
(134) 0x42b44c VMOVSD (%R12),%XMM8 |
(134) 0x42b452 LEA (%R8,%RCX,1),%R9 |
(134) 0x42b456 LEA (%R11,%RCX,1),%R8 |
(134) 0x42b45a VMULSD (%R14),%XMM8,%XMM5 |
(134) 0x42b45f LEA (%R15,%R8,8),%R8 |
(134) 0x42b463 VFMADD132SD (%RBX),%XMM5,%XMM1 |
(134) 0x42b468 VADDSD %XMM1,%XMM10,%XMM12 |
(134) 0x42b46c VMULSD %XMM3,%XMM12,%XMM13 |
(134) 0x42b470 VMOVSD %XMM13,(%R10,%R9,8) |
(134) 0x42b476 MOV 0xa8(%RSP),%R9 |
(134) 0x42b47e MOV 0xb0(%RSP),%R10D |
(134) 0x42b486 VMOVSD (%R8),%XMM14 |
(134) 0x42b48b ADD %R9,%RCX |
(134) 0x42b48e VSUBSD (%RDI),%XMM14,%XMM15 |
(134) 0x42b492 MOV 0xe8(%RSP),%RDI |
(134) 0x42b49a VADDSD %XMM13,%XMM15,%XMM0 |
(134) 0x42b49f VMOVSD %XMM0,(%RDI,%RCX,8) |
(134) 0x42b4a4 MOV 0xfc(%RSP),%ECX |
(134) 0x42b4ab ADD $0x2,%ECX |
(134) 0x42b4ae CMP %R10D,%ECX |
(134) 0x42b4b1 JAE 42b55f |
(134) 0x42b4b7 MOV 0xd0(%RSP),%R9 |
(134) 0x42b4bf CLTQ |
(134) 0x42b4c1 MOV 0xc8(%RSP),%R10 |
(134) 0x42b4c9 VMOVSD (%R14),%XMM5 |
(134) 0x42b4ce MOV 0xc0(%RSP),%RCX |
(134) 0x42b4d6 ADD %RAX,%R11 |
(134) 0x42b4d9 ADD %RAX,%R9 |
(134) 0x42b4dc ADD %RAX,%R10 |
(134) 0x42b4df MOV 0xb8(%RSP),%RDI |
(134) 0x42b4e7 VMOVSD (%RBX),%XMM9 |
(134) 0x42b4eb VMOVSD (%RDX,%R9,8),%XMM6 |
(134) 0x42b4f1 VMULSD (%R12),%XMM5,%XMM1 |
(134) 0x42b4f7 ADD %RAX,%RCX |
(134) 0x42b4fa VMOVSD (%RDX,%RCX,8),%XMM7 |
(134) 0x42b4ff ADD %RAX,%RDI |
(134) 0x42b502 MOV 0xd8(%RSP),%RDX |
(134) 0x42b50a VMULSD (%R13,%R10,8),%XMM6,%XMM8 |
(134) 0x42b511 MOV 0xa8(%RSP),%RBX |
(134) 0x42b519 ADD %RAX,%RDX |
(134) 0x42b51c ADD %RAX,%RBX |
(134) 0x42b51f MOV 0xe8(%RSP),%RAX |
(134) 0x42b527 VFMADD231SD (%RSI),%XMM9,%XMM1 |
(134) 0x42b52c VFMADD231SD (%R13,%RDI,8),%XMM7,%XMM8 |
(134) 0x42b533 MOV 0xe0(%RSP),%R13 |
(134) 0x42b53b VADDSD %XMM1,%XMM8,%XMM10 |
(134) 0x42b53f VMULSD %XMM3,%XMM10,%XMM11 |
(134) 0x42b543 VMOVSD %XMM11,(%R13,%RDX,8) |
(134) 0x42b54a VMOVSD (%R15,%R11,8),%XMM12 |
(134) 0x42b550 VSUBSD (%R8),%XMM12,%XMM13 |
(134) 0x42b555 VADDSD %XMM11,%XMM13,%XMM14 |
(134) 0x42b55a VMOVSD %XMM14,(%RAX,%RBX,8) |
(134) 0x42b55f MOV 0xb0(%RSP),%R15D |
(134) 0x42b567 MOV %R15D,0xfc(%RSP) |
(134) 0x42b56f INCL 0xb4(%RSP) |
(134) 0x42b576 INCQ 0x98(%RSP) |
(134) 0x42b57e MOV 0xb4(%RSP),%ESI |
(134) 0x42b585 CMP %ESI,0x70(%RSP) |
(134) 0x42b589 JLE 42b5b8 |
(134) 0x42b58b MOV 0x68(%RSP),%ECX |
(134) 0x42b58f MOV 0xfc(%RSP),%R14D |
(134) 0x42b597 MOV 0x6c(%RSP),%R12D |
(134) 0x42b59c MOV 0x74(%RSP),%R8D |
(134) 0x42b5a1 SUB %R14D,%ECX |
(134) 0x42b5a4 MOV %R12D,0xf8(%RSP) |
(134) 0x42b5ac JMP 42ae40 |
0x42b5b1 NOPL (%RAX) |
0x42b5b8 VZEROUPPER |
0x42b5bb LEA -0x28(%RBP),%RSP |
0x42b5bf POP %RBX |
0x42b5c0 POP %R12 |
0x42b5c2 POP %R13 |
0x42b5c4 POP %R14 |
0x42b5c6 POP %R15 |
0x42b5c8 POP %RBP |
0x42b5c9 RET |
0x42b5ca NOPW (%RAX,%RAX,1) |
(134) 0x42b5d0 MOV 0xf8(%RSP),%EAX |
(134) 0x42b5d7 XOR %ESI,%ESI |
(134) 0x42b5d9 JMP 42b1d7 |
0x42b5de INC %ECX |
0x42b5e0 XOR %EDX,%EDX |
0x42b5e2 JMP 42ada3 |
0x42b5e7 NOPW (%RAX,%RAX,1) |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
○98.49 | gomp_thread_start | team.c:130 | libgomp.so.1.0.0 |
○1.51 | GOMP_parallel | libgomp.h:985 | libgomp.so.1.0.0 |
Path / |
Source file and lines | advec_mom.cpp:95-100 |
Module | exec |
nb instructions | 87 |
nb uops | 97 |
loop length | 337 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 1 |
used ymm registers | 1 |
used zmm registers | 1 |
nb stack references | 14 |
micro-operation queue | 16.17 cycles |
front end | 16.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.30 | 8.00 | 6.67 | 6.67 | 10.50 | 6.20 | 6.30 | 10.50 | 10.50 | 10.50 | 6.20 | 6.67 |
cycles | 6.30 | 11.73 | 6.67 | 6.67 | 10.50 | 6.20 | 6.30 | 10.50 | 10.50 | 10.50 | 6.20 | 6.67 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 15.42-15.52 |
Stall cycles | 0.00 |
Front-end | 16.17 |
Dispatch | 11.73 |
DIV/SQRT | 12.00 |
Overall L1 | 16.17 |
all | 3% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 9% |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 2% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 9% |
all | 8% |
load | 10% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 8% |
all | 12% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
all | 9% |
load | 10% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 9% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0x100,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x30(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x34(%RDI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%RDI),%EDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x3,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%RAX),%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x6c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ECX,0x70(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %ECX,%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 42b5bb <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x89b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %ECX,%R14D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x4(%RDI),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R12D,%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R15D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 42b5bb <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x89b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R15D,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %EDX,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ESI,0x74(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x74(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %R14D,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R13D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 42b5de <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x8be> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %ECX,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RCX,%R9,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R10D,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R10D,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 42b5bb <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x89b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R9D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x6c(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RBX),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x74(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x10(%RBX),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RBX),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R9D,0xfc(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD 0x37ae2(%RIP),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDI,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RSI,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15D,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x20(%RBX),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RBX),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VBROADCASTSD %XMM3,%YMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VBROADCASTSD %XMM3,%ZMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %R15,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %R12D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %EDX,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %EAX,%R12 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R11D,0xf8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R11D,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EAX,0xb4(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,0x98(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 42ada3 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x83> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | advec_mom.cpp:95-100 |
Module | exec |
nb instructions | 87 |
nb uops | 97 |
loop length | 337 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 1 |
used ymm registers | 1 |
used zmm registers | 1 |
nb stack references | 14 |
micro-operation queue | 16.17 cycles |
front end | 16.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.30 | 8.00 | 6.67 | 6.67 | 10.50 | 6.20 | 6.30 | 10.50 | 10.50 | 10.50 | 6.20 | 6.67 |
cycles | 6.30 | 11.73 | 6.67 | 6.67 | 10.50 | 6.20 | 6.30 | 10.50 | 10.50 | 10.50 | 6.20 | 6.67 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 15.42-15.52 |
Stall cycles | 0.00 |
Front-end | 16.17 |
Dispatch | 11.73 |
DIV/SQRT | 12.00 |
Overall L1 | 16.17 |
all | 3% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 9% |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 2% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 9% |
all | 8% |
load | 10% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 8% |
all | 12% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
all | 9% |
load | 10% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 9% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0x100,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x30(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x34(%RDI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%RDI),%EDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x3,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%RAX),%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x6c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ECX,0x70(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %ECX,%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 42b5bb <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x89b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %ECX,%R14D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x4(%RDI),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R12D,%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R15D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 42b5bb <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x89b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R15D,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %EDX,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ESI,0x74(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x74(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %R14D,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R13D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 42b5de <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x8be> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %ECX,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RCX,%R9,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R10D,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R10D,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 42b5bb <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x89b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R9D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x6c(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RBX),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x74(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x10(%RBX),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RBX),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R9D,0xfc(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD 0x37ae2(%RIP),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDI,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RSI,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15D,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x20(%RBX),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RBX),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VBROADCASTSD %XMM3,%YMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VBROADCASTSD %XMM3,%ZMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %R15,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %R12D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %EDX,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %EAX,%R12 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R11D,0xf8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R11D,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EAX,0xb4(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,0x98(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 42ada3 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x83> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D | 3.04 | 2.27 |
▼Loop 134 - advec_mom.cpp:97-100 - exec– | 0.01 | 0 |
○Loop 135 - advec_mom.cpp:98-100 - exec | 3.03 | 2.26 |