Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ... | Module: exec | Source: advec_cell.cpp:44-48 [...] | Coverage: 1.52% |
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Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ... | Module: exec | Source: advec_cell.cpp:44-48 [...] | Coverage: 1.52% |
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/scratch_na/users/xoserete/qaas_runs/171-415-4687/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69 |
-------------------------------------------------------------------------------- |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
/scratch_na/users/xoserete/qaas_runs/171-415-4687/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp: 44 - 48 |
-------------------------------------------------------------------------------- |
44: #pragma omp parallel for simd collapse(2) |
45: for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) { |
46: for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) { |
47: pre_vol(i, j) = volume(i, j) + (vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j) + vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j)); |
48: post_vol(i, j) = pre_vol(i, j) - (vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j)); |
0x424f20 PUSH %RBP |
0x424f21 MOV %RSP,%RBP |
0x424f24 PUSH %R15 |
0x424f26 PUSH %R14 |
0x424f28 PUSH %R13 |
0x424f2a PUSH %R12 |
0x424f2c MOV %RDI,%R12 |
0x424f2f PUSH %RBX |
0x424f30 AND $-0x40,%RSP |
0x424f34 SUB $0xc0,%RSP |
0x424f3b MOV 0x30(%RDI),%EAX |
0x424f3e MOV 0x34(%RDI),%ECX |
0x424f41 MOV 0x28(%RDI),%EDI |
0x424f44 MOV 0x2c(%R12),%EDX |
0x424f49 ADD $0x4,%ECX |
0x424f4c LEA -0x1(%RAX),%R15D |
0x424f50 DEC %EDI |
0x424f52 MOV %ECX,0x5c(%RSP) |
0x424f56 MOV %EDI,0x58(%RSP) |
0x424f5a CMP %ECX,%R15D |
0x424f5d JGE 4256b3 |
0x424f63 MOV %ECX,%EBX |
0x424f65 LEA 0x4(%RDX),%R14D |
0x424f69 SUB %R15D,%EBX |
0x424f6c CMP %R14D,%EDI |
0x424f6f JGE 4256b3 |
0x424f75 MOV %R14D,%ESI |
0x424f78 SUB %EDI,%ESI |
0x424f7a MOV %ESI,0x88(%RSP) |
0x424f81 CALL 4046c0 <omp_get_num_threads@plt> |
0x424f86 MOV %EAX,%R13D |
0x424f89 CALL 4045b0 <omp_get_thread_num@plt> |
0x424f8e XOR %EDX,%EDX |
0x424f90 MOV %EAX,%R8D |
0x424f93 MOV 0x88(%RSP),%EAX |
0x424f9a IMUL %EBX,%EAX |
0x424f9d DIV %R13D |
0x424fa0 MOV %EAX,%ESI |
0x424fa2 CMP %EDX,%R8D |
0x424fa5 JB 4256e7 |
0x424fab IMUL %ESI,%R8D |
0x424faf LEA (%R8,%RDX,1),%R9D |
0x424fb3 LEA (%RSI,%R9,1),%R10D |
0x424fb7 MOV %R10D,0x54(%RSP) |
0x424fbc CMP %R10D,%R9D |
0x424fbf JAE 4256b3 |
0x424fc5 MOV %R9D,%EAX |
0x424fc8 XOR %EDX,%EDX |
0x424fca MOV 0x58(%RSP),%R11D |
0x424fcf MOV (%R12),%RCX |
0x424fd3 DIVL 0x88(%RSP) |
0x424fda MOV 0x8(%R12),%RDI |
0x424fdf MOV 0x18(%R12),%RBX |
0x424fe4 MOV %RCX,0x48(%RSP) |
0x424fe9 MOV %RDI,0x40(%RSP) |
0x424fee MOV %RBX,0x30(%RSP) |
0x424ff3 MOV %R14D,%R10D |
0x424ff6 MOV 0x10(%R12),%R14 |
0x424ffb MOV 0x20(%R12),%R12 |
0x425000 MOV %R14,0x38(%RSP) |
0x425005 MOV %R12,0x28(%RSP) |
0x42500a ADD %EDX,%R11D |
0x42500d LEA (%RAX,%R15,1),%R15D |
0x425011 MOV %R11D,0xa0(%RSP) |
0x425019 SUB %R11D,%R10D |
0x42501c MOVSXD %R15D,%RCX |
0x42501f NOP |
(105) 0x425020 CMP %R10D,%ESI |
(105) 0x425023 CMOVBE %ESI,%R10D |
(105) 0x425027 LEA (%R9,%R10,1),%ESI |
(105) 0x42502b MOV %R10D,%EDX |
(105) 0x42502e MOV %ESI,0x8c(%RSP) |
(105) 0x425035 CMP %ESI,%R9D |
(105) 0x425038 JAE 4256c8 |
(105) 0x42503e MOV 0x38(%RSP),%RAX |
(105) 0x425043 LEA 0x1(%RCX),%R14 |
(105) 0x425047 MOV 0x48(%RSP),%R8 |
(105) 0x42504c MOV 0x40(%RSP),%R10 |
(105) 0x425051 MOV 0x30(%RSP),%R13 |
(105) 0x425056 MOV %R14,0x60(%RSP) |
(105) 0x42505b MOV (%RAX),%R12 |
(105) 0x42505e MOV (%R8),%RSI |
(105) 0x425061 MOV (%R10),%R11 |
(105) 0x425064 MOV 0x10(%RAX),%RDI |
(105) 0x425068 IMUL %R12,%R14 |
(105) 0x42506c MOV 0x28(%RSP),%RAX |
(105) 0x425071 MOV 0x10(%R8),%R15 |
(105) 0x425075 IMUL %RCX,%RSI |
(105) 0x425079 MOV 0x10(%R10),%R8 |
(105) 0x42507d MOV 0x10(%R13),%R10 |
(105) 0x425081 IMUL %RCX,%R11 |
(105) 0x425085 MOV %R15,0x98(%RSP) |
(105) 0x42508d MOV %R14,%RBX |
(105) 0x425090 MOV %R14,0x78(%RSP) |
(105) 0x425095 SUB %R12,%RBX |
(105) 0x425098 MOV (%R13),%R12 |
(105) 0x42509c MOV 0x10(%RAX),%R13 |
(105) 0x4250a0 MOV %RSI,0x68(%RSP) |
(105) 0x4250a5 MOV %R11,0x70(%RSP) |
(105) 0x4250aa IMUL %RCX,%R12 |
(105) 0x4250ae MOV %RBX,0x80(%RSP) |
(105) 0x4250b6 IMUL (%RAX),%RCX |
(105) 0x4250ba MOV %R10,0xa8(%RSP) |
(105) 0x4250c2 MOV %R13,0xb8(%RSP) |
(105) 0x4250ca MOV %R12,0x90(%RSP) |
(105) 0x4250d2 MOV %RCX,0xb0(%RSP) |
(105) 0x4250da LEA -0x1(%RDX),%ECX |
(105) 0x4250dd CMP $0x6,%ECX |
(105) 0x4250e0 JBE 4256d8 |
(105) 0x4250e6 MOVSXD 0xa0(%RSP),%RAX |
(105) 0x4250ee LEA 0x1(%R11,%RAX,1),%R11 |
(105) 0x4250f3 LEA (%RSI,%RAX,1),%R10 |
(105) 0x4250f7 SAL $0x3,%R11 |
(105) 0x4250fb LEA (%R14,%RAX,1),%R14 |
(105) 0x4250ff LEA (%RBX,%RAX,1),%RBX |
(105) 0x425103 LEA (%R8,%R11,1),%RCX |
(105) 0x425107 LEA -0x8(%R8,%R11,1),%RSI |
(105) 0x42510c MOV 0xb0(%RSP),%R11 |
(105) 0x425114 LEA (%R12,%RAX,1),%R12 |
(105) 0x425118 LEA (%R15,%R10,8),%R15 |
(105) 0x42511c MOV 0xa8(%RSP),%R10 |
(105) 0x425124 ADD %R11,%RAX |
(105) 0x425127 MOV %EDX,%R11D |
(105) 0x42512a LEA (%RDI,%R14,8),%R13 |
(105) 0x42512e SHR $0x3,%R11D |
(105) 0x425132 LEA (%R10,%R12,8),%R12 |
(105) 0x425136 LEA (%RDI,%RBX,8),%R14 |
(105) 0x42513a MOV 0xb8(%RSP),%RBX |
(105) 0x425142 SAL $0x6,%R11 |
(105) 0x425146 LEA -0x40(%R11),%R10 |
(105) 0x42514a LEA (%RBX,%RAX,8),%RBX |
(105) 0x42514e XOR %EAX,%EAX |
(105) 0x425150 SHR $0x6,%R10 |
(105) 0x425154 INC %R10 |
(105) 0x425157 AND $0x3,%R10D |
(105) 0x42515b JE 425263 |
(105) 0x425161 CMP $0x1,%R10 |
(105) 0x425165 JE 42520a |
(105) 0x42516b CMP $0x2,%R10 |
(105) 0x42516f JE 4251ba |
(105) 0x425171 VMOVUPD (%RCX),%ZMM4 |
(105) 0x425177 VMOVUPD (%R14),%ZMM5 |
(105) 0x42517d MOV $0x40,%EAX |
(105) 0x425182 VADDPD (%R15),%ZMM4,%ZMM0 |
(105) 0x425188 VADDPD (%RSI),%ZMM5,%ZMM1 |
(105) 0x42518e VSUBPD %ZMM1,%ZMM0,%ZMM2 |
(105) 0x425194 VADDPD (%R13),%ZMM2,%ZMM3 |
(105) 0x42519b VMOVUPD %ZMM3,(%R12) |
(105) 0x4251a2 VMOVUPD (%RSI),%ZMM6 |
(105) 0x4251a8 VSUBPD (%RCX),%ZMM6,%ZMM7 |
(105) 0x4251ae VADDPD %ZMM3,%ZMM7,%ZMM8 |
(105) 0x4251b4 VMOVUPD %ZMM8,(%RBX) |
(105) 0x4251ba VMOVUPD (%RCX,%RAX,1),%ZMM9 |
(105) 0x4251c1 VMOVUPD (%R14,%RAX,1),%ZMM11 |
(105) 0x4251c8 VADDPD (%R15,%RAX,1),%ZMM9,%ZMM10 |
(105) 0x4251cf VADDPD (%RSI,%RAX,1),%ZMM11,%ZMM12 |
(105) 0x4251d6 VSUBPD %ZMM12,%ZMM10,%ZMM13 |
(105) 0x4251dc VADDPD (%R13,%RAX,1),%ZMM13,%ZMM14 |
(105) 0x4251e4 VMOVUPD %ZMM14,(%R12,%RAX,1) |
(105) 0x4251eb VMOVUPD (%RSI,%RAX,1),%ZMM15 |
(105) 0x4251f2 VSUBPD (%RCX,%RAX,1),%ZMM15,%ZMM4 |
(105) 0x4251f9 VADDPD %ZMM14,%ZMM4,%ZMM0 |
(105) 0x4251ff VMOVUPD %ZMM0,(%RBX,%RAX,1) |
(105) 0x425206 ADD $0x40,%RAX |
(105) 0x42520a VMOVUPD (%RCX,%RAX,1),%ZMM5 |
(105) 0x425211 VMOVUPD (%R14,%RAX,1),%ZMM1 |
(105) 0x425218 VADDPD (%R15,%RAX,1),%ZMM5,%ZMM2 |
(105) 0x42521f VADDPD (%RSI,%RAX,1),%ZMM1,%ZMM3 |
(105) 0x425226 VSUBPD %ZMM3,%ZMM2,%ZMM6 |
(105) 0x42522c VADDPD (%R13,%RAX,1),%ZMM6,%ZMM7 |
(105) 0x425234 VMOVUPD %ZMM7,(%R12,%RAX,1) |
(105) 0x42523b VMOVUPD (%RSI,%RAX,1),%ZMM8 |
(105) 0x425242 VSUBPD (%RCX,%RAX,1),%ZMM8,%ZMM9 |
(105) 0x425249 VADDPD %ZMM7,%ZMM9,%ZMM10 |
(105) 0x42524f VMOVUPD %ZMM10,(%RBX,%RAX,1) |
(105) 0x425256 ADD $0x40,%RAX |
(105) 0x42525a CMP %RAX,%R11 |
(105) 0x42525d JE 4253ba |
(106) 0x425263 VMOVUPD (%RCX,%RAX,1),%ZMM11 |
(106) 0x42526a VMOVUPD (%R14,%RAX,1),%ZMM13 |
(106) 0x425271 VADDPD (%R15,%RAX,1),%ZMM11,%ZMM12 |
(106) 0x425278 VADDPD (%RSI,%RAX,1),%ZMM13,%ZMM14 |
(106) 0x42527f VSUBPD %ZMM14,%ZMM12,%ZMM15 |
(106) 0x425285 VADDPD (%R13,%RAX,1),%ZMM15,%ZMM4 |
(106) 0x42528d VMOVUPD %ZMM4,(%R12,%RAX,1) |
(106) 0x425294 VMOVUPD (%RSI,%RAX,1),%ZMM0 |
(106) 0x42529b VSUBPD (%RCX,%RAX,1),%ZMM0,%ZMM5 |
(106) 0x4252a2 VADDPD %ZMM4,%ZMM5,%ZMM2 |
(106) 0x4252a8 VMOVUPD %ZMM2,(%RBX,%RAX,1) |
(106) 0x4252af VMOVUPD 0x40(%RCX,%RAX,1),%ZMM1 |
(106) 0x4252b7 VMOVUPD 0x40(%R14,%RAX,1),%ZMM6 |
(106) 0x4252bf VADDPD 0x40(%R15,%RAX,1),%ZMM1,%ZMM3 |
(106) 0x4252c7 VADDPD 0x40(%RSI,%RAX,1),%ZMM6,%ZMM7 |
(106) 0x4252cf VSUBPD %ZMM7,%ZMM3,%ZMM8 |
(106) 0x4252d5 VADDPD 0x40(%R13,%RAX,1),%ZMM8,%ZMM9 |
(106) 0x4252dd VMOVUPD %ZMM9,0x40(%R12,%RAX,1) |
(106) 0x4252e5 VMOVUPD 0x40(%RSI,%RAX,1),%ZMM10 |
(106) 0x4252ed VSUBPD 0x40(%RCX,%RAX,1),%ZMM10,%ZMM11 |
(106) 0x4252f5 VADDPD %ZMM9,%ZMM11,%ZMM12 |
(106) 0x4252fb VMOVUPD %ZMM12,0x40(%RBX,%RAX,1) |
(106) 0x425303 VMOVUPD 0x80(%RCX,%RAX,1),%ZMM13 |
(106) 0x42530b VMOVUPD 0x80(%R14,%RAX,1),%ZMM15 |
(106) 0x425313 VADDPD 0x80(%R15,%RAX,1),%ZMM13,%ZMM14 |
(106) 0x42531b VADDPD 0x80(%RSI,%RAX,1),%ZMM15,%ZMM4 |
(106) 0x425323 VSUBPD %ZMM4,%ZMM14,%ZMM0 |
(106) 0x425329 VADDPD 0x80(%R13,%RAX,1),%ZMM0,%ZMM5 |
(106) 0x425331 VMOVUPD %ZMM5,0x80(%R12,%RAX,1) |
(106) 0x425339 VMOVUPD 0x80(%RSI,%RAX,1),%ZMM2 |
(106) 0x425341 VSUBPD 0x80(%RCX,%RAX,1),%ZMM2,%ZMM1 |
(106) 0x425349 VADDPD %ZMM5,%ZMM1,%ZMM3 |
(106) 0x42534f VMOVUPD %ZMM3,0x80(%RBX,%RAX,1) |
(106) 0x425357 VMOVUPD 0xc0(%RCX,%RAX,1),%ZMM6 |
(106) 0x42535f VMOVUPD 0xc0(%R14,%RAX,1),%ZMM8 |
(106) 0x425367 VADDPD 0xc0(%R15,%RAX,1),%ZMM6,%ZMM7 |
(106) 0x42536f VADDPD 0xc0(%RSI,%RAX,1),%ZMM8,%ZMM9 |
(106) 0x425377 VSUBPD %ZMM9,%ZMM7,%ZMM10 |
(106) 0x42537d VADDPD 0xc0(%R13,%RAX,1),%ZMM10,%ZMM11 |
(106) 0x425385 VMOVUPD %ZMM11,0xc0(%R12,%RAX,1) |
(106) 0x42538d VMOVUPD 0xc0(%RSI,%RAX,1),%ZMM12 |
(106) 0x425395 VSUBPD 0xc0(%RCX,%RAX,1),%ZMM12,%ZMM13 |
(106) 0x42539d VADDPD %ZMM11,%ZMM13,%ZMM14 |
(106) 0x4253a3 VMOVUPD %ZMM14,0xc0(%RBX,%RAX,1) |
(106) 0x4253ab ADD $0x100,%RAX |
(106) 0x4253b1 CMP %RAX,%R11 |
(106) 0x4253b4 JNE 425263 |
(105) 0x4253ba MOV 0xa0(%RSP),%R15D |
(105) 0x4253c2 MOV %EDX,%R13D |
(105) 0x4253c5 AND $-0x8,%R13D |
(105) 0x4253c9 ADD %R13D,%R9D |
(105) 0x4253cc LEA (%R13,%R15,1),%ESI |
(105) 0x4253d1 TEST $0x7,%DL |
(105) 0x4253d4 JE 42567b |
(105) 0x4253da SUB %R13D,%EDX |
(105) 0x4253dd LEA -0x1(%RDX),%ECX |
(105) 0x4253e0 CMP $0x2,%ECX |
(105) 0x4253e3 JBE 4254b0 |
(105) 0x4253e9 MOVSXD 0xa0(%RSP),%RAX |
(105) 0x4253f1 MOV 0x70(%RSP),%R14 |
(105) 0x4253f6 MOV 0x78(%RSP),%R15 |
(105) 0x4253fb MOV 0x68(%RSP),%R10 |
(105) 0x425400 LEA (%R14,%RAX,1),%R12 |
(105) 0x425404 LEA 0x1(%R13,%R12,1),%R11 |
(105) 0x425409 LEA (%R15,%RAX,1),%R12 |
(105) 0x42540d MOV 0x90(%RSP),%R15 |
(105) 0x425415 SAL $0x3,%R11 |
(105) 0x425419 ADD %R13,%R12 |
(105) 0x42541c LEA (%R10,%RAX,1),%R14 |
(105) 0x425420 MOV 0x80(%RSP),%R10 |
(105) 0x425428 LEA (%R8,%R11,1),%RBX |
(105) 0x42542c VMOVUPD (%RDI,%R12,8),%YMM15 |
(105) 0x425432 LEA -0x8(%R8,%R11,1),%RCX |
(105) 0x425437 MOV 0x98(%RSP),%R11 |
(105) 0x42543f VMOVUPD (%RBX),%YMM0 |
(105) 0x425443 ADD %R13,%R14 |
(105) 0x425446 LEA (%R15,%RAX,1),%R12 |
(105) 0x42544a VADDPD (%R11,%R14,8),%YMM15,%YMM4 |
(105) 0x425450 LEA (%R10,%RAX,1),%R14 |
(105) 0x425454 MOV 0xa8(%RSP),%R11 |
(105) 0x42545c ADD %R13,%R12 |
(105) 0x42545f VSUBPD (%RCX),%YMM0,%YMM5 |
(105) 0x425463 ADD %R13,%R14 |
(105) 0x425466 VADDPD %YMM5,%YMM4,%YMM2 |
(105) 0x42546a VSUBPD (%RDI,%R14,8),%YMM2,%YMM3 |
(105) 0x425470 VMOVUPD %YMM3,(%R11,%R12,8) |
(105) 0x425476 VMOVUPD (%RCX),%YMM1 |
(105) 0x42547a VSUBPD (%RBX),%YMM1,%YMM6 |
(105) 0x42547e MOV 0xb0(%RSP),%RBX |
(105) 0x425486 ADD %RBX,%RAX |
(105) 0x425489 VADDPD %YMM3,%YMM6,%YMM7 |
(105) 0x42548d ADD %R13,%RAX |
(105) 0x425490 MOV 0xb8(%RSP),%R13 |
(105) 0x425498 VMOVUPD %YMM7,(%R13,%RAX,8) |
(105) 0x42549f TEST $0x3,%DL |
(105) 0x4254a2 JE 42567b |
(105) 0x4254a8 AND $-0x4,%EDX |
(105) 0x4254ab ADD %EDX,%R9D |
(105) 0x4254ae ADD %EDX,%ESI |
(105) 0x4254b0 MOV 0x70(%RSP),%R15 |
(105) 0x4254b5 LEA 0x1(%RSI),%EDX |
(105) 0x4254b8 MOV 0x68(%RSP),%R14 |
(105) 0x4254bd MOVSXD %ESI,%RAX |
(105) 0x4254c0 MOVSXD %EDX,%RDX |
(105) 0x4254c3 MOV 0x98(%RSP),%R12 |
(105) 0x4254cb MOV 0x78(%RSP),%R13 |
(105) 0x4254d0 LEA (%R15,%RDX,1),%RCX |
(105) 0x4254d4 LEA (%R14,%RAX,1),%RBX |
(105) 0x4254d8 LEA (%R8,%RCX,8),%RCX |
(105) 0x4254dc VMOVSD (%R12,%RBX,8),%XMM8 |
(105) 0x4254e2 LEA (%R15,%RAX,1),%R10 |
(105) 0x4254e6 MOV 0x80(%RSP),%R12 |
(105) 0x4254ee VMOVSD (%RCX),%XMM10 |
(105) 0x4254f2 LEA (%R8,%R10,8),%R10 |
(105) 0x4254f6 LEA (%R13,%RAX,1),%R11 |
(105) 0x4254fb VADDSD (%RDI,%R11,8),%XMM8,%XMM9 |
(105) 0x425501 LEA (%R12,%RAX,1),%RBX |
(105) 0x425505 MOV 0x90(%RSP),%R11 |
(105) 0x42550d VSUBSD (%R10),%XMM10,%XMM11 |
(105) 0x425512 LEA (%R11,%RAX,1),%R11 |
(105) 0x425516 VADDSD %XMM11,%XMM9,%XMM12 |
(105) 0x42551b VSUBSD (%RDI,%RBX,8),%XMM12,%XMM13 |
(105) 0x425520 MOV 0xa8(%RSP),%RBX |
(105) 0x425528 VMOVSD %XMM13,(%RBX,%R11,8) |
(105) 0x42552e MOV 0xb0(%RSP),%R11 |
(105) 0x425536 MOV 0x8c(%RSP),%EBX |
(105) 0x42553d VMOVSD (%R10),%XMM14 |
(105) 0x425542 MOV 0xb8(%RSP),%R10 |
(105) 0x42554a ADD %R11,%RAX |
(105) 0x42554d VSUBSD (%RCX),%XMM14,%XMM15 |
(105) 0x425551 VADDSD %XMM13,%XMM15,%XMM4 |
(105) 0x425556 VMOVSD %XMM4,(%R10,%RAX,8) |
(105) 0x42555c LEA 0x1(%R9),%EAX |
(105) 0x425560 CMP %EBX,%EAX |
(105) 0x425562 JAE 42567b |
(105) 0x425568 LEA 0x2(%RSI),%EAX |
(105) 0x42556b MOV %R15,%RBX |
(105) 0x42556e LEA (%RDX,%R14,1),%R11 |
(105) 0x425572 ADD $0x2,%R9D |
(105) 0x425576 CLTQ |
(105) 0x425578 LEA (%R15,%RAX,1),%R15 |
(105) 0x42557c LEA (%R8,%R15,8),%R10 |
(105) 0x425580 MOV 0x98(%RSP),%R15 |
(105) 0x425588 MOV %R10,0xa0(%RSP) |
(105) 0x425590 VMOVSD (%R15,%R11,8),%XMM0 |
(105) 0x425596 MOV %R12,%R15 |
(105) 0x425599 LEA (%R12,%RDX,1),%R12 |
(105) 0x42559d VMOVSD (%RDI,%R12,8),%XMM2 |
(105) 0x4255a3 MOV 0x90(%RSP),%R12 |
(105) 0x4255ab VADDSD (%R10),%XMM0,%XMM5 |
(105) 0x4255b0 LEA (%R13,%RDX,1),%R10 |
(105) 0x4255b5 VADDSD (%RCX),%XMM2,%XMM3 |
(105) 0x4255b9 LEA (%R12,%RDX,1),%R11 |
(105) 0x4255bd VSUBSD %XMM3,%XMM5,%XMM1 |
(105) 0x4255c1 VADDSD (%RDI,%R10,8),%XMM1,%XMM6 |
(105) 0x4255c7 MOV 0xa8(%RSP),%R10 |
(105) 0x4255cf VMOVSD %XMM6,(%R10,%R11,8) |
(105) 0x4255d5 MOV 0xb0(%RSP),%R11 |
(105) 0x4255dd VMOVSD (%RCX),%XMM7 |
(105) 0x4255e1 MOV 0xa0(%RSP),%RCX |
(105) 0x4255e9 ADD %R11,%RDX |
(105) 0x4255ec VSUBSD (%RCX),%XMM7,%XMM8 |
(105) 0x4255f0 MOV 0xb8(%RSP),%RCX |
(105) 0x4255f8 VADDSD %XMM6,%XMM8,%XMM9 |
(105) 0x4255fc VMOVSD %XMM9,(%RCX,%RDX,8) |
(105) 0x425601 MOV 0x8c(%RSP),%EDX |
(105) 0x425608 CMP %EDX,%R9D |
(105) 0x42560b JAE 42567b |
(105) 0x42560d ADD $0x3,%ESI |
(105) 0x425610 ADD %RAX,%R14 |
(105) 0x425613 ADD %RAX,%R15 |
(105) 0x425616 ADD %RAX,%R13 |
(105) 0x425619 MOVSXD %ESI,%R9 |
(105) 0x42561c MOV 0x98(%RSP),%RSI |
(105) 0x425624 VMOVSD (%RDI,%R15,8),%XMM12 |
(105) 0x42562a ADD %RAX,%R12 |
(105) 0x42562d ADD %RBX,%R9 |
(105) 0x425630 MOV 0xa0(%RSP),%RBX |
(105) 0x425638 ADD %RAX,%R11 |
(105) 0x42563b VMOVSD (%RSI,%R14,8),%XMM10 |
(105) 0x425641 LEA (%R8,%R9,8),%R8 |
(105) 0x425645 VADDSD (%RBX),%XMM12,%XMM13 |
(105) 0x425649 VADDSD (%R8),%XMM10,%XMM11 |
(105) 0x42564e VSUBSD %XMM13,%XMM11,%XMM14 |
(105) 0x425653 VADDSD (%RDI,%R13,8),%XMM14,%XMM15 |
(105) 0x425659 MOV 0xb8(%RSP),%RDI |
(105) 0x425661 VMOVSD %XMM15,(%R10,%R12,8) |
(105) 0x425667 VMOVSD (%RBX),%XMM4 |
(105) 0x42566b VSUBSD (%R8),%XMM4,%XMM0 |
(105) 0x425670 VADDSD %XMM15,%XMM0,%XMM5 |
(105) 0x425675 VMOVSD %XMM5,(%RDI,%R11,8) |
(105) 0x42567b MOV 0x8c(%RSP),%R9D |
(105) 0x425683 MOV 0x60(%RSP),%RCX |
(105) 0x425688 LEA (%RCX),%EAX |
(105) 0x42568a CMP %EAX,0x5c(%RSP) |
(105) 0x42568e JLE 4256b0 |
(105) 0x425690 MOV 0x54(%RSP),%ESI |
(105) 0x425694 MOV 0x58(%RSP),%EDX |
(105) 0x425698 MOV 0x88(%RSP),%R10D |
(105) 0x4256a0 MOV %EDX,0xa0(%RSP) |
(105) 0x4256a7 SUB %R9D,%ESI |
(105) 0x4256aa JMP 425020 |
0x4256af NOP |
0x4256b0 VZEROUPPER |
0x4256b3 LEA -0x28(%RBP),%RSP |
0x4256b7 POP %RBX |
0x4256b8 POP %R12 |
0x4256ba POP %R13 |
0x4256bc POP %R14 |
0x4256be POP %R15 |
0x4256c0 POP %RBP |
0x4256c1 RET |
0x4256c2 NOPW (%RAX,%RAX,1) |
(105) 0x4256c8 LEA 0x1(%RCX),%R13 |
(105) 0x4256cc MOV %R13,0x60(%RSP) |
(105) 0x4256d1 JMP 425683 |
0x4256d3 NOPL (%RAX,%RAX,1) |
(105) 0x4256d8 MOV 0xa0(%RSP),%ESI |
(105) 0x4256df XOR %R13D,%R13D |
(105) 0x4256e2 JMP 4253da |
0x4256e7 INC %ESI |
0x4256e9 XOR %EDX,%EDX |
0x4256eb JMP 424fab |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
○98.16 | gomp_thread_start | team.c:130 | libgomp.so.1.0.0 |
○1.84 | GOMP_parallel | libgomp.h:985 | libgomp.so.1.0.0 |
Path / |
Source file and lines | advec_cell.cpp:44-48 |
Module | exec |
nb instructions | 82 |
nb uops | 92 |
loop length | 295 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 11 |
micro-operation queue | 15.33 cycles |
front end | 15.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.10 | 8.00 | 6.33 | 6.33 | 9.00 | 6.07 | 5.90 | 9.00 | 9.00 | 9.00 | 5.93 | 6.33 |
cycles | 6.10 | 11.93 | 6.33 | 6.33 | 9.00 | 6.07 | 5.90 | 9.00 | 9.00 | 9.00 | 5.93 | 6.33 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.56-14.66 |
Stall cycles | 0.00 |
Front-end | 15.33 |
Dispatch | 11.93 |
DIV/SQRT | 12.00 |
Overall L1 | 15.33 |
all | 3% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 11% |
all | 8% |
load | 9% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 9% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0xc0,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x30(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x34(%RDI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RDI),%EDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%R12),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x4,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA -0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
DEC %EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ECX,0x5c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EDI,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %ECX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 4256b3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0.lto_priv.0+0x793> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %ECX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x4(%RDX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 4256b3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0.lto_priv.0+0x793> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R14D,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %EDI,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ESI,0x88(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x88(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R13D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 4256e7 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0.lto_priv.0+0x7c7> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %ESI,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RSI,%R9,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R10D,0x54(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R10D,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 4256b3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0.lto_priv.0+0x793> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R9D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x58(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R12),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x88(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x8(%R12),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%R12),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDI,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14D,%R10D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x10(%R12),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%R12),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R14,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%RAX,%R15,1),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R11D,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R11D,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %R15D,%RCX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 424fab <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0.lto_priv.0+0x8b> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
Source file and lines | advec_cell.cpp:44-48 |
Module | exec |
nb instructions | 82 |
nb uops | 92 |
loop length | 295 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 11 |
micro-operation queue | 15.33 cycles |
front end | 15.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.10 | 8.00 | 6.33 | 6.33 | 9.00 | 6.07 | 5.90 | 9.00 | 9.00 | 9.00 | 5.93 | 6.33 |
cycles | 6.10 | 11.93 | 6.33 | 6.33 | 9.00 | 6.07 | 5.90 | 9.00 | 9.00 | 9.00 | 5.93 | 6.33 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.56-14.66 |
Stall cycles | 0.00 |
Front-end | 15.33 |
Dispatch | 11.93 |
DIV/SQRT | 12.00 |
Overall L1 | 15.33 |
all | 3% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 11% |
all | 8% |
load | 9% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 9% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0xc0,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x30(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x34(%RDI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RDI),%EDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%R12),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x4,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA -0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
DEC %EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ECX,0x5c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EDI,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %ECX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 4256b3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0.lto_priv.0+0x793> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %ECX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x4(%RDX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 4256b3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0.lto_priv.0+0x793> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R14D,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %EDI,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ESI,0x88(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x88(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R13D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 4256e7 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0.lto_priv.0+0x7c7> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %ESI,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RSI,%R9,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R10D,0x54(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R10D,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 4256b3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0.lto_priv.0+0x793> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R9D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x58(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R12),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x88(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x8(%R12),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%R12),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDI,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14D,%R10D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x10(%R12),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%R12),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R14,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%RAX,%R15,1),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R11D,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R11D,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %R15D,%RCX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 424fab <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0.lto_priv.0+0x8b> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D | 1.52 | 1.14 |
▼Loop 105 - advec_cell.cpp:44-48 - exec– | 0 | 0 |
○Loop 106 - advec_cell.cpp:47-48 - exec | 1.52 | 1.13 |