Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ... | Module: exec | Source: advec_mom.cpp:44-48 [...] | Coverage: 3.06% |
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Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ... | Module: exec | Source: advec_mom.cpp:44-48 [...] | Coverage: 3.06% |
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/scratch_na/users/xoserete/qaas_runs/171-415-4687/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69 |
-------------------------------------------------------------------------------- |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
/scratch_na/users/xoserete/qaas_runs/171-415-4687/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp: 44 - 48 |
-------------------------------------------------------------------------------- |
44: #pragma omp parallel for simd collapse(2) |
45: for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) { |
46: for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) { |
47: post_vol(i, j) = volume(i, j) + vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j); |
48: pre_vol(i, j) = post_vol(i, j) + vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j); |
0x428e40 PUSH %RBP |
0x428e41 MOV %RSP,%RBP |
0x428e44 PUSH %R15 |
0x428e46 PUSH %R14 |
0x428e48 PUSH %R13 |
0x428e4a PUSH %R12 |
0x428e4c MOV %RDI,%R12 |
0x428e4f PUSH %RBX |
0x428e50 AND $-0x40,%RSP |
0x428e54 SUB $0xc0,%RSP |
0x428e5b MOV 0x30(%RDI),%EAX |
0x428e5e MOV 0x34(%RDI),%EDX |
0x428e61 MOV 0x28(%RDI),%ESI |
0x428e64 MOV 0x2c(%R12),%ECX |
0x428e69 ADD $0x4,%EDX |
0x428e6c LEA -0x1(%RAX),%R15D |
0x428e70 LEA -0x1(%RSI),%EDI |
0x428e73 MOV %EDX,0x60(%RSP) |
0x428e77 MOV %EDI,0x5c(%RSP) |
0x428e7b CMP %EDX,%R15D |
0x428e7e JGE 4294db |
0x428e84 MOV %EDX,%EBX |
0x428e86 LEA 0x4(%RCX),%R14D |
0x428e8a SUB %R15D,%EBX |
0x428e8d CMP %R14D,%EDI |
0x428e90 JGE 4294db |
0x428e96 MOV %R14D,%R8D |
0x428e99 SUB %EDI,%R8D |
0x428e9c MOV %R8D,0x64(%RSP) |
0x428ea1 CALL 4046c0 <omp_get_num_threads@plt> |
0x428ea6 MOV %EAX,%R13D |
0x428ea9 CALL 4045b0 <omp_get_thread_num@plt> |
0x428eae XOR %EDX,%EDX |
0x428eb0 MOV %EAX,%R9D |
0x428eb3 MOV 0x64(%RSP),%EAX |
0x428eb7 IMUL %EBX,%EAX |
0x428eba DIV %R13D |
0x428ebd MOV %EAX,%R13D |
0x428ec0 CMP %EDX,%R9D |
0x428ec3 JB 429510 |
0x428ec9 IMUL %R13D,%R9D |
0x428ecd LEA (%R9,%RDX,1),%EDI |
0x428ed1 LEA (%R13,%RDI,1),%R10D |
0x428ed6 MOV %R10D,0x58(%RSP) |
0x428edb CMP %R10D,%EDI |
0x428ede JAE 4294db |
0x428ee4 MOV %EDI,%EAX |
0x428ee6 XOR %EDX,%EDX |
0x428ee8 MOV 0x5c(%RSP),%R11D |
0x428eed MOV (%R12),%R8 |
0x428ef1 DIVL 0x64(%RSP) |
0x428ef5 MOV 0x10(%R12),%RSI |
0x428efa MOV 0x20(%R12),%RBX |
0x428eff MOV %R8,0x38(%RSP) |
0x428f04 MOV %RSI,0x50(%RSP) |
0x428f09 MOV %RBX,0x40(%RSP) |
0x428f0e ADD %EDX,%R11D |
0x428f11 MOV %R14D,%EDX |
0x428f14 MOV 0x8(%R12),%R14 |
0x428f19 MOV 0x18(%R12),%R12 |
0x428f1e MOV %R11D,0xb4(%RSP) |
0x428f26 LEA (%RAX,%R15,1),%R15D |
0x428f2a SUB %R11D,%EDX |
0x428f2d MOV %R14,0x48(%RSP) |
0x428f32 MOVSXD %R15D,%R8 |
0x428f35 MOV %R12,0x30(%RSP) |
0x428f3a NOPW (%RAX,%RAX,1) |
(124) 0x428f40 CMP %EDX,%R13D |
(124) 0x428f43 CMOVBE %R13D,%EDX |
(124) 0x428f47 LEA (%RDI,%RDX,1),%ECX |
(124) 0x428f4a MOV %ECX,0xb0(%RSP) |
(124) 0x428f51 CMP %ECX,%EDI |
(124) 0x428f53 JAE 4294f0 |
(124) 0x428f59 MOV 0x48(%RSP),%R10 |
(124) 0x428f5e LEA 0x1(%R8),%R14 |
(124) 0x428f62 MOV 0x50(%RSP),%R9 |
(124) 0x428f67 MOV %R14,0x68(%RSP) |
(124) 0x428f6c MOV 0x40(%RSP),%R11 |
(124) 0x428f71 MOV (%R10),%RAX |
(124) 0x428f74 MOV 0x10(%R9),%R13 |
(124) 0x428f78 MOV (%R9),%R15 |
(124) 0x428f7b MOV 0x10(%R10),%RCX |
(124) 0x428f7f IMUL %RAX,%R14 |
(124) 0x428f83 MOV 0x38(%RSP),%R9 |
(124) 0x428f88 MOV 0x10(%R11),%R12 |
(124) 0x428f8c MOV %R13,0xa0(%RSP) |
(124) 0x428f94 MOV (%R11),%R11 |
(124) 0x428f97 IMUL %R8,%R15 |
(124) 0x428f9b MOV 0x10(%R9),%RSI |
(124) 0x428f9f MOV (%R9),%R9 |
(124) 0x428fa2 MOV %R12,0xa8(%RSP) |
(124) 0x428faa MOV %R14,%RBX |
(124) 0x428fad IMUL %R8,%R11 |
(124) 0x428fb1 MOV %R14,0x78(%RSP) |
(124) 0x428fb6 SUB %RAX,%RBX |
(124) 0x428fb9 MOV 0x30(%RSP),%RAX |
(124) 0x428fbe IMUL %R8,%R9 |
(124) 0x428fc2 MOV %R15,0x70(%RSP) |
(124) 0x428fc7 MOV %RBX,0x80(%RSP) |
(124) 0x428fcf MOV 0x10(%RAX),%R10 |
(124) 0x428fd3 MOV %R11,0x88(%RSP) |
(124) 0x428fdb MOV %R9,0x90(%RSP) |
(124) 0x428fe3 MOV %R10,0xb8(%RSP) |
(124) 0x428feb MOV (%RAX),%R10 |
(124) 0x428fee IMUL %R8,%R10 |
(124) 0x428ff2 LEA -0x1(%RDX),%R8D |
(124) 0x428ff6 MOV %R10,0x98(%RSP) |
(124) 0x428ffe CMP $0x6,%R8D |
(124) 0x429002 JBE 429500 |
(124) 0x429008 MOVSXD 0xb4(%RSP),%RAX |
(124) 0x429010 LEA 0x1(%R9,%RAX,1),%R8 |
(124) 0x429015 MOV %EDX,%R9D |
(124) 0x429018 LEA (%RBX,%RAX,1),%RBX |
(124) 0x42901c SHR $0x3,%R9D |
(124) 0x429020 LEA (%R11,%RAX,1),%R11 |
(124) 0x429024 SAL $0x3,%R8 |
(124) 0x429028 LEA (%R15,%RAX,1),%R15 |
(124) 0x42902c SAL $0x6,%R9 |
(124) 0x429030 LEA (%R13,%R15,8),%R15 |
(124) 0x429035 LEA (%R12,%R11,8),%R12 |
(124) 0x429039 LEA (%RCX,%RBX,8),%R13 |
(124) 0x42903d LEA -0x8(%RSI,%R8,1),%R11 |
(124) 0x429042 LEA (%RSI,%R8,1),%RBX |
(124) 0x429046 LEA -0x40(%R9),%R8 |
(124) 0x42904a LEA (%R14,%RAX,1),%R14 |
(124) 0x42904e SHR $0x6,%R8 |
(124) 0x429052 ADD %R10,%RAX |
(124) 0x429055 MOV 0xb8(%RSP),%R10 |
(124) 0x42905d INC %R8 |
(124) 0x429060 LEA (%RCX,%R14,8),%R14 |
(124) 0x429064 LEA (%R10,%RAX,8),%R10 |
(124) 0x429068 XOR %EAX,%EAX |
(124) 0x42906a AND $0x3,%R8D |
(124) 0x42906e JE 429138 |
(124) 0x429074 CMP $0x1,%R8 |
(124) 0x429078 JE 4290f3 |
(124) 0x42907a CMP $0x2,%R8 |
(124) 0x42907e JE 4290b7 |
(124) 0x429080 VMOVUPD (%R14),%ZMM7 |
(124) 0x429086 MOV $0x40,%EAX |
(124) 0x42908b VADDPD (%R15),%ZMM7,%ZMM0 |
(124) 0x429091 VSUBPD (%R13),%ZMM0,%ZMM2 |
(124) 0x429098 VMOVUPD %ZMM2,(%R12) |
(124) 0x42909f VMOVUPD (%RBX),%ZMM1 |
(124) 0x4290a5 VSUBPD (%R11),%ZMM1,%ZMM3 |
(124) 0x4290ab VADDPD %ZMM2,%ZMM3,%ZMM4 |
(124) 0x4290b1 VMOVUPD %ZMM4,(%R10) |
(124) 0x4290b7 VMOVUPD (%R14,%RAX,1),%ZMM5 |
(124) 0x4290be VADDPD (%R15,%RAX,1),%ZMM5,%ZMM6 |
(124) 0x4290c5 VSUBPD (%R13,%RAX,1),%ZMM6,%ZMM8 |
(124) 0x4290cd VMOVUPD %ZMM8,(%R12,%RAX,1) |
(124) 0x4290d4 VMOVUPD (%RBX,%RAX,1),%ZMM9 |
(124) 0x4290db VSUBPD (%R11,%RAX,1),%ZMM9,%ZMM10 |
(124) 0x4290e2 VADDPD %ZMM8,%ZMM10,%ZMM11 |
(124) 0x4290e8 VMOVUPD %ZMM11,(%R10,%RAX,1) |
(124) 0x4290ef ADD $0x40,%RAX |
(124) 0x4290f3 VMOVUPD (%R14,%RAX,1),%ZMM12 |
(124) 0x4290fa VADDPD (%R15,%RAX,1),%ZMM12,%ZMM13 |
(124) 0x429101 VSUBPD (%R13,%RAX,1),%ZMM13,%ZMM14 |
(124) 0x429109 VMOVUPD %ZMM14,(%R12,%RAX,1) |
(124) 0x429110 VMOVUPD (%RBX,%RAX,1),%ZMM15 |
(124) 0x429117 VSUBPD (%R11,%RAX,1),%ZMM15,%ZMM7 |
(124) 0x42911e VADDPD %ZMM14,%ZMM7,%ZMM0 |
(124) 0x429124 VMOVUPD %ZMM0,(%R10,%RAX,1) |
(124) 0x42912b ADD $0x40,%RAX |
(124) 0x42912f CMP %RAX,%R9 |
(124) 0x429132 JE 429239 |
(125) 0x429138 VMOVUPD (%R14,%RAX,1),%ZMM2 |
(125) 0x42913f VADDPD (%R15,%RAX,1),%ZMM2,%ZMM1 |
(125) 0x429146 VSUBPD (%R13,%RAX,1),%ZMM1,%ZMM3 |
(125) 0x42914e VMOVUPD %ZMM3,(%R12,%RAX,1) |
(125) 0x429155 VMOVUPD (%RBX,%RAX,1),%ZMM4 |
(125) 0x42915c VSUBPD (%R11,%RAX,1),%ZMM4,%ZMM5 |
(125) 0x429163 VADDPD %ZMM3,%ZMM5,%ZMM6 |
(125) 0x429169 VMOVUPD %ZMM6,(%R10,%RAX,1) |
(125) 0x429170 VMOVUPD 0x40(%R14,%RAX,1),%ZMM8 |
(125) 0x429178 VADDPD 0x40(%R15,%RAX,1),%ZMM8,%ZMM9 |
(125) 0x429180 VSUBPD 0x40(%R13,%RAX,1),%ZMM9,%ZMM10 |
(125) 0x429188 VMOVUPD %ZMM10,0x40(%R12,%RAX,1) |
(125) 0x429190 VMOVUPD 0x40(%RBX,%RAX,1),%ZMM11 |
(125) 0x429198 VSUBPD 0x40(%R11,%RAX,1),%ZMM11,%ZMM12 |
(125) 0x4291a0 VADDPD %ZMM10,%ZMM12,%ZMM13 |
(125) 0x4291a6 VMOVUPD %ZMM13,0x40(%R10,%RAX,1) |
(125) 0x4291ae VMOVUPD 0x80(%R14,%RAX,1),%ZMM14 |
(125) 0x4291b6 VADDPD 0x80(%R15,%RAX,1),%ZMM14,%ZMM15 |
(125) 0x4291be VSUBPD 0x80(%R13,%RAX,1),%ZMM15,%ZMM7 |
(125) 0x4291c6 VMOVUPD %ZMM7,0x80(%R12,%RAX,1) |
(125) 0x4291ce VMOVUPD 0x80(%RBX,%RAX,1),%ZMM0 |
(125) 0x4291d6 VSUBPD 0x80(%R11,%RAX,1),%ZMM0,%ZMM2 |
(125) 0x4291de VADDPD %ZMM7,%ZMM2,%ZMM1 |
(125) 0x4291e4 VMOVUPD %ZMM1,0x80(%R10,%RAX,1) |
(125) 0x4291ec VMOVUPD 0xc0(%R14,%RAX,1),%ZMM3 |
(125) 0x4291f4 VADDPD 0xc0(%R15,%RAX,1),%ZMM3,%ZMM4 |
(125) 0x4291fc VSUBPD 0xc0(%R13,%RAX,1),%ZMM4,%ZMM6 |
(125) 0x429204 VMOVUPD %ZMM6,0xc0(%R12,%RAX,1) |
(125) 0x42920c VMOVUPD 0xc0(%RBX,%RAX,1),%ZMM5 |
(125) 0x429214 VSUBPD 0xc0(%R11,%RAX,1),%ZMM5,%ZMM8 |
(125) 0x42921c VADDPD %ZMM6,%ZMM8,%ZMM9 |
(125) 0x429222 VMOVUPD %ZMM9,0xc0(%R10,%RAX,1) |
(125) 0x42922a ADD $0x100,%RAX |
(125) 0x429230 CMP %RAX,%R9 |
(125) 0x429233 JNE 429138 |
(124) 0x429239 MOV 0xb4(%RSP),%R15D |
(124) 0x429241 MOV %EDX,%R13D |
(124) 0x429244 AND $-0x8,%R13D |
(124) 0x429248 ADD %R13D,%EDI |
(124) 0x42924b LEA (%R13,%R15,1),%R9D |
(124) 0x429250 TEST $0x7,%DL |
(124) 0x429253 JE 4294a0 |
(124) 0x429259 SUB %R13D,%EDX |
(124) 0x42925c LEA -0x1(%RDX),%R14D |
(124) 0x429260 CMP $0x2,%R14D |
(124) 0x429264 JBE 429320 |
(124) 0x42926a MOVSXD 0xb4(%RSP),%R12 |
(124) 0x429272 MOV 0x78(%RSP),%R15 |
(124) 0x429277 MOV 0x90(%RSP),%RBX |
(124) 0x42927f MOV 0x70(%RSP),%R10 |
(124) 0x429284 LEA (%R15,%R12,1),%R14 |
(124) 0x429288 ADD %R13,%R14 |
(124) 0x42928b LEA (%RBX,%R12,1),%R11 |
(124) 0x42928f LEA (%R10,%R12,1),%RAX |
(124) 0x429293 MOV 0xa0(%RSP),%RBX |
(124) 0x42929b VMOVUPD (%RCX,%R14,8),%YMM10 |
(124) 0x4292a1 LEA 0x1(%R13,%R11,1),%R8 |
(124) 0x4292a6 ADD %R13,%RAX |
(124) 0x4292a9 MOV 0x80(%RSP),%R11 |
(124) 0x4292b1 MOV 0xa8(%RSP),%R14 |
(124) 0x4292b9 VADDPD (%RBX,%RAX,8),%YMM10,%YMM11 |
(124) 0x4292be LEA (%R11,%R12,1),%R10 |
(124) 0x4292c2 MOV 0x88(%RSP),%RAX |
(124) 0x4292ca ADD %R13,%R10 |
(124) 0x4292cd LEA (%RAX,%R12,1),%R15 |
(124) 0x4292d1 VSUBPD (%RCX,%R10,8),%YMM11,%YMM12 |
(124) 0x4292d7 ADD %R13,%R15 |
(124) 0x4292da VMOVUPD %YMM12,(%R14,%R15,8) |
(124) 0x4292e0 VMOVUPD (%RSI,%R8,8),%YMM13 |
(124) 0x4292e6 VSUBPD -0x8(%RSI,%R8,8),%YMM13,%YMM14 |
(124) 0x4292ed MOV 0x98(%RSP),%R8 |
(124) 0x4292f5 ADD %R8,%R12 |
(124) 0x4292f8 VADDPD %YMM12,%YMM14,%YMM15 |
(124) 0x4292fd ADD %R13,%R12 |
(124) 0x429300 MOV 0xb8(%RSP),%R13 |
(124) 0x429308 VMOVUPD %YMM15,(%R13,%R12,8) |
(124) 0x42930f TEST $0x3,%DL |
(124) 0x429312 JE 4294a0 |
(124) 0x429318 AND $-0x4,%EDX |
(124) 0x42931b ADD %EDX,%EDI |
(124) 0x42931d ADD %EDX,%R9D |
(124) 0x429320 MOV 0x78(%RSP),%R15 |
(124) 0x429325 MOVSXD %R9D,%RDX |
(124) 0x429328 MOV 0x70(%RSP),%R14 |
(124) 0x42932d MOV 0xa0(%RSP),%RBX |
(124) 0x429335 MOV 0x88(%RSP),%R13 |
(124) 0x42933d LEA (%R15,%RDX,1),%R12 |
(124) 0x429341 LEA (%R14,%RDX,1),%R11 |
(124) 0x429345 MOV 0xa8(%RSP),%R8 |
(124) 0x42934d VMOVSD (%RCX,%R12,8),%XMM7 |
(124) 0x429353 LEA (%R13,%RDX,1),%RAX |
(124) 0x429358 VADDSD (%RBX,%R11,8),%XMM7,%XMM0 |
(124) 0x42935e MOV 0x80(%RSP),%R11 |
(124) 0x429366 MOV 0x90(%RSP),%RBX |
(124) 0x42936e LEA (%R11,%RDX,1),%R10 |
(124) 0x429372 VSUBSD (%RCX,%R10,8),%XMM0,%XMM2 |
(124) 0x429378 VMOVSD %XMM2,(%R8,%RAX,8) |
(124) 0x42937e LEA 0x1(%R9),%EAX |
(124) 0x429382 CLTQ |
(124) 0x429384 LEA (%RBX,%RAX,1),%R12 |
(124) 0x429388 LEA (%RSI,%R12,8),%R8 |
(124) 0x42938c MOV 0x98(%RSP),%R12 |
(124) 0x429394 VMOVSD (%R8),%XMM1 |
(124) 0x429399 LEA (%R12,%RDX,1),%R10 |
(124) 0x42939d ADD %RBX,%RDX |
(124) 0x4293a0 VSUBSD (%RSI,%RDX,8),%XMM1,%XMM3 |
(124) 0x4293a5 MOV 0xb8(%RSP),%RDX |
(124) 0x4293ad VADDSD %XMM2,%XMM3,%XMM4 |
(124) 0x4293b1 VMOVSD %XMM4,(%RDX,%R10,8) |
(124) 0x4293b7 MOV 0xb0(%RSP),%R10D |
(124) 0x4293bf LEA 0x1(%RDI),%EDX |
(124) 0x4293c2 CMP %R10D,%EDX |
(124) 0x4293c5 JAE 4294a0 |
(124) 0x4293cb LEA (%RAX,%R15,1),%R10 |
(124) 0x4293cf LEA (%RAX,%R14,1),%RDX |
(124) 0x4293d3 ADD $0x2,%EDI |
(124) 0x4293d6 VMOVSD (%RCX,%R10,8),%XMM6 |
(124) 0x4293dc MOV 0xa0(%RSP),%R10 |
(124) 0x4293e4 VADDSD (%R10,%RDX,8),%XMM6,%XMM5 |
(124) 0x4293ea LEA (%RAX,%R11,1),%RDX |
(124) 0x4293ee MOV 0xa8(%RSP),%R10 |
(124) 0x4293f6 VSUBSD (%RCX,%RDX,8),%XMM5,%XMM8 |
(124) 0x4293fb LEA (%RAX,%R13,1),%RDX |
(124) 0x4293ff ADD %R12,%RAX |
(124) 0x429402 VMOVSD %XMM8,(%R10,%RDX,8) |
(124) 0x429408 LEA 0x2(%R9),%EDX |
(124) 0x42940c MOVSXD %EDX,%RDX |
(124) 0x42940f LEA (%RBX,%RDX,1),%R10 |
(124) 0x429413 LEA (%RSI,%R10,8),%R10 |
(124) 0x429417 VMOVSD (%R10),%XMM9 |
(124) 0x42941c VSUBSD (%R8),%XMM9,%XMM10 |
(124) 0x429421 MOV 0xb8(%RSP),%R8 |
(124) 0x429429 VADDSD %XMM8,%XMM10,%XMM11 |
(124) 0x42942e VMOVSD %XMM11,(%R8,%RAX,8) |
(124) 0x429434 MOV 0xb0(%RSP),%EAX |
(124) 0x42943b CMP %EAX,%EDI |
(124) 0x42943d JAE 4294a0 |
(124) 0x42943f MOV %R15,%RDI |
(124) 0x429442 MOV 0xa0(%RSP),%R15 |
(124) 0x42944a ADD %RDX,%R14 |
(124) 0x42944d ADD %RDX,%R11 |
(124) 0x429450 ADD %RDX,%RDI |
(124) 0x429453 ADD $0x3,%R9D |
(124) 0x429457 ADD %RDX,%R13 |
(124) 0x42945a ADD %RDX,%R12 |
(124) 0x42945d VMOVSD (%R15,%R14,8),%XMM12 |
(124) 0x429463 MOVSXD %R9D,%R9 |
(124) 0x429466 ADD %RBX,%R9 |
(124) 0x429469 VADDSD (%RCX,%RDI,8),%XMM12,%XMM13 |
(124) 0x42946e VSUBSD (%RCX,%R11,8),%XMM13,%XMM14 |
(124) 0x429474 MOV 0xa8(%RSP),%RCX |
(124) 0x42947c VMOVSD %XMM14,(%RCX,%R13,8) |
(124) 0x429482 VMOVSD (%RSI,%R9,8),%XMM15 |
(124) 0x429488 MOV 0xb8(%RSP),%RSI |
(124) 0x429490 VSUBSD (%R10),%XMM15,%XMM7 |
(124) 0x429495 VADDSD %XMM14,%XMM7,%XMM0 |
(124) 0x42949a VMOVSD %XMM0,(%RSI,%R12,8) |
(124) 0x4294a0 MOV 0xb0(%RSP),%EDI |
(124) 0x4294a7 MOV 0x68(%RSP),%R8 |
(124) 0x4294ac LEA (%R8),%EBX |
(124) 0x4294af CMP %EBX,0x60(%RSP) |
(124) 0x4294b3 JLE 4294d8 |
(124) 0x4294b5 MOV 0x58(%RSP),%R13D |
(124) 0x4294ba MOV 0x5c(%RSP),%R10D |
(124) 0x4294bf MOV 0x64(%RSP),%EDX |
(124) 0x4294c3 MOV %R10D,0xb4(%RSP) |
(124) 0x4294cb SUB %EDI,%R13D |
(124) 0x4294ce JMP 428f40 |
0x4294d3 NOPL (%RAX,%RAX,1) |
0x4294d8 VZEROUPPER |
0x4294db LEA -0x28(%RBP),%RSP |
0x4294df POP %RBX |
0x4294e0 POP %R12 |
0x4294e2 POP %R13 |
0x4294e4 POP %R14 |
0x4294e6 POP %R15 |
0x4294e8 POP %RBP |
0x4294e9 RET |
0x4294ea NOPW (%RAX,%RAX,1) |
(124) 0x4294f0 LEA 0x1(%R8),%R13 |
(124) 0x4294f4 MOV %R13,0x68(%RSP) |
(124) 0x4294f9 JMP 4294a7 |
0x4294fb NOPL (%RAX,%RAX,1) |
(124) 0x429500 MOV 0xb4(%RSP),%R9D |
(124) 0x429508 XOR %R13D,%R13D |
(124) 0x42950b JMP 429259 |
0x429510 INC %R13D |
0x429513 XOR %EDX,%EDX |
0x429515 JMP 428ec9 |
0x42951a NOPW (%RAX,%RAX,1) |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
○98.16 | gomp_thread_start | team.c:130 | libgomp.so.1.0.0 |
○1.84 | GOMP_parallel | libgomp.h:985 | libgomp.so.1.0.0 |
Path / |
Source file and lines | advec_mom.cpp:44-48 |
Module | exec |
nb instructions | 83 |
nb uops | 93 |
loop length | 306 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 11 |
micro-operation queue | 15.50 cycles |
front end | 15.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.10 | 8.00 | 6.33 | 6.33 | 9.00 | 6.07 | 5.90 | 9.00 | 9.00 | 9.00 | 5.93 | 6.33 |
cycles | 6.10 | 11.93 | 6.33 | 6.33 | 9.00 | 6.07 | 5.90 | 9.00 | 9.00 | 9.00 | 5.93 | 6.33 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.75-14.83 |
Stall cycles | 0.00 |
Front-end | 15.50 |
Dispatch | 11.93 |
DIV/SQRT | 12.00 |
Overall L1 | 15.50 |
all | 3% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 12% |
all | 9% |
load | 10% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 9% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0xc0,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x30(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x34(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%R12),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x4,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA -0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA -0x1(%RSI),%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x60(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EDI,0x5c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 4294db <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x69b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x4(%RCX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 4294db <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x69b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R14D,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %EDI,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R8D,0x64(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R9D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x64(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R13D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 429510 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x6d0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %R13D,%R9D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R9,%RDX,1),%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%R13,%RDI,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R10D,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R10D,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 4294db <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x69b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EDI,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x5c(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R12),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x64(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x10(%R12),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%R12),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R8,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RSI,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x8(%R12),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%R12),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R11D,0xb4(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%RAX,%R15,1),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R11D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVSXD %R15D,%R8 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R12,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %R13D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 428ec9 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x89> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | advec_mom.cpp:44-48 |
Module | exec |
nb instructions | 83 |
nb uops | 93 |
loop length | 306 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 11 |
micro-operation queue | 15.50 cycles |
front end | 15.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.10 | 8.00 | 6.33 | 6.33 | 9.00 | 6.07 | 5.90 | 9.00 | 9.00 | 9.00 | 5.93 | 6.33 |
cycles | 6.10 | 11.93 | 6.33 | 6.33 | 9.00 | 6.07 | 5.90 | 9.00 | 9.00 | 9.00 | 5.93 | 6.33 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.75-14.83 |
Stall cycles | 0.00 |
Front-end | 15.50 |
Dispatch | 11.93 |
DIV/SQRT | 12.00 |
Overall L1 | 15.50 |
all | 3% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 12% |
all | 9% |
load | 10% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 9% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0xc0,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x30(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x34(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%R12),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x4,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA -0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA -0x1(%RSI),%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x60(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EDI,0x5c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 4294db <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x69b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x4(%RCX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 4294db <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x69b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R14D,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %EDI,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R8D,0x64(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R9D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x64(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R13D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 429510 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x6d0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %R13D,%R9D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R9,%RDX,1),%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%R13,%RDI,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R10D,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R10D,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 4294db <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x69b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EDI,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x5c(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R12),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x64(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x10(%R12),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%R12),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R8,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RSI,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x8(%R12),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%R12),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R11D,0xb4(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%RAX,%R15,1),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R11D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVSXD %R15D,%R8 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R12,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %R13D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 428ec9 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x89> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D | 3.06 | 2.29 |
▼Loop 124 - advec_mom.cpp:44-48 - exec– | 0.01 | 0.01 |
○Loop 125 - advec_mom.cpp:47-48 - exec | 3.05 | 2.28 |