Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ... | Module: exec | Source: advec_mom.cpp:62-66 [...] | Coverage: 2.56% |
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Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ... | Module: exec | Source: advec_mom.cpp:62-66 [...] | Coverage: 2.56% |
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/scratch_na/users/xoserete/qaas_runs/171-415-4687/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69 |
-------------------------------------------------------------------------------- |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
/scratch_na/users/xoserete/qaas_runs/171-415-4687/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp: 62 - 66 |
-------------------------------------------------------------------------------- |
62: #pragma omp parallel for simd collapse(2) |
63: for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) { |
64: for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) { |
65: post_vol(i, j) = volume(i, j); |
66: pre_vol(i, j) = post_vol(i, j) + vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j); |
0x429c10 PUSH %RBP |
0x429c11 MOV %RSP,%RBP |
0x429c14 PUSH %R15 |
0x429c16 PUSH %R14 |
0x429c18 PUSH %R13 |
0x429c1a MOV %RDI,%R13 |
0x429c1d PUSH %R12 |
0x429c1f PUSH %RBX |
0x429c20 AND $-0x40,%RSP |
0x429c24 ADD $-0x80,%RSP |
0x429c28 MOV 0x28(%RDI),%EAX |
0x429c2b MOV 0x2c(%RDI),%EDX |
0x429c2e MOV 0x20(%RDI),%EBX |
0x429c31 MOV 0x24(%R13),%ECX |
0x429c35 ADD $0x4,%EDX |
0x429c38 LEA -0x1(%RAX),%R15D |
0x429c3c LEA -0x1(%RBX),%EDI |
0x429c3f MOV %EDX,0x40(%RSP) |
0x429c43 MOV %EDI,0x3c(%RSP) |
0x429c47 CMP %EDX,%R15D |
0x429c4a JGE 42a1f3 |
0x429c50 MOV %EDX,%EBX |
0x429c52 LEA 0x4(%RCX),%R14D |
0x429c56 SUB %R15D,%EBX |
0x429c59 CMP %R14D,%EDI |
0x429c5c JGE 42a1f3 |
0x429c62 MOV %R14D,%ESI |
0x429c65 SUB %EDI,%ESI |
0x429c67 MOV %ESI,0x44(%RSP) |
0x429c6b CALL 4046c0 <omp_get_num_threads@plt> |
0x429c70 MOV %EAX,%R12D |
0x429c73 CALL 4045b0 <omp_get_thread_num@plt> |
0x429c78 XOR %EDX,%EDX |
0x429c7a MOV %EAX,%R8D |
0x429c7d MOV 0x44(%RSP),%EAX |
0x429c81 IMUL %EBX,%EAX |
0x429c84 DIV %R12D |
0x429c87 MOV %EAX,%R12D |
0x429c8a CMP %EDX,%R8D |
0x429c8d JB 42a224 |
0x429c93 IMUL %R12D,%R8D |
0x429c97 LEA (%R8,%RDX,1),%EBX |
0x429c9b LEA (%R12,%RBX,1),%R9D |
0x429c9f MOV %R9D,0x38(%RSP) |
0x429ca4 CMP %R9D,%EBX |
0x429ca7 JAE 42a1f3 |
0x429cad MOV %EBX,%EAX |
0x429caf XOR %EDX,%EDX |
0x429cb1 MOV 0x3c(%RSP),%R10D |
0x429cb6 MOV 0x18(%R13),%RDI |
0x429cba DIVL 0x44(%RSP) |
0x429cbe MOV %RDI,0x28(%RSP) |
0x429cc3 ADD %EDX,%R10D |
0x429cc6 LEA (%RAX,%R15,1),%R11D |
0x429cca MOV %R14D,%EDX |
0x429ccd MOV 0x8(%R13),%R15 |
0x429cd1 MOV (%R13),%R14 |
0x429cd5 MOV 0x10(%R13),%R13 |
0x429cd9 MOV %R10D,0x7c(%RSP) |
0x429cde SUB %R10D,%EDX |
0x429ce1 MOV %R15,0x30(%RSP) |
0x429ce6 MOVSXD %R11D,%RSI |
0x429ce9 MOV %R14,0x20(%RSP) |
0x429cee MOV %R13,0x18(%RSP) |
0x429cf3 NOPL (%RAX,%RAX,1) |
(128) 0x429cf8 CMP %EDX,%R12D |
(128) 0x429cfb CMOVBE %R12D,%EDX |
(128) 0x429cff LEA (%RBX,%RDX,1),%ECX |
(128) 0x429d02 MOV %ECX,0x78(%RSP) |
(128) 0x429d06 CMP %ECX,%EBX |
(128) 0x429d08 JAE 42a208 |
(128) 0x429d0e MOV 0x20(%RSP),%RAX |
(128) 0x429d13 MOV 0x30(%RSP),%R12 |
(128) 0x429d18 MOV 0x28(%RSP),%R8 |
(128) 0x429d1d MOV 0x18(%RSP),%RCX |
(128) 0x429d22 MOV (%RAX),%R11 |
(128) 0x429d25 MOV (%R12),%R9 |
(128) 0x429d29 MOV 0x10(%R12),%R15 |
(128) 0x429d2e LEA 0x1(%RSI),%R12 |
(128) 0x429d32 MOV (%R8),%R10 |
(128) 0x429d35 IMUL %RSI,%R9 |
(128) 0x429d39 MOV 0x10(%R8),%R14 |
(128) 0x429d3d MOV 0x10(%RAX),%RDI |
(128) 0x429d41 MOV %R12,0x50(%RSP) |
(128) 0x429d46 IMUL %R11,%R12 |
(128) 0x429d4a LEA -0x1(%RDX),%EAX |
(128) 0x429d4d MOV 0x10(%RCX),%R13 |
(128) 0x429d51 IMUL %RSI,%R10 |
(128) 0x429d55 IMUL (%RCX),%RSI |
(128) 0x429d59 MOV %R9,0x58(%RSP) |
(128) 0x429d5e MOV %R12,%R8 |
(128) 0x429d61 SUB %R11,%R8 |
(128) 0x429d64 MOV %R10,0x60(%RSP) |
(128) 0x429d69 MOV %R8,0x68(%RSP) |
(128) 0x429d6e MOV %RSI,0x70(%RSP) |
(128) 0x429d73 CMP $0x6,%EAX |
(128) 0x429d76 JBE 42a218 |
(128) 0x429d7c MOVSXD 0x7c(%RSP),%RAX |
(128) 0x429d81 LEA (%R10,%RAX,1),%RCX |
(128) 0x429d85 LEA (%R9,%RAX,1),%R9 |
(128) 0x429d89 LEA (%R14,%RCX,8),%R10 |
(128) 0x429d8d MOV %EDX,%ECX |
(128) 0x429d8f LEA (%R8,%RAX,1),%R8 |
(128) 0x429d93 SHR $0x3,%ECX |
(128) 0x429d96 LEA (%R15,%R9,8),%R11 |
(128) 0x429d9a LEA (%R12,%RAX,1),%R9 |
(128) 0x429d9e ADD %RSI,%RAX |
(128) 0x429da1 SAL $0x6,%RCX |
(128) 0x429da5 LEA (%R13,%RAX,8),%RSI |
(128) 0x429daa LEA (%RDI,%R9,8),%R9 |
(128) 0x429dae XOR %EAX,%EAX |
(128) 0x429db0 MOV %RCX,0x48(%RSP) |
(128) 0x429db5 SUB $0x40,%RCX |
(128) 0x429db9 LEA (%RDI,%R8,8),%R8 |
(128) 0x429dbd SHR $0x6,%RCX |
(128) 0x429dc1 INC %RCX |
(128) 0x429dc4 AND $0x7,%ECX |
(128) 0x429dc7 JE 429f15 |
(128) 0x429dcd CMP $0x1,%RCX |
(128) 0x429dd1 JE 429ee3 |
(128) 0x429dd7 CMP $0x2,%RCX |
(128) 0x429ddb JE 429ebc |
(128) 0x429de1 CMP $0x3,%RCX |
(128) 0x429de5 JE 429e95 |
(128) 0x429deb CMP $0x4,%RCX |
(128) 0x429def JE 429e6e |
(128) 0x429df1 CMP $0x5,%RCX |
(128) 0x429df5 JE 429e47 |
(128) 0x429df7 CMP $0x6,%RCX |
(128) 0x429dfb JE 429e20 |
(128) 0x429dfd VMOVUPD (%R11),%ZMM0 |
(128) 0x429e03 MOV $0x40,%EAX |
(128) 0x429e08 VMOVUPD %ZMM0,(%R10) |
(128) 0x429e0e VADDPD (%R9),%ZMM0,%ZMM1 |
(128) 0x429e14 VSUBPD (%R8),%ZMM1,%ZMM2 |
(128) 0x429e1a VMOVUPD %ZMM2,(%RSI) |
(128) 0x429e20 VMOVUPD (%R11,%RAX,1),%ZMM3 |
(128) 0x429e27 VMOVUPD %ZMM3,(%R10,%RAX,1) |
(128) 0x429e2e VADDPD (%R9,%RAX,1),%ZMM3,%ZMM4 |
(128) 0x429e35 VSUBPD (%R8,%RAX,1),%ZMM4,%ZMM5 |
(128) 0x429e3c VMOVUPD %ZMM5,(%RSI,%RAX,1) |
(128) 0x429e43 ADD $0x40,%RAX |
(128) 0x429e47 VMOVUPD (%R11,%RAX,1),%ZMM6 |
(128) 0x429e4e VMOVUPD %ZMM6,(%R10,%RAX,1) |
(128) 0x429e55 VADDPD (%R9,%RAX,1),%ZMM6,%ZMM7 |
(128) 0x429e5c VSUBPD (%R8,%RAX,1),%ZMM7,%ZMM8 |
(128) 0x429e63 VMOVUPD %ZMM8,(%RSI,%RAX,1) |
(128) 0x429e6a ADD $0x40,%RAX |
(128) 0x429e6e VMOVUPD (%R11,%RAX,1),%ZMM9 |
(128) 0x429e75 VMOVUPD %ZMM9,(%R10,%RAX,1) |
(128) 0x429e7c VADDPD (%R9,%RAX,1),%ZMM9,%ZMM10 |
(128) 0x429e83 VSUBPD (%R8,%RAX,1),%ZMM10,%ZMM11 |
(128) 0x429e8a VMOVUPD %ZMM11,(%RSI,%RAX,1) |
(128) 0x429e91 ADD $0x40,%RAX |
(128) 0x429e95 VMOVUPD (%R11,%RAX,1),%ZMM12 |
(128) 0x429e9c VMOVUPD %ZMM12,(%R10,%RAX,1) |
(128) 0x429ea3 VADDPD (%R9,%RAX,1),%ZMM12,%ZMM13 |
(128) 0x429eaa VSUBPD (%R8,%RAX,1),%ZMM13,%ZMM14 |
(128) 0x429eb1 VMOVUPD %ZMM14,(%RSI,%RAX,1) |
(128) 0x429eb8 ADD $0x40,%RAX |
(128) 0x429ebc VMOVUPD (%R11,%RAX,1),%ZMM15 |
(128) 0x429ec3 VMOVUPD %ZMM15,(%R10,%RAX,1) |
(128) 0x429eca VADDPD (%R9,%RAX,1),%ZMM15,%ZMM0 |
(128) 0x429ed1 VSUBPD (%R8,%RAX,1),%ZMM0,%ZMM1 |
(128) 0x429ed8 VMOVUPD %ZMM1,(%RSI,%RAX,1) |
(128) 0x429edf ADD $0x40,%RAX |
(128) 0x429ee3 VMOVUPD (%R11,%RAX,1),%ZMM2 |
(128) 0x429eea VMOVUPD %ZMM2,(%R10,%RAX,1) |
(128) 0x429ef1 VADDPD (%R9,%RAX,1),%ZMM2,%ZMM3 |
(128) 0x429ef8 VSUBPD (%R8,%RAX,1),%ZMM3,%ZMM4 |
(128) 0x429eff VMOVUPD %ZMM4,(%RSI,%RAX,1) |
(128) 0x429f06 ADD $0x40,%RAX |
(128) 0x429f0a CMP %RAX,0x48(%RSP) |
(128) 0x429f0f JE 42a061 |
(129) 0x429f15 VMOVUPD (%R11,%RAX,1),%ZMM5 |
(129) 0x429f1c VMOVUPD %ZMM5,(%R10,%RAX,1) |
(129) 0x429f23 VADDPD (%R9,%RAX,1),%ZMM5,%ZMM6 |
(129) 0x429f2a VSUBPD (%R8,%RAX,1),%ZMM6,%ZMM7 |
(129) 0x429f31 VMOVUPD %ZMM7,(%RSI,%RAX,1) |
(129) 0x429f38 VMOVUPD 0x40(%R11,%RAX,1),%ZMM8 |
(129) 0x429f40 VMOVUPD %ZMM8,0x40(%R10,%RAX,1) |
(129) 0x429f48 VADDPD 0x40(%R9,%RAX,1),%ZMM8,%ZMM9 |
(129) 0x429f50 VSUBPD 0x40(%R8,%RAX,1),%ZMM9,%ZMM10 |
(129) 0x429f58 VMOVUPD %ZMM10,0x40(%RSI,%RAX,1) |
(129) 0x429f60 VMOVUPD 0x80(%R11,%RAX,1),%ZMM11 |
(129) 0x429f68 VMOVUPD %ZMM11,0x80(%R10,%RAX,1) |
(129) 0x429f70 VADDPD 0x80(%R9,%RAX,1),%ZMM11,%ZMM12 |
(129) 0x429f78 VSUBPD 0x80(%R8,%RAX,1),%ZMM12,%ZMM13 |
(129) 0x429f80 VMOVUPD %ZMM13,0x80(%RSI,%RAX,1) |
(129) 0x429f88 VMOVUPD 0xc0(%R11,%RAX,1),%ZMM14 |
(129) 0x429f90 VMOVUPD %ZMM14,0xc0(%R10,%RAX,1) |
(129) 0x429f98 VADDPD 0xc0(%R9,%RAX,1),%ZMM14,%ZMM15 |
(129) 0x429fa0 VSUBPD 0xc0(%R8,%RAX,1),%ZMM15,%ZMM0 |
(129) 0x429fa8 VMOVUPD %ZMM0,0xc0(%RSI,%RAX,1) |
(129) 0x429fb0 VMOVUPD 0x100(%R11,%RAX,1),%ZMM1 |
(129) 0x429fb8 VMOVUPD %ZMM1,0x100(%R10,%RAX,1) |
(129) 0x429fc0 VADDPD 0x100(%R9,%RAX,1),%ZMM1,%ZMM2 |
(129) 0x429fc8 VSUBPD 0x100(%R8,%RAX,1),%ZMM2,%ZMM3 |
(129) 0x429fd0 VMOVUPD %ZMM3,0x100(%RSI,%RAX,1) |
(129) 0x429fd8 VMOVUPD 0x140(%R11,%RAX,1),%ZMM4 |
(129) 0x429fe0 VMOVUPD %ZMM4,0x140(%R10,%RAX,1) |
(129) 0x429fe8 VADDPD 0x140(%R9,%RAX,1),%ZMM4,%ZMM5 |
(129) 0x429ff0 VSUBPD 0x140(%R8,%RAX,1),%ZMM5,%ZMM6 |
(129) 0x429ff8 VMOVUPD %ZMM6,0x140(%RSI,%RAX,1) |
(129) 0x42a000 VMOVUPD 0x180(%R11,%RAX,1),%ZMM7 |
(129) 0x42a008 VMOVUPD %ZMM7,0x180(%R10,%RAX,1) |
(129) 0x42a010 VADDPD 0x180(%R9,%RAX,1),%ZMM7,%ZMM8 |
(129) 0x42a018 VSUBPD 0x180(%R8,%RAX,1),%ZMM8,%ZMM9 |
(129) 0x42a020 VMOVUPD %ZMM9,0x180(%RSI,%RAX,1) |
(129) 0x42a028 VMOVUPD 0x1c0(%R11,%RAX,1),%ZMM10 |
(129) 0x42a030 VMOVUPD %ZMM10,0x1c0(%R10,%RAX,1) |
(129) 0x42a038 VADDPD 0x1c0(%R9,%RAX,1),%ZMM10,%ZMM11 |
(129) 0x42a040 VSUBPD 0x1c0(%R8,%RAX,1),%ZMM11,%ZMM12 |
(129) 0x42a048 VMOVUPD %ZMM12,0x1c0(%RSI,%RAX,1) |
(129) 0x42a050 ADD $0x200,%RAX |
(129) 0x42a056 CMP %RAX,0x48(%RSP) |
(129) 0x42a05b JNE 429f15 |
(128) 0x42a061 MOV 0x7c(%RSP),%R11D |
(128) 0x42a066 MOV %EDX,%R10D |
(128) 0x42a069 AND $-0x8,%R10D |
(128) 0x42a06d ADD %R10D,%EBX |
(128) 0x42a070 LEA (%R10,%R11,1),%ESI |
(128) 0x42a074 TEST $0x7,%DL |
(128) 0x42a077 JE 42a1ba |
(128) 0x42a07d SUB %R10D,%EDX |
(128) 0x42a080 LEA -0x1(%RDX),%R9D |
(128) 0x42a084 CMP $0x2,%R9D |
(128) 0x42a088 JBE 42a0f4 |
(128) 0x42a08a MOVSXD 0x7c(%RSP),%RCX |
(128) 0x42a08f MOV 0x58(%RSP),%R8 |
(128) 0x42a094 MOV 0x60(%RSP),%R11 |
(128) 0x42a099 LEA (%R8,%RCX,1),%RAX |
(128) 0x42a09d LEA (%R12,%RCX,1),%R8 |
(128) 0x42a0a1 ADD %R10,%RAX |
(128) 0x42a0a4 LEA (%R11,%RCX,1),%R9 |
(128) 0x42a0a8 ADD %R10,%R8 |
(128) 0x42a0ab VMOVUPD (%R15,%RAX,8),%YMM13 |
(128) 0x42a0b1 ADD %R10,%R9 |
(128) 0x42a0b4 MOV 0x68(%RSP),%RAX |
(128) 0x42a0b9 VMOVUPD %YMM13,(%R14,%R9,8) |
(128) 0x42a0bf LEA (%RAX,%RCX,1),%R11 |
(128) 0x42a0c3 MOV 0x70(%RSP),%R9 |
(128) 0x42a0c8 VADDPD (%RDI,%R8,8),%YMM13,%YMM14 |
(128) 0x42a0ce ADD %R10,%R11 |
(128) 0x42a0d1 ADD %R9,%RCX |
(128) 0x42a0d4 ADD %R10,%RCX |
(128) 0x42a0d7 VSUBPD (%RDI,%R11,8),%YMM14,%YMM15 |
(128) 0x42a0dd VMOVUPD %YMM15,(%R13,%RCX,8) |
(128) 0x42a0e4 TEST $0x3,%DL |
(128) 0x42a0e7 JE 42a1ba |
(128) 0x42a0ed AND $-0x4,%EDX |
(128) 0x42a0f0 ADD %EDX,%EBX |
(128) 0x42a0f2 ADD %EDX,%ESI |
(128) 0x42a0f4 MOV 0x58(%RSP),%R10 |
(128) 0x42a0f9 MOVSXD %ESI,%RAX |
(128) 0x42a0fc MOV 0x60(%RSP),%R11 |
(128) 0x42a101 LEA (%R12,%RAX,1),%R8 |
(128) 0x42a105 MOV 0x70(%RSP),%R9 |
(128) 0x42a10a LEA (%R10,%RAX,1),%RDX |
(128) 0x42a10e LEA (%R11,%RAX,1),%RCX |
(128) 0x42a112 VMOVSD (%R15,%RDX,8),%XMM0 |
(128) 0x42a118 LEA (%R9,%RAX,1),%RDX |
(128) 0x42a11c VMOVSD %XMM0,(%R14,%RCX,8) |
(128) 0x42a122 MOV 0x78(%RSP),%ECX |
(128) 0x42a126 VADDSD (%RDI,%R8,8),%XMM0,%XMM1 |
(128) 0x42a12c MOV 0x68(%RSP),%R8 |
(128) 0x42a131 ADD %R8,%RAX |
(128) 0x42a134 VSUBSD (%RDI,%RAX,8),%XMM1,%XMM2 |
(128) 0x42a139 LEA 0x1(%RSI),%EAX |
(128) 0x42a13c VMOVSD %XMM2,(%R13,%RDX,8) |
(128) 0x42a143 LEA 0x1(%RBX),%EDX |
(128) 0x42a146 CMP %ECX,%EDX |
(128) 0x42a148 JAE 42a1ba |
(128) 0x42a14a CLTQ |
(128) 0x42a14c ADD $0x2,%EBX |
(128) 0x42a14f ADD $0x2,%ESI |
(128) 0x42a152 LEA (%R10,%RAX,1),%RDX |
(128) 0x42a156 LEA (%R11,%RAX,1),%RCX |
(128) 0x42a15a VMOVSD (%R15,%RDX,8),%XMM3 |
(128) 0x42a160 LEA (%R9,%RAX,1),%RDX |
(128) 0x42a164 VMOVSD %XMM3,(%R14,%RCX,8) |
(128) 0x42a16a LEA (%R12,%RAX,1),%RCX |
(128) 0x42a16e ADD %R8,%RAX |
(128) 0x42a171 VADDSD (%RDI,%RCX,8),%XMM3,%XMM4 |
(128) 0x42a176 VSUBSD (%RDI,%RAX,8),%XMM4,%XMM5 |
(128) 0x42a17b MOV 0x78(%RSP),%EAX |
(128) 0x42a17f VMOVSD %XMM5,(%R13,%RDX,8) |
(128) 0x42a186 CMP %EAX,%EBX |
(128) 0x42a188 JAE 42a1ba |
(128) 0x42a18a MOVSXD %ESI,%RBX |
(128) 0x42a18d ADD %RBX,%R10 |
(128) 0x42a190 ADD %RBX,%R11 |
(128) 0x42a193 ADD %RBX,%R12 |
(128) 0x42a196 ADD %RBX,%R9 |
(128) 0x42a199 VMOVSD (%R15,%R10,8),%XMM6 |
(128) 0x42a19f ADD %R8,%RBX |
(128) 0x42a1a2 VMOVSD %XMM6,(%R14,%R11,8) |
(128) 0x42a1a8 VADDSD (%RDI,%R12,8),%XMM6,%XMM7 |
(128) 0x42a1ae VSUBSD (%RDI,%RBX,8),%XMM7,%XMM8 |
(128) 0x42a1b3 VMOVSD %XMM8,(%R13,%R9,8) |
(128) 0x42a1ba MOV 0x78(%RSP),%EBX |
(128) 0x42a1be MOV 0x50(%RSP),%RSI |
(128) 0x42a1c3 LEA (%RSI),%R15D |
(128) 0x42a1c6 CMP %R15D,0x40(%RSP) |
(128) 0x42a1cb JLE 42a1f0 |
(128) 0x42a1cd MOV 0x38(%RSP),%R12D |
(128) 0x42a1d2 MOV 0x3c(%RSP),%R14D |
(128) 0x42a1d7 MOV 0x44(%RSP),%EDX |
(128) 0x42a1db MOV %R14D,0x7c(%RSP) |
(128) 0x42a1e0 SUB %EBX,%R12D |
(128) 0x42a1e3 JMP 429cf8 |
0x42a1e8 NOPL (%RAX,%RAX,1) |
0x42a1f0 VZEROUPPER |
0x42a1f3 LEA -0x28(%RBP),%RSP |
0x42a1f7 POP %RBX |
0x42a1f8 POP %R12 |
0x42a1fa POP %R13 |
0x42a1fc POP %R14 |
0x42a1fe POP %R15 |
0x42a200 POP %RBP |
0x42a201 RET |
0x42a202 NOPW (%RAX,%RAX,1) |
(128) 0x42a208 LEA 0x1(%RSI),%RSI |
(128) 0x42a20c MOV %RSI,0x50(%RSP) |
(128) 0x42a211 JMP 42a1be |
0x42a213 NOPL (%RAX,%RAX,1) |
(128) 0x42a218 MOV 0x7c(%RSP),%ESI |
(128) 0x42a21c XOR %R10D,%R10D |
(128) 0x42a21f JMP 42a07d |
0x42a224 INC %R12D |
0x42a227 XOR %EDX,%EDX |
0x42a229 JMP 429c93 |
0x42a22e XCHG %AX,%AX |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
○98.20 | gomp_thread_start | team.c:130 | libgomp.so.1.0.0 |
○1.80 | GOMP_parallel | libgomp.h:985 | libgomp.so.1.0.0 |
Path / |
Source file and lines | advec_mom.cpp:62-66 |
Module | exec |
nb instructions | 81 |
nb uops | 91 |
loop length | 281 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 10 |
micro-operation queue | 15.17 cycles |
front end | 15.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 5.70 | 8.00 | 6.00 | 6.00 | 8.50 | 5.87 | 5.70 | 8.50 | 8.50 | 8.50 | 5.73 | 6.00 |
cycles | 5.70 | 11.73 | 6.00 | 6.00 | 8.50 | 5.87 | 5.70 | 8.50 | 8.50 | 8.50 | 5.73 | 6.00 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.41-14.53 |
Stall cycles | 0.00 |
Front-end | 15.17 |
Dispatch | 11.73 |
DIV/SQRT | 12.00 |
Overall L1 | 15.17 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 14% |
all | 8% |
load | 8% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 9% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD $-0x80,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x28(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RDI),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x24(%R13),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x4,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA -0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA -0x1(%RBX),%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EDI,0x3c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 42a1f3 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.2+0x5e3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x4(%RCX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 42a1f3 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.2+0x5e3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R14D,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %EDI,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ESI,0x44(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x44(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 42a224 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.2+0x614> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %R12D,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%R12,%RBX,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R9D,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R9D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 42a1f3 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.2+0x5e3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EBX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x3c(%RSP),%R10D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%R13),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x44(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV %RDI,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%RAX,%R15,1),%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R14D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x8(%R13),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R13),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%R13),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10D,0x7c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R10D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R15,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVSXD %R11D,%RSI | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R14,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R13,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 429c93 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.2+0x83> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | advec_mom.cpp:62-66 |
Module | exec |
nb instructions | 81 |
nb uops | 91 |
loop length | 281 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 10 |
micro-operation queue | 15.17 cycles |
front end | 15.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 5.70 | 8.00 | 6.00 | 6.00 | 8.50 | 5.87 | 5.70 | 8.50 | 8.50 | 8.50 | 5.73 | 6.00 |
cycles | 5.70 | 11.73 | 6.00 | 6.00 | 8.50 | 5.87 | 5.70 | 8.50 | 8.50 | 8.50 | 5.73 | 6.00 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.41-14.53 |
Stall cycles | 0.00 |
Front-end | 15.17 |
Dispatch | 11.73 |
DIV/SQRT | 12.00 |
Overall L1 | 15.17 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 14% |
all | 8% |
load | 8% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 9% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD $-0x80,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x28(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RDI),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x24(%R13),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x4,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA -0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA -0x1(%RBX),%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EDI,0x3c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 42a1f3 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.2+0x5e3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x4(%RCX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 42a1f3 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.2+0x5e3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R14D,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %EDI,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ESI,0x44(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x44(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 42a224 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.2+0x614> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %R12D,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%R12,%RBX,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R9D,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R9D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 42a1f3 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.2+0x5e3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EBX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x3c(%RSP),%R10D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%R13),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x44(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV %RDI,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%RAX,%R15,1),%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R14D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x8(%R13),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R13),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%R13),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10D,0x7c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R10D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R15,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVSXD %R11D,%RSI | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R14,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R13,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 429c93 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.2+0x83> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D | 2.56 | 1.91 |
▼Loop 128 - advec_mom.cpp:62-66 - exec– | 0.01 | 0.01 |
○Loop 129 - advec_mom.cpp:65-66 - exec | 2.56 | 1.91 |