Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ... | Module: exec | Source: advec_cell.cpp:208-216 [...] | Coverage: 3.59% |
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Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ... | Module: exec | Source: advec_cell.cpp:208-216 [...] | Coverage: 3.59% |
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/scratch_na/users/xoserete/qaas_runs/171-415-4687/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69 |
-------------------------------------------------------------------------------- |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
/scratch_na/users/xoserete/qaas_runs/171-415-4687/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp: 208 - 216 |
-------------------------------------------------------------------------------- |
208: #pragma omp parallel for simd collapse(2) |
209: for (int j = (y_min + 1); j < (y_max + 2); j++) { |
210: for (int i = (x_min + 1); i < (x_max + 2); i++) { |
211: double pre_mass_s = density1(i, j) * pre_vol(i, j); |
212: double post_mass_s = pre_mass_s + mass_flux_y(i, j) - mass_flux_y(i + 0, j + 1); |
213: double post_ener_s = (energy1(i, j) * pre_mass_s + ener_flux(i, j) - ener_flux(i + 0, j + 1)) / post_mass_s; |
214: double advec_vol_s = pre_vol(i, j) + vol_flux_y(i, j) - vol_flux_y(i + 0, j + 1); |
215: density1(i, j) = post_mass_s / advec_vol_s; |
216: energy1(i, j) = post_ener_s; |
0x428660 PUSH %RBP |
0x428661 MOV %RSP,%RBP |
0x428664 PUSH %R15 |
0x428666 PUSH %R14 |
0x428668 PUSH %R13 |
0x42866a PUSH %R12 |
0x42866c PUSH %RBX |
0x42866d MOV %RDI,%RBX |
0x428670 AND $-0x40,%RSP |
0x428674 SUB $0x100,%RSP |
0x42867b MOV 0x38(%RDI),%EAX |
0x42867e MOV 0x3c(%RDI),%EDX |
0x428681 MOV 0x30(%RDI),%EDI |
0x428684 MOV 0x34(%RBX),%ESI |
0x428687 ADD $0x2,%EDX |
0x42868a LEA 0x1(%RAX),%R15D |
0x42868e INC %EDI |
0x428690 MOV %EDX,0x70(%RSP) |
0x428694 MOV %EDI,0x6c(%RSP) |
0x428698 CMP %EDX,%R15D |
0x42869b JGE 428e13 |
0x4286a1 MOV %EDX,%R13D |
0x4286a4 LEA 0x2(%RSI),%R14D |
0x4286a8 SUB %R15D,%R13D |
0x4286ab CMP %R14D,%EDI |
0x4286ae JGE 428e13 |
0x4286b4 MOV %R14D,%ECX |
0x4286b7 SUB %EDI,%ECX |
0x4286b9 MOV %ECX,0x74(%RSP) |
0x4286bd CALL 4046c0 <omp_get_num_threads@plt> |
0x4286c2 MOV %EAX,%R12D |
0x4286c5 CALL 4045b0 <omp_get_thread_num@plt> |
0x4286ca XOR %EDX,%EDX |
0x4286cc MOV %EAX,%R8D |
0x4286cf MOV 0x74(%RSP),%EAX |
0x4286d3 IMUL %R13D,%EAX |
0x4286d7 DIV %R12D |
0x4286da MOV %EAX,%ECX |
0x4286dc CMP %EDX,%R8D |
0x4286df JB 428e36 |
0x4286e5 IMUL %ECX,%R8D |
0x4286e9 LEA (%R8,%RDX,1),%R11D |
0x4286ed LEA (%RCX,%R11,1),%R9D |
0x4286f1 MOV %R9D,0x68(%RSP) |
0x4286f6 CMP %R9D,%R11D |
0x4286f9 JAE 428e13 |
0x4286ff MOV %R11D,%EAX |
0x428702 XOR %EDX,%EDX |
0x428704 MOV 0x6c(%RSP),%R10D |
0x428709 MOV (%RBX),%RDI |
0x42870c DIVL 0x74(%RSP) |
0x428710 MOV 0x20(%RBX),%RSI |
0x428714 MOV 0x8(%RBX),%R13 |
0x428718 MOV 0x28(%RBX),%R12 |
0x42871c MOV %RDI,0x60(%RSP) |
0x428721 MOV %RSI,0x58(%RSP) |
0x428726 MOV %R13,0x48(%RSP) |
0x42872b MOV %R12,0x40(%RSP) |
0x428730 LEA (%RAX,%R15,1),%R15D |
0x428734 MOV %R14D,%EAX |
0x428737 MOV 0x10(%RBX),%R14 |
0x42873b MOV 0x18(%RBX),%RBX |
0x42873f ADD %EDX,%R10D |
0x428742 MOVSXD %R15D,%R8 |
0x428745 MOV %R11D,%R15D |
0x428748 MOV %R10D,0xd4(%RSP) |
0x428750 SUB %R10D,%EAX |
0x428753 MOV %R14,0x50(%RSP) |
0x428758 MOV %RBX,0x38(%RSP) |
0x42875d MOV %R8,0xc8(%RSP) |
0x428765 NOPL (%RAX) |
(122) 0x428768 CMP %EAX,%ECX |
(122) 0x42876a CMOVBE %ECX,%EAX |
(122) 0x42876d LEA (%R15,%RAX,1),%ECX |
(122) 0x428771 MOV %EAX,%EDX |
(122) 0x428773 MOV %ECX,0xd0(%RSP) |
(122) 0x42877a CMP %ECX,%R15D |
(122) 0x42877d JAE 428dd7 |
(122) 0x428783 MOV 0x50(%RSP),%R10 |
(122) 0x428788 MOV 0xc8(%RSP),%RSI |
(122) 0x428790 MOV 0x58(%RSP),%R9 |
(122) 0x428795 MOV 0x48(%RSP),%R12 |
(122) 0x42879a MOV (%R10),%R14 |
(122) 0x42879d MOV 0x40(%RSP),%RCX |
(122) 0x4287a2 MOV 0x10(%R9),%RAX |
(122) 0x4287a6 MOV 0x10(%R10),%RDI |
(122) 0x4287aa MOV %RSI,%R10 |
(122) 0x4287ad MOV 0x10(%R12),%R8 |
(122) 0x4287b2 IMUL %R14,%R10 |
(122) 0x4287b6 MOV 0x60(%RSP),%R11 |
(122) 0x4287bb MOV %RAX,0xe8(%RSP) |
(122) 0x4287c3 MOV (%RCX),%RAX |
(122) 0x4287c6 MOV 0x10(%R11),%R13 |
(122) 0x4287ca MOV (%R11),%RBX |
(122) 0x4287cd MOV %R8,0xf0(%RSP) |
(122) 0x4287d5 MOV %RSI,%R8 |
(122) 0x4287d8 IMUL %RAX,%R8 |
(122) 0x4287dc ADD %R10,%R14 |
(122) 0x4287df MOV (%R9),%R11 |
(122) 0x4287e2 MOV (%R12),%R9 |
(122) 0x4287e6 MOV %R14,0xa8(%RSP) |
(122) 0x4287ee MOV 0x10(%RCX),%R14 |
(122) 0x4287f2 IMUL %RSI,%RBX |
(122) 0x4287f6 MOV 0x38(%RSP),%RCX |
(122) 0x4287fb IMUL %RSI,%R11 |
(122) 0x4287ff MOV %R13,0xb0(%RSP) |
(122) 0x428807 IMUL %RSI,%R9 |
(122) 0x42880b LEA (%RAX,%R8,1),%R12 |
(122) 0x42880f MOV %R10,0x98(%RSP) |
(122) 0x428817 MOV (%RCX),%RAX |
(122) 0x42881a MOV %R12,0xf8(%RSP) |
(122) 0x428822 MOV 0x10(%RCX),%R12 |
(122) 0x428826 LEA -0x1(%RDX),%ECX |
(122) 0x428829 MOV %RBX,0x88(%RSP) |
(122) 0x428831 IMUL %RAX,%RSI |
(122) 0x428835 MOV %R11,0x90(%RSP) |
(122) 0x42883d MOV %R9,0xb8(%RSP) |
(122) 0x428845 MOV %R8,0xc0(%RSP) |
(122) 0x42884d MOV %RSI,0xd8(%RSP) |
(122) 0x428855 LEA (%RAX,%RSI,1),%RSI |
(122) 0x428859 MOV %RSI,0xe0(%RSP) |
(122) 0x428861 CMP $0x6,%ECX |
(122) 0x428864 JBE 428e28 |
(122) 0x42886a MOVSXD 0xd4(%RSP),%RAX |
(122) 0x428872 MOV 0xa8(%RSP),%RCX |
(122) 0x42887a LEA (%RBX,%RAX,1),%RBX |
(122) 0x42887e LEA (%R10,%RAX,1),%R10 |
(122) 0x428882 ADD %RAX,%RCX |
(122) 0x428885 ADD %RAX,%R8 |
(122) 0x428888 LEA (%R13,%RBX,8),%RSI |
(122) 0x42888d LEA (%R11,%RAX,1),%R13 |
(122) 0x428891 MOV 0xe8(%RSP),%R11 |
(122) 0x428899 LEA (%RDI,%R10,8),%RBX |
(122) 0x42889d MOV 0xf0(%RSP),%R10 |
(122) 0x4288a5 LEA (%R9,%RAX,1),%R9 |
(122) 0x4288a9 LEA (%R11,%R13,8),%R13 |
(122) 0x4288ad LEA (%RDI,%RCX,8),%R11 |
(122) 0x4288b1 MOV %R11,0x80(%RSP) |
(122) 0x4288b9 LEA (%R14,%R8,8),%R11 |
(122) 0x4288bd MOV 0xf8(%RSP),%R8 |
(122) 0x4288c5 LEA (%R10,%R9,8),%RCX |
(122) 0x4288c9 MOV 0xd8(%RSP),%R9 |
(122) 0x4288d1 ADD %RAX,%R8 |
(122) 0x4288d4 LEA (%R14,%R8,8),%R10 |
(122) 0x4288d8 LEA (%R9,%RAX,1),%R8 |
(122) 0x4288dc LEA (%R12,%R8,8),%R9 |
(122) 0x4288e0 MOV 0xe0(%RSP),%R8 |
(122) 0x4288e8 ADD %R8,%RAX |
(122) 0x4288eb LEA (%R12,%RAX,8),%R8 |
(122) 0x4288ef MOV %EDX,%EAX |
(122) 0x4288f1 SHR $0x3,%EAX |
(122) 0x4288f4 MOV %RAX,0x78(%RSP) |
(122) 0x4288f9 SAL $0x6,%RAX |
(122) 0x4288fd MOV %RAX,0xa0(%RSP) |
(122) 0x428905 XOR %EAX,%EAX |
(122) 0x428907 TESTB $0x1,0x78(%RSP) |
(122) 0x42890c JE 428979 |
(122) 0x42890e VMOVUPD (%R13),%ZMM0 |
(122) 0x428915 VMOVUPD (%R11),%ZMM6 |
(122) 0x42891b MOV 0x80(%RSP),%RAX |
(122) 0x428923 CMPQ $0x40,0xa0(%RSP) |
(122) 0x42892c VMULPD (%RSI),%ZMM0,%ZMM1 |
(122) 0x428932 VSUBPD (%R10),%ZMM6,%ZMM3 |
(122) 0x428938 VADDPD (%R9),%ZMM0,%ZMM5 |
(122) 0x42893e VSUBPD (%R8),%ZMM5,%ZMM7 |
(122) 0x428944 VSUBPD (%RAX),%ZMM1,%ZMM2 |
(122) 0x42894a VFMADD132PD (%RCX),%ZMM3,%ZMM1 |
(122) 0x428950 MOV $0x40,%EAX |
(122) 0x428955 VADDPD (%RBX),%ZMM2,%ZMM4 |
(122) 0x42895b VDIVPD %ZMM7,%ZMM4,%ZMM8 |
(122) 0x428961 VDIVPD %ZMM4,%ZMM1,%ZMM9 |
(122) 0x428967 VMOVUPD %ZMM8,(%RSI) |
(122) 0x42896d VMOVUPD %ZMM9,(%RCX) |
(122) 0x428973 JE 428a5b |
(122) 0x428979 MOV %R15D,0x78(%RSP) |
(122) 0x42897e MOV 0x80(%RSP),%R15 |
(123) 0x428986 VMOVUPD (%R13,%RAX,1),%ZMM10 |
(123) 0x42898e VMOVUPD (%R11,%RAX,1),%ZMM14 |
(123) 0x428995 VMULPD (%RSI,%RAX,1),%ZMM10,%ZMM11 |
(123) 0x42899c VSUBPD (%R10,%RAX,1),%ZMM14,%ZMM15 |
(123) 0x4289a3 VADDPD (%R9,%RAX,1),%ZMM10,%ZMM0 |
(123) 0x4289aa VSUBPD (%R8,%RAX,1),%ZMM0,%ZMM1 |
(123) 0x4289b1 VSUBPD (%R15,%RAX,1),%ZMM11,%ZMM12 |
(123) 0x4289b8 VFMADD132PD (%RCX,%RAX,1),%ZMM15,%ZMM11 |
(123) 0x4289bf VADDPD (%RBX,%RAX,1),%ZMM12,%ZMM13 |
(123) 0x4289c6 VDIVPD %ZMM13,%ZMM11,%ZMM4 |
(123) 0x4289cc VDIVPD %ZMM1,%ZMM13,%ZMM2 |
(123) 0x4289d2 VMOVUPD %ZMM2,(%RSI,%RAX,1) |
(123) 0x4289d9 VMOVUPD %ZMM4,(%RCX,%RAX,1) |
(123) 0x4289e0 VMOVUPD 0x40(%R13,%RAX,1),%ZMM6 |
(123) 0x4289e8 VMOVUPD 0x40(%R11,%RAX,1),%ZMM5 |
(123) 0x4289f0 VMULPD 0x40(%RSI,%RAX,1),%ZMM6,%ZMM7 |
(123) 0x4289f8 VSUBPD 0x40(%R10,%RAX,1),%ZMM5,%ZMM9 |
(123) 0x428a00 VADDPD 0x40(%R9,%RAX,1),%ZMM6,%ZMM10 |
(123) 0x428a08 VSUBPD 0x40(%R8,%RAX,1),%ZMM10,%ZMM11 |
(123) 0x428a10 VSUBPD 0x40(%R15,%RAX,1),%ZMM7,%ZMM3 |
(123) 0x428a18 VFMADD132PD 0x40(%RCX,%RAX,1),%ZMM9,%ZMM7 |
(123) 0x428a20 VADDPD 0x40(%RBX,%RAX,1),%ZMM3,%ZMM8 |
(123) 0x428a28 VDIVPD %ZMM11,%ZMM8,%ZMM12 |
(123) 0x428a2e VDIVPD %ZMM8,%ZMM7,%ZMM13 |
(123) 0x428a34 VMOVUPD %ZMM12,0x40(%RSI,%RAX,1) |
(123) 0x428a3c VMOVUPD %ZMM13,0x40(%RCX,%RAX,1) |
(123) 0x428a44 SUB $-0x80,%RAX |
(123) 0x428a48 CMP %RAX,0xa0(%RSP) |
(123) 0x428a50 JNE 428986 |
(122) 0x428a56 MOV 0x78(%RSP),%R15D |
(122) 0x428a5b MOV 0xd4(%RSP),%ESI |
(122) 0x428a62 MOV %EDX,%ECX |
(122) 0x428a64 AND $-0x8,%ECX |
(122) 0x428a67 ADD %ECX,%R15D |
(122) 0x428a6a LEA (%RCX,%RSI,1),%ESI |
(122) 0x428a6d TEST $0x7,%DL |
(122) 0x428a70 JE 428dcf |
(122) 0x428a76 SUB %ECX,%EDX |
(122) 0x428a78 LEA -0x1(%RDX),%R13D |
(122) 0x428a7c CMP $0x2,%R13D |
(122) 0x428a80 JBE 428b86 |
(122) 0x428a86 MOVSXD 0xd4(%RSP),%RAX |
(122) 0x428a8e MOV 0x88(%RSP),%RBX |
(122) 0x428a96 MOV 0xb0(%RSP),%R10 |
(122) 0x428a9e MOV 0xb8(%RSP),%R9 |
(122) 0x428aa6 LEA (%RBX,%RAX,1),%R11 |
(122) 0x428aaa MOV 0xf0(%RSP),%R13 |
(122) 0x428ab2 ADD %RCX,%R11 |
(122) 0x428ab5 LEA (%R9,%RAX,1),%R8 |
(122) 0x428ab9 MOV 0xd8(%RSP),%R9 |
(122) 0x428ac1 LEA (%R10,%R11,8),%RBX |
(122) 0x428ac5 MOV 0xe0(%RSP),%R10 |
(122) 0x428acd ADD %RCX,%R8 |
(122) 0x428ad0 LEA (%R13,%R8,8),%R11 |
(122) 0x428ad5 MOV 0xe8(%RSP),%R13 |
(122) 0x428add ADD %RAX,%R9 |
(122) 0x428ae0 LEA (%R10,%RAX,1),%R8 |
(122) 0x428ae4 MOV 0x90(%RSP),%R10 |
(122) 0x428aec ADD %RCX,%R9 |
(122) 0x428aef ADD %RCX,%R8 |
(122) 0x428af2 ADD %RAX,%R10 |
(122) 0x428af5 ADD %RCX,%R10 |
(122) 0x428af8 VMOVUPD (%R13,%R10,8),%YMM14 |
(122) 0x428aff MOV 0xa8(%RSP),%R10 |
(122) 0x428b07 MOV 0x98(%RSP),%R13 |
(122) 0x428b0f VMULPD (%RBX),%YMM14,%YMM15 |
(122) 0x428b13 ADD %RAX,%R10 |
(122) 0x428b16 VADDPD (%R12,%R9,8),%YMM14,%YMM6 |
(122) 0x428b1c ADD %RCX,%R10 |
(122) 0x428b1f ADD %RAX,%R13 |
(122) 0x428b22 ADD %RCX,%R13 |
(122) 0x428b25 VSUBPD (%R12,%R8,8),%YMM6,%YMM7 |
(122) 0x428b2b VSUBPD (%RDI,%R10,8),%YMM15,%YMM0 |
(122) 0x428b31 MOV 0xc0(%RSP),%R10 |
(122) 0x428b39 ADD %RAX,%R10 |
(122) 0x428b3c VADDPD (%RDI,%R13,8),%YMM0,%YMM1 |
(122) 0x428b42 MOV 0xf8(%RSP),%R13 |
(122) 0x428b4a ADD %RCX,%R10 |
(122) 0x428b4d VMOVUPD (%R14,%R10,8),%YMM2 |
(122) 0x428b53 ADD %R13,%RAX |
(122) 0x428b56 VDIVPD %YMM7,%YMM1,%YMM3 |
(122) 0x428b5a ADD %RCX,%RAX |
(122) 0x428b5d VSUBPD (%R14,%RAX,8),%YMM2,%YMM4 |
(122) 0x428b63 VFMADD132PD (%R11),%YMM4,%YMM15 |
(122) 0x428b68 VDIVPD %YMM1,%YMM15,%YMM8 |
(122) 0x428b6c VMOVUPD %YMM3,(%RBX) |
(122) 0x428b70 VMOVUPD %YMM8,(%R11) |
(122) 0x428b75 TEST $0x3,%DL |
(122) 0x428b78 JE 428dcf |
(122) 0x428b7e AND $-0x4,%EDX |
(122) 0x428b81 ADD %EDX,%R15D |
(122) 0x428b84 ADD %EDX,%ESI |
(122) 0x428b86 MOV 0x90(%RSP),%R11 |
(122) 0x428b8e MOVSXD %ESI,%RAX |
(122) 0x428b91 MOV 0xe8(%RSP),%R9 |
(122) 0x428b99 MOV 0x88(%RSP),%RBX |
(122) 0x428ba1 MOV 0xb0(%RSP),%RCX |
(122) 0x428ba9 LEA (%R11,%RAX,1),%R8 |
(122) 0x428bad MOV 0xa8(%RSP),%R10 |
(122) 0x428bb5 VMOVSD (%R9,%R8,8),%XMM5 |
(122) 0x428bbb LEA (%RBX,%RAX,1),%RDX |
(122) 0x428bbf MOV 0xb8(%RSP),%R9 |
(122) 0x428bc7 LEA (%RCX,%RDX,8),%RCX |
(122) 0x428bcb LEA (%R10,%RAX,1),%R13 |
(122) 0x428bcf MOV 0xf0(%RSP),%R8 |
(122) 0x428bd7 VMULSD (%RCX),%XMM5,%XMM9 |
(122) 0x428bdb ADD %RAX,%R9 |
(122) 0x428bde VSUBSD (%RDI,%R13,8),%XMM9,%XMM10 |
(122) 0x428be4 MOV 0x98(%RSP),%R13 |
(122) 0x428bec LEA (%R13,%RAX,1),%RDX |
(122) 0x428bf1 VADDSD (%RDI,%RDX,8),%XMM10,%XMM11 |
(122) 0x428bf6 LEA (%R8,%R9,8),%RDX |
(122) 0x428bfa MOV 0xc0(%RSP),%R9 |
(122) 0x428c02 MOV 0xf8(%RSP),%R8 |
(122) 0x428c0a ADD %RAX,%R9 |
(122) 0x428c0d VMOVSD (%R14,%R9,8),%XMM12 |
(122) 0x428c13 MOV 0xd8(%RSP),%R9 |
(122) 0x428c1b ADD %RAX,%R8 |
(122) 0x428c1e VSUBSD (%R14,%R8,8),%XMM12,%XMM13 |
(122) 0x428c24 LEA (%R9,%RAX,1),%R8 |
(122) 0x428c28 MOV 0xe0(%RSP),%R9 |
(122) 0x428c30 VADDSD (%R12,%R8,8),%XMM5,%XMM14 |
(122) 0x428c36 ADD %R9,%RAX |
(122) 0x428c39 VFMADD132SD (%RDX),%XMM13,%XMM9 |
(122) 0x428c3e VSUBSD (%R12,%RAX,8),%XMM14,%XMM15 |
(122) 0x428c44 LEA 0x1(%RSI),%EAX |
(122) 0x428c47 VDIVSD %XMM15,%XMM11,%XMM0 |
(122) 0x428c4c VDIVSD %XMM11,%XMM9,%XMM1 |
(122) 0x428c51 VMOVSD %XMM0,(%RCX) |
(122) 0x428c55 MOV 0xd0(%RSP),%ECX |
(122) 0x428c5c VMOVSD %XMM1,(%RDX) |
(122) 0x428c60 LEA 0x1(%R15),%EDX |
(122) 0x428c64 CMP %ECX,%EDX |
(122) 0x428c66 JAE 428dcf |
(122) 0x428c6c CLTQ |
(122) 0x428c6e MOV 0xb0(%RSP),%R9 |
(122) 0x428c76 ADD $0x2,%ESI |
(122) 0x428c79 LEA (%RBX,%RAX,1),%R8 |
(122) 0x428c7d LEA (%R11,%RAX,1),%RDX |
(122) 0x428c81 LEA (%R9,%R8,8),%RCX |
(122) 0x428c85 MOV 0xe8(%RSP),%R8 |
(122) 0x428c8d LEA (%R10,%RAX,1),%R9 |
(122) 0x428c91 VMOVSD (%R8,%RDX,8),%XMM4 |
(122) 0x428c97 MOV 0xf0(%RSP),%R8 |
(122) 0x428c9f LEA (%R13,%RAX,1),%RDX |
(122) 0x428ca4 VMULSD (%RCX),%XMM4,%XMM6 |
(122) 0x428ca8 VSUBSD (%RDI,%R9,8),%XMM6,%XMM2 |
(122) 0x428cae MOV 0xb8(%RSP),%R9 |
(122) 0x428cb6 ADD %RAX,%R9 |
(122) 0x428cb9 VADDSD (%RDI,%RDX,8),%XMM2,%XMM7 |
(122) 0x428cbe LEA (%R8,%R9,8),%RDX |
(122) 0x428cc2 MOV 0xc0(%RSP),%R9 |
(122) 0x428cca MOV 0xf8(%RSP),%R8 |
(122) 0x428cd2 ADD %RAX,%R9 |
(122) 0x428cd5 VMOVSD (%R14,%R9,8),%XMM3 |
(122) 0x428cdb ADD %RAX,%R8 |
(122) 0x428cde MOV 0xd8(%RSP),%R9 |
(122) 0x428ce6 VSUBSD (%R14,%R8,8),%XMM3,%XMM8 |
(122) 0x428cec LEA (%R9,%RAX,1),%R8 |
(122) 0x428cf0 VADDSD (%R12,%R8,8),%XMM4,%XMM5 |
(122) 0x428cf6 MOV 0xe0(%RSP),%R8 |
(122) 0x428cfe VFMADD132SD (%RDX),%XMM8,%XMM6 |
(122) 0x428d03 ADD %R8,%RAX |
(122) 0x428d06 VSUBSD (%R12,%RAX,8),%XMM5,%XMM9 |
(122) 0x428d0c LEA 0x2(%R15),%EAX |
(122) 0x428d10 MOV 0xd0(%RSP),%R15D |
(122) 0x428d18 VDIVSD %XMM9,%XMM7,%XMM10 |
(122) 0x428d1d VDIVSD %XMM7,%XMM6,%XMM11 |
(122) 0x428d21 VMOVSD %XMM10,(%RCX) |
(122) 0x428d25 VMOVSD %XMM11,(%RDX) |
(122) 0x428d29 CMP %R15D,%EAX |
(122) 0x428d2c JAE 428dcf |
(122) 0x428d32 MOVSXD %ESI,%RSI |
(122) 0x428d35 MOV 0xe8(%RSP),%RDX |
(122) 0x428d3d MOV %RBX,%RCX |
(122) 0x428d40 MOV 0xb0(%RSP),%RBX |
(122) 0x428d48 ADD %RSI,%R11 |
(122) 0x428d4b ADD %RSI,%RCX |
(122) 0x428d4e ADD %RSI,%R10 |
(122) 0x428d51 ADD %RSI,%R13 |
(122) 0x428d54 VMOVSD (%RDX,%R11,8),%XMM12 |
(122) 0x428d5a LEA (%RBX,%RCX,8),%RAX |
(122) 0x428d5e MOV 0xc0(%RSP),%RCX |
(122) 0x428d66 ADD %RSI,%R9 |
(122) 0x428d69 MOV 0xf8(%RSP),%R11 |
(122) 0x428d71 MOV 0xf0(%RSP),%R15 |
(122) 0x428d79 ADD %RSI,%R8 |
(122) 0x428d7c VMULSD (%RAX),%XMM12,%XMM13 |
(122) 0x428d80 ADD %RSI,%RCX |
(122) 0x428d83 VADDSD (%R12,%R9,8),%XMM12,%XMM4 |
(122) 0x428d89 VMOVSD (%R14,%RCX,8),%XMM0 |
(122) 0x428d8f ADD %RSI,%R11 |
(122) 0x428d92 VSUBSD (%R14,%R11,8),%XMM0,%XMM1 |
(122) 0x428d98 VSUBSD (%R12,%R8,8),%XMM4,%XMM6 |
(122) 0x428d9e VSUBSD (%RDI,%R10,8),%XMM13,%XMM14 |
(122) 0x428da4 VADDSD (%RDI,%R13,8),%XMM14,%XMM15 |
(122) 0x428daa MOV 0xb8(%RSP),%RDI |
(122) 0x428db2 ADD %RSI,%RDI |
(122) 0x428db5 LEA (%R15,%RDI,8),%RBX |
(122) 0x428db9 VDIVSD %XMM6,%XMM15,%XMM2 |
(122) 0x428dbd VFMADD132SD (%RBX),%XMM1,%XMM13 |
(122) 0x428dc2 VDIVSD %XMM15,%XMM13,%XMM7 |
(122) 0x428dc7 VMOVSD %XMM2,(%RAX) |
(122) 0x428dcb VMOVSD %XMM7,(%RBX) |
(122) 0x428dcf MOV 0xd0(%RSP),%R15D |
(122) 0x428dd7 INCQ 0xc8(%RSP) |
(122) 0x428ddf MOV 0xc8(%RSP),%R14 |
(122) 0x428de7 ADD $0,%R14D |
(122) 0x428deb CMP %R14D,0x70(%RSP) |
(122) 0x428df0 JLE 428e10 |
(122) 0x428df2 MOV 0x68(%RSP),%ECX |
(122) 0x428df6 MOV 0x6c(%RSP),%R12D |
(122) 0x428dfb MOV 0x74(%RSP),%EAX |
(122) 0x428dff MOV %R12D,0xd4(%RSP) |
(122) 0x428e07 SUB %R15D,%ECX |
(122) 0x428e0a JMP 428768 |
0x428e0f NOP |
0x428e10 VZEROUPPER |
0x428e13 LEA -0x28(%RBP),%RSP |
0x428e17 POP %RBX |
0x428e18 POP %R12 |
0x428e1a POP %R13 |
0x428e1c POP %R14 |
0x428e1e POP %R15 |
0x428e20 POP %RBP |
0x428e21 RET |
0x428e22 NOPW (%RAX,%RAX,1) |
(122) 0x428e28 MOV 0xd4(%RSP),%ESI |
(122) 0x428e2f XOR %ECX,%ECX |
(122) 0x428e31 JMP 428a76 |
0x428e36 INC %ECX |
0x428e38 XOR %EDX,%EDX |
0x428e3a JMP 4286e5 |
0x428e3f NOP |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
○98.18 | gomp_thread_start | team.c:130 | libgomp.so.1.0.0 |
○1.82 | GOMP_parallel | libgomp.h:985 | libgomp.so.1.0.0 |
Path / |
Source file and lines | advec_cell.cpp:208-216 |
Module | exec |
nb instructions | 86 |
nb uops | 96 |
loop length | 299 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 13 |
micro-operation queue | 16.00 cycles |
front end | 16.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.10 | 8.00 | 6.67 | 6.67 | 10.00 | 6.07 | 5.90 | 10.00 | 10.00 | 10.00 | 5.93 | 6.67 |
cycles | 6.10 | 11.93 | 6.67 | 6.67 | 10.00 | 6.07 | 5.90 | 10.00 | 10.00 | 10.00 | 5.93 | 6.67 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 15.23-15.34 |
Stall cycles | 0.00 |
Front-end | 16.00 |
Dispatch | 11.93 |
DIV/SQRT | 12.00 |
Overall L1 | 16.00 |
all | 3% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 14% |
all | 9% |
load | 10% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 8% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0x100,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x38(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x3c(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x30(%RDI),%EDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x34(%RBX),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x2,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
INC %EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EDX,0x70(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EDI,0x6c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 428e13 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7.lto_priv.0+0x7b3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EDX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x2(%RSI),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%R13D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 428e13 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7.lto_priv.0+0x7b3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R14D,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %EDI,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ECX,0x74(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x74(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %R13D,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 428e36 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7.lto_priv.0+0x7d6> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %ECX,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RCX,%R11,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R9D,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R9D,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 428e13 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7.lto_priv.0+0x7b3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R11D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x6c(%RSP),%R10D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RBX),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x74(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x20(%RBX),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RBX),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RBX),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDI,0x60(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RSI,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R13,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%RAX,%R15,1),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R14D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x10(%RBX),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RBX),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %EDX,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %R15D,%R8 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R11D,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R10D,0xd4(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R10D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,0xc8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 4286e5 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7.lto_priv.0+0x85> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | advec_cell.cpp:208-216 |
Module | exec |
nb instructions | 86 |
nb uops | 96 |
loop length | 299 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 13 |
micro-operation queue | 16.00 cycles |
front end | 16.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.10 | 8.00 | 6.67 | 6.67 | 10.00 | 6.07 | 5.90 | 10.00 | 10.00 | 10.00 | 5.93 | 6.67 |
cycles | 6.10 | 11.93 | 6.67 | 6.67 | 10.00 | 6.07 | 5.90 | 10.00 | 10.00 | 10.00 | 5.93 | 6.67 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 15.23-15.34 |
Stall cycles | 0.00 |
Front-end | 16.00 |
Dispatch | 11.93 |
DIV/SQRT | 12.00 |
Overall L1 | 16.00 |
all | 3% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 14% |
all | 9% |
load | 10% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 8% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0x100,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x38(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x3c(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x30(%RDI),%EDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x34(%RBX),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x2,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
INC %EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EDX,0x70(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EDI,0x6c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 428e13 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7.lto_priv.0+0x7b3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EDX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x2(%RSI),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%R13D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 428e13 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7.lto_priv.0+0x7b3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R14D,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %EDI,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ECX,0x74(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x74(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %R13D,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 428e36 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7.lto_priv.0+0x7d6> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %ECX,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RCX,%R11,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R9D,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R9D,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 428e13 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7.lto_priv.0+0x7b3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R11D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x6c(%RSP),%R10D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RBX),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x74(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x20(%RBX),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RBX),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RBX),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDI,0x60(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RSI,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R13,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%RAX,%R15,1),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R14D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x10(%RBX),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RBX),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %EDX,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %R15D,%R8 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R11D,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R10D,0xd4(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R10D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,0xc8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 4286e5 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7.lto_priv.0+0x85> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D | 3.59 | 2.68 |
▼Loop 122 - advec_cell.cpp:211-216 - exec– | 0 | 0 |
○Loop 123 - advec_cell.cpp:211-216 - exec | 3.59 | 2.68 |