Function: initialise_chunk(int, global_variables&) [clone ._omp_fn.4] [clone .lto_priv.0] | Module: exec | Source: initialise_chunk.cpp:77-82 [...] | Coverage: 0.03% |
---|
Function: initialise_chunk(int, global_variables&) [clone ._omp_fn.4] [clone .lto_priv.0] | Module: exec | Source: initialise_chunk.cpp:77-82 [...] | Coverage: 0.03% |
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/scratch_na/users/xoserete/qaas_runs/171-415-4687/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 46 - 69 |
-------------------------------------------------------------------------------- |
46: T &operator[](size_t i) const { return data[i]; } |
[...] |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
/scratch_na/users/xoserete/qaas_runs/171-415-4687/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/initialise_chunk.cpp: 77 - 82 |
-------------------------------------------------------------------------------- |
77: #pragma omp parallel for simd collapse(2) |
78: for (int j = (0); j < (yrange1); j++) { |
79: for (int i = (0); i < (xrange1); i++) { |
80: field.volume(i, j) = dx * dy; |
81: field.xarea(i, j) = field.celldy[j]; |
82: field.yarea(i, j) = field.celldx[i]; |
0x43b810 PUSH %RBP |
0x43b811 MOV %RSP,%RBP |
0x43b814 PUSH %R15 |
0x43b816 PUSH %R14 |
0x43b818 PUSH %R13 |
0x43b81a PUSH %R12 |
0x43b81c PUSH %RBX |
0x43b81d AND $-0x40,%RSP |
0x43b821 SUB $0x40,%RSP |
0x43b825 MOV 0x1c(%RDI),%R14D |
0x43b829 MOV 0x18(%RDI),%R15D |
0x43b82d MOV %R14D,0x10(%RSP) |
0x43b832 MOV %R15D,0x4(%RSP) |
0x43b837 TEST %R14D,%R14D |
0x43b83a JLE 43bd93 |
0x43b840 TEST %R15D,%R15D |
0x43b843 JLE 43bd93 |
0x43b849 MOV %RDI,%R12 |
0x43b84c CALL 4046c0 <omp_get_num_threads@plt> |
0x43b851 MOV %EAX,%EBX |
0x43b853 CALL 4045b0 <omp_get_thread_num@plt> |
0x43b858 XOR %EDX,%EDX |
0x43b85a MOV %EAX,%ESI |
0x43b85c MOV %R14D,%EAX |
0x43b85f IMUL %R15D,%EAX |
0x43b863 DIV %EBX |
0x43b865 MOV %EAX,%ECX |
0x43b867 CMP %EDX,%ESI |
0x43b869 JB 43bdb4 |
0x43b86f IMUL %ECX,%ESI |
0x43b872 LEA (%RSI,%RDX,1),%R10D |
0x43b876 LEA (%RCX,%R10,1),%EDI |
0x43b87a MOV %EDI,(%RSP) |
0x43b87d CMP %EDI,%R10D |
0x43b880 JAE 43bd93 |
0x43b886 MOV 0x4(%RSP),%R8D |
0x43b88b MOV %R10D,%EAX |
0x43b88e XOR %EDX,%EDX |
0x43b890 VMOVSD 0x8(%R12),%XMM2 |
0x43b897 MOV 0x10(%R12),%R13 |
0x43b89c DIV %R8D |
0x43b89f VMULSD (%R12),%XMM2,%XMM8 |
0x43b8a5 VBROADCASTSD %XMM8,%YMM3 |
0x43b8aa VBROADCASTSD %XMM8,%ZMM0 |
0x43b8b0 SUB %EDX,%R8D |
0x43b8b3 MOV %EDX,0x30(%RSP) |
0x43b8b7 MOVSXD %EAX,%RBX |
0x43b8ba MOV %R8D,%EDX |
0x43b8bd NOPL (%RAX) |
(213) 0x43b8c0 CMP %EDX,%ECX |
(213) 0x43b8c2 CMOVBE %ECX,%EDX |
(213) 0x43b8c5 LEA (%R10,%RDX,1),%ECX |
(213) 0x43b8c9 MOV %ECX,0x14(%RSP) |
(213) 0x43b8cd CMP %ECX,%R10D |
(213) 0x43b8d0 JAE 43bd68 |
(213) 0x43b8d6 MOV 0x290(%R13),%R11 |
(213) 0x43b8dd MOV 0x2a8(%R13),%RDI |
(213) 0x43b8e4 LEA -0x1(%RDX),%R8D |
(213) 0x43b8e8 MOV 0x2c0(%R13),%RAX |
(213) 0x43b8ef MOV 0x248(%R13),%R9 |
(213) 0x43b8f6 IMUL %RBX,%R11 |
(213) 0x43b8fa MOV 0x2d0(%R13),%RSI |
(213) 0x43b901 MOV 0x2a0(%R13),%R15 |
(213) 0x43b908 IMUL %RBX,%RDI |
(213) 0x43b90c MOV 0x2b8(%R13),%R14 |
(213) 0x43b913 MOV 0x228(%R13),%R12 |
(213) 0x43b91a LEA (%R9,%RBX,8),%RCX |
(213) 0x43b91e IMUL %RBX,%RAX |
(213) 0x43b922 MOV %RSI,0x38(%RSP) |
(213) 0x43b927 MOV %R11,0x18(%RSP) |
(213) 0x43b92c MOV %RDI,0x20(%RSP) |
(213) 0x43b931 MOV %RAX,0x28(%RSP) |
(213) 0x43b936 CMP $0x6,%R8D |
(213) 0x43b93a JBE 43bda8 |
(213) 0x43b940 MOVSXD 0x30(%RSP),%RAX |
(213) 0x43b945 LEA (%RDI,%RAX,1),%RSI |
(213) 0x43b949 MOV 0x28(%RSP),%RDI |
(213) 0x43b94e LEA (%R11,%RAX,1),%R11 |
(213) 0x43b952 LEA (%R14,%RSI,8),%R9 |
(213) 0x43b956 MOV 0x38(%RSP),%RSI |
(213) 0x43b95b LEA (%R12,%RAX,8),%R8 |
(213) 0x43b95f ADD %RDI,%RAX |
(213) 0x43b962 LEA (%R15,%R11,8),%R11 |
(213) 0x43b966 LEA (%RSI,%RAX,8),%RDI |
(213) 0x43b96a MOV %EDX,%ESI |
(213) 0x43b96c XOR %EAX,%EAX |
(213) 0x43b96e SHR $0x3,%ESI |
(213) 0x43b971 SAL $0x6,%RSI |
(213) 0x43b975 MOV %RSI,0x8(%RSP) |
(213) 0x43b97a SUB $0x40,%RSI |
(213) 0x43b97e SHR $0x6,%RSI |
(213) 0x43b982 INC %RSI |
(213) 0x43b985 AND $0x7,%ESI |
(213) 0x43b988 JE 43bad0 |
(213) 0x43b98e CMP $0x1,%RSI |
(213) 0x43b992 JE 43ba9f |
(213) 0x43b998 CMP $0x2,%RSI |
(213) 0x43b99c JE 43ba79 |
(213) 0x43b9a2 CMP $0x3,%RSI |
(213) 0x43b9a6 JE 43ba53 |
(213) 0x43b9ac CMP $0x4,%RSI |
(213) 0x43b9b0 JE 43ba2d |
(213) 0x43b9b2 CMP $0x5,%RSI |
(213) 0x43b9b6 JE 43ba07 |
(213) 0x43b9b8 CMP $0x6,%RSI |
(213) 0x43b9bc JE 43b9e1 |
(213) 0x43b9be VMOVUPD %ZMM0,(%R11) |
(213) 0x43b9c4 MOV $0x40,%EAX |
(213) 0x43b9c9 VBROADCASTSD (%RCX),%ZMM1 |
(213) 0x43b9cf VMOVUPD %ZMM1,(%R9) |
(213) 0x43b9d5 VMOVUPD (%R8),%ZMM5 |
(213) 0x43b9db VMOVUPD %ZMM5,(%RDI) |
(213) 0x43b9e1 VMOVUPD %ZMM0,(%R11,%RAX,1) |
(213) 0x43b9e8 VBROADCASTSD (%RCX),%ZMM4 |
(213) 0x43b9ee VMOVUPD %ZMM4,(%R9,%RAX,1) |
(213) 0x43b9f5 VMOVUPD (%R8,%RAX,1),%ZMM7 |
(213) 0x43b9fc VMOVUPD %ZMM7,(%RDI,%RAX,1) |
(213) 0x43ba03 ADD $0x40,%RAX |
(213) 0x43ba07 VMOVUPD %ZMM0,(%R11,%RAX,1) |
(213) 0x43ba0e VBROADCASTSD (%RCX),%ZMM6 |
(213) 0x43ba14 VMOVUPD %ZMM6,(%R9,%RAX,1) |
(213) 0x43ba1b VMOVUPD (%R8,%RAX,1),%ZMM9 |
(213) 0x43ba22 VMOVUPD %ZMM9,(%RDI,%RAX,1) |
(213) 0x43ba29 ADD $0x40,%RAX |
(213) 0x43ba2d VMOVUPD %ZMM0,(%R11,%RAX,1) |
(213) 0x43ba34 VBROADCASTSD (%RCX),%ZMM10 |
(213) 0x43ba3a VMOVUPD %ZMM10,(%R9,%RAX,1) |
(213) 0x43ba41 VMOVUPD (%R8,%RAX,1),%ZMM11 |
(213) 0x43ba48 VMOVUPD %ZMM11,(%RDI,%RAX,1) |
(213) 0x43ba4f ADD $0x40,%RAX |
(213) 0x43ba53 VMOVUPD %ZMM0,(%R11,%RAX,1) |
(213) 0x43ba5a VBROADCASTSD (%RCX),%ZMM12 |
(213) 0x43ba60 VMOVUPD %ZMM12,(%R9,%RAX,1) |
(213) 0x43ba67 VMOVUPD (%R8,%RAX,1),%ZMM13 |
(213) 0x43ba6e VMOVUPD %ZMM13,(%RDI,%RAX,1) |
(213) 0x43ba75 ADD $0x40,%RAX |
(213) 0x43ba79 VMOVUPD %ZMM0,(%R11,%RAX,1) |
(213) 0x43ba80 VBROADCASTSD (%RCX),%ZMM14 |
(213) 0x43ba86 VMOVUPD %ZMM14,(%R9,%RAX,1) |
(213) 0x43ba8d VMOVUPD (%R8,%RAX,1),%ZMM15 |
(213) 0x43ba94 VMOVUPD %ZMM15,(%RDI,%RAX,1) |
(213) 0x43ba9b ADD $0x40,%RAX |
(213) 0x43ba9f VMOVUPD %ZMM0,(%R11,%RAX,1) |
(213) 0x43baa6 VBROADCASTSD (%RCX),%ZMM2 |
(213) 0x43baac VMOVUPD %ZMM2,(%R9,%RAX,1) |
(213) 0x43bab3 VMOVUPD (%R8,%RAX,1),%ZMM1 |
(213) 0x43baba VMOVUPD %ZMM1,(%RDI,%RAX,1) |
(213) 0x43bac1 ADD $0x40,%RAX |
(213) 0x43bac5 CMP %RAX,0x8(%RSP) |
(213) 0x43baca JE 43bc0d |
(214) 0x43bad0 VMOVUPD %ZMM0,(%R11,%RAX,1) |
(214) 0x43bad7 VBROADCASTSD (%RCX),%ZMM5 |
(214) 0x43badd VMOVUPD %ZMM5,(%R9,%RAX,1) |
(214) 0x43bae4 VMOVUPD (%R8,%RAX,1),%ZMM4 |
(214) 0x43baeb VMOVUPD %ZMM4,(%RDI,%RAX,1) |
(214) 0x43baf2 VMOVUPD %ZMM0,0x40(%R11,%RAX,1) |
(214) 0x43bafa VBROADCASTSD (%RCX),%ZMM7 |
(214) 0x43bb00 VMOVUPD %ZMM7,0x40(%R9,%RAX,1) |
(214) 0x43bb08 VMOVUPD 0x40(%R8,%RAX,1),%ZMM6 |
(214) 0x43bb10 VMOVUPD %ZMM6,0x40(%RDI,%RAX,1) |
(214) 0x43bb18 VMOVUPD %ZMM0,0x80(%R11,%RAX,1) |
(214) 0x43bb20 VBROADCASTSD (%RCX),%ZMM9 |
(214) 0x43bb26 VMOVUPD %ZMM9,0x80(%R9,%RAX,1) |
(214) 0x43bb2e VMOVUPD 0x80(%R8,%RAX,1),%ZMM10 |
(214) 0x43bb36 VMOVUPD %ZMM10,0x80(%RDI,%RAX,1) |
(214) 0x43bb3e VMOVUPD %ZMM0,0xc0(%R11,%RAX,1) |
(214) 0x43bb46 VBROADCASTSD (%RCX),%ZMM11 |
(214) 0x43bb4c VMOVUPD %ZMM11,0xc0(%R9,%RAX,1) |
(214) 0x43bb54 VMOVUPD 0xc0(%R8,%RAX,1),%ZMM12 |
(214) 0x43bb5c VMOVUPD %ZMM12,0xc0(%RDI,%RAX,1) |
(214) 0x43bb64 VMOVUPD %ZMM0,0x100(%R11,%RAX,1) |
(214) 0x43bb6c VBROADCASTSD (%RCX),%ZMM13 |
(214) 0x43bb72 VMOVUPD %ZMM13,0x100(%R9,%RAX,1) |
(214) 0x43bb7a VMOVUPD 0x100(%R8,%RAX,1),%ZMM14 |
(214) 0x43bb82 VMOVUPD %ZMM14,0x100(%RDI,%RAX,1) |
(214) 0x43bb8a VMOVUPD %ZMM0,0x140(%R11,%RAX,1) |
(214) 0x43bb92 VBROADCASTSD (%RCX),%ZMM15 |
(214) 0x43bb98 VMOVUPD %ZMM15,0x140(%R9,%RAX,1) |
(214) 0x43bba0 VMOVUPD 0x140(%R8,%RAX,1),%ZMM2 |
(214) 0x43bba8 VMOVUPD %ZMM2,0x140(%RDI,%RAX,1) |
(214) 0x43bbb0 VMOVUPD %ZMM0,0x180(%R11,%RAX,1) |
(214) 0x43bbb8 VBROADCASTSD (%RCX),%ZMM1 |
(214) 0x43bbbe VMOVUPD %ZMM1,0x180(%R9,%RAX,1) |
(214) 0x43bbc6 VMOVUPD 0x180(%R8,%RAX,1),%ZMM5 |
(214) 0x43bbce VMOVUPD %ZMM5,0x180(%RDI,%RAX,1) |
(214) 0x43bbd6 VMOVUPD %ZMM0,0x1c0(%R11,%RAX,1) |
(214) 0x43bbde VBROADCASTSD (%RCX),%ZMM4 |
(214) 0x43bbe4 VMOVUPD %ZMM4,0x1c0(%R9,%RAX,1) |
(214) 0x43bbec VMOVUPD 0x1c0(%R8,%RAX,1),%ZMM7 |
(214) 0x43bbf4 VMOVUPD %ZMM7,0x1c0(%RDI,%RAX,1) |
(214) 0x43bbfc ADD $0x200,%RAX |
(214) 0x43bc02 CMP %RAX,0x8(%RSP) |
(214) 0x43bc07 JNE 43bad0 |
(213) 0x43bc0d MOV 0x30(%RSP),%R11D |
(213) 0x43bc12 MOV %EDX,%R9D |
(213) 0x43bc15 AND $-0x8,%R9D |
(213) 0x43bc19 ADD %R9D,%R10D |
(213) 0x43bc1c LEA (%R9,%R11,1),%EDI |
(213) 0x43bc20 TEST $0x7,%DL |
(213) 0x43bc23 JE 43bd63 |
(213) 0x43bc29 SUB %R9D,%EDX |
(213) 0x43bc2c LEA -0x1(%RDX),%R8D |
(213) 0x43bc30 CMP $0x2,%R8D |
(213) 0x43bc34 JBE 43bc99 |
(213) 0x43bc36 MOVSXD 0x30(%RSP),%RAX |
(213) 0x43bc3b MOV 0x18(%RSP),%RSI |
(213) 0x43bc40 MOV 0x20(%RSP),%R8 |
(213) 0x43bc45 VMOVSD (%RCX),%XMM6 |
(213) 0x43bc49 LEA (%RSI,%RAX,1),%R11 |
(213) 0x43bc4d LEA (%R8,%RAX,1),%RSI |
(213) 0x43bc51 MOV 0x28(%RSP),%R8 |
(213) 0x43bc56 ADD %R9,%R11 |
(213) 0x43bc59 VBROADCASTSD %XMM6,%YMM9 |
(213) 0x43bc5e ADD %R9,%RSI |
(213) 0x43bc61 VMOVUPD %YMM3,(%R15,%R11,8) |
(213) 0x43bc67 LEA (%RAX,%R9,1),%R11 |
(213) 0x43bc6b VMOVUPD %YMM9,(%R14,%RSI,8) |
(213) 0x43bc71 ADD %R8,%RAX |
(213) 0x43bc74 ADD %R9,%RAX |
(213) 0x43bc77 VMOVUPD (%R12,%R11,8),%YMM10 |
(213) 0x43bc7d MOV 0x38(%RSP),%R9 |
(213) 0x43bc82 VMOVUPD %YMM10,(%R9,%RAX,8) |
(213) 0x43bc88 TEST $0x3,%DL |
(213) 0x43bc8b JE 43bd63 |
(213) 0x43bc91 AND $-0x4,%EDX |
(213) 0x43bc94 ADD %EDX,%R10D |
(213) 0x43bc97 ADD %EDX,%EDI |
(213) 0x43bc99 MOV 0x18(%RSP),%R9 |
(213) 0x43bc9e MOVSXD %EDI,%RAX |
(213) 0x43bca1 MOV 0x20(%RSP),%R11 |
(213) 0x43bca6 LEA (,%RAX,8),%R8 |
(213) 0x43bcae LEA (%R9,%RAX,1),%RDX |
(213) 0x43bcb2 LEA (%R11,%RAX,1),%RSI |
(213) 0x43bcb6 MOV %R8,0x30(%RSP) |
(213) 0x43bcbb MOV 0x28(%RSP),%R8 |
(213) 0x43bcc0 VMOVSD %XMM8,(%R15,%RDX,8) |
(213) 0x43bcc6 MOV 0x38(%RSP),%RDX |
(213) 0x43bccb VMOVSD (%RCX),%XMM11 |
(213) 0x43bccf VMOVSD %XMM11,(%R14,%RSI,8) |
(213) 0x43bcd5 LEA 0x1(%R10),%ESI |
(213) 0x43bcd9 VMOVSD (%R12,%RAX,8),%XMM12 |
(213) 0x43bcdf ADD %R8,%RAX |
(213) 0x43bce2 VMOVSD %XMM12,(%RDX,%RAX,8) |
(213) 0x43bce7 MOV 0x14(%RSP),%EDX |
(213) 0x43bceb LEA 0x1(%RDI),%EAX |
(213) 0x43bcee CMP %EDX,%ESI |
(213) 0x43bcf0 JAE 43bd63 |
(213) 0x43bcf2 CLTQ |
(213) 0x43bcf4 ADD $0x2,%R10D |
(213) 0x43bcf8 ADD $0x2,%EDI |
(213) 0x43bcfb LEA (%R9,%RAX,1),%RSI |
(213) 0x43bcff VMOVSD %XMM8,(%R15,%RSI,8) |
(213) 0x43bd05 LEA (%R11,%RAX,1),%RSI |
(213) 0x43bd09 ADD %R8,%RAX |
(213) 0x43bd0c VMOVSD (%RCX),%XMM13 |
(213) 0x43bd10 VMOVSD %XMM13,(%R14,%RSI,8) |
(213) 0x43bd16 MOV 0x30(%RSP),%RSI |
(213) 0x43bd1b VMOVSD 0x8(%R12,%RSI,1),%XMM14 |
(213) 0x43bd22 MOV %R8,%RSI |
(213) 0x43bd25 MOV 0x38(%RSP),%R8 |
(213) 0x43bd2a VMOVSD %XMM14,(%R8,%RAX,8) |
(213) 0x43bd30 CMP %EDX,%R10D |
(213) 0x43bd33 JAE 43bd63 |
(213) 0x43bd35 MOVSXD %EDI,%R10 |
(213) 0x43bd38 ADD %R10,%R9 |
(213) 0x43bd3b ADD %R10,%R11 |
(213) 0x43bd3e ADD %R10,%RSI |
(213) 0x43bd41 VMOVSD %XMM8,(%R15,%R9,8) |
(213) 0x43bd47 MOV 0x30(%RSP),%R15 |
(213) 0x43bd4c VMOVSD (%RCX),%XMM15 |
(213) 0x43bd50 VMOVSD %XMM15,(%R14,%R11,8) |
(213) 0x43bd56 VMOVSD 0x10(%R12,%R15,1),%XMM2 |
(213) 0x43bd5d VMOVSD %XMM2,(%R8,%RSI,8) |
(213) 0x43bd63 MOV 0x14(%RSP),%R10D |
(213) 0x43bd68 INC %RBX |
(213) 0x43bd6b CMP %EBX,0x10(%RSP) |
(213) 0x43bd6f JLE 43bd90 |
(213) 0x43bd71 MOV (%RSP),%ECX |
(213) 0x43bd74 MOV 0x4(%RSP),%EDX |
(213) 0x43bd78 MOVL $0,0x30(%RSP) |
(213) 0x43bd80 SUB %R10D,%ECX |
(213) 0x43bd83 JMP 43b8c0 |
0x43bd88 NOPL (%RAX,%RAX,1) |
0x43bd90 VZEROUPPER |
0x43bd93 LEA -0x28(%RBP),%RSP |
0x43bd97 POP %RBX |
0x43bd98 POP %R12 |
0x43bd9a POP %R13 |
0x43bd9c POP %R14 |
0x43bd9e POP %R15 |
0x43bda0 POP %RBP |
0x43bda1 RET |
0x43bda2 NOPW (%RAX,%RAX,1) |
(213) 0x43bda8 MOV 0x30(%RSP),%EDI |
(213) 0x43bdac XOR %R9D,%R9D |
(213) 0x43bdaf JMP 43bc29 |
0x43bdb4 INC %ECX |
0x43bdb6 XOR %EDX,%EDX |
0x43bdb8 JMP 43b86f |
0x43bdbd NOPL (%RAX) |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
○98.12 | gomp_thread_start | team.c:130 | libgomp.so.1.0.0 |
○1.88 | GOMP_parallel | libgomp.h:985 | libgomp.so.1.0.0 |
Path / |
Source file and lines | initialise_chunk.cpp:77-82 |
Module | exec |
nb instructions | 64 |
nb uops | 73 |
loop length | 220 |
used x86 registers | 14 |
used mmx registers | 0 |
used xmm registers | 2 |
used ymm registers | 1 |
used zmm registers | 1 |
nb stack references | 5 |
micro-operation queue | 12.17 cycles |
front end | 12.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 4.60 | 8.00 | 4.33 | 4.33 | 6.00 | 4.40 | 4.60 | 6.00 | 6.00 | 6.00 | 4.40 | 4.33 |
cycles | 4.60 | 10.13 | 4.33 | 4.33 | 6.00 | 4.40 | 4.60 | 6.00 | 6.00 | 6.00 | 4.40 | 4.33 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 12.18-12.22 |
Stall cycles | 0.01-0.05 |
ROB full (events) | 0.02-0.08 |
Front-end | 12.17 |
Dispatch | 10.13 |
DIV/SQRT | 12.00 |
Overall L1 | 12.17 |
all | 5% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 11% |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 0% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 4% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 11% |
all | 7% |
load | 7% |
store | 6% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 9% |
all | 12% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 12% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
all | 8% |
load | 9% |
store | 6% |
mul | 12% |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 10% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0x40,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x1c(%RDI),%R14D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RDI),%R15D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R14D,0x10(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15D,0x4(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %R14D,%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 43bd93 <_Z16initialise_chunkiR16global_variables._omp_fn.4.lto_priv.0+0x583> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
TEST %R15D,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 43bd93 <_Z16initialise_chunkiR16global_variables._omp_fn.4.lto_priv.0+0x583> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R14D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %R15D,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %EBX | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 43bdb4 <_Z16initialise_chunkiR16global_variables._omp_fn.4.lto_priv.0+0x5a4> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %ECX,%ESI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%RSI,%RDX,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RCX,%R10,1),%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDI,(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDI,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 43bd93 <_Z16initialise_chunkiR16global_variables._omp_fn.4.lto_priv.0+0x583> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x4(%RSP),%R8D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVSD 0x8(%R12),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%R12),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIV %R8D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
VMULSD (%R12),%XMM2,%XMM8 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VBROADCASTSD %XMM8,%YMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VBROADCASTSD %XMM8,%ZMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
SUB %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EDX,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVSXD %EAX,%RBX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R8D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 43b86f <_Z16initialise_chunkiR16global_variables._omp_fn.4.lto_priv.0+0x5f> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | initialise_chunk.cpp:77-82 |
Module | exec |
nb instructions | 64 |
nb uops | 73 |
loop length | 220 |
used x86 registers | 14 |
used mmx registers | 0 |
used xmm registers | 2 |
used ymm registers | 1 |
used zmm registers | 1 |
nb stack references | 5 |
micro-operation queue | 12.17 cycles |
front end | 12.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 4.60 | 8.00 | 4.33 | 4.33 | 6.00 | 4.40 | 4.60 | 6.00 | 6.00 | 6.00 | 4.40 | 4.33 |
cycles | 4.60 | 10.13 | 4.33 | 4.33 | 6.00 | 4.40 | 4.60 | 6.00 | 6.00 | 6.00 | 4.40 | 4.33 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 12.18-12.22 |
Stall cycles | 0.01-0.05 |
ROB full (events) | 0.02-0.08 |
Front-end | 12.17 |
Dispatch | 10.13 |
DIV/SQRT | 12.00 |
Overall L1 | 12.17 |
all | 5% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 11% |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 0% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 4% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 11% |
all | 7% |
load | 7% |
store | 6% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 9% |
all | 12% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 12% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
all | 8% |
load | 9% |
store | 6% |
mul | 12% |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 10% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0x40,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x1c(%RDI),%R14D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RDI),%R15D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R14D,0x10(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15D,0x4(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %R14D,%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 43bd93 <_Z16initialise_chunkiR16global_variables._omp_fn.4.lto_priv.0+0x583> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
TEST %R15D,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 43bd93 <_Z16initialise_chunkiR16global_variables._omp_fn.4.lto_priv.0+0x583> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R14D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %R15D,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %EBX | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 43bdb4 <_Z16initialise_chunkiR16global_variables._omp_fn.4.lto_priv.0+0x5a4> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %ECX,%ESI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%RSI,%RDX,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RCX,%R10,1),%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDI,(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDI,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 43bd93 <_Z16initialise_chunkiR16global_variables._omp_fn.4.lto_priv.0+0x583> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x4(%RSP),%R8D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVSD 0x8(%R12),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%R12),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIV %R8D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
VMULSD (%R12),%XMM2,%XMM8 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VBROADCASTSD %XMM8,%YMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VBROADCASTSD %XMM8,%ZMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
SUB %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EDX,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVSXD %EAX,%RBX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R8D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 43b86f <_Z16initialise_chunkiR16global_variables._omp_fn.4.lto_priv.0+0x5f> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼initialise_chunk(int, global_variables&) [clone ._omp_fn.4] [clone .lto_priv.0]– | 0.03 | 0.02 |
▼Loop 213 - initialise_chunk.cpp:77-82 - exec– | 0 | 0 |
○Loop 214 - initialise_chunk.cpp:80-82 - exec | 0.03 | 0.02 |