Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ... | Module: exec | Source: advec_mom.cpp:85-88 [...] | Coverage: 0.98% |
---|
Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ... | Module: exec | Source: advec_mom.cpp:85-88 [...] | Coverage: 0.98% |
---|
/scratch_na/users/xoserete/qaas_runs/171-415-4687/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69 |
-------------------------------------------------------------------------------- |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
/scratch_na/users/xoserete/qaas_runs/171-415-4687/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp: 85 - 88 |
-------------------------------------------------------------------------------- |
85: #pragma omp parallel for simd collapse(2) |
86: for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) { |
87: for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) { |
88: node_flux(i, j) = 0.25 * (mass_flux_x(i + 0, j - 1) + mass_flux_x(i, j) + mass_flux_x(i + 1, j - 1) + mass_flux_x(i + 1, j + 0)); |
0x42a840 PUSH %RBP |
0x42a841 MOV %RSP,%RBP |
0x42a844 PUSH %R15 |
0x42a846 PUSH %R14 |
0x42a848 MOV %RDI,%R14 |
0x42a84b PUSH %R13 |
0x42a84d PUSH %R12 |
0x42a84f PUSH %RBX |
0x42a850 AND $-0x40,%RSP |
0x42a854 SUB $0x40,%RSP |
0x42a858 MOV 0x18(%RDI),%EAX |
0x42a85b MOV 0x1c(%RDI),%EDX |
0x42a85e MOV 0x10(%RDI),%ESI |
0x42a861 MOV 0x14(%R14),%ECX |
0x42a865 ADD $0x3,%EDX |
0x42a868 LEA 0x1(%RAX),%R13D |
0x42a86c LEA -0x1(%RSI),%EDI |
0x42a86f MOV %EDX,0x1c(%RSP) |
0x42a873 MOV %EDI,0x18(%RSP) |
0x42a877 CMP %EDX,%R13D |
0x42a87a JGE 42aceb |
0x42a880 MOV %EDX,%EBX |
0x42a882 LEA 0x4(%RCX),%R15D |
0x42a886 SUB %R13D,%EBX |
0x42a889 CMP %R15D,%EDI |
0x42a88c JGE 42aceb |
0x42a892 MOV %R15D,%R8D |
0x42a895 SUB %EDI,%R8D |
0x42a898 MOV %R8D,0x28(%RSP) |
0x42a89d CALL 4046c0 <omp_get_num_threads@plt> |
0x42a8a2 MOV %EAX,%R12D |
0x42a8a5 CALL 4045b0 <omp_get_thread_num@plt> |
0x42a8aa XOR %EDX,%EDX |
0x42a8ac MOV %EAX,%R9D |
0x42a8af MOV 0x28(%RSP),%EAX |
0x42a8b3 IMUL %EBX,%EAX |
0x42a8b6 DIV %R12D |
0x42a8b9 MOV %EAX,%EDI |
0x42a8bb CMP %EDX,%R9D |
0x42a8be JB 42ad0c |
0x42a8c4 IMUL %EDI,%R9D |
0x42a8c8 LEA (%R9,%RDX,1),%R12D |
0x42a8cc LEA (%RDI,%R12,1),%R10D |
0x42a8d0 MOV %R10D,0x14(%RSP) |
0x42a8d5 CMP %R10D,%R12D |
0x42a8d8 JAE 42aceb |
0x42a8de MOV %R12D,%EAX |
0x42a8e1 XOR %EDX,%EDX |
0x42a8e3 MOV 0x18(%RSP),%R11D |
0x42a8e8 MOV (%R14),%RSI |
0x42a8eb DIVL 0x28(%RSP) |
0x42a8ef MOV 0x8(%R14),%R14 |
0x42a8f3 VMOVSD 0x37fcd(%RIP),%XMM3 |
0x42a8fb MOV %RSI,0x8(%RSP) |
0x42a900 MOV %R14,(%RSP) |
0x42a904 VBROADCASTSD %XMM3,%YMM4 |
0x42a909 VBROADCASTSD %XMM3,%ZMM2 |
0x42a90f ADD %R13D,%EAX |
0x42a912 ADD %EDX,%R11D |
0x42a915 MOV %R15D,%EDX |
0x42a918 MOV %EAX,0x38(%RSP) |
0x42a91c CLTQ |
0x42a91e SUB %R11D,%EDX |
0x42a921 MOV %R11D,0x3c(%RSP) |
0x42a926 MOV %RAX,0x20(%RSP) |
0x42a92b NOPL (%RAX,%RAX,1) |
(132) 0x42a930 CMP %EDX,%EDI |
(132) 0x42a932 CMOVBE %EDI,%EDX |
(132) 0x42a935 LEA (%R12,%RDX,1),%R13D |
(132) 0x42a939 MOV %R13D,0x2c(%RSP) |
(132) 0x42a93e CMP %R13D,%R12D |
(132) 0x42a941 JAE 42acb6 |
(132) 0x42a947 MOV 0x8(%RSP),%RDI |
(132) 0x42a94c MOV 0x38(%RSP),%R15D |
(132) 0x42a951 LEA -0x1(%RDX),%R9D |
(132) 0x42a955 MOV 0x20(%RSP),%R10 |
(132) 0x42a95a MOV (%RSP),%R8 |
(132) 0x42a95e LEA -0x1(%R15),%EBX |
(132) 0x42a962 MOV 0x10(%RDI),%RCX |
(132) 0x42a966 MOV (%RDI),%RDI |
(132) 0x42a969 MOVSXD %EBX,%RSI |
(132) 0x42a96c MOV 0x10(%R8),%R15 |
(132) 0x42a970 IMUL %RDI,%RSI |
(132) 0x42a974 IMUL %R10,%RDI |
(132) 0x42a978 IMUL (%R8),%R10 |
(132) 0x42a97c MOV %R10,0x30(%RSP) |
(132) 0x42a981 CMP $0x6,%R9D |
(132) 0x42a985 JBE 42ad00 |
(132) 0x42a98b MOVSXD 0x3c(%RSP),%RAX |
(132) 0x42a990 MOV %EDX,%R9D |
(132) 0x42a993 SHR $0x3,%R9D |
(132) 0x42a997 LEA (%RSI,%RAX,1),%R11 |
(132) 0x42a99b LEA (%RDI,%RAX,1),%R8 |
(132) 0x42a99f SAL $0x6,%R9 |
(132) 0x42a9a3 ADD %R10,%RAX |
(132) 0x42a9a6 SAL $0x3,%R11 |
(132) 0x42a9aa SAL $0x3,%R8 |
(132) 0x42a9ae LEA (%R15,%RAX,8),%R10 |
(132) 0x42a9b2 XOR %EAX,%EAX |
(132) 0x42a9b4 LEA (%RCX,%R11,1),%R14 |
(132) 0x42a9b8 LEA (%RCX,%R8,1),%R13 |
(132) 0x42a9bc LEA 0x8(%RCX,%R11,1),%RBX |
(132) 0x42a9c1 LEA 0x8(%RCX,%R8,1),%R11 |
(132) 0x42a9c6 LEA -0x40(%R9),%R8 |
(132) 0x42a9ca SHR $0x6,%R8 |
(132) 0x42a9ce INC %R8 |
(132) 0x42a9d1 AND $0x3,%R8D |
(132) 0x42a9d5 JE 42aa88 |
(132) 0x42a9db CMP $0x1,%R8 |
(132) 0x42a9df JE 42aa4b |
(132) 0x42a9e1 CMP $0x2,%R8 |
(132) 0x42a9e5 JE 42aa17 |
(132) 0x42a9e7 VMOVUPD (%R13),%ZMM7 |
(132) 0x42a9ee VMOVUPD (%R11),%ZMM1 |
(132) 0x42a9f4 MOV $0x40,%EAX |
(132) 0x42a9f9 VADDPD (%R14),%ZMM7,%ZMM0 |
(132) 0x42a9ff VADDPD (%RBX),%ZMM1,%ZMM5 |
(132) 0x42aa05 VADDPD %ZMM5,%ZMM0,%ZMM6 |
(132) 0x42aa0b VMULPD %ZMM2,%ZMM6,%ZMM8 |
(132) 0x42aa11 VMOVUPD %ZMM8,(%R10) |
(132) 0x42aa17 VMOVUPD (%R13,%RAX,1),%ZMM9 |
(132) 0x42aa1f VMOVUPD (%R11,%RAX,1),%ZMM11 |
(132) 0x42aa26 VADDPD (%R14,%RAX,1),%ZMM9,%ZMM10 |
(132) 0x42aa2d VADDPD (%RBX,%RAX,1),%ZMM11,%ZMM12 |
(132) 0x42aa34 VADDPD %ZMM12,%ZMM10,%ZMM13 |
(132) 0x42aa3a VMULPD %ZMM2,%ZMM13,%ZMM14 |
(132) 0x42aa40 VMOVUPD %ZMM14,(%R10,%RAX,1) |
(132) 0x42aa47 ADD $0x40,%RAX |
(132) 0x42aa4b VMOVUPD (%R13,%RAX,1),%ZMM15 |
(132) 0x42aa53 VMOVUPD (%R11,%RAX,1),%ZMM7 |
(132) 0x42aa5a VADDPD (%R14,%RAX,1),%ZMM15,%ZMM0 |
(132) 0x42aa61 VADDPD (%RBX,%RAX,1),%ZMM7,%ZMM1 |
(132) 0x42aa68 VADDPD %ZMM1,%ZMM0,%ZMM5 |
(132) 0x42aa6e VMULPD %ZMM2,%ZMM5,%ZMM6 |
(132) 0x42aa74 VMOVUPD %ZMM6,(%R10,%RAX,1) |
(132) 0x42aa7b ADD $0x40,%RAX |
(132) 0x42aa7f CMP %RAX,%R9 |
(132) 0x42aa82 JE 42ab63 |
(133) 0x42aa88 VMOVUPD (%R13,%RAX,1),%ZMM8 |
(133) 0x42aa90 VMOVUPD (%R11,%RAX,1),%ZMM10 |
(133) 0x42aa97 VADDPD (%R14,%RAX,1),%ZMM8,%ZMM9 |
(133) 0x42aa9e VADDPD (%RBX,%RAX,1),%ZMM10,%ZMM11 |
(133) 0x42aaa5 VADDPD %ZMM11,%ZMM9,%ZMM12 |
(133) 0x42aaab VMULPD %ZMM2,%ZMM12,%ZMM13 |
(133) 0x42aab1 VMOVUPD %ZMM13,(%R10,%RAX,1) |
(133) 0x42aab8 VMOVUPD 0x40(%R13,%RAX,1),%ZMM14 |
(133) 0x42aac0 VMOVUPD 0x40(%R11,%RAX,1),%ZMM0 |
(133) 0x42aac8 VADDPD 0x40(%R14,%RAX,1),%ZMM14,%ZMM15 |
(133) 0x42aad0 VADDPD 0x40(%RBX,%RAX,1),%ZMM0,%ZMM7 |
(133) 0x42aad8 VADDPD %ZMM7,%ZMM15,%ZMM1 |
(133) 0x42aade VMULPD %ZMM2,%ZMM1,%ZMM5 |
(133) 0x42aae4 VMOVUPD %ZMM5,0x40(%R10,%RAX,1) |
(133) 0x42aaec VMOVUPD 0x80(%R13,%RAX,1),%ZMM6 |
(133) 0x42aaf4 VMOVUPD 0x80(%R11,%RAX,1),%ZMM9 |
(133) 0x42aafc VADDPD 0x80(%R14,%RAX,1),%ZMM6,%ZMM8 |
(133) 0x42ab04 VADDPD 0x80(%RBX,%RAX,1),%ZMM9,%ZMM10 |
(133) 0x42ab0c VADDPD %ZMM10,%ZMM8,%ZMM11 |
(133) 0x42ab12 VMULPD %ZMM2,%ZMM11,%ZMM12 |
(133) 0x42ab18 VMOVUPD %ZMM12,0x80(%R10,%RAX,1) |
(133) 0x42ab20 VMOVUPD 0xc0(%R13,%RAX,1),%ZMM13 |
(133) 0x42ab28 VMOVUPD 0xc0(%R11,%RAX,1),%ZMM15 |
(133) 0x42ab30 VADDPD 0xc0(%R14,%RAX,1),%ZMM13,%ZMM14 |
(133) 0x42ab38 VADDPD 0xc0(%RBX,%RAX,1),%ZMM15,%ZMM0 |
(133) 0x42ab40 VADDPD %ZMM0,%ZMM14,%ZMM7 |
(133) 0x42ab46 VMULPD %ZMM2,%ZMM7,%ZMM1 |
(133) 0x42ab4c VMOVUPD %ZMM1,0xc0(%R10,%RAX,1) |
(133) 0x42ab54 ADD $0x100,%RAX |
(133) 0x42ab5a CMP %RAX,%R9 |
(133) 0x42ab5d JNE 42aa88 |
(132) 0x42ab63 MOV 0x3c(%RSP),%EAX |
(132) 0x42ab67 MOV %EDX,%R14D |
(132) 0x42ab6a AND $-0x8,%R14D |
(132) 0x42ab6e ADD %R14D,%R12D |
(132) 0x42ab71 ADD %R14D,%EAX |
(132) 0x42ab74 TEST $0x7,%DL |
(132) 0x42ab77 JE 42acb1 |
(132) 0x42ab7d SUB %R14D,%EDX |
(132) 0x42ab80 LEA -0x1(%RDX),%R13D |
(132) 0x42ab84 CMP $0x2,%R13D |
(132) 0x42ab88 JBE 42abe0 |
(132) 0x42ab8a MOVSXD 0x3c(%RSP),%R9 |
(132) 0x42ab8f MOV 0x30(%RSP),%R10 |
(132) 0x42ab94 LEA (%RSI,%R9,1),%RBX |
(132) 0x42ab98 LEA (%RDI,%R9,1),%R11 |
(132) 0x42ab9c ADD %R10,%R9 |
(132) 0x42ab9f ADD %R14,%RBX |
(132) 0x42aba2 ADD %R14,%R11 |
(132) 0x42aba5 ADD %R14,%R9 |
(132) 0x42aba8 VMOVUPD 0x8(%RCX,%RBX,8),%YMM5 |
(132) 0x42abae VMOVUPD (%RCX,%R11,8),%YMM8 |
(132) 0x42abb4 VADDPD 0x8(%RCX,%R11,8),%YMM5,%YMM6 |
(132) 0x42abbb VADDPD (%RCX,%RBX,8),%YMM8,%YMM9 |
(132) 0x42abc0 VADDPD %YMM9,%YMM6,%YMM10 |
(132) 0x42abc5 VMULPD %YMM4,%YMM10,%YMM11 |
(132) 0x42abc9 VMOVUPD %YMM11,(%R15,%R9,8) |
(132) 0x42abcf TEST $0x3,%DL |
(132) 0x42abd2 JE 42acb1 |
(132) 0x42abd8 AND $-0x4,%EDX |
(132) 0x42abdb ADD %EDX,%R12D |
(132) 0x42abde ADD %EDX,%EAX |
(132) 0x42abe0 LEA 0x1(%RAX),%R14D |
(132) 0x42abe4 MOVSXD %EAX,%RDX |
(132) 0x42abe7 MOVSXD %R14D,%R8 |
(132) 0x42abea MOV 0x30(%RSP),%R14 |
(132) 0x42abef LEA (%R8,%RSI,1),%R13 |
(132) 0x42abf3 LEA (%R8,%RDI,1),%RBX |
(132) 0x42abf7 LEA (%RCX,%R13,8),%R9 |
(132) 0x42abfb LEA (%RDI,%RDX,1),%R13 |
(132) 0x42abff VMOVSD (%RCX,%R13,8),%XMM12 |
(132) 0x42ac05 VMOVSD (%R9),%XMM14 |
(132) 0x42ac0a LEA (%R14,%RDX,1),%R11 |
(132) 0x42ac0e LEA (%RCX,%RBX,8),%R10 |
(132) 0x42ac12 ADD %RSI,%RDX |
(132) 0x42ac15 MOV 0x2c(%RSP),%R13D |
(132) 0x42ac1a VADDSD (%RCX,%RDX,8),%XMM12,%XMM13 |
(132) 0x42ac1f VADDSD (%R10),%XMM14,%XMM15 |
(132) 0x42ac24 LEA 0x1(%R12),%EDX |
(132) 0x42ac29 VADDSD %XMM15,%XMM13,%XMM0 |
(132) 0x42ac2e VMULSD %XMM3,%XMM0,%XMM7 |
(132) 0x42ac32 VMOVSD %XMM7,(%R15,%R11,8) |
(132) 0x42ac38 CMP %R13D,%EDX |
(132) 0x42ac3b JAE 42acb1 |
(132) 0x42ac3d LEA 0x2(%RAX),%EBX |
(132) 0x42ac40 VMOVSD (%R10),%XMM1 |
(132) 0x42ac45 ADD %R14,%R8 |
(132) 0x42ac48 ADD $0x2,%R12D |
(132) 0x42ac4c MOVSXD %EBX,%RDX |
(132) 0x42ac4f LEA (%RSI,%RDX,1),%R11 |
(132) 0x42ac53 VADDSD (%R9),%XMM1,%XMM5 |
(132) 0x42ac58 LEA (%RCX,%R11,8),%RBX |
(132) 0x42ac5c LEA (%RDI,%RDX,1),%R11 |
(132) 0x42ac60 LEA (%RCX,%R11,8),%R11 |
(132) 0x42ac64 VMOVSD (%R11),%XMM6 |
(132) 0x42ac69 VADDSD (%RBX),%XMM6,%XMM8 |
(132) 0x42ac6d VADDSD %XMM8,%XMM5,%XMM9 |
(132) 0x42ac72 VMULSD %XMM3,%XMM9,%XMM10 |
(132) 0x42ac76 VMOVSD %XMM10,(%R15,%R8,8) |
(132) 0x42ac7c CMP %R13D,%R12D |
(132) 0x42ac7f JAE 42acb1 |
(132) 0x42ac81 ADD $0x3,%EAX |
(132) 0x42ac84 VMOVSD (%RBX),%XMM13 |
(132) 0x42ac88 ADD %RDX,%R14 |
(132) 0x42ac8b CLTQ |
(132) 0x42ac8d ADD %RAX,%RSI |
(132) 0x42ac90 ADD %RDI,%RAX |
(132) 0x42ac93 VADDSD (%R11),%XMM13,%XMM14 |
(132) 0x42ac98 VMOVSD (%RCX,%RSI,8),%XMM11 |
(132) 0x42ac9d VADDSD (%RCX,%RAX,8),%XMM11,%XMM12 |
(132) 0x42aca2 VADDSD %XMM14,%XMM12,%XMM15 |
(132) 0x42aca7 VMULSD %XMM3,%XMM15,%XMM0 |
(132) 0x42acab VMOVSD %XMM0,(%R15,%R14,8) |
(132) 0x42acb1 MOV 0x2c(%RSP),%R12D |
(132) 0x42acb6 INCL 0x38(%RSP) |
(132) 0x42acba INCQ 0x20(%RSP) |
(132) 0x42acbf MOV 0x38(%RSP),%ECX |
(132) 0x42acc3 CMP %ECX,0x1c(%RSP) |
(132) 0x42acc7 JLE 42ace8 |
(132) 0x42acc9 MOV 0x14(%RSP),%EDI |
(132) 0x42accd MOV 0x18(%RSP),%ESI |
(132) 0x42acd1 MOV 0x28(%RSP),%EDX |
(132) 0x42acd5 MOV %ESI,0x3c(%RSP) |
(132) 0x42acd9 SUB %R12D,%EDI |
(132) 0x42acdc JMP 42a930 |
0x42ace1 NOPL (%RAX) |
0x42ace8 VZEROUPPER |
0x42aceb LEA -0x28(%RBP),%RSP |
0x42acef POP %RBX |
0x42acf0 POP %R12 |
0x42acf2 POP %R13 |
0x42acf4 POP %R14 |
0x42acf6 POP %R15 |
0x42acf8 POP %RBP |
0x42acf9 RET |
0x42acfa NOPW (%RAX,%RAX,1) |
(132) 0x42ad00 MOV 0x3c(%RSP),%EAX |
(132) 0x42ad04 XOR %R14D,%R14D |
(132) 0x42ad07 JMP 42ab7d |
0x42ad0c INC %EDI |
0x42ad0e XOR %EDX,%EDX |
0x42ad10 JMP 42a8c4 |
0x42ad15 NOPW %CS:(%RAX,%RAX,1) |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
○98.25 | gomp_thread_start | team.c:130 | libgomp.so.1.0.0 |
○1.75 | GOMP_parallel | libgomp.h:985 | libgomp.so.1.0.0 |
Path / |
Source file and lines | advec_mom.cpp:85-88 |
Module | exec |
nb instructions | 81 |
nb uops | 91 |
loop length | 291 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 1 |
used ymm registers | 1 |
used zmm registers | 1 |
nb stack references | 10 |
micro-operation queue | 15.17 cycles |
front end | 15.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.30 | 8.00 | 5.67 | 5.67 | 8.50 | 6.20 | 6.30 | 8.50 | 8.50 | 8.50 | 6.20 | 5.67 |
cycles | 6.30 | 11.90 | 5.67 | 5.67 | 8.50 | 6.20 | 6.30 | 8.50 | 8.50 | 8.50 | 6.20 | 5.67 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.42-14.53 |
Stall cycles | 0.00 |
Front-end | 15.17 |
Dispatch | 11.90 |
DIV/SQRT | 12.00 |
Overall L1 | 15.17 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 10% |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 3% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 10% |
all | 8% |
load | 6% |
store | 8% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 8% |
all | 12% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
all | 8% |
load | 8% |
store | 8% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 10% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0x40,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x18(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x1c(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x14(%R14),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x3,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%RAX),%R13D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA -0x1(%RSI),%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x1c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EDI,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%R13D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 42aceb <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x4ab> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x4(%RCX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R13D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R15D,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 42aceb <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x4ab> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R15D,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %EDI,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R8D,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R9D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x28(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 42ad0c <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x4cc> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %EDI,%R9D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R9,%RDX,1),%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RDI,%R12,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R10D,0x14(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R10D,%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 42aceb <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x4ab> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R12D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x18(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R14),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x28(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x8(%R14),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0x37fcd(%RIP),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VBROADCASTSD %XMM3,%YMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VBROADCASTSD %XMM3,%ZMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %R13D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %EDX,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R15D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %EAX,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CLTQ | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
SUB %R11D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R11D,0x3c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 42a8c4 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x84> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | advec_mom.cpp:85-88 |
Module | exec |
nb instructions | 81 |
nb uops | 91 |
loop length | 291 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 1 |
used ymm registers | 1 |
used zmm registers | 1 |
nb stack references | 10 |
micro-operation queue | 15.17 cycles |
front end | 15.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.30 | 8.00 | 5.67 | 5.67 | 8.50 | 6.20 | 6.30 | 8.50 | 8.50 | 8.50 | 6.20 | 5.67 |
cycles | 6.30 | 11.90 | 5.67 | 5.67 | 8.50 | 6.20 | 6.30 | 8.50 | 8.50 | 8.50 | 6.20 | 5.67 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.42-14.53 |
Stall cycles | 0.00 |
Front-end | 15.17 |
Dispatch | 11.90 |
DIV/SQRT | 12.00 |
Overall L1 | 15.17 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 10% |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 3% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 10% |
all | 8% |
load | 6% |
store | 8% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 8% |
all | 12% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
all | 8% |
load | 8% |
store | 8% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 10% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0x40,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x18(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x1c(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x14(%R14),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x3,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%RAX),%R13D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA -0x1(%RSI),%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x1c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EDI,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%R13D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 42aceb <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x4ab> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x4(%RCX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R13D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R15D,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 42aceb <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x4ab> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R15D,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %EDI,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R8D,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R9D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x28(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 42ad0c <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x4cc> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %EDI,%R9D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R9,%RDX,1),%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RDI,%R12,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R10D,0x14(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R10D,%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 42aceb <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x4ab> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R12D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x18(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R14),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x28(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x8(%R14),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0x37fcd(%RIP),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VBROADCASTSD %XMM3,%YMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VBROADCASTSD %XMM3,%ZMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %R13D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %EDX,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R15D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %EAX,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CLTQ | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
SUB %R11D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R11D,0x3c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 42a8c4 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x84> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D | 0.98 | 0.73 |
▼Loop 132 - advec_mom.cpp:87-88 - exec– | 0.01 | 0.01 |
○Loop 133 - advec_mom.cpp:88-88 - exec | 0.97 | 0.72 |