Function: generate_chunk(int, global_variables&) [clone ._omp_fn.0] [clone .lto_priv.0] | Module: exec | Source: generate_chunk.cpp:74-80 [...] | Coverage: 0.04% |
---|
Function: generate_chunk(int, global_variables&) [clone ._omp_fn.0] [clone .lto_priv.0] | Module: exec | Source: generate_chunk.cpp:74-80 [...] | Coverage: 0.04% |
---|
/scratch_na/users/xoserete/qaas_runs/171-415-4687/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 46 - 69 |
-------------------------------------------------------------------------------- |
46: T &operator[](size_t i) const { return data[i]; } |
[...] |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
/scratch_na/users/xoserete/qaas_runs/171-415-4687/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/generate_chunk.cpp: 74 - 80 |
-------------------------------------------------------------------------------- |
74: #pragma omp parallel for simd collapse(2) |
75: for (int j = (0); j < (yrange); j++) { |
76: for (int i = (0); i < (xrange); i++) { |
77: field.energy0(i, j) = state_energy[0]; |
78: field.density0(i, j) = state_density[0]; |
79: field.xvel0(i, j) = state_xvel[0]; |
80: field.yvel0(i, j) = state_yvel[0]; |
0x439ec0 PUSH %RBP |
0x439ec1 MOV %RSP,%RBP |
0x439ec4 PUSH %R15 |
0x439ec6 PUSH %R14 |
0x439ec8 PUSH %R13 |
0x439eca PUSH %R12 |
0x439ecc PUSH %RBX |
0x439ecd AND $-0x40,%RSP |
0x439ed1 ADD $-0x80,%RSP |
0x439ed5 MOV 0x2c(%RDI),%R14D |
0x439ed9 MOV 0x28(%RDI),%R15D |
0x439edd MOV %R14D,0x48(%RSP) |
0x439ee2 MOV %R15D,0x2c(%RSP) |
0x439ee7 TEST %R14D,%R14D |
0x439eea JLE 43a45b |
0x439ef0 TEST %R15D,%R15D |
0x439ef3 JLE 43a45b |
0x439ef9 MOV %RDI,%RBX |
0x439efc CALL 4046c0 <omp_get_num_threads@plt> |
0x439f01 MOV %EAX,%R12D |
0x439f04 CALL 4045b0 <omp_get_thread_num@plt> |
0x439f09 XOR %EDX,%EDX |
0x439f0b MOV %EAX,%ESI |
0x439f0d MOV %R14D,%EAX |
0x439f10 IMUL %R15D,%EAX |
0x439f14 DIV %R12D |
0x439f17 MOV %EAX,%R12D |
0x439f1a CMP %EDX,%ESI |
0x439f1c JB 43a47d |
0x439f22 IMUL %R12D,%ESI |
0x439f26 LEA (%RSI,%RDX,1),%R14D |
0x439f2a LEA (%R12,%R14,1),%EDI |
0x439f2e MOV %EDI,0x28(%RSP) |
0x439f32 CMP %EDI,%R14D |
0x439f35 JAE 43a45b |
0x439f3b MOV 0x2c(%RSP),%R8D |
0x439f40 MOV %R14D,%EAX |
0x439f43 XOR %EDX,%EDX |
0x439f45 MOV 0x8(%RBX),%R9 |
0x439f49 MOV (%RBX),%R10 |
0x439f4c MOV 0x10(%RBX),%R11 |
0x439f50 DIV %R8D |
0x439f53 MOV 0x18(%RBX),%R15 |
0x439f57 MOV 0x20(%RBX),%R13 |
0x439f5b MOV %R9,0x20(%RSP) |
0x439f60 MOV %R10,0x18(%RSP) |
0x439f65 MOV %R11,0x10(%RSP) |
0x439f6a MOV %R15,0x8(%RSP) |
0x439f6f MOV %EDX,0x60(%RSP) |
0x439f73 SUB %EDX,%R8D |
0x439f76 MOVSXD %EAX,%RBX |
0x439f79 NOPL (%RAX) |
(207) 0x439f80 CMP %R8D,%R12D |
(207) 0x439f83 CMOVBE %R12D,%R8D |
(207) 0x439f87 LEA (%R14,%R8,1),%ECX |
(207) 0x439f8b MOV %R8D,0x64(%RSP) |
(207) 0x439f90 MOV %ECX,0x4c(%RSP) |
(207) 0x439f94 CMP %ECX,%R14D |
(207) 0x439f97 JAE 43a42f |
(207) 0x439f9d MOV 0x18(%RSP),%RSI |
(207) 0x439fa2 MOV 0x10(%RSP),%R9 |
(207) 0x439fa7 MOV 0xb8(%R13),%R11 |
(207) 0x439fae MOV 0x10(%R13),%RAX |
(207) 0x439fb2 MOV 0x8(%RSP),%R15 |
(207) 0x439fb7 MOV 0x30(%R13),%RDX |
(207) 0x439fbb MOV 0x8(%RSI),%RDI |
(207) 0x439fbf MOV (%R13),%R10 |
(207) 0x439fc3 MOV %R11,0x70(%RSP) |
(207) 0x439fc8 MOV 0x8(%R9),%RSI |
(207) 0x439fcc MOV 0xa8(%R13),%R11 |
(207) 0x439fd3 IMUL %RBX,%RDX |
(207) 0x439fd7 MOV %RAX,0x68(%RSP) |
(207) 0x439fdc MOV 0xd8(%R13),%R9 |
(207) 0x439fe3 MOV 0x20(%RSP),%R12 |
(207) 0x439fe8 IMUL %RBX,%R10 |
(207) 0x439fec MOV 0xe8(%R13),%RAX |
(207) 0x439ff3 IMUL %RBX,%R11 |
(207) 0x439ff7 MOV 0x8(%R15),%RCX |
(207) 0x439ffb IMUL %RBX,%R9 |
(207) 0x439fff MOV 0x64(%RSP),%R15D |
(207) 0x43a004 MOV 0x8(%R12),%R8 |
(207) 0x43a009 MOV %RDX,0x30(%RSP) |
(207) 0x43a00e MOV 0x40(%R13),%R12 |
(207) 0x43a012 MOV %RAX,0x78(%RSP) |
(207) 0x43a017 LEA -0x1(%R15),%EAX |
(207) 0x43a01b MOV %R10,0x38(%RSP) |
(207) 0x43a020 MOV %R12,0x50(%RSP) |
(207) 0x43a025 MOV %R11,0x40(%RSP) |
(207) 0x43a02a MOV %R9,0x58(%RSP) |
(207) 0x43a02f CMP $0x6,%EAX |
(207) 0x43a032 JBE 43a470 |
(207) 0x43a038 MOVSXD 0x60(%RSP),%RAX |
(207) 0x43a03d LEA (%R10,%RAX,1),%R9 |
(207) 0x43a041 MOV 0x68(%RSP),%R10 |
(207) 0x43a046 LEA (%RDX,%RAX,1),%RDX |
(207) 0x43a04a LEA (%R12,%RDX,8),%R15 |
(207) 0x43a04e MOV 0x70(%RSP),%RDX |
(207) 0x43a053 LEA (%R11,%RAX,1),%R11 |
(207) 0x43a057 LEA (%R10,%R9,8),%R12 |
(207) 0x43a05b MOV 0x58(%RSP),%R9 |
(207) 0x43a060 MOV 0x78(%RSP),%R10 |
(207) 0x43a065 LEA (%RDX,%R11,8),%RDX |
(207) 0x43a069 ADD %R9,%RAX |
(207) 0x43a06c LEA (%R10,%RAX,8),%R11 |
(207) 0x43a070 MOV 0x64(%RSP),%R10D |
(207) 0x43a075 XOR %EAX,%EAX |
(207) 0x43a077 SHR $0x3,%R10D |
(207) 0x43a07b SAL $0x6,%R10 |
(207) 0x43a07f LEA -0x40(%R10),%R9 |
(207) 0x43a083 SHR $0x6,%R9 |
(207) 0x43a087 INC %R9 |
(207) 0x43a08a AND $0x3,%R9D |
(207) 0x43a08e JE 43a14f |
(207) 0x43a094 CMP $0x1,%R9 |
(207) 0x43a098 JE 43a10e |
(207) 0x43a09a CMP $0x2,%R9 |
(207) 0x43a09e JE 43a0d6 |
(207) 0x43a0a0 VBROADCASTSD (%R8),%ZMM0 |
(207) 0x43a0a6 MOV $0x40,%EAX |
(207) 0x43a0ab VMOVUPD %ZMM0,(%R15) |
(207) 0x43a0b1 VBROADCASTSD (%RDI),%ZMM1 |
(207) 0x43a0b7 VMOVUPD %ZMM1,(%R12) |
(207) 0x43a0be VBROADCASTSD (%RSI),%ZMM2 |
(207) 0x43a0c4 VMOVUPD %ZMM2,(%RDX) |
(207) 0x43a0ca VBROADCASTSD (%RCX),%ZMM3 |
(207) 0x43a0d0 VMOVUPD %ZMM3,(%R11) |
(207) 0x43a0d6 VBROADCASTSD (%R8),%ZMM4 |
(207) 0x43a0dc VMOVUPD %ZMM4,(%R15,%RAX,1) |
(207) 0x43a0e3 VBROADCASTSD (%RDI),%ZMM5 |
(207) 0x43a0e9 VMOVUPD %ZMM5,(%R12,%RAX,1) |
(207) 0x43a0f0 VBROADCASTSD (%RSI),%ZMM6 |
(207) 0x43a0f6 VMOVUPD %ZMM6,(%RDX,%RAX,1) |
(207) 0x43a0fd VBROADCASTSD (%RCX),%ZMM7 |
(207) 0x43a103 VMOVUPD %ZMM7,(%R11,%RAX,1) |
(207) 0x43a10a ADD $0x40,%RAX |
(207) 0x43a10e VBROADCASTSD (%R8),%ZMM8 |
(207) 0x43a114 VMOVUPD %ZMM8,(%R15,%RAX,1) |
(207) 0x43a11b VBROADCASTSD (%RDI),%ZMM9 |
(207) 0x43a121 VMOVUPD %ZMM9,(%R12,%RAX,1) |
(207) 0x43a128 VBROADCASTSD (%RSI),%ZMM10 |
(207) 0x43a12e VMOVUPD %ZMM10,(%RDX,%RAX,1) |
(207) 0x43a135 VBROADCASTSD (%RCX),%ZMM11 |
(207) 0x43a13b VMOVUPD %ZMM11,(%R11,%RAX,1) |
(207) 0x43a142 ADD $0x40,%RAX |
(207) 0x43a146 CMP %RAX,%R10 |
(207) 0x43a149 JE 43a23a |
(208) 0x43a14f VBROADCASTSD (%R8),%ZMM12 |
(208) 0x43a155 VMOVUPD %ZMM12,(%R15,%RAX,1) |
(208) 0x43a15c VBROADCASTSD (%RDI),%ZMM13 |
(208) 0x43a162 VMOVUPD %ZMM13,(%R12,%RAX,1) |
(208) 0x43a169 VBROADCASTSD (%RSI),%ZMM14 |
(208) 0x43a16f VMOVUPD %ZMM14,(%RDX,%RAX,1) |
(208) 0x43a176 VBROADCASTSD (%RCX),%ZMM15 |
(208) 0x43a17c VMOVUPD %ZMM15,(%R11,%RAX,1) |
(208) 0x43a183 VBROADCASTSD (%R8),%ZMM0 |
(208) 0x43a189 VMOVUPD %ZMM0,0x40(%R15,%RAX,1) |
(208) 0x43a191 VBROADCASTSD (%RDI),%ZMM1 |
(208) 0x43a197 VMOVUPD %ZMM1,0x40(%R12,%RAX,1) |
(208) 0x43a19f VBROADCASTSD (%RSI),%ZMM2 |
(208) 0x43a1a5 VMOVUPD %ZMM2,0x40(%RDX,%RAX,1) |
(208) 0x43a1ad VBROADCASTSD (%RCX),%ZMM3 |
(208) 0x43a1b3 VMOVUPD %ZMM3,0x40(%R11,%RAX,1) |
(208) 0x43a1bb VBROADCASTSD (%R8),%ZMM4 |
(208) 0x43a1c1 VMOVUPD %ZMM4,0x80(%R15,%RAX,1) |
(208) 0x43a1c9 VBROADCASTSD (%RDI),%ZMM5 |
(208) 0x43a1cf VMOVUPD %ZMM5,0x80(%R12,%RAX,1) |
(208) 0x43a1d7 VBROADCASTSD (%RSI),%ZMM6 |
(208) 0x43a1dd VMOVUPD %ZMM6,0x80(%RDX,%RAX,1) |
(208) 0x43a1e5 VBROADCASTSD (%RCX),%ZMM7 |
(208) 0x43a1eb VMOVUPD %ZMM7,0x80(%R11,%RAX,1) |
(208) 0x43a1f3 VBROADCASTSD (%R8),%ZMM8 |
(208) 0x43a1f9 VMOVUPD %ZMM8,0xc0(%R15,%RAX,1) |
(208) 0x43a201 VBROADCASTSD (%RDI),%ZMM9 |
(208) 0x43a207 VMOVUPD %ZMM9,0xc0(%R12,%RAX,1) |
(208) 0x43a20f VBROADCASTSD (%RSI),%ZMM10 |
(208) 0x43a215 VMOVUPD %ZMM10,0xc0(%RDX,%RAX,1) |
(208) 0x43a21d VBROADCASTSD (%RCX),%ZMM11 |
(208) 0x43a223 VMOVUPD %ZMM11,0xc0(%R11,%RAX,1) |
(208) 0x43a22b ADD $0x100,%RAX |
(208) 0x43a231 CMP %RAX,%R10 |
(208) 0x43a234 JNE 43a14f |
(207) 0x43a23a MOV 0x64(%RSP),%R15D |
(207) 0x43a23f MOV 0x60(%RSP),%EDX |
(207) 0x43a243 MOV %R15D,%R12D |
(207) 0x43a246 AND $-0x8,%R12D |
(207) 0x43a24a ADD %R12D,%R14D |
(207) 0x43a24d LEA (%R12,%RDX,1),%R10D |
(207) 0x43a251 TEST $0x7,%R15B |
(207) 0x43a255 JE 43a42a |
(207) 0x43a25b MOV 0x64(%RSP),%EDX |
(207) 0x43a25f SUB %R12D,%EDX |
(207) 0x43a262 LEA -0x1(%RDX),%R11D |
(207) 0x43a266 CMP $0x2,%R11D |
(207) 0x43a26a JBE 43a302 |
(207) 0x43a270 MOVSXD 0x60(%RSP),%RAX |
(207) 0x43a275 MOV 0x30(%RSP),%R9 |
(207) 0x43a27a VBROADCASTSD (%R8),%YMM15 |
(207) 0x43a27f MOV 0x50(%RSP),%R15 |
(207) 0x43a284 LEA (%R9,%RAX,1),%R11 |
(207) 0x43a288 MOV 0x38(%RSP),%R9 |
(207) 0x43a28d VMOVSD (%RDI),%XMM12 |
(207) 0x43a291 ADD %R12,%R11 |
(207) 0x43a294 VMOVSD (%RSI),%XMM13 |
(207) 0x43a298 VMOVSD (%RCX),%XMM14 |
(207) 0x43a29c VMOVUPD %YMM15,(%R15,%R11,8) |
(207) 0x43a2a2 LEA (%R9,%RAX,1),%R11 |
(207) 0x43a2a6 MOV 0x68(%RSP),%R15 |
(207) 0x43a2ab MOV 0x40(%RSP),%R9 |
(207) 0x43a2b0 VBROADCASTSD %XMM12,%YMM0 |
(207) 0x43a2b5 VBROADCASTSD %XMM13,%YMM1 |
(207) 0x43a2ba VBROADCASTSD %XMM14,%YMM2 |
(207) 0x43a2bf ADD %R12,%R11 |
(207) 0x43a2c2 VMOVUPD %YMM0,(%R15,%R11,8) |
(207) 0x43a2c8 LEA (%R9,%RAX,1),%R11 |
(207) 0x43a2cc MOV 0x58(%RSP),%R9 |
(207) 0x43a2d1 MOV 0x70(%RSP),%R15 |
(207) 0x43a2d6 ADD %R12,%R11 |
(207) 0x43a2d9 ADD %R9,%RAX |
(207) 0x43a2dc VMOVUPD %YMM1,(%R15,%R11,8) |
(207) 0x43a2e2 ADD %R12,%RAX |
(207) 0x43a2e5 MOV 0x78(%RSP),%R12 |
(207) 0x43a2ea VMOVUPD %YMM2,(%R12,%RAX,8) |
(207) 0x43a2f0 TEST $0x3,%DL |
(207) 0x43a2f3 JE 43a42a |
(207) 0x43a2f9 AND $-0x4,%EDX |
(207) 0x43a2fc ADD %EDX,%R14D |
(207) 0x43a2ff ADD %EDX,%R10D |
(207) 0x43a302 MOV 0x30(%RSP),%R9 |
(207) 0x43a307 VMOVSD (%R8),%XMM3 |
(207) 0x43a30c MOVSXD %R10D,%RAX |
(207) 0x43a30f MOV 0x50(%RSP),%R11 |
(207) 0x43a314 MOV 0x38(%RSP),%R15 |
(207) 0x43a319 LEA (%R9,%RAX,1),%RDX |
(207) 0x43a31d VMOVSD %XMM3,(%R11,%RDX,8) |
(207) 0x43a323 MOV 0x68(%RSP),%RDX |
(207) 0x43a328 LEA (%R15,%RAX,1),%R12 |
(207) 0x43a32c MOV 0x40(%RSP),%R11 |
(207) 0x43a331 VMOVSD (%RDI),%XMM4 |
(207) 0x43a335 VMOVSD %XMM4,(%RDX,%R12,8) |
(207) 0x43a33b MOV 0x70(%RSP),%R12 |
(207) 0x43a340 LEA (%R11,%RAX,1),%RDX |
(207) 0x43a344 VMOVSD (%RSI),%XMM5 |
(207) 0x43a348 VMOVSD %XMM5,(%R12,%RDX,8) |
(207) 0x43a34e MOV 0x58(%RSP),%RDX |
(207) 0x43a353 MOV 0x78(%RSP),%R12 |
(207) 0x43a358 VMOVSD (%RCX),%XMM6 |
(207) 0x43a35c ADD %RDX,%RAX |
(207) 0x43a35f LEA 0x1(%R14),%EDX |
(207) 0x43a363 VMOVSD %XMM6,(%R12,%RAX,8) |
(207) 0x43a369 MOV 0x4c(%RSP),%R12D |
(207) 0x43a36e LEA 0x1(%R10),%EAX |
(207) 0x43a372 CMP %R12D,%EDX |
(207) 0x43a375 JAE 43a42a |
(207) 0x43a37b VMOVSD (%R8),%XMM7 |
(207) 0x43a380 CLTQ |
(207) 0x43a382 MOV 0x50(%RSP),%R12 |
(207) 0x43a387 ADD $0x2,%R14D |
(207) 0x43a38b LEA (%R9,%RAX,1),%RDX |
(207) 0x43a38f ADD $0x2,%R10D |
(207) 0x43a393 VMOVSD %XMM7,(%R12,%RDX,8) |
(207) 0x43a399 MOV 0x68(%RSP),%R12 |
(207) 0x43a39e LEA (%R15,%RAX,1),%RDX |
(207) 0x43a3a2 VMOVSD (%RDI),%XMM8 |
(207) 0x43a3a6 VMOVSD %XMM8,(%R12,%RDX,8) |
(207) 0x43a3ac MOV 0x70(%RSP),%R12 |
(207) 0x43a3b1 LEA (%R11,%RAX,1),%RDX |
(207) 0x43a3b5 VMOVSD (%RSI),%XMM9 |
(207) 0x43a3b9 VMOVSD %XMM9,(%R12,%RDX,8) |
(207) 0x43a3bf MOV 0x58(%RSP),%RDX |
(207) 0x43a3c4 MOV 0x78(%RSP),%R12 |
(207) 0x43a3c9 VMOVSD (%RCX),%XMM10 |
(207) 0x43a3cd ADD %RDX,%RAX |
(207) 0x43a3d0 VMOVSD %XMM10,(%R12,%RAX,8) |
(207) 0x43a3d6 MOV 0x4c(%RSP),%EAX |
(207) 0x43a3da CMP %EAX,%R14D |
(207) 0x43a3dd JAE 43a42a |
(207) 0x43a3df VMOVSD (%R8),%XMM11 |
(207) 0x43a3e4 MOVSXD %R10D,%R14 |
(207) 0x43a3e7 MOV 0x50(%RSP),%R8 |
(207) 0x43a3ec ADD %R14,%R9 |
(207) 0x43a3ef ADD %R14,%R15 |
(207) 0x43a3f2 ADD %R14,%R11 |
(207) 0x43a3f5 ADD %R14,%RDX |
(207) 0x43a3f8 VMOVSD %XMM11,(%R8,%R9,8) |
(207) 0x43a3fe VMOVSD (%RDI),%XMM12 |
(207) 0x43a402 MOV 0x68(%RSP),%RDI |
(207) 0x43a407 VMOVSD %XMM12,(%RDI,%R15,8) |
(207) 0x43a40d VMOVSD (%RSI),%XMM13 |
(207) 0x43a411 MOV 0x70(%RSP),%RSI |
(207) 0x43a416 VMOVSD %XMM13,(%RSI,%R11,8) |
(207) 0x43a41c VMOVSD (%RCX),%XMM14 |
(207) 0x43a420 MOV 0x78(%RSP),%RCX |
(207) 0x43a425 VMOVSD %XMM14,(%RCX,%RDX,8) |
(207) 0x43a42a MOV 0x4c(%RSP),%R14D |
(207) 0x43a42f INC %RBX |
(207) 0x43a432 CMP %EBX,0x48(%RSP) |
(207) 0x43a436 JLE 43a458 |
(207) 0x43a438 MOV 0x28(%RSP),%R12D |
(207) 0x43a43d MOV 0x2c(%RSP),%R8D |
(207) 0x43a442 MOVL $0,0x60(%RSP) |
(207) 0x43a44a SUB %R14D,%R12D |
(207) 0x43a44d JMP 439f80 |
0x43a452 NOPW (%RAX,%RAX,1) |
0x43a458 VZEROUPPER |
0x43a45b LEA -0x28(%RBP),%RSP |
0x43a45f POP %RBX |
0x43a460 POP %R12 |
0x43a462 POP %R13 |
0x43a464 POP %R14 |
0x43a466 POP %R15 |
0x43a468 POP %RBP |
0x43a469 RET |
0x43a46a NOPW (%RAX,%RAX,1) |
(207) 0x43a470 MOV 0x60(%RSP),%R10D |
(207) 0x43a475 XOR %R12D,%R12D |
(207) 0x43a478 JMP 43a25b |
0x43a47d INC %R12D |
0x43a480 XOR %EDX,%EDX |
0x43a482 JMP 439f22 |
0x43a487 NOPW (%RAX,%RAX,1) |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
○98.25 | gomp_thread_start | team.c:130 | libgomp.so.1.0.0 |
○1.75 | GOMP_parallel | libgomp.h:985 | libgomp.so.1.0.0 |
Path / |
Source file and lines | generate_chunk.cpp:74-80 |
Module | exec |
nb instructions | 67 |
nb uops | 76 |
loop length | 241 |
used x86 registers | 15 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 9 |
micro-operation queue | 12.67 cycles |
front end | 12.67 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 3.70 | 8.00 | 5.00 | 5.00 | 8.00 | 3.87 | 3.70 | 8.00 | 8.00 | 8.00 | 3.73 | 5.00 |
cycles | 3.70 | 10.13 | 5.00 | 5.00 | 8.00 | 3.87 | 3.70 | 8.00 | 8.00 | 8.00 | 3.73 | 5.00 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 12.20-12.27 |
Stall cycles | 0.00 |
Front-end | 12.67 |
Dispatch | 10.13 |
DIV/SQRT | 12.00 |
Overall L1 | 12.67 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 20% |
all | 9% |
load | 10% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 10% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD $-0x80,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x2c(%RDI),%R14D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RDI),%R15D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R14D,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15D,0x2c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %R14D,%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 43a45b <_Z14generate_chunkiR16global_variables._omp_fn.0.lto_priv.0+0x59b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
TEST %R15D,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 43a45b <_Z14generate_chunkiR16global_variables._omp_fn.0.lto_priv.0+0x59b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R14D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %R15D,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 43a47d <_Z14generate_chunkiR16global_variables._omp_fn.0.lto_priv.0+0x5bd> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %R12D,%ESI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%RSI,%RDX,1),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%R12,%R14,1),%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDI,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDI,%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 43a45b <_Z14generate_chunkiR16global_variables._omp_fn.0.lto_priv.0+0x59b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x2c(%RSP),%R8D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R14D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x8(%RBX),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RBX),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%RBX),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIV %R8D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV 0x18(%RBX),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RBX),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R9,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0x10(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15,0x8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EDX,0x60(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %EAX,%RBX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 439f22 <_Z14generate_chunkiR16global_variables._omp_fn.0.lto_priv.0+0x62> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | generate_chunk.cpp:74-80 |
Module | exec |
nb instructions | 67 |
nb uops | 76 |
loop length | 241 |
used x86 registers | 15 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 9 |
micro-operation queue | 12.67 cycles |
front end | 12.67 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 3.70 | 8.00 | 5.00 | 5.00 | 8.00 | 3.87 | 3.70 | 8.00 | 8.00 | 8.00 | 3.73 | 5.00 |
cycles | 3.70 | 10.13 | 5.00 | 5.00 | 8.00 | 3.87 | 3.70 | 8.00 | 8.00 | 8.00 | 3.73 | 5.00 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 12.20-12.27 |
Stall cycles | 0.00 |
Front-end | 12.67 |
Dispatch | 10.13 |
DIV/SQRT | 12.00 |
Overall L1 | 12.67 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 20% |
all | 9% |
load | 10% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 10% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD $-0x80,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x2c(%RDI),%R14D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RDI),%R15D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R14D,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15D,0x2c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %R14D,%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 43a45b <_Z14generate_chunkiR16global_variables._omp_fn.0.lto_priv.0+0x59b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
TEST %R15D,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 43a45b <_Z14generate_chunkiR16global_variables._omp_fn.0.lto_priv.0+0x59b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R14D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %R15D,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 43a47d <_Z14generate_chunkiR16global_variables._omp_fn.0.lto_priv.0+0x5bd> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %R12D,%ESI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%RSI,%RDX,1),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%R12,%R14,1),%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDI,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDI,%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 43a45b <_Z14generate_chunkiR16global_variables._omp_fn.0.lto_priv.0+0x59b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x2c(%RSP),%R8D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R14D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x8(%RBX),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RBX),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%RBX),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIV %R8D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV 0x18(%RBX),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RBX),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R9,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0x10(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15,0x8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EDX,0x60(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %EAX,%RBX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 439f22 <_Z14generate_chunkiR16global_variables._omp_fn.0.lto_priv.0+0x62> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼generate_chunk(int, global_variables&) [clone ._omp_fn.0] [clone .lto_priv.0]– | 0.04 | 0.03 |
▼Loop 207 - generate_chunk.cpp:74-80 - exec– | 0 | 0 |
○Loop 208 - generate_chunk.cpp:77-80 - exec | 0.04 | 0.03 |