Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ... | Module: exec | Source: advec_cell.cpp:146-150 [...] | Coverage: 1.3% |
---|
Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ... | Module: exec | Source: advec_cell.cpp:146-150 [...] | Coverage: 1.3% |
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/scratch_na/users/xoserete/qaas_runs/171-415-4687/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69 |
-------------------------------------------------------------------------------- |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
/scratch_na/users/xoserete/qaas_runs/171-415-4687/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp: 146 - 150 |
-------------------------------------------------------------------------------- |
146: #pragma omp parallel for simd collapse(2) |
147: for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) { |
148: for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) { |
149: pre_vol(i, j) = volume(i, j) + vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j); |
150: post_vol(i, j) = volume(i, j); |
0x427590 PUSH %RBP |
0x427591 MOV %RSP,%RBP |
0x427594 PUSH %R15 |
0x427596 PUSH %R14 |
0x427598 PUSH %R13 |
0x42759a PUSH %R12 |
0x42759c PUSH %RBX |
0x42759d AND $-0x40,%RSP |
0x4275a1 ADD $-0x80,%RSP |
0x4275a5 MOV 0x28(%RDI),%EAX |
0x4275a8 MOV 0x2c(%RDI),%EDX |
0x4275ab MOV 0x20(%RDI),%EBX |
0x4275ae MOV 0x24(%RDI),%ECX |
0x4275b1 ADD $0x4,%EDX |
0x4275b4 LEA -0x1(%RAX),%R15D |
0x4275b8 LEA -0x1(%RBX),%ESI |
0x4275bb MOV %EDX,0x40(%RSP) |
0x4275bf MOV %ESI,0x3c(%RSP) |
0x4275c3 CMP %EDX,%R15D |
0x4275c6 JGE 427aa3 |
0x4275cc MOV %EDX,%EBX |
0x4275ce LEA 0x4(%RCX),%R14D |
0x4275d2 SUB %R15D,%EBX |
0x4275d5 CMP %R14D,%ESI |
0x4275d8 JGE 427aa3 |
0x4275de MOV %RDI,%R13 |
0x4275e1 MOV %R14D,%EDI |
0x4275e4 SUB %ESI,%EDI |
0x4275e6 MOV %EDI,0x44(%RSP) |
0x4275ea CALL 4046c0 <omp_get_num_threads@plt> |
0x4275ef MOV %EAX,%R12D |
0x4275f2 CALL 4045b0 <omp_get_thread_num@plt> |
0x4275f7 XOR %EDX,%EDX |
0x4275f9 MOV %EAX,%R8D |
0x4275fc MOV 0x44(%RSP),%EAX |
0x427600 IMUL %EBX,%EAX |
0x427603 DIV %R12D |
0x427606 MOV %EAX,%EDI |
0x427608 CMP %EDX,%R8D |
0x42760b JB 427ac4 |
0x427611 IMUL %EDI,%R8D |
0x427615 LEA (%R8,%RDX,1),%EBX |
0x427619 LEA (%RDI,%RBX,1),%R9D |
0x42761d MOV %R9D,0x38(%RSP) |
0x427622 CMP %R9D,%EBX |
0x427625 JAE 427aa3 |
0x42762b XOR %EDX,%EDX |
0x42762d MOV %EBX,%EAX |
0x42762f MOV 0x3c(%RSP),%R10D |
0x427634 MOV 0x8(%R13),%RCX |
0x427638 DIVL 0x44(%RSP) |
0x42763c MOV %RCX,0x28(%RSP) |
0x427641 ADD %EDX,%R10D |
0x427644 MOV %R14D,%EDX |
0x427647 LEA (%RAX,%R15,1),%R11D |
0x42764b MOV 0x10(%R13),%R14 |
0x42764f SUB %R10D,%EDX |
0x427652 MOV (%R13),%R15 |
0x427656 MOV 0x18(%R13),%R13 |
0x42765a MOV %R10D,0x74(%RSP) |
0x42765f CMP %EDX,%EDI |
0x427661 MOV %R14,0x20(%RSP) |
0x427666 MOVSXD %R11D,%RCX |
0x427669 CMOVBE %EDI,%EDX |
0x42766c MOV %R15,0x30(%RSP) |
0x427671 MOV %R13,0x18(%RSP) |
0x427676 LEA (%RBX,%RDX,1),%ESI |
0x427679 MOV %ESI,0x70(%RSP) |
0x42767d CMP %ESI,%EBX |
0x42767f JAE 427a83 |
0x427685 NOPL (%RAX) |
(116) 0x427688 MOV 0x28(%RSP),%R8 |
(116) 0x42768d MOV 0x30(%RSP),%R12 |
(116) 0x427692 MOV 0x20(%RSP),%RAX |
(116) 0x427697 MOV 0x18(%RSP),%R13 |
(116) 0x42769c MOV (%R8),%R9 |
(116) 0x42769f MOV 0x10(%R8),%RSI |
(116) 0x4276a3 LEA 0x1(%RCX),%R8 |
(116) 0x4276a7 MOV (%R12),%R11 |
(116) 0x4276ab MOV 0x10(%R13),%RDI |
(116) 0x4276af MOV %R8,0x48(%RSP) |
(116) 0x4276b4 IMUL %R9,%R8 |
(116) 0x4276b8 MOV 0x10(%R12),%R15 |
(116) 0x4276bd MOV 0x10(%RAX),%R14 |
(116) 0x4276c1 IMUL %RCX,%R11 |
(116) 0x4276c5 MOV %RDI,0x78(%RSP) |
(116) 0x4276ca MOV %R8,%R10 |
(116) 0x4276cd SUB %R9,%R10 |
(116) 0x4276d0 MOV (%RAX),%R9 |
(116) 0x4276d3 MOV %R11,0x50(%RSP) |
(116) 0x4276d8 MOV %R10,0x58(%RSP) |
(116) 0x4276dd IMUL %RCX,%R9 |
(116) 0x4276e1 IMUL (%R13),%RCX |
(116) 0x4276e6 MOV %R9,0x60(%RSP) |
(116) 0x4276eb MOV %RCX,0x68(%RSP) |
(116) 0x4276f0 LEA -0x1(%RDX),%ECX |
(116) 0x4276f3 CMP $0x6,%ECX |
(116) 0x4276f6 JBE 427ab8 |
(116) 0x4276fc MOVSXD 0x74(%RSP),%RAX |
(116) 0x427701 MOV 0x68(%RSP),%RDI |
(116) 0x427706 LEA (%R11,%RAX,1),%R11 |
(116) 0x42770a LEA (%R9,%RAX,1),%R9 |
(116) 0x42770e LEA (%R15,%R11,8),%RCX |
(116) 0x427712 LEA (%R14,%R9,8),%R11 |
(116) 0x427716 MOV %EDX,%R9D |
(116) 0x427719 SHR $0x3,%R9D |
(116) 0x42771d LEA (%R10,%RAX,1),%R10 |
(116) 0x427721 LEA (%R8,%RAX,1),%R13 |
(116) 0x427725 ADD %RDI,%RAX |
(116) 0x427728 SAL $0x6,%R9 |
(116) 0x42772c LEA (%RSI,%R10,8),%R12 |
(116) 0x427730 MOV 0x78(%RSP),%R10 |
(116) 0x427735 LEA (%RSI,%R13,8),%R13 |
(116) 0x427739 LEA -0x40(%R9),%RDI |
(116) 0x42773d SHR $0x6,%RDI |
(116) 0x427741 LEA (%R10,%RAX,8),%R10 |
(116) 0x427745 XOR %EAX,%EAX |
(116) 0x427747 INC %RDI |
(116) 0x42774a AND $0x3,%EDI |
(116) 0x42774d JE 4277f1 |
(116) 0x427753 CMP $0x1,%RDI |
(116) 0x427757 JE 4277b9 |
(116) 0x427759 CMP $0x2,%RDI |
(116) 0x42775d JE 42778a |
(116) 0x42775f VMOVUPD (%R13),%ZMM6 |
(116) 0x427766 MOV $0x40,%EAX |
(116) 0x42776b VADDPD (%RCX),%ZMM6,%ZMM0 |
(116) 0x427771 VSUBPD (%R12),%ZMM0,%ZMM1 |
(116) 0x427778 VMOVUPD %ZMM1,(%R11) |
(116) 0x42777e VMOVUPD (%RCX),%ZMM7 |
(116) 0x427784 VMOVUPD %ZMM7,(%R10) |
(116) 0x42778a VMOVUPD (%R13,%RAX,1),%ZMM2 |
(116) 0x427792 VADDPD (%RCX,%RAX,1),%ZMM2,%ZMM3 |
(116) 0x427799 VSUBPD (%R12,%RAX,1),%ZMM3,%ZMM4 |
(116) 0x4277a0 VMOVUPD %ZMM4,(%R11,%RAX,1) |
(116) 0x4277a7 VMOVUPD (%RCX,%RAX,1),%ZMM5 |
(116) 0x4277ae VMOVUPD %ZMM5,(%R10,%RAX,1) |
(116) 0x4277b5 ADD $0x40,%RAX |
(116) 0x4277b9 VMOVUPD (%R13,%RAX,1),%ZMM8 |
(116) 0x4277c1 VADDPD (%RCX,%RAX,1),%ZMM8,%ZMM9 |
(116) 0x4277c8 VSUBPD (%R12,%RAX,1),%ZMM9,%ZMM10 |
(116) 0x4277cf VMOVUPD %ZMM10,(%R11,%RAX,1) |
(116) 0x4277d6 VMOVUPD (%RCX,%RAX,1),%ZMM11 |
(116) 0x4277dd VMOVUPD %ZMM11,(%R10,%RAX,1) |
(116) 0x4277e4 ADD $0x40,%RAX |
(116) 0x4277e8 CMP %RAX,%R9 |
(116) 0x4277eb JE 4278bb |
(117) 0x4277f1 VMOVUPD (%R13,%RAX,1),%ZMM12 |
(117) 0x4277f9 VADDPD (%RCX,%RAX,1),%ZMM12,%ZMM13 |
(117) 0x427800 VSUBPD (%R12,%RAX,1),%ZMM13,%ZMM14 |
(117) 0x427807 VMOVUPD %ZMM14,(%R11,%RAX,1) |
(117) 0x42780e VMOVUPD (%RCX,%RAX,1),%ZMM15 |
(117) 0x427815 VMOVUPD %ZMM15,(%R10,%RAX,1) |
(117) 0x42781c VMOVUPD 0x40(%R13,%RAX,1),%ZMM6 |
(117) 0x427824 VADDPD 0x40(%RCX,%RAX,1),%ZMM6,%ZMM0 |
(117) 0x42782c VSUBPD 0x40(%R12,%RAX,1),%ZMM0,%ZMM1 |
(117) 0x427834 VMOVUPD %ZMM1,0x40(%R11,%RAX,1) |
(117) 0x42783c VMOVUPD 0x40(%RCX,%RAX,1),%ZMM7 |
(117) 0x427844 VMOVUPD %ZMM7,0x40(%R10,%RAX,1) |
(117) 0x42784c VMOVUPD 0x80(%R13,%RAX,1),%ZMM2 |
(117) 0x427854 VADDPD 0x80(%RCX,%RAX,1),%ZMM2,%ZMM3 |
(117) 0x42785c VSUBPD 0x80(%R12,%RAX,1),%ZMM3,%ZMM4 |
(117) 0x427864 VMOVUPD %ZMM4,0x80(%R11,%RAX,1) |
(117) 0x42786c VMOVUPD 0x80(%RCX,%RAX,1),%ZMM5 |
(117) 0x427874 VMOVUPD %ZMM5,0x80(%R10,%RAX,1) |
(117) 0x42787c VMOVUPD 0xc0(%R13,%RAX,1),%ZMM8 |
(117) 0x427884 VADDPD 0xc0(%RCX,%RAX,1),%ZMM8,%ZMM9 |
(117) 0x42788c VSUBPD 0xc0(%R12,%RAX,1),%ZMM9,%ZMM10 |
(117) 0x427894 VMOVUPD %ZMM10,0xc0(%R11,%RAX,1) |
(117) 0x42789c VMOVUPD 0xc0(%RCX,%RAX,1),%ZMM11 |
(117) 0x4278a4 VMOVUPD %ZMM11,0xc0(%R10,%RAX,1) |
(117) 0x4278ac ADD $0x100,%RAX |
(117) 0x4278b2 CMP %RAX,%R9 |
(117) 0x4278b5 JNE 4277f1 |
(116) 0x4278bb MOV 0x74(%RSP),%ECX |
(116) 0x4278bf MOV %EDX,%R12D |
(116) 0x4278c2 AND $-0x8,%R12D |
(116) 0x4278c6 ADD %R12D,%EBX |
(116) 0x4278c9 LEA (%R12,%RCX,1),%EDI |
(116) 0x4278cd TEST $0x7,%DL |
(116) 0x4278d0 JE 427a4a |
(116) 0x4278d6 SUB %R12D,%EDX |
(116) 0x4278d9 LEA -0x1(%RDX),%R13D |
(116) 0x4278dd CMP $0x2,%R13D |
(116) 0x4278e1 JBE 427958 |
(116) 0x4278e3 MOVSXD 0x74(%RSP),%RAX |
(116) 0x4278e8 MOV 0x50(%RSP),%R11 |
(116) 0x4278ed MOV 0x58(%RSP),%R13 |
(116) 0x4278f2 LEA (%R8,%RAX,1),%R9 |
(116) 0x4278f6 LEA (%R11,%RAX,1),%R10 |
(116) 0x4278fa ADD %R12,%R9 |
(116) 0x4278fd ADD %R12,%R10 |
(116) 0x427900 LEA (%R13,%RAX,1),%R11 |
(116) 0x427905 VMOVUPD (%RSI,%R9,8),%YMM12 |
(116) 0x42790b LEA (%R15,%R10,8),%RCX |
(116) 0x42790f ADD %R12,%R11 |
(116) 0x427912 MOV 0x60(%RSP),%R10 |
(116) 0x427917 VADDPD (%RCX),%YMM12,%YMM13 |
(116) 0x42791b LEA (%R10,%RAX,1),%R9 |
(116) 0x42791f ADD %R12,%R9 |
(116) 0x427922 VSUBPD (%RSI,%R11,8),%YMM13,%YMM14 |
(116) 0x427928 VMOVUPD %YMM14,(%R14,%R9,8) |
(116) 0x42792e VMOVUPD (%RCX),%YMM15 |
(116) 0x427932 MOV 0x68(%RSP),%RCX |
(116) 0x427937 ADD %RCX,%RAX |
(116) 0x42793a ADD %R12,%RAX |
(116) 0x42793d MOV 0x78(%RSP),%R12 |
(116) 0x427942 VMOVUPD %YMM15,(%R12,%RAX,8) |
(116) 0x427948 TEST $0x3,%DL |
(116) 0x42794b JE 427a4a |
(116) 0x427951 AND $-0x4,%EDX |
(116) 0x427954 ADD %EDX,%EBX |
(116) 0x427956 ADD %EDX,%EDI |
(116) 0x427958 MOVSXD %EDI,%RAX |
(116) 0x42795b MOV 0x50(%RSP),%R10 |
(116) 0x427960 MOV 0x58(%RSP),%R12 |
(116) 0x427965 LEA (%R8,%RAX,1),%R9 |
(116) 0x427969 MOV 0x60(%RSP),%R11 |
(116) 0x42796e VMOVSD (%RSI,%R9,8),%XMM6 |
(116) 0x427974 LEA (%R10,%RAX,1),%RDX |
(116) 0x427978 LEA 0x1(%RBX),%R9D |
(116) 0x42797c LEA (%R15,%RDX,8),%R13 |
(116) 0x427980 LEA (%R12,%RAX,1),%RDX |
(116) 0x427984 VADDSD (%R13),%XMM6,%XMM0 |
(116) 0x42798a LEA (%R11,%RAX,1),%RCX |
(116) 0x42798e VSUBSD (%RSI,%RDX,8),%XMM0,%XMM1 |
(116) 0x427993 MOV 0x70(%RSP),%EDX |
(116) 0x427997 VMOVSD %XMM1,(%R14,%RCX,8) |
(116) 0x42799d MOV 0x78(%RSP),%RCX |
(116) 0x4279a2 VMOVSD (%R13),%XMM7 |
(116) 0x4279a8 MOV 0x68(%RSP),%R13 |
(116) 0x4279ad ADD %R13,%RAX |
(116) 0x4279b0 VMOVSD %XMM7,(%RCX,%RAX,8) |
(116) 0x4279b5 LEA 0x1(%RDI),%EAX |
(116) 0x4279b8 CMP %EDX,%R9D |
(116) 0x4279bb JAE 427a4a |
(116) 0x4279c1 CLTQ |
(116) 0x4279c3 ADD $0x2,%EBX |
(116) 0x4279c6 ADD $0x2,%EDI |
(116) 0x4279c9 LEA (%R8,%RAX,1),%R9 |
(116) 0x4279cd LEA (%R10,%RAX,1),%RCX |
(116) 0x4279d1 VMOVSD (%RSI,%R9,8),%XMM2 |
(116) 0x4279d7 LEA (%R15,%RCX,8),%RDX |
(116) 0x4279db LEA (%R12,%RAX,1),%R9 |
(116) 0x4279df LEA (%R11,%RAX,1),%RCX |
(116) 0x4279e3 ADD %R13,%RAX |
(116) 0x4279e6 VADDSD (%RDX),%XMM2,%XMM3 |
(116) 0x4279ea VSUBSD (%RSI,%R9,8),%XMM3,%XMM4 |
(116) 0x4279f0 MOV %R13,%R9 |
(116) 0x4279f3 MOV 0x78(%RSP),%R13 |
(116) 0x4279f8 VMOVSD %XMM4,(%R14,%RCX,8) |
(116) 0x4279fe VMOVSD (%RDX),%XMM5 |
(116) 0x427a02 VMOVSD %XMM5,(%R13,%RAX,8) |
(116) 0x427a09 MOV 0x70(%RSP),%EAX |
(116) 0x427a0d CMP %EAX,%EBX |
(116) 0x427a0f JAE 427a4a |
(116) 0x427a11 MOVSXD %EDI,%RBX |
(116) 0x427a14 ADD %RBX,%R8 |
(116) 0x427a17 ADD %RBX,%R10 |
(116) 0x427a1a ADD %RBX,%R12 |
(116) 0x427a1d ADD %RBX,%R11 |
(116) 0x427a20 VMOVSD (%RSI,%R8,8),%XMM8 |
(116) 0x427a26 LEA (%R15,%R10,8),%R15 |
(116) 0x427a2a ADD %RBX,%R9 |
(116) 0x427a2d VADDSD (%R15),%XMM8,%XMM9 |
(116) 0x427a32 VSUBSD (%RSI,%R12,8),%XMM9,%XMM10 |
(116) 0x427a38 VMOVSD %XMM10,(%R14,%R11,8) |
(116) 0x427a3e VMOVSD (%R15),%XMM11 |
(116) 0x427a43 VMOVSD %XMM11,(%R13,%R9,8) |
(116) 0x427a4a MOV 0x48(%RSP),%RCX |
(116) 0x427a4f MOV 0x70(%RSP),%EBX |
(116) 0x427a53 LEA (%RCX),%ESI |
(116) 0x427a55 CMP %ESI,0x40(%RSP) |
(116) 0x427a59 JLE 427aa0 |
(116) 0x427a5b MOV 0x38(%RSP),%EDI |
(116) 0x427a5f MOV 0x44(%RSP),%EDX |
(116) 0x427a63 MOV 0x3c(%RSP),%R8D |
(116) 0x427a68 SUB %EBX,%EDI |
(116) 0x427a6a CMP %EDX,%EDI |
(116) 0x427a6c MOV %R8D,0x74(%RSP) |
(116) 0x427a71 CMOVBE %EDI,%EDX |
(116) 0x427a74 LEA (%RBX,%RDX,1),%ESI |
(116) 0x427a77 MOV %ESI,0x70(%RSP) |
(116) 0x427a7b CMP %ESI,%EBX |
(116) 0x427a7d JB 427688 |
(118) 0x427a83 LEA 0x1(%RCX),%RDI |
(118) 0x427a87 MOV %RDI,0x48(%RSP) |
(118) 0x427a8c MOV 0x48(%RSP),%RCX |
(118) 0x427a91 LEA (%RCX),%ESI |
(118) 0x427a93 CMP %ESI,0x40(%RSP) |
(118) 0x427a97 JG 427a5b |
0x427a99 NOPL (%RAX) |
0x427aa0 VZEROUPPER |
0x427aa3 LEA -0x28(%RBP),%RSP |
0x427aa7 POP %RBX |
0x427aa8 POP %R12 |
0x427aaa POP %R13 |
0x427aac POP %R14 |
0x427aae POP %R15 |
0x427ab0 POP %RBP |
0x427ab1 RET |
0x427ab2 NOPW (%RAX,%RAX,1) |
(116) 0x427ab8 MOV 0x74(%RSP),%EDI |
(116) 0x427abc XOR %R12D,%R12D |
(116) 0x427abf JMP 4278d6 |
0x427ac4 INC %EDI |
0x427ac6 XOR %EDX,%EDX |
0x427ac8 JMP 427611 |
0x427acd NOPL (%RAX) |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
○98.25 | gomp_thread_start | team.c:130 | libgomp.so.1.0.0 |
○1.75 | GOMP_parallel | libgomp.h:985 | libgomp.so.1.0.0 |
Path / |
Source file and lines | advec_cell.cpp:146-150 |
Module | exec |
nb instructions | 86 |
nb uops | 97 |
loop length | 291 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 11 |
micro-operation queue | 16.17 cycles |
front end | 16.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 7.20 | 8.00 | 6.00 | 6.00 | 9.00 | 7.27 | 7.20 | 9.00 | 9.00 | 9.00 | 7.33 | 6.00 |
cycles | 7.20 | 12.33 | 6.00 | 6.00 | 9.00 | 7.27 | 7.20 | 9.00 | 9.00 | 9.00 | 7.33 | 6.00 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 15.42-15.54 |
Stall cycles | 0.00 |
Front-end | 16.17 |
Dispatch | 12.33 |
DIV/SQRT | 12.00 |
Overall L1 | 16.17 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 12% |
all | 8% |
load | 8% |
store | 8% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 8% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD $-0x80,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x28(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RDI),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x24(%RDI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x4,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA -0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA -0x1(%RBX),%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ESI,0x3c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 427aa3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5.lto_priv.0+0x513> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x4(%RCX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 427aa3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5.lto_priv.0+0x513> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R14D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %ESI,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EDI,0x44(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x44(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 427ac4 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5.lto_priv.0+0x534> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %EDI,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RDI,%RBX,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R9D,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R9D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 427aa3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5.lto_priv.0+0x513> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EBX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x3c(%RSP),%R10D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%R13),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x44(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV %RCX,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA (%RAX,%R15,1),%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV 0x10(%R13),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %R10D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV (%R13),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%R13),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10D,0x74(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVSXD %R11D,%RCX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
CMOVBE %EDI,%EDX | 2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1-2 | 1 |
MOV %R15,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R13,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%RBX,%RDX,1),%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %ESI,0x70(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %ESI,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 427a83 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5.lto_priv.0+0x4f3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 427611 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5.lto_priv.0+0x81> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | advec_cell.cpp:146-150 |
Module | exec |
nb instructions | 86 |
nb uops | 97 |
loop length | 291 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 11 |
micro-operation queue | 16.17 cycles |
front end | 16.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 7.20 | 8.00 | 6.00 | 6.00 | 9.00 | 7.27 | 7.20 | 9.00 | 9.00 | 9.00 | 7.33 | 6.00 |
cycles | 7.20 | 12.33 | 6.00 | 6.00 | 9.00 | 7.27 | 7.20 | 9.00 | 9.00 | 9.00 | 7.33 | 6.00 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 15.42-15.54 |
Stall cycles | 0.00 |
Front-end | 16.17 |
Dispatch | 12.33 |
DIV/SQRT | 12.00 |
Overall L1 | 16.17 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 12% |
all | 8% |
load | 8% |
store | 8% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 8% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD $-0x80,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x28(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RDI),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x24(%RDI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x4,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA -0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA -0x1(%RBX),%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ESI,0x3c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 427aa3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5.lto_priv.0+0x513> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x4(%RCX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 427aa3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5.lto_priv.0+0x513> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R14D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %ESI,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EDI,0x44(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4046c0 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 4045b0 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x44(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 427ac4 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5.lto_priv.0+0x534> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %EDI,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RDI,%RBX,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R9D,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R9D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 427aa3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5.lto_priv.0+0x513> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EBX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x3c(%RSP),%R10D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%R13),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x44(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV %RCX,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA (%RAX,%R15,1),%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV 0x10(%R13),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %R10D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV (%R13),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%R13),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10D,0x74(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVSXD %R11D,%RCX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
CMOVBE %EDI,%EDX | 2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1-2 | 1 |
MOV %R15,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R13,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%RBX,%RDX,1),%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %ESI,0x70(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %ESI,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 427a83 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5.lto_priv.0+0x4f3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 427611 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5.lto_priv.0+0x81> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D | 1.3 | 0.97 |
▼Loop 118 - advec_cell.cpp:149-150 - exec– | 0 | 0 |
▼Loop 116 - advec_cell.cpp:149-150 - exec– | 0 | 0 |
○Loop 117 - advec_cell.cpp:149-150 - exec | 1.3 | 0.97 |