Loop Id: 119 | Module: exec | Source: advec_cell.cpp:159-202 [...] | Coverage: 0.01% |
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Loop Id: 119 | Module: exec | Source: advec_cell.cpp:159-202 [...] | Coverage: 0.01% |
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0x427bf8 CMP %EAX,%R13D |
0x427bfb LEA 0x3(%RCX),%EBX |
0x427bfe CMOVBE %R13D,%EAX |
0x427c02 MOV 0x2f8(%RSP),%R13D |
0x427c0a MOV %EAX,%R12D |
0x427c0d LEA (%R13,%RAX,1),%EAX |
0x427c12 MOV %EAX,0x2e4(%RSP) |
0x427c19 CMP %EAX,%R13D |
0x427c1c JAE 428630 |
0x427c22 MOV 0x40(%RSP),%R15 |
0x427c27 MOV 0x38(%RSP),%R14 |
0x427c2c MOV 0x20(%RSP),%R11 |
0x427c31 MOV 0x28(%RSP),%R13 |
0x427c36 MOV 0x10(%R15),%RSI |
0x427c3a MOV (%R14),%RDI |
0x427c3d MOV 0x30(%RSP),%R9 |
0x427c42 MOV 0x10(%R13),%RDX |
0x427c46 MOV 0x10(%R14),%R10 |
0x427c4a MOV 0x2e8(%RSP),%RAX |
0x427c52 MOV %RSI,0x2c8(%RSP) |
0x427c5a MOV 0x10(%R11),%RSI |
0x427c5e MOV 0x8(%R9),%R14 |
0x427c62 MOV %RDI,0x2d8(%RSP) |
0x427c6a MOV 0x18(%RSP),%RDI |
0x427c6f MOV (%R13),%R9 |
0x427c73 MOV %RDX,0x1c0(%RSP) |
0x427c7b INC %RAX |
0x427c7e MOV (%R15),%R8 |
0x427c81 MOV (%R11),%R11 |
0x427c84 MOV %RSI,0x2c0(%RSP) |
0x427c8c LEA (%R14,%RAX,8),%R15 |
0x427c90 MOV 0x10(%RDI),%RSI |
0x427c94 MOV (%RDI),%R13 |
0x427c97 MOV %RAX,0x2f0(%RSP) |
0x427c9f MOV 0x10(%RSP),%RDI |
0x427ca4 IMUL %RAX,%R8 |
0x427ca8 IMUL %RAX,%R11 |
0x427cac MOV 0x10(%RDI),%RDX |
0x427cb0 MOV %R8,0x68(%RSP) |
0x427cb5 MOV %RDX,0x78(%RSP) |
0x427cba MOV (%RDI),%RDX |
0x427cbd MOV %R11,0x60(%RSP) |
0x427cc2 IMUL %RAX,%RDX |
0x427cc6 LEA 0x1(%RCX),%EAX |
0x427cc9 MOVSXD %ECX,%RCX |
0x427ccc MOV %EAX,0x2e0(%RSP) |
0x427cd3 MOVSXD %EAX,%RDI |
0x427cd6 MOV %RCX,0x2d0(%RSP) |
0x427cde MOV %RDX,0x70(%RSP) |
0x427ce3 MOV 0x4c(%RSP),%EDX |
0x427ce7 LEA 0x2(%RDX),%EAX |
0x427cea LEA -0x1(%R12),%EDX |
0x427cef CMP %EBX,%EAX |
0x427cf1 MOV %EAX,0x5c(%RSP) |
0x427cf5 CMOVG %EBX,%EAX |
0x427cf8 MOVSXD %EAX,%RCX |
0x427cfb CMP $0xe,%EDX |
0x427cfe JBE 4282fb |
0x427d04 MOVSXD 0x2fc(%RSP),%RAX |
0x427d0c MOV 0x2c8(%RSP),%RDX |
0x427d14 VPBROADCASTQ %RCX,%ZMM22 |
0x427d1a VPBROADCASTQ %RDI,%ZMM29 |
0x427d20 KXNORB %K1,%K1,%K1 |
0x427d24 MOV 0x70(%RSP),%RCX |
0x427d29 VPBROADCASTD 0x2fc(%RSP),%ZMM0 |
0x427d34 VPBROADCASTQ %R9,%ZMM27 |
0x427d3a VPBROADCASTQ %R13,%ZMM30 |
0x427d40 ADD %RAX,%R8 |
0x427d43 MOV 0x2c0(%RSP),%RDI |
0x427d4b LEA (%R11,%RAX,1),%R11 |
0x427d4f VPBROADCASTQ 0x2d0(%RSP),%ZMM1 |
0x427d57 LEA (%RDX,%R8,8),%R8 |
0x427d5b MOV 0x78(%RSP),%RDX |
0x427d60 ADD %RCX,%RAX |
0x427d63 VPADDD 0x3ab93(%RIP),%ZMM0,%ZMM7 |
0x427d6d VPBROADCASTQ 0x2d8(%RSP),%ZMM2 |
0x427d75 LEA (%RDI,%R11,8),%RDI |
0x427d79 MOV %R12D,%R11D |
0x427d7c VPBROADCASTQ 0x2f0(%RSP),%ZMM25 |
0x427d84 LEA (%RDX,%RAX,8),%RCX |
0x427d88 MOV $0x10,%EDX |
0x427d8d SHR $0x4,%R11D |
0x427d91 VBROADCASTSD 0x3ace5(%RIP),%ZMM28 |
0x427d9b VPBROADCASTD %EDX,%ZMM3 |
0x427da1 VBROADCASTSD 0x3aced(%RIP),%ZMM31 |
0x427dab MOV 0x1c0(%RSP),%RDX |
0x427db3 VMOVDQA32 %ZMM7,0x280(%RSP) |
0x427dbb VMOVDQA64 %ZMM1,0x100(%RSP) |
0x427dc3 SAL $0x7,%R11 |
0x427dc7 XOR %EAX,%EAX |
0x427dc9 VXORPD %XMM26,%XMM26,%XMM26 |
0x427dcf VMOVDQA64 %ZMM2,0xc0(%RSP) |
0x427dd7 VMOVDQA32 %ZMM3,0x80(%RSP) |
0x427ddf NOP |
(121) 0x427de0 VMOVUPD (%R8,%RAX,1),%ZMM9 |
(121) 0x427de7 VMOVDQA64 0xc0(%RSP),%ZMM0 |
(121) 0x427def KMOVB %K1,%K4 |
(121) 0x427df3 KMOVB %K1,%K6 |
(121) 0x427df7 KMOVB %K1,%K7 |
(121) 0x427dfb KMOVB %K1,%K5 |
(121) 0x427dff VMOVUPD 0x40(%R8,%RAX,1),%ZMM10 |
(121) 0x427e07 VMOVDQA32 0x280(%RSP),%ZMM5 |
(121) 0x427e0f VCMPPD $0xe,%ZMM26,%ZMM9,%K3 |
(121) 0x427e16 VMOVDQA64 0x100(%RSP),%ZMM15 |
(121) 0x427e1e VCMPPD $0xe,%ZMM26,%ZMM10,%K2 |
(121) 0x427e25 VPADDD 0x80(%RSP),%ZMM5,%ZMM6 |
(121) 0x427e2d VPMOVSXDQ %YMM5,%ZMM7 |
(121) 0x427e33 VBROADCASTSD (%R15),%ZMM10 |
(121) 0x427e39 VEXTRACTI32X8 $0x1,%ZMM5,%YMM8 |
(121) 0x427e40 VPBLENDMQ %ZMM29,%ZMM25,%ZMM13{%K3} |
(121) 0x427e46 VMOVDQA32 %ZMM6,0x280(%RSP) |
(121) 0x427e4e VPBLENDMQ %ZMM29,%ZMM22,%ZMM11{%K3} |
(121) 0x427e54 VANDPD (%R8,%RAX,1),%ZMM28,%ZMM6 |
(121) 0x427e5b VXORPS %XMM20,%XMM20,%XMM20 |
(121) 0x427e61 VPMULLQ %ZMM0,%ZMM13,%ZMM20 |
(121) 0x427e67 VPBLENDMQ %ZMM29,%ZMM25,%ZMM12{%K2} |
(121) 0x427e6d VPBLENDMQ %ZMM29,%ZMM22,%ZMM4{%K2} |
(121) 0x427e73 VXORPS %XMM3,%XMM3,%XMM3 |
(121) 0x427e77 VPMULLQ %ZMM0,%ZMM12,%ZMM3 |
(121) 0x427e7d VGATHERQPD (%R14,%ZMM11,8),%ZMM0{%K6} |
(121) 0x427e84 VGATHERQPD (%R14,%ZMM4,8),%ZMM11{%K7} |
(121) 0x427e8b KMOVB %K1,%K6 |
(121) 0x427e8f KMOVB %K1,%K7 |
(121) 0x427e93 VPMOVSXDQ %YMM8,%ZMM2 |
(121) 0x427e99 VPBLENDMQ %ZMM15,%ZMM22,%ZMM16{%K3} |
(121) 0x427e9f VPBLENDMQ %ZMM15,%ZMM22,%ZMM15{%K2} |
(121) 0x427ea5 VANDPD 0x40(%R8,%RAX,1),%ZMM28,%ZMM8 |
(121) 0x427ead VPBLENDMQ %ZMM25,%ZMM29,%ZMM14{%K3} |
(121) 0x427eb3 VPBLENDMQ %ZMM25,%ZMM29,%ZMM18{%K2} |
(121) 0x427eb9 KMOVB %K1,%K3 |
(121) 0x427ebd KMOVB %K1,%K2 |
(121) 0x427ec1 VXORPS %XMM21,%XMM21,%XMM21 |
(121) 0x427ec7 VPMULLQ %ZMM27,%ZMM12,%ZMM21 |
(121) 0x427ecd VXORPS %XMM17,%XMM17,%XMM17 |
(121) 0x427ed3 VPMULLQ %ZMM18,%ZMM27,%ZMM17 |
(121) 0x427ed9 VPADDQ %ZMM7,%ZMM20,%ZMM20 |
(121) 0x427edf VPMULLQ %ZMM30,%ZMM12,%ZMM12 |
(121) 0x427ee5 VGATHERQPD (%R10,%ZMM20,8),%ZMM1{%K4} |
(121) 0x427eec VPADDQ %ZMM2,%ZMM3,%ZMM23 |
(121) 0x427ef2 KMOVB %K1,%K4 |
(121) 0x427ef6 VDIVPD %ZMM1,%ZMM6,%ZMM9 |
(121) 0x427efc VDIVPD %ZMM0,%ZMM10,%ZMM1 |
(121) 0x427f02 VDIVPD %ZMM11,%ZMM10,%ZMM6 |
(121) 0x427f08 VXORPS %XMM10,%XMM10,%XMM10 |
(121) 0x427f0d VPMULLQ %ZMM27,%ZMM13,%ZMM10 |
(121) 0x427f13 VADDPD %ZMM31,%ZMM9,%ZMM4 |
(121) 0x427f19 VGATHERQPD (%R10,%ZMM23,8),%ZMM5{%K5} |
(121) 0x427f20 VXORPS %XMM11,%XMM11,%XMM11 |
(121) 0x427f25 VPMULLQ %ZMM27,%ZMM16,%ZMM11 |
(121) 0x427f2b VDIVPD %ZMM5,%ZMM8,%ZMM8 |
(121) 0x427f31 KMOVB %K1,%K5 |
(121) 0x427f35 VPMULLQ %ZMM30,%ZMM13,%ZMM13 |
(121) 0x427f3b VADDPD %ZMM31,%ZMM8,%ZMM5 |
(121) 0x427f41 VPADDQ %ZMM2,%ZMM21,%ZMM21 |
(121) 0x427f47 VPMULLQ %ZMM30,%ZMM16,%ZMM16 |
(121) 0x427f4d VMULPD %ZMM1,%ZMM4,%ZMM3 |
(121) 0x427f53 VMULPD %ZMM6,%ZMM5,%ZMM0 |
(121) 0x427f59 VBROADCASTSD 0x3ab2d(%RIP),%ZMM6 |
(121) 0x427f63 VPADDQ %ZMM7,%ZMM10,%ZMM24 |
(121) 0x427f69 VXORPS %XMM10,%XMM10,%XMM10 |
(121) 0x427f6e VPMULLQ %ZMM27,%ZMM15,%ZMM10 |
(121) 0x427f74 VSUBPD %ZMM9,%ZMM6,%ZMM1 |
(121) 0x427f7a VSUBPD %ZMM8,%ZMM6,%ZMM19 |
(121) 0x427f80 VPMULLQ %ZMM30,%ZMM15,%ZMM15 |
(121) 0x427f86 VSUBPD %ZMM8,%ZMM31,%ZMM8 |
(121) 0x427f8c VSUBPD %ZMM9,%ZMM31,%ZMM9 |
(121) 0x427f92 VMOVAPD %ZMM3,0x300(%RSP) |
(121) 0x427f9a VPADDQ %ZMM7,%ZMM11,%ZMM3 |
(121) 0x427fa0 VGATHERQPD (%RDX,%ZMM3,8),%ZMM4{%K4} |
(121) 0x427fa7 VGATHERQPD (%RDX,%ZMM24,8),%ZMM6{%K3} |
(121) 0x427fae VGATHERQPD (%RDX,%ZMM21,8),%ZMM5{%K2} |
(121) 0x427fb5 VPADDQ %ZMM2,%ZMM10,%ZMM11 |
(121) 0x427fbb VXORPS %XMM10,%XMM10,%XMM10 |
(121) 0x427fc0 VPMULLQ %ZMM27,%ZMM14,%ZMM10 |
(121) 0x427fc6 VSUBPD %ZMM4,%ZMM6,%ZMM4 |
(121) 0x427fcc VGATHERQPD (%RDX,%ZMM11,8),%ZMM3{%K5} |
(121) 0x427fd3 VPMULLQ %ZMM30,%ZMM14,%ZMM14 |
(121) 0x427fd9 VSUBPD %ZMM3,%ZMM5,%ZMM3 |
(121) 0x427fdf VPADDQ %ZMM7,%ZMM10,%ZMM11 |
(121) 0x427fe5 VGATHERQPD (%RDX,%ZMM11,8),%ZMM10{%K6} |
(121) 0x427fec VMOVDQA64 %ZMM18,0x240(%RSP) |
(121) 0x427ff4 VPADDQ %ZMM2,%ZMM17,%ZMM18 |
(121) 0x427ffa KMOVB %K1,%K6 |
(121) 0x427ffe VGATHERQPD (%RDX,%ZMM18,8),%ZMM11{%K7} |
(121) 0x428005 VSUBPD %ZMM6,%ZMM10,%ZMM10 |
(121) 0x42800b KMOVB %K1,%K7 |
(121) 0x42800f VSUBPD %ZMM5,%ZMM11,%ZMM11 |
(121) 0x428015 VCMPPD $0x2,%ZMM26,%ZMM10,%K3 |
(121) 0x42801c VCMPPD $0x2,%ZMM26,%ZMM11,%K2 |
(121) 0x428023 VBLENDMPD 0x3a913(%RIP),%ZMM31,%ZMM17{%K3} |
(121) 0x42802d KMOVB %K1,%K3 |
(121) 0x428031 VBLENDMPD 0x3a905(%RIP),%ZMM31,%ZMM18{%K2} |
(121) 0x42803b VMOVAPD %ZMM17,0x200(%RSP) |
(121) 0x428043 KMOVB %K1,%K2 |
(121) 0x428047 VMULPD %ZMM10,%ZMM4,%ZMM17 |
(121) 0x42804d VMOVAPD %ZMM18,0x1c0(%RSP) |
(121) 0x428055 VANDPD %ZMM28,%ZMM10,%ZMM10 |
(121) 0x42805b VANDPD %ZMM28,%ZMM4,%ZMM4 |
(121) 0x428061 VMULPD %ZMM11,%ZMM3,%ZMM18 |
(121) 0x428067 VANDPD %ZMM28,%ZMM11,%ZMM11 |
(121) 0x42806d VANDPD %ZMM28,%ZMM3,%ZMM3 |
(121) 0x428073 VMULPD 0x1c0(%RSP),%ZMM8,%ZMM8 |
(121) 0x42807b VMOVAPD %ZMM17,0x180(%RSP) |
(121) 0x428083 VMULPD %ZMM10,%ZMM1,%ZMM17 |
(121) 0x428089 VMOVAPD %ZMM18,0x140(%RSP) |
(121) 0x428091 VMULPD %ZMM11,%ZMM19,%ZMM18 |
(121) 0x428097 VFMADD231PD 0x300(%RSP),%ZMM4,%ZMM17 |
(121) 0x42809f VMINPD %ZMM10,%ZMM4,%ZMM4 |
(121) 0x4280a5 VFMADD231PD %ZMM3,%ZMM0,%ZMM18 |
(121) 0x4280ab VMINPD %ZMM11,%ZMM3,%ZMM3 |
(121) 0x4280b1 VMULPD 0x3a8c5(%RIP),%ZMM18,%ZMM18 |
(121) 0x4280bb VMOVAPD 0x180(%RSP),%ZMM11 |
(121) 0x4280c3 VMULPD 0x3a8b3(%RIP),%ZMM17,%ZMM17 |
(121) 0x4280cd VCMPPD $0xe,%ZMM26,%ZMM11,%K4 |
(121) 0x4280d4 VMULPD 0x200(%RSP),%ZMM9,%ZMM11 |
(121) 0x4280dc VMOVAPD 0x140(%RSP),%ZMM9 |
(121) 0x4280e4 VMINPD %ZMM3,%ZMM18,%ZMM3 |
(121) 0x4280ea VCMPPD $0xe,%ZMM26,%ZMM9,%K5 |
(121) 0x4280f1 VMINPD %ZMM4,%ZMM17,%ZMM10 |
(121) 0x4280f7 VFMADD231PD %ZMM3,%ZMM8,%ZMM5{%K5} |
(121) 0x4280fd VPADDQ %ZMM7,%ZMM13,%ZMM3 |
(121) 0x428103 KMOVB %K1,%K5 |
(121) 0x428107 VFMADD231PD %ZMM10,%ZMM11,%ZMM6{%K4} |
(121) 0x42810d VPADDQ %ZMM2,%ZMM12,%ZMM11 |
(121) 0x428113 VPADDQ %ZMM2,%ZMM15,%ZMM12 |
(121) 0x428119 KMOVB %K1,%K4 |
(121) 0x42811d VMULPD 0x40(%R8,%RAX,1),%ZMM5,%ZMM5 |
(121) 0x428125 VMULPD (%R8,%RAX,1),%ZMM6,%ZMM6 |
(121) 0x42812c VMOVUPD %ZMM5,0x40(%RDI,%RAX,1) |
(121) 0x428134 VMOVUPD %ZMM6,(%RDI,%RAX,1) |
(121) 0x42813b VGATHERQPD (%RSI,%ZMM11,8),%ZMM13{%K5} |
(121) 0x428142 VGATHERQPD (%R10,%ZMM23,8),%ZMM10{%K2} |
(121) 0x428149 VGATHERQPD (%RDX,%ZMM21,8),%ZMM8{%K7} |
(121) 0x428150 KMOVB %K1,%K7 |
(121) 0x428154 KMOVB %K1,%K2 |
(121) 0x428158 VGATHERQPD (%RSI,%ZMM12,8),%ZMM11{%K7} |
(121) 0x42815f VPADDQ %ZMM7,%ZMM16,%ZMM23 |
(121) 0x428165 VXORPS %XMM12,%XMM12,%XMM12 |
(121) 0x42816a VPMULLQ 0x240(%RSP),%ZMM30,%ZMM12 |
(121) 0x428172 VPADDQ %ZMM7,%ZMM14,%ZMM7 |
(121) 0x428178 VPADDQ %ZMM2,%ZMM12,%ZMM2 |
(121) 0x42817e VGATHERQPD (%R10,%ZMM20,8),%ZMM9{%K3} |
(121) 0x428185 VGATHERQPD (%RDX,%ZMM24,8),%ZMM4{%K6} |
(121) 0x42818c KMOVB %K1,%K3 |
(121) 0x428190 KMOVB %K1,%K6 |
(121) 0x428194 VGATHERQPD (%RSI,%ZMM3,8),%ZMM20{%K4} |
(121) 0x42819b VGATHERQPD (%RSI,%ZMM7,8),%ZMM15{%K3} |
(121) 0x4281a2 VGATHERQPD (%RSI,%ZMM2,8),%ZMM14{%K2} |
(121) 0x4281a9 VGATHERQPD (%RSI,%ZMM23,8),%ZMM3{%K6} |
(121) 0x4281b0 VSUBPD %ZMM13,%ZMM14,%ZMM7 |
(121) 0x4281b6 VSUBPD %ZMM20,%ZMM15,%ZMM2 |
(121) 0x4281bc VSUBPD %ZMM3,%ZMM20,%ZMM3 |
(121) 0x4281c2 VSUBPD %ZMM11,%ZMM13,%ZMM11 |
(121) 0x4281c8 VMULPD %ZMM9,%ZMM4,%ZMM4 |
(121) 0x4281ce VMULPD %ZMM10,%ZMM8,%ZMM8 |
(121) 0x4281d4 VCMPPD $0x2,%ZMM26,%ZMM2,%K4 |
(121) 0x4281db VCMPPD $0x2,%ZMM26,%ZMM7,%K5 |
(121) 0x4281e2 VMULPD %ZMM2,%ZMM3,%ZMM15 |
(121) 0x4281e8 VANDPD %ZMM28,%ZMM2,%ZMM2 |
(121) 0x4281ee VANDPD %ZMM28,%ZMM3,%ZMM3 |
(121) 0x4281f4 VMULPD %ZMM7,%ZMM11,%ZMM12 |
(121) 0x4281fa VANDPD %ZMM28,%ZMM7,%ZMM7 |
(121) 0x428200 VANDPD %ZMM28,%ZMM11,%ZMM11 |
(121) 0x428206 VMULPD %ZMM7,%ZMM19,%ZMM19 |
(121) 0x42820c VBLENDMPD 0x3a72a(%RIP),%ZMM31,%ZMM14{%K4} |
(121) 0x428216 VBLENDMPD 0x3a720(%RIP),%ZMM31,%ZMM24{%K5} |
(121) 0x428220 VMULPD %ZMM2,%ZMM1,%ZMM1 |
(121) 0x428226 VCMPPD $0xe,%ZMM26,%ZMM15,%K6 |
(121) 0x42822d VCMPPD $0xe,%ZMM26,%ZMM12,%K7 |
(121) 0x428234 VANDPD %ZMM28,%ZMM5,%ZMM12 |
(121) 0x42823a VFMADD132PD %ZMM11,%ZMM19,%ZMM0 |
(121) 0x428240 VMINPD %ZMM7,%ZMM11,%ZMM11 |
(121) 0x428246 VDIVPD %ZMM8,%ZMM12,%ZMM10 |
(121) 0x42824c VFMADD231PD 0x300(%RSP),%ZMM3,%ZMM1 |
(121) 0x428254 VMINPD %ZMM2,%ZMM3,%ZMM3 |
(121) 0x42825a VMULPD 0x3a71c(%RIP),%ZMM0,%ZMM0 |
(121) 0x428264 VMULPD 0x3a712(%RIP),%ZMM1,%ZMM15 |
(121) 0x42826e VANDPD %ZMM28,%ZMM6,%ZMM1 |
(121) 0x428274 VDIVPD %ZMM4,%ZMM1,%ZMM9 |
(121) 0x42827a VMINPD %ZMM11,%ZMM0,%ZMM7 |
(121) 0x428280 VSUBPD %ZMM9,%ZMM31,%ZMM11 |
(121) 0x428286 VMINPD %ZMM3,%ZMM15,%ZMM2 |
(121) 0x42828c VMULPD %ZMM24,%ZMM7,%ZMM0 |
(121) 0x428292 VSUBPD %ZMM10,%ZMM31,%ZMM7 |
(121) 0x428298 VMULPD %ZMM14,%ZMM2,%ZMM14 |
(121) 0x42829e VFMADD231PD %ZMM7,%ZMM0,%ZMM13{%K7} |
(121) 0x4282a4 VFMADD231PD %ZMM11,%ZMM14,%ZMM20{%K6} |
(121) 0x4282aa VMULPD %ZMM6,%ZMM20,%ZMM21 |
(121) 0x4282b0 VMULPD %ZMM5,%ZMM13,%ZMM6 |
(121) 0x4282b6 VMOVUPD %ZMM21,(%RCX,%RAX,1) |
(121) 0x4282bd VMOVUPD %ZMM6,0x40(%RCX,%RAX,1) |
(121) 0x4282c5 SUB $-0x80,%RAX |
(121) 0x4282c9 CMP %R11,%RAX |
(121) 0x4282cc JNE 427de0 |
0x4282d2 MOV %R12D,%R8D |
0x4282d5 MOV %RDX,0x1c0(%RSP) |
0x4282dd AND $-0x10,%R8D |
0x4282e1 ADD %R8D,0x2f8(%RSP) |
0x4282e9 ADD %R8D,0x2fc(%RSP) |
0x4282f1 AND $0xf,%R12D |
0x4282f5 JE 4285d7 |
0x4282fb MOV 0x2c8(%RSP),%R12 |
0x428303 MOV 0x68(%RSP),%RDI |
0x428308 VXORPD %XMM5,%XMM5,%XMM5 |
0x42830c MOV 0x2c0(%RSP),%R11 |
0x428314 MOV 0x60(%RSP),%RDX |
0x428319 LEA (%R12,%RDI,8),%RCX |
0x42831d MOV 0x78(%RSP),%R12 |
0x428322 MOV 0x70(%RSP),%RDI |
0x428327 LEA (%R11,%RDX,8),%R8 |
0x42832b MOVSXD 0x2fc(%RSP),%RAX |
0x428333 MOV 0x1c0(%RSP),%RDX |
0x42833b MOV %RCX,0x280(%RSP) |
0x428343 LEA (%R12,%RDI,8),%RCX |
0x428347 MOV %R8,0x240(%RSP) |
0x42834f VMOVSD 0x3a5e9(%RIP),%XMM8 |
0x428357 MOV %RCX,0x300(%RSP) |
0x42835f MOV 0x5c(%RSP),%ECX |
0x428363 MOV %EBX,0x1c0(%RSP) |
0x42836a CMP %EBX,%ECX |
0x42836c CMOVG %EBX,%ECX |
0x42836f MOVSXD %ECX,%R11 |
0x428372 MOV %R11,0x200(%RSP) |
0x42837a JMP 428563 |
(120) 0x428380 MOV 0x2e8(%RSP),%RCX |
(120) 0x428388 MOV 0x2d0(%RSP),%R8 |
(120) 0x428390 MOV 0x2f0(%RSP),%RDI |
(120) 0x428398 MOV %RCX,%R12 |
(120) 0x42839b MOV 0x2d8(%RSP),%R11 |
(120) 0x4283a3 VMOVSD (%R15),%XMM3 |
(120) 0x4283a8 VANDPD 0x3a6d0(%RIP),%XMM13,%XMM0 |
(120) 0x4283b0 VMOVSD 0x3a6d8(%RIP),%XMM1 |
(120) 0x4283b8 IMUL %RCX,%R11 |
(120) 0x4283bc VDIVSD (%R14,%R12,8),%XMM3,%XMM2 |
(120) 0x4283c2 MOV %R9,%R12 |
(120) 0x4283c5 VMOVSD 0x3a6cb(%RIP),%XMM6 |
(120) 0x4283cd IMUL %RCX,%R12 |
(120) 0x4283d1 ADD %RAX,%R11 |
(120) 0x4283d4 LEA (%R10,%R11,8),%RBX |
(120) 0x4283d8 MOV %R9,%R11 |
(120) 0x4283db ADD %RAX,%R12 |
(120) 0x4283de IMUL %R8,%R11 |
(120) 0x4283e2 LEA (%RDX,%R12,8),%R12 |
(120) 0x4283e6 VDIVSD (%RBX),%XMM0,%XMM15 |
(120) 0x4283ea VMOVSD (%R12),%XMM11 |
(120) 0x4283f0 VADDSD 0x3a6a0(%RIP),%XMM15,%XMM14 |
(120) 0x4283f8 VSUBSD %XMM15,%XMM1,%XMM4 |
(120) 0x4283fd ADD %RAX,%R11 |
(120) 0x428400 VSUBSD (%RDX,%R11,8),%XMM11,%XMM7 |
(120) 0x428406 VMULSD %XMM14,%XMM2,%XMM12 |
(120) 0x42840b MOV %R9,%R11 |
(120) 0x42840e IMUL %RDI,%R11 |
(120) 0x428412 ADD %RAX,%R11 |
(120) 0x428415 VMOVSD (%RDX,%R11,8),%XMM9 |
(120) 0x42841b VSUBSD %XMM11,%XMM9,%XMM0 |
(120) 0x428420 VMULSD %XMM0,%XMM7,%XMM2 |
(120) 0x428424 VCMPSD $0x6,%XMM5,%XMM0,%XMM10 |
(120) 0x428429 VBLENDVPD %XMM10,%XMM6,%XMM8,%XMM3 |
(120) 0x42842f VCOMISD %XMM5,%XMM2 |
(120) 0x428433 JBE 428476 |
(120) 0x428435 VANDPD 0x3a643(%RIP),%XMM0,%XMM1 |
(120) 0x42843d VANDPD 0x3a63b(%RIP),%XMM7,%XMM14 |
(120) 0x428445 VMOVSD 0x3a64b(%RIP),%XMM6 |
(120) 0x42844d VMULSD %XMM4,%XMM1,%XMM7 |
(120) 0x428451 VMINSD %XMM14,%XMM1,%XMM9 |
(120) 0x428456 VSUBSD %XMM15,%XMM6,%XMM15 |
(120) 0x42845b VFMADD231SD %XMM12,%XMM14,%XMM7 |
(120) 0x428460 VMULSD 0x3a518(%RIP),%XMM7,%XMM0 |
(120) 0x428468 VMINSD %XMM0,%XMM9,%XMM10 |
(120) 0x42846c VMULSD %XMM15,%XMM10,%XMM2 |
(120) 0x428471 VFMADD231SD %XMM3,%XMM2,%XMM11 |
(120) 0x428476 VMULSD %XMM13,%XMM11,%XMM13 |
(120) 0x42847b IMUL %R13,%RCX |
(120) 0x42847f MOV 0x240(%RSP),%R11 |
(120) 0x428487 VMOVSD 0x3a609(%RIP),%XMM10 |
(120) 0x42848f IMUL %R13,%RDI |
(120) 0x428493 IMUL %R13,%R8 |
(120) 0x428497 ADD %RAX,%RCX |
(120) 0x42849a ADD %RAX,%RDI |
(120) 0x42849d VMOVSD %XMM13,(%R11,%RAX,8) |
(120) 0x4284a3 ADD %RAX,%R8 |
(120) 0x4284a6 VMOVSD (%RSI,%RCX,8),%XMM14 |
(120) 0x4284ab VMOVSD (%RSI,%RDI,8),%XMM7 |
(120) 0x4284b0 VMOVSD (%R12),%XMM11 |
(120) 0x4284b6 VMOVSD (%RBX),%XMM3 |
(120) 0x4284ba VSUBSD %XMM14,%XMM7,%XMM0 |
(120) 0x4284bf VSUBSD (%RSI,%R8,8),%XMM14,%XMM1 |
(120) 0x4284c5 VMULSD %XMM1,%XMM0,%XMM15 |
(120) 0x4284c9 VCMPSD $0x6,%XMM5,%XMM0,%XMM9 |
(120) 0x4284ce VBLENDVPD %XMM9,%XMM10,%XMM8,%XMM6 |
(120) 0x4284d4 VCOMISD %XMM5,%XMM15 |
(120) 0x4284d8 JBE 4285b8 |
(120) 0x4284de VMULSD %XMM11,%XMM3,%XMM11 |
(120) 0x4284e3 VANDPD 0x3a595(%RIP),%XMM13,%XMM2 |
(120) 0x4284eb VANDPD 0x3a58d(%RIP),%XMM0,%XMM7 |
(120) 0x4284f3 VANDPD 0x3a585(%RIP),%XMM1,%XMM1 |
(120) 0x4284fb VMOVSD 0x3a595(%RIP),%XMM3 |
(120) 0x428503 VMULSD %XMM4,%XMM7,%XMM4 |
(120) 0x428507 MOV 0x300(%RSP),%RDI |
(120) 0x42850f VMINSD %XMM1,%XMM7,%XMM10 |
(120) 0x428513 VDIVSD %XMM11,%XMM2,%XMM0 |
(120) 0x428518 VFMADD231SD %XMM12,%XMM1,%XMM4 |
(120) 0x42851d VMULSD 0x3a45b(%RIP),%XMM4,%XMM15 |
(120) 0x428525 VMINSD %XMM15,%XMM10,%XMM12 |
(120) 0x42852a VSUBSD %XMM0,%XMM3,%XMM9 |
(120) 0x42852e VMULSD %XMM12,%XMM9,%XMM1 |
(120) 0x428533 VFMADD132SD %XMM6,%XMM14,%XMM1 |
(120) 0x428538 VMULSD %XMM1,%XMM13,%XMM13 |
(120) 0x42853c VMOVSD %XMM13,(%RDI,%RAX,8) |
(120) 0x428541 MOV 0x2f8(%RSP),%ECX |
(120) 0x428548 MOV 0x2fc(%RSP),%EBX |
(120) 0x42854f INC %RAX |
(120) 0x428552 MOV 0x2e4(%RSP),%R12D |
(120) 0x42855a SUB %EBX,%ECX |
(120) 0x42855c ADD %EAX,%ECX |
(120) 0x42855e CMP %R12D,%ECX |
(120) 0x428561 JAE 4285d0 |
(120) 0x428563 MOV 0x280(%RSP),%RBX |
(120) 0x42856b VMOVSD (%RBX,%RAX,8),%XMM13 |
(120) 0x428570 VCOMISD %XMM5,%XMM13 |
(120) 0x428574 JA 428380 |
(120) 0x42857a MOV 0x200(%RSP),%R8 |
(120) 0x428582 MOV 0x2e8(%RSP),%RDI |
(120) 0x42858a MOV 0x2f0(%RSP),%RCX |
(120) 0x428592 MOV %R8,%R12 |
(120) 0x428595 JMP 42839b |
(120) 0x4285b8 VMULSD %XMM13,%XMM14,%XMM12 |
(120) 0x4285bd MOV 0x300(%RSP),%R8 |
(120) 0x4285c5 VMOVSD %XMM12,(%R8,%RAX,8) |
(120) 0x4285cb JMP 428541 |
0x4285d0 MOV 0x1c0(%RSP),%EBX |
0x4285d7 MOV 0x2e4(%RSP),%EAX |
0x4285de MOV %EAX,0x2f8(%RSP) |
0x4285e5 MOV 0x2f0(%RSP),%RDX |
0x4285ed MOV 0x2e0(%RSP),%ECX |
0x4285f4 MOV %RDX,0x2e8(%RSP) |
0x4285fc CMP %EBX,0x54(%RSP) |
0x428600 JLE 4285a0 |
0x428602 MOV 0x48(%RSP),%R13D |
0x428607 MOV 0x2f8(%RSP),%ESI |
0x42860e MOV 0x50(%RSP),%R9D |
0x428613 MOV 0x58(%RSP),%EAX |
0x428617 SUB %ESI,%R13D |
0x42861a MOV %R9D,0x2fc(%RSP) |
0x428622 JMP 427bf8 |
0x428630 MOV 0x2e8(%RSP),%R11 |
0x428638 LEA 0x1(%RCX),%EDX |
0x42863b MOV %EDX,0x2e0(%RSP) |
0x428642 INC %R11 |
0x428645 MOV %R11,0x2f0(%RSP) |
0x42864d JMP 4285e5 |
/software/compilers/gcc/gcc-13.1.0-full+isl+binutils/include/c++/13.1.0/bits/stl_algobase.h: 238 - 238 |
-------------------------------------------------------------------------------- |
238: if (__b < __a) |
/scratch_na/users/xoserete/qaas_runs/171-415-4687/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 46 - 69 |
-------------------------------------------------------------------------------- |
46: T &operator[](size_t i) const { return data[i]; } |
[...] |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
/scratch_na/users/xoserete/qaas_runs/171-415-4687/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp: 159 - 202 |
-------------------------------------------------------------------------------- |
159: for (int i = (x_min + 1); i < (x_max + 2); i++) |
160: ({ |
161: int upwind, donor, downwind, dif; |
162: double sigmat, sigma3, sigma4, sigmav, sigmam, diffuw, diffdw, limiter, wind; |
163: if (vol_flux_y(i, j) > 0.0) { |
[...] |
169: upwind = std::min(j + 1, y_max + 2); |
170: donor = j; |
171: downwind = j - 1; |
172: dif = upwind; |
173: } |
174: sigmat = std::fabs(vol_flux_y(i, j)) / pre_vol(i, donor); |
175: sigma3 = (1.0 + sigmat) * (vertexdy[j] / vertexdy[dif]); |
176: sigma4 = 2.0 - sigmat; |
177: sigmav = sigmat; |
178: diffuw = density1(i, donor) - density1(i, upwind); |
179: diffdw = density1(i, downwind) - density1(i, donor); |
180: wind = 1.0; |
181: if (diffdw <= 0.0) wind = -1.0; |
182: if (diffuw * diffdw > 0.0) { |
183: limiter = (1.0 - sigmav) * wind * |
184: std::fmin(std::fmin(std::fabs(diffuw), std::fabs(diffdw)), |
185: one_by_six * (sigma3 * std::fabs(diffuw) + sigma4 * std::fabs(diffdw))); |
186: } else { |
187: limiter = 0.0; |
188: } |
189: mass_flux_y(i, j) = vol_flux_y(i, j) * (density1(i, donor) + limiter); |
190: sigmam = std::fabs(mass_flux_y(i, j)) / (density1(i, donor) * pre_vol(i, donor)); |
191: diffuw = energy1(i, donor) - energy1(i, upwind); |
192: diffdw = energy1(i, downwind) - energy1(i, donor); |
193: wind = 1.0; |
194: if (diffdw <= 0.0) wind = -1.0; |
195: if (diffuw * diffdw > 0.0) { |
196: limiter = (1.0 - sigmam) * wind * |
197: std::fmin(std::fmin(std::fabs(diffuw), std::fabs(diffdw)), |
198: one_by_six * (sigma3 * std::fabs(diffuw) + sigma4 * std::fabs(diffdw))); |
199: } else { |
200: limiter = 0.0; |
201: } |
202: ener_flux(i, j) = mass_flux_y(i, j) * (energy1(i, donor) + limiter); |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
○99.28 | gomp_thread_start | team.c:130 | libgomp.so.1.0.0 |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 4.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 1.45 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.28 |
Bottlenecks | micro-operation queue, |
Function | advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D |
Source | stl_algobase.h:238-238,context.h:46-46,context.h:69-69,advec_cell.cpp:159-159,advec_cell.cpp:163-163,advec_cell.cpp:169-171,advec_cell.cpp:174-175,advec_cell.cpp:178-180,advec_cell.cpp:202-202 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 24.67 |
CQA cycles if no scalar integer | 6.17 |
CQA cycles if FP arith vectorized | 24.67 |
CQA cycles if fully vectorized | 17.02 |
Front-end cycles | 24.67 |
DIV/SQRT cycles | 8.80 |
P0 cycles | 8.87 |
P1 cycles | 19.33 |
P2 cycles | 19.33 |
P3 cycles | 15.00 |
P4 cycles | 8.80 |
P5 cycles | 8.80 |
P6 cycles | 15.00 |
P7 cycles | 15.00 |
P8 cycles | 15.00 |
P9 cycles | 8.73 |
P10 cycles | 19.33 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | 25.12 |
Stall cycles (UFS) | 0.00 |
Nb insns | 145.00 |
Nb uops | 148.00 |
Nb loads | 58.00 |
Nb stores | 30.00 |
Nb stack references | 35.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 35.84 |
Bytes prefetched | 0.00 |
Bytes loaded | 456.00 |
Bytes stored | 428.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 12.28 |
Vectorization ratio load | 5.88 |
Vectorization ratio store | 13.33 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 10.53 |
Vector-efficiency ratio all | 18.53 |
Vector-efficiency ratio load | 15.44 |
Vector-efficiency ratio store | 22.29 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 100.00 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 11.18 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 4.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 1.45 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.28 |
Bottlenecks | micro-operation queue, |
Function | advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D |
Source | stl_algobase.h:238-238,context.h:46-46,context.h:69-69,advec_cell.cpp:159-159,advec_cell.cpp:163-163,advec_cell.cpp:169-171,advec_cell.cpp:174-175,advec_cell.cpp:178-180,advec_cell.cpp:202-202 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 24.67 |
CQA cycles if no scalar integer | 6.17 |
CQA cycles if FP arith vectorized | 24.67 |
CQA cycles if fully vectorized | 17.02 |
Front-end cycles | 24.67 |
DIV/SQRT cycles | 8.80 |
P0 cycles | 8.87 |
P1 cycles | 19.33 |
P2 cycles | 19.33 |
P3 cycles | 15.00 |
P4 cycles | 8.80 |
P5 cycles | 8.80 |
P6 cycles | 15.00 |
P7 cycles | 15.00 |
P8 cycles | 15.00 |
P9 cycles | 8.73 |
P10 cycles | 19.33 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | 25.12 |
Stall cycles (UFS) | 0.00 |
Nb insns | 145.00 |
Nb uops | 148.00 |
Nb loads | 58.00 |
Nb stores | 30.00 |
Nb stack references | 35.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 35.84 |
Bytes prefetched | 0.00 |
Bytes loaded | 456.00 |
Bytes stored | 428.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 12.28 |
Vectorization ratio load | 5.88 |
Vectorization ratio store | 13.33 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 10.53 |
Vector-efficiency ratio all | 18.53 |
Vector-efficiency ratio load | 15.44 |
Vector-efficiency ratio store | 22.29 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 100.00 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 11.18 |
Path / |
nb instructions | 145 |
nb uops | 148 |
loop length | 779 |
used x86 registers | 15 |
used mmx registers | 0 |
used xmm registers | 3 |
used ymm registers | 0 |
used zmm registers | 12 |
nb stack references | 35 |
micro-operation queue | 24.67 cycles |
front end | 24.67 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 8.80 | 8.87 | 19.33 | 19.33 | 15.00 | 8.80 | 8.80 | 15.00 | 15.00 | 15.00 | 8.73 | 19.33 |
cycles | 8.80 | 8.87 | 19.33 | 19.33 | 15.00 | 8.80 | 8.80 | 15.00 | 15.00 | 15.00 | 8.73 | 19.33 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 25.12 |
Stall cycles | 0.00 |
Front-end | 24.67 |
Dispatch | 19.33 |
Overall L1 | 24.67 |
all | 9% |
load | 7% |
store | 13% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 40% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 50% |
all | 12% |
load | 5% |
store | 13% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 10% |
all | 18% |
load | 16% |
store | 22% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 9% |
all | 17% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 18% |
all | 18% |
load | 15% |
store | 22% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 11% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CMP %EAX,%R13D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x3(%RCX),%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
CMOVBE %R13D,%EAX | 2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1-2 | 1 |
MOV 0x2f8(%RSP),%R13D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA (%R13,%RAX,1),%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EAX,0x2e4(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EAX,%R13D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 428630 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.6.lto_priv.0+0xb60> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x40(%RSP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x38(%RSP),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RSP),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%R15),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R14),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x30(%RSP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%R13),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%R14),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2e8(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x2c8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x10(%R11),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%R9),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDI,0x2d8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x18(%RSP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R13),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,0x1c0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV (%R15),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R11),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x2c0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%R14,%RAX,8),%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x10(%RDI),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDI),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x2f0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x10(%RSP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %RAX,%R8 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
IMUL %RAX,%R11 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV 0x10(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R8,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R11,0x60(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
IMUL %RAX,%RDX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA 0x1(%RCX),%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOVSXD %ECX,%RCX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %EAX,0x2e0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVSXD %EAX,%RDI | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %RCX,0x2d0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,0x70(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x4c(%RSP),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA 0x2(%RDX),%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA -0x1(%R12),%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
CMP %EBX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EAX,0x5c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMOVG %EBX,%EAX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOVSXD %EAX,%RCX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
CMP $0xe,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JBE 4282fb <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.6.lto_priv.0+0x82b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOVSXD 0x2fc(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c8(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VPBROADCASTQ %RCX,%ZMM22 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VPBROADCASTQ %RDI,%ZMM29 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
KXNORB %K1,%K1,%K1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
MOV 0x70(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VPBROADCASTD 0x2fc(%RSP),%ZMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
VPBROADCASTQ %R9,%ZMM27 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VPBROADCASTQ %R13,%ZMM30 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %RAX,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x2c0(%RSP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%R11,%RAX,1),%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VPBROADCASTQ 0x2d0(%RSP),%ZMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
LEA (%RDX,%R8,8),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x78(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RCX,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VPADDD 0x3ab93(%RIP),%ZMM0,%ZMM7 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.67 |
VPBROADCASTQ 0x2d8(%RSP),%ZMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
LEA (%RDI,%R11,8),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R12D,%R11D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VPBROADCASTQ 0x2f0(%RSP),%ZMM25 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
LEA (%RDX,%RAX,8),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0x10,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SHR $0x4,%R11D | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
VBROADCASTSD 0x3ace5(%RIP),%ZMM28 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
VPBROADCASTD %EDX,%ZMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VBROADCASTSD 0x3aced(%RIP),%ZMM31 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
MOV 0x1c0(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVDQA32 %ZMM7,0x280(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVDQA64 %ZMM1,0x100(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
SAL $0x7,%R11 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VXORPD %XMM26,%XMM26,%XMM26 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVDQA64 %ZMM2,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVDQA32 %ZMM3,0x80(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R12D,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RDX,0x1c0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
AND $-0x10,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD %R8D,0x2f8(%RSP) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
ADD %R8D,0x2fc(%RSP) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
AND $0xf,%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
JE 4285d7 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.6.lto_priv.0+0xb07> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x2c8(%RSP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x68(%RSP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VXORPD %XMM5,%XMM5,%XMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x2c0(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x60(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%R12,%RDI,8),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x78(%RSP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x70(%RSP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%R11,%RDX,8),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOVSXD 0x2fc(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x1c0(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x280(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%R12,%RDI,8),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R8,0x240(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD 0x3a5e9(%RIP),%XMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x300(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x5c(%RSP),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EBX,0x1c0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EBX,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVG %EBX,%ECX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOVSXD %ECX,%R11 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R11,0x200(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JMP 428563 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.6.lto_priv.0+0xa93> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV 0x1c0(%RSP),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2e4(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EAX,0x2f8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x2f0(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2e0(%RSP),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,0x2e8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EBX,0x54(%RSP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JLE 4285a0 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.6.lto_priv.0+0xad0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x48(%RSP),%R13D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2f8(%RSP),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x50(%RSP),%R9D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x58(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %ESI,%R13D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R9D,0x2fc(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JMP 427bf8 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.6.lto_priv.0+0x128> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV 0x2e8(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA 0x1(%RCX),%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x2e0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R11,0x2f0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JMP 4285e5 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.6.lto_priv.0+0xb15> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
nb instructions | 145 |
nb uops | 148 |
loop length | 779 |
used x86 registers | 15 |
used mmx registers | 0 |
used xmm registers | 3 |
used ymm registers | 0 |
used zmm registers | 12 |
nb stack references | 35 |
micro-operation queue | 24.67 cycles |
front end | 24.67 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 8.80 | 8.87 | 19.33 | 19.33 | 15.00 | 8.80 | 8.80 | 15.00 | 15.00 | 15.00 | 8.73 | 19.33 |
cycles | 8.80 | 8.87 | 19.33 | 19.33 | 15.00 | 8.80 | 8.80 | 15.00 | 15.00 | 15.00 | 8.73 | 19.33 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 25.12 |
Stall cycles | 0.00 |
Front-end | 24.67 |
Dispatch | 19.33 |
Overall L1 | 24.67 |
all | 9% |
load | 7% |
store | 13% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 40% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 50% |
all | 12% |
load | 5% |
store | 13% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 10% |
all | 18% |
load | 16% |
store | 22% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 9% |
all | 17% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 18% |
all | 18% |
load | 15% |
store | 22% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 11% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CMP %EAX,%R13D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x3(%RCX),%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
CMOVBE %R13D,%EAX | 2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1-2 | 1 |
MOV 0x2f8(%RSP),%R13D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA (%R13,%RAX,1),%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EAX,0x2e4(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EAX,%R13D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 428630 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.6.lto_priv.0+0xb60> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x40(%RSP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x38(%RSP),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RSP),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%R15),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R14),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x30(%RSP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%R13),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%R14),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2e8(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x2c8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x10(%R11),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%R9),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDI,0x2d8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x18(%RSP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R13),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,0x1c0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV (%R15),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R11),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x2c0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%R14,%RAX,8),%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x10(%RDI),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDI),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x2f0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x10(%RSP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %RAX,%R8 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
IMUL %RAX,%R11 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV 0x10(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R8,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R11,0x60(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
IMUL %RAX,%RDX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA 0x1(%RCX),%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOVSXD %ECX,%RCX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %EAX,0x2e0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVSXD %EAX,%RDI | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %RCX,0x2d0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,0x70(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x4c(%RSP),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA 0x2(%RDX),%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA -0x1(%R12),%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
CMP %EBX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EAX,0x5c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMOVG %EBX,%EAX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOVSXD %EAX,%RCX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
CMP $0xe,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JBE 4282fb <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.6.lto_priv.0+0x82b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOVSXD 0x2fc(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c8(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VPBROADCASTQ %RCX,%ZMM22 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VPBROADCASTQ %RDI,%ZMM29 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
KXNORB %K1,%K1,%K1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
MOV 0x70(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VPBROADCASTD 0x2fc(%RSP),%ZMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
VPBROADCASTQ %R9,%ZMM27 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VPBROADCASTQ %R13,%ZMM30 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %RAX,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x2c0(%RSP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%R11,%RAX,1),%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VPBROADCASTQ 0x2d0(%RSP),%ZMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
LEA (%RDX,%R8,8),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x78(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RCX,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VPADDD 0x3ab93(%RIP),%ZMM0,%ZMM7 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.67 |
VPBROADCASTQ 0x2d8(%RSP),%ZMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
LEA (%RDI,%R11,8),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R12D,%R11D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VPBROADCASTQ 0x2f0(%RSP),%ZMM25 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
LEA (%RDX,%RAX,8),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0x10,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SHR $0x4,%R11D | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
VBROADCASTSD 0x3ace5(%RIP),%ZMM28 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
VPBROADCASTD %EDX,%ZMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VBROADCASTSD 0x3aced(%RIP),%ZMM31 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
MOV 0x1c0(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVDQA32 %ZMM7,0x280(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVDQA64 %ZMM1,0x100(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
SAL $0x7,%R11 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VXORPD %XMM26,%XMM26,%XMM26 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVDQA64 %ZMM2,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
VMOVDQA32 %ZMM3,0x80(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R12D,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RDX,0x1c0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
AND $-0x10,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD %R8D,0x2f8(%RSP) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
ADD %R8D,0x2fc(%RSP) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
AND $0xf,%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
JE 4285d7 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.6.lto_priv.0+0xb07> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x2c8(%RSP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x68(%RSP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VXORPD %XMM5,%XMM5,%XMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x2c0(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x60(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%R12,%RDI,8),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x78(%RSP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x70(%RSP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%R11,%RDX,8),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOVSXD 0x2fc(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x1c0(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x280(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%R12,%RDI,8),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R8,0x240(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD 0x3a5e9(%RIP),%XMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x300(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x5c(%RSP),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EBX,0x1c0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EBX,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVG %EBX,%ECX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOVSXD %ECX,%R11 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R11,0x200(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JMP 428563 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.6.lto_priv.0+0xa93> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV 0x1c0(%RSP),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2e4(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EAX,0x2f8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x2f0(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2e0(%RSP),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,0x2e8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EBX,0x54(%RSP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JLE 4285a0 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.6.lto_priv.0+0xad0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x48(%RSP),%R13D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2f8(%RSP),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x50(%RSP),%R9D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x58(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %ESI,%R13D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R9D,0x2fc(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JMP 427bf8 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.6.lto_priv.0+0x128> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV 0x2e8(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA 0x1(%RCX),%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x2e0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R11,0x2f0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JMP 4285e5 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.6.lto_priv.0+0xb15> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |