Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ... | Module: exec | Source: advec_mom.cpp:85-88 [...] | Coverage: 0.96% |
---|
Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ... | Module: exec | Source: advec_mom.cpp:85-88 [...] | Coverage: 0.96% |
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/scratch_na/users/xoserete/qaas_runs/171-291-1828/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69 |
-------------------------------------------------------------------------------- |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
/scratch_na/users/xoserete/qaas_runs/171-291-1828/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp: 85 - 88 |
-------------------------------------------------------------------------------- |
85: #pragma omp parallel for simd collapse(2) |
86: for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) { |
87: for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) { |
88: node_flux(i, j) = 0.25 * (mass_flux_x(i + 0, j - 1) + mass_flux_x(i, j) + mass_flux_x(i + 1, j - 1) + mass_flux_x(i + 1, j + 0)); |
0x42cec0 PUSH %RBP |
0x42cec1 MOV %RSP,%RBP |
0x42cec4 PUSH %R15 |
0x42cec6 PUSH %R14 |
0x42cec8 MOV %RDI,%R14 |
0x42cecb PUSH %R13 |
0x42cecd PUSH %R12 |
0x42cecf PUSH %RBX |
0x42ced0 AND $-0x40,%RSP |
0x42ced4 SUB $0x40,%RSP |
0x42ced8 MOV 0x18(%RDI),%EAX |
0x42cedb MOV 0x1c(%RDI),%EDX |
0x42cede MOV 0x10(%RDI),%ESI |
0x42cee1 MOV 0x14(%R14),%ECX |
0x42cee5 ADD $0x3,%EDX |
0x42cee8 LEA 0x1(%RAX),%R13D |
0x42ceec LEA -0x1(%RSI),%EDI |
0x42ceef MOV %EDX,0x1c(%RSP) |
0x42cef3 MOV %EDI,0x18(%RSP) |
0x42cef7 CMP %EDX,%R13D |
0x42cefa JGE 42d36b |
0x42cf00 MOV %EDX,%EBX |
0x42cf02 LEA 0x4(%RCX),%R15D |
0x42cf06 SUB %R13D,%EBX |
0x42cf09 CMP %R15D,%EDI |
0x42cf0c JGE 42d36b |
0x42cf12 MOV %R15D,%R8D |
0x42cf15 SUB %EDI,%R8D |
0x42cf18 MOV %R8D,0x28(%RSP) |
0x42cf1d CALL 404650 <omp_get_num_threads@plt> |
0x42cf22 MOV %EAX,%R12D |
0x42cf25 CALL 404540 <omp_get_thread_num@plt> |
0x42cf2a XOR %EDX,%EDX |
0x42cf2c MOV %EAX,%R9D |
0x42cf2f MOV 0x28(%RSP),%EAX |
0x42cf33 IMUL %EBX,%EAX |
0x42cf36 DIV %R12D |
0x42cf39 MOV %EAX,%EDI |
0x42cf3b CMP %EDX,%R9D |
0x42cf3e JB 42d38c |
0x42cf44 IMUL %EDI,%R9D |
0x42cf48 LEA (%R9,%RDX,1),%R12D |
0x42cf4c LEA (%RDI,%R12,1),%R10D |
0x42cf50 MOV %R10D,0x14(%RSP) |
0x42cf55 CMP %R10D,%R12D |
0x42cf58 JAE 42d36b |
0x42cf5e MOV %R12D,%EAX |
0x42cf61 XOR %EDX,%EDX |
0x42cf63 MOV 0x18(%RSP),%R11D |
0x42cf68 MOV (%R14),%RSI |
0x42cf6b DIVL 0x28(%RSP) |
0x42cf6f MOV 0x8(%R14),%R14 |
0x42cf73 VMOVSD 0x31885(%RIP),%XMM3 |
0x42cf7b MOV %RSI,0x8(%RSP) |
0x42cf80 MOV %R14,(%RSP) |
0x42cf84 VBROADCASTSD %XMM3,%YMM4 |
0x42cf89 VBROADCASTSD %XMM3,%ZMM2 |
0x42cf8f ADD %R13D,%EAX |
0x42cf92 ADD %EDX,%R11D |
0x42cf95 MOV %R15D,%EDX |
0x42cf98 MOV %EAX,0x38(%RSP) |
0x42cf9c CLTQ |
0x42cf9e SUB %R11D,%EDX |
0x42cfa1 MOV %R11D,0x3c(%RSP) |
0x42cfa6 MOV %RAX,0x20(%RSP) |
0x42cfab NOPL (%RAX,%RAX,1) |
(188) 0x42cfb0 CMP %EDX,%EDI |
(188) 0x42cfb2 CMOVBE %EDI,%EDX |
(188) 0x42cfb5 LEA (%R12,%RDX,1),%R13D |
(188) 0x42cfb9 MOV %R13D,0x2c(%RSP) |
(188) 0x42cfbe CMP %R13D,%R12D |
(188) 0x42cfc1 JAE 42d336 |
(188) 0x42cfc7 MOV 0x8(%RSP),%RDI |
(188) 0x42cfcc MOV 0x38(%RSP),%R15D |
(188) 0x42cfd1 LEA -0x1(%RDX),%R9D |
(188) 0x42cfd5 MOV 0x20(%RSP),%R10 |
(188) 0x42cfda MOV (%RSP),%R8 |
(188) 0x42cfde LEA -0x1(%R15),%EBX |
(188) 0x42cfe2 MOV 0x10(%RDI),%RCX |
(188) 0x42cfe6 MOV (%RDI),%RDI |
(188) 0x42cfe9 MOVSXD %EBX,%RSI |
(188) 0x42cfec MOV 0x10(%R8),%R15 |
(188) 0x42cff0 IMUL %RDI,%RSI |
(188) 0x42cff4 IMUL %R10,%RDI |
(188) 0x42cff8 IMUL (%R8),%R10 |
(188) 0x42cffc MOV %R10,0x30(%RSP) |
(188) 0x42d001 CMP $0x6,%R9D |
(188) 0x42d005 JBE 42d380 |
(188) 0x42d00b MOV %EDX,%R9D |
(188) 0x42d00e MOVSXD 0x3c(%RSP),%RAX |
(188) 0x42d013 SHR $0x3,%R9D |
(188) 0x42d017 SAL $0x6,%R9 |
(188) 0x42d01b LEA (%RSI,%RAX,1),%R11 |
(188) 0x42d01f LEA (%RDI,%RAX,1),%RBX |
(188) 0x42d023 ADD %R10,%RAX |
(188) 0x42d026 LEA -0x40(%R9),%R8 |
(188) 0x42d02a SAL $0x3,%R11 |
(188) 0x42d02e SAL $0x3,%RBX |
(188) 0x42d032 LEA (%R15,%RAX,8),%R10 |
(188) 0x42d036 SHR $0x6,%R8 |
(188) 0x42d03a LEA (%RCX,%R11,1),%R13 |
(188) 0x42d03e LEA (%RCX,%RBX,1),%R14 |
(188) 0x42d042 XOR %EAX,%EAX |
(188) 0x42d044 INC %R8 |
(188) 0x42d047 LEA 0x8(%RCX,%R11,1),%R11 |
(188) 0x42d04c LEA 0x8(%RCX,%RBX,1),%RBX |
(188) 0x42d051 AND $0x3,%R8D |
(188) 0x42d055 JE 42d108 |
(188) 0x42d05b CMP $0x1,%R8 |
(188) 0x42d05f JE 42d0cb |
(188) 0x42d061 CMP $0x2,%R8 |
(188) 0x42d065 JE 42d097 |
(188) 0x42d067 VMOVUPD (%R13),%ZMM7 |
(188) 0x42d06e VMOVUPD (%R11),%ZMM1 |
(188) 0x42d074 MOV $0x40,%EAX |
(188) 0x42d079 VADDPD (%R14),%ZMM7,%ZMM0 |
(188) 0x42d07f VADDPD (%RBX),%ZMM1,%ZMM5 |
(188) 0x42d085 VADDPD %ZMM5,%ZMM0,%ZMM6 |
(188) 0x42d08b VMULPD %ZMM2,%ZMM6,%ZMM8 |
(188) 0x42d091 VMOVUPD %ZMM8,(%R10) |
(188) 0x42d097 VMOVUPD (%R13,%RAX,1),%ZMM9 |
(188) 0x42d09f VMOVUPD (%R11,%RAX,1),%ZMM11 |
(188) 0x42d0a6 VADDPD (%R14,%RAX,1),%ZMM9,%ZMM10 |
(188) 0x42d0ad VADDPD (%RBX,%RAX,1),%ZMM11,%ZMM12 |
(188) 0x42d0b4 VADDPD %ZMM12,%ZMM10,%ZMM13 |
(188) 0x42d0ba VMULPD %ZMM2,%ZMM13,%ZMM14 |
(188) 0x42d0c0 VMOVUPD %ZMM14,(%R10,%RAX,1) |
(188) 0x42d0c7 ADD $0x40,%RAX |
(188) 0x42d0cb VMOVUPD (%R13,%RAX,1),%ZMM15 |
(188) 0x42d0d3 VMOVUPD (%R11,%RAX,1),%ZMM7 |
(188) 0x42d0da VADDPD (%R14,%RAX,1),%ZMM15,%ZMM0 |
(188) 0x42d0e1 VADDPD (%RBX,%RAX,1),%ZMM7,%ZMM1 |
(188) 0x42d0e8 VADDPD %ZMM1,%ZMM0,%ZMM5 |
(188) 0x42d0ee VMULPD %ZMM2,%ZMM5,%ZMM6 |
(188) 0x42d0f4 VMOVUPD %ZMM6,(%R10,%RAX,1) |
(188) 0x42d0fb ADD $0x40,%RAX |
(188) 0x42d0ff CMP %RAX,%R9 |
(188) 0x42d102 JE 42d1e3 |
(189) 0x42d108 VMOVUPD (%R13,%RAX,1),%ZMM8 |
(189) 0x42d110 VMOVUPD (%R11,%RAX,1),%ZMM10 |
(189) 0x42d117 VADDPD (%R14,%RAX,1),%ZMM8,%ZMM9 |
(189) 0x42d11e VADDPD (%RBX,%RAX,1),%ZMM10,%ZMM11 |
(189) 0x42d125 VADDPD %ZMM11,%ZMM9,%ZMM12 |
(189) 0x42d12b VMULPD %ZMM2,%ZMM12,%ZMM13 |
(189) 0x42d131 VMOVUPD %ZMM13,(%R10,%RAX,1) |
(189) 0x42d138 VMOVUPD 0x40(%R13,%RAX,1),%ZMM14 |
(189) 0x42d140 VMOVUPD 0x40(%R11,%RAX,1),%ZMM0 |
(189) 0x42d148 VADDPD 0x40(%R14,%RAX,1),%ZMM14,%ZMM15 |
(189) 0x42d150 VADDPD 0x40(%RBX,%RAX,1),%ZMM0,%ZMM7 |
(189) 0x42d158 VADDPD %ZMM7,%ZMM15,%ZMM1 |
(189) 0x42d15e VMULPD %ZMM2,%ZMM1,%ZMM5 |
(189) 0x42d164 VMOVUPD %ZMM5,0x40(%R10,%RAX,1) |
(189) 0x42d16c VMOVUPD 0x80(%R13,%RAX,1),%ZMM6 |
(189) 0x42d174 VMOVUPD 0x80(%R11,%RAX,1),%ZMM9 |
(189) 0x42d17c VADDPD 0x80(%R14,%RAX,1),%ZMM6,%ZMM8 |
(189) 0x42d184 VADDPD 0x80(%RBX,%RAX,1),%ZMM9,%ZMM10 |
(189) 0x42d18c VADDPD %ZMM10,%ZMM8,%ZMM11 |
(189) 0x42d192 VMULPD %ZMM2,%ZMM11,%ZMM12 |
(189) 0x42d198 VMOVUPD %ZMM12,0x80(%R10,%RAX,1) |
(189) 0x42d1a0 VMOVUPD 0xc0(%R13,%RAX,1),%ZMM13 |
(189) 0x42d1a8 VMOVUPD 0xc0(%R11,%RAX,1),%ZMM15 |
(189) 0x42d1b0 VADDPD 0xc0(%R14,%RAX,1),%ZMM13,%ZMM14 |
(189) 0x42d1b8 VADDPD 0xc0(%RBX,%RAX,1),%ZMM15,%ZMM0 |
(189) 0x42d1c0 VADDPD %ZMM0,%ZMM14,%ZMM7 |
(189) 0x42d1c6 VMULPD %ZMM2,%ZMM7,%ZMM1 |
(189) 0x42d1cc VMOVUPD %ZMM1,0xc0(%R10,%RAX,1) |
(189) 0x42d1d4 ADD $0x100,%RAX |
(189) 0x42d1da CMP %RAX,%R9 |
(189) 0x42d1dd JNE 42d108 |
(188) 0x42d1e3 MOV 0x3c(%RSP),%EAX |
(188) 0x42d1e7 MOV %EDX,%R14D |
(188) 0x42d1ea AND $-0x8,%R14D |
(188) 0x42d1ee ADD %R14D,%R12D |
(188) 0x42d1f1 ADD %R14D,%EAX |
(188) 0x42d1f4 TEST $0x7,%DL |
(188) 0x42d1f7 JE 42d331 |
(188) 0x42d1fd SUB %R14D,%EDX |
(188) 0x42d200 LEA -0x1(%RDX),%R13D |
(188) 0x42d204 CMP $0x2,%R13D |
(188) 0x42d208 JBE 42d260 |
(188) 0x42d20a MOVSXD 0x3c(%RSP),%R9 |
(188) 0x42d20f MOV 0x30(%RSP),%R10 |
(188) 0x42d214 LEA (%RSI,%R9,1),%RBX |
(188) 0x42d218 LEA (%RDI,%R9,1),%R11 |
(188) 0x42d21c ADD %R10,%R9 |
(188) 0x42d21f ADD %R14,%RBX |
(188) 0x42d222 ADD %R14,%R11 |
(188) 0x42d225 ADD %R14,%R9 |
(188) 0x42d228 VMOVUPD 0x8(%RCX,%RBX,8),%YMM5 |
(188) 0x42d22e VMOVUPD (%RCX,%R11,8),%YMM8 |
(188) 0x42d234 VADDPD 0x8(%RCX,%R11,8),%YMM5,%YMM6 |
(188) 0x42d23b VADDPD (%RCX,%RBX,8),%YMM8,%YMM9 |
(188) 0x42d240 VADDPD %YMM9,%YMM6,%YMM10 |
(188) 0x42d245 VMULPD %YMM4,%YMM10,%YMM11 |
(188) 0x42d249 VMOVUPD %YMM11,(%R15,%R9,8) |
(188) 0x42d24f TEST $0x3,%DL |
(188) 0x42d252 JE 42d331 |
(188) 0x42d258 AND $-0x4,%EDX |
(188) 0x42d25b ADD %EDX,%R12D |
(188) 0x42d25e ADD %EDX,%EAX |
(188) 0x42d260 LEA 0x1(%RAX),%R14D |
(188) 0x42d264 MOVSXD %EAX,%RDX |
(188) 0x42d267 MOVSXD %R14D,%R8 |
(188) 0x42d26a MOV 0x30(%RSP),%R14 |
(188) 0x42d26f LEA (%R8,%RSI,1),%R13 |
(188) 0x42d273 LEA (%R8,%RDI,1),%RBX |
(188) 0x42d277 LEA (%RCX,%R13,8),%R9 |
(188) 0x42d27b LEA (%RDI,%RDX,1),%R13 |
(188) 0x42d27f VMOVSD (%RCX,%R13,8),%XMM12 |
(188) 0x42d285 VMOVSD (%R9),%XMM14 |
(188) 0x42d28a LEA (%R14,%RDX,1),%R11 |
(188) 0x42d28e LEA (%RCX,%RBX,8),%R10 |
(188) 0x42d292 ADD %RSI,%RDX |
(188) 0x42d295 MOV 0x2c(%RSP),%R13D |
(188) 0x42d29a VADDSD (%RCX,%RDX,8),%XMM12,%XMM13 |
(188) 0x42d29f VADDSD (%R10),%XMM14,%XMM15 |
(188) 0x42d2a4 LEA 0x1(%R12),%EDX |
(188) 0x42d2a9 VADDSD %XMM15,%XMM13,%XMM0 |
(188) 0x42d2ae VMULSD %XMM3,%XMM0,%XMM7 |
(188) 0x42d2b2 VMOVSD %XMM7,(%R15,%R11,8) |
(188) 0x42d2b8 CMP %R13D,%EDX |
(188) 0x42d2bb JAE 42d331 |
(188) 0x42d2bd LEA 0x2(%RAX),%EBX |
(188) 0x42d2c0 VMOVSD (%R10),%XMM1 |
(188) 0x42d2c5 ADD %R14,%R8 |
(188) 0x42d2c8 ADD $0x2,%R12D |
(188) 0x42d2cc MOVSXD %EBX,%RDX |
(188) 0x42d2cf LEA (%RSI,%RDX,1),%R11 |
(188) 0x42d2d3 VADDSD (%R9),%XMM1,%XMM5 |
(188) 0x42d2d8 LEA (%RCX,%R11,8),%RBX |
(188) 0x42d2dc LEA (%RDI,%RDX,1),%R11 |
(188) 0x42d2e0 LEA (%RCX,%R11,8),%R11 |
(188) 0x42d2e4 VMOVSD (%R11),%XMM6 |
(188) 0x42d2e9 VADDSD (%RBX),%XMM6,%XMM8 |
(188) 0x42d2ed VADDSD %XMM8,%XMM5,%XMM9 |
(188) 0x42d2f2 VMULSD %XMM3,%XMM9,%XMM10 |
(188) 0x42d2f6 VMOVSD %XMM10,(%R15,%R8,8) |
(188) 0x42d2fc CMP %R13D,%R12D |
(188) 0x42d2ff JAE 42d331 |
(188) 0x42d301 ADD $0x3,%EAX |
(188) 0x42d304 VMOVSD (%RBX),%XMM13 |
(188) 0x42d308 ADD %RDX,%R14 |
(188) 0x42d30b CLTQ |
(188) 0x42d30d ADD %RAX,%RSI |
(188) 0x42d310 ADD %RDI,%RAX |
(188) 0x42d313 VADDSD (%R11),%XMM13,%XMM14 |
(188) 0x42d318 VMOVSD (%RCX,%RSI,8),%XMM11 |
(188) 0x42d31d VADDSD (%RCX,%RAX,8),%XMM11,%XMM12 |
(188) 0x42d322 VADDSD %XMM14,%XMM12,%XMM15 |
(188) 0x42d327 VMULSD %XMM3,%XMM15,%XMM0 |
(188) 0x42d32b VMOVSD %XMM0,(%R15,%R14,8) |
(188) 0x42d331 MOV 0x2c(%RSP),%R12D |
(188) 0x42d336 INCL 0x38(%RSP) |
(188) 0x42d33a INCQ 0x20(%RSP) |
(188) 0x42d33f MOV 0x38(%RSP),%ECX |
(188) 0x42d343 CMP %ECX,0x1c(%RSP) |
(188) 0x42d347 JLE 42d368 |
(188) 0x42d349 MOV 0x14(%RSP),%EDI |
(188) 0x42d34d MOV 0x18(%RSP),%ESI |
(188) 0x42d351 MOV 0x28(%RSP),%EDX |
(188) 0x42d355 MOV %ESI,0x3c(%RSP) |
(188) 0x42d359 SUB %R12D,%EDI |
(188) 0x42d35c JMP 42cfb0 |
0x42d361 NOPL (%RAX) |
0x42d368 VZEROUPPER |
0x42d36b LEA -0x28(%RBP),%RSP |
0x42d36f POP %RBX |
0x42d370 POP %R12 |
0x42d372 POP %R13 |
0x42d374 POP %R14 |
0x42d376 POP %R15 |
0x42d378 POP %RBP |
0x42d379 RET |
0x42d37a NOPW (%RAX,%RAX,1) |
(188) 0x42d380 MOV 0x3c(%RSP),%EAX |
(188) 0x42d384 XOR %R14D,%R14D |
(188) 0x42d387 JMP 42d1fd |
0x42d38c INC %EDI |
0x42d38e XOR %EDX,%EDX |
0x42d390 JMP 42cf44 |
0x42d395 NOPW %CS:(%RAX,%RAX,1) |
Path / |
Source file and lines | advec_mom.cpp:85-88 |
Module | exec |
nb instructions | 81 |
nb uops | 91 |
loop length | 291 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 1 |
used ymm registers | 1 |
used zmm registers | 1 |
nb stack references | 10 |
micro-operation queue | 15.17 cycles |
front end | 15.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.30 | 8.00 | 5.67 | 5.67 | 8.50 | 6.20 | 6.30 | 8.50 | 8.50 | 8.50 | 6.20 | 5.67 |
cycles | 6.30 | 11.90 | 5.67 | 5.67 | 8.50 | 6.20 | 6.30 | 8.50 | 8.50 | 8.50 | 6.20 | 5.67 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.42-14.53 |
Stall cycles | 0.00 |
Front-end | 15.17 |
Dispatch | 11.90 |
DIV/SQRT | 12.00 |
Overall L1 | 15.17 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 10% |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 3% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 10% |
all | 8% |
load | 6% |
store | 8% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 8% |
all | 12% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
all | 8% |
load | 8% |
store | 8% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 10% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0x40,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x18(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x1c(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x14(%R14),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x3,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%RAX),%R13D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA -0x1(%RSI),%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x1c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EDI,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%R13D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 42d36b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x4ab> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x4(%RCX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R13D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R15D,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 42d36b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x4ab> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R15D,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %EDI,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R8D,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 404650 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 404540 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R9D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x28(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 42d38c <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x4cc> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %EDI,%R9D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R9,%RDX,1),%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RDI,%R12,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R10D,0x14(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R10D,%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 42d36b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x4ab> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R12D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x18(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R14),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x28(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x8(%R14),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0x31885(%RIP),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VBROADCASTSD %XMM3,%YMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VBROADCASTSD %XMM3,%ZMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %R13D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %EDX,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R15D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %EAX,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CLTQ | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
SUB %R11D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R11D,0x3c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 42cf44 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x84> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | advec_mom.cpp:85-88 |
Module | exec |
nb instructions | 81 |
nb uops | 91 |
loop length | 291 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 1 |
used ymm registers | 1 |
used zmm registers | 1 |
nb stack references | 10 |
micro-operation queue | 15.17 cycles |
front end | 15.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.30 | 8.00 | 5.67 | 5.67 | 8.50 | 6.20 | 6.30 | 8.50 | 8.50 | 8.50 | 6.20 | 5.67 |
cycles | 6.30 | 11.90 | 5.67 | 5.67 | 8.50 | 6.20 | 6.30 | 8.50 | 8.50 | 8.50 | 6.20 | 5.67 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.42-14.53 |
Stall cycles | 0.00 |
Front-end | 15.17 |
Dispatch | 11.90 |
DIV/SQRT | 12.00 |
Overall L1 | 15.17 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 10% |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 3% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 10% |
all | 8% |
load | 6% |
store | 8% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 8% |
all | 12% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
all | 8% |
load | 8% |
store | 8% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 10% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0x40,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x18(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x1c(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x14(%R14),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x3,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%RAX),%R13D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA -0x1(%RSI),%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x1c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EDI,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%R13D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 42d36b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x4ab> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x4(%RCX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R13D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R15D,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 42d36b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x4ab> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R15D,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %EDI,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R8D,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 404650 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 404540 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R9D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x28(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 42d38c <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x4cc> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %EDI,%R9D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R9,%RDX,1),%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RDI,%R12,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R10D,0x14(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R10D,%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 42d36b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x4ab> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R12D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x18(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R14),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x28(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x8(%R14),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0x31885(%RIP),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VBROADCASTSD %XMM3,%YMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VBROADCASTSD %XMM3,%ZMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %R13D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %EDX,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R15D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %EAX,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CLTQ | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
SUB %R11D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R11D,0x3c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 42cf44 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x84> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D | 0.96 | 0.72 |
▼Loop 188 - advec_mom.cpp:87-88 - exec– | 0.01 | 0.01 |
○Loop 189 - advec_mom.cpp:88-88 - exec | 0.96 | 0.72 |