Function: revert_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, cl ... | Module: exec | Source: revert.cpp:34-38 [...] | Coverage: 2.26% |
---|
Function: revert_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, cl ... | Module: exec | Source: revert.cpp:34-38 [...] | Coverage: 2.26% |
---|
/scratch_na/users/xoserete/qaas_runs/171-291-1828/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/revert.cpp: 34 - 38 |
-------------------------------------------------------------------------------- |
34: #pragma omp parallel for simd collapse(2) |
35: for (int j = (y_min + 1); j < (y_max + 2); j++) { |
36: for (int i = (x_min + 1); i < (x_max + 2); i++) { |
37: density1(i, j) = density0(i, j); |
38: energy1(i, j) = energy0(i, j); |
/scratch_na/users/xoserete/qaas_runs/171-291-1828/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69 |
-------------------------------------------------------------------------------- |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
0x440fe0 PUSH %RBP |
0x440fe1 MOV %RSP,%RBP |
0x440fe4 PUSH %R15 |
0x440fe6 PUSH %R14 |
0x440fe8 PUSH %R13 |
0x440fea PUSH %R12 |
0x440fec PUSH %RBX |
0x440fed AND $-0x40,%RSP |
0x440ff1 ADD $-0x80,%RSP |
0x440ff5 MOV 0x28(%RDI),%EAX |
0x440ff8 MOV 0x2c(%RDI),%EDX |
0x440ffb MOV 0x20(%RDI),%EBX |
0x440ffe MOV 0x24(%RDI),%ECX |
0x441001 ADD $0x2,%EDX |
0x441004 LEA 0x1(%RAX),%R15D |
0x441008 LEA 0x1(%RBX),%ESI |
0x44100b MOV %EDX,0x50(%RSP) |
0x44100f MOV %ESI,0x4c(%RSP) |
0x441013 CMP %EDX,%R15D |
0x441016 JGE 44150b |
0x44101c MOV %EDX,%EBX |
0x44101e LEA 0x2(%RCX),%R14D |
0x441022 SUB %R15D,%EBX |
0x441025 CMP %R14D,%ESI |
0x441028 JGE 44150b |
0x44102e MOV %RDI,%R13 |
0x441031 MOV %R14D,%EDI |
0x441034 SUB %ESI,%EDI |
0x441036 MOV %EDI,0x54(%RSP) |
0x44103a CALL 404650 <omp_get_num_threads@plt> |
0x44103f MOV %EAX,%R12D |
0x441042 CALL 404540 <omp_get_thread_num@plt> |
0x441047 XOR %EDX,%EDX |
0x441049 MOV %EAX,%R8D |
0x44104c MOV 0x54(%RSP),%EAX |
0x441050 IMUL %EBX,%EAX |
0x441053 DIV %R12D |
0x441056 MOV %EAX,%R12D |
0x441059 CMP %EDX,%R8D |
0x44105c JB 44152c |
0x441062 IMUL %R12D,%R8D |
0x441066 LEA (%R8,%RDX,1),%R9D |
0x44106a LEA (%R12,%R9,1),%R10D |
0x44106e MOV %R10D,0x48(%RSP) |
0x441073 CMP %R10D,%R9D |
0x441076 JAE 44150b |
0x44107c MOV %R9D,%EAX |
0x44107f XOR %EDX,%EDX |
0x441081 MOV 0x4c(%RSP),%R11D |
0x441086 MOV 0x8(%R13),%RSI |
0x44108a DIVL 0x54(%RSP) |
0x44108e MOV 0x18(%R13),%RBX |
0x441092 MOV %RSI,0x38(%RSP) |
0x441097 MOV %RBX,0x28(%RSP) |
0x44109c ADD %EDX,%R11D |
0x44109f ADD %R15D,%EAX |
0x4410a2 MOV %R14D,%EDX |
0x4410a5 MOV (%R13),%R15 |
0x4410a9 MOV 0x10(%R13),%R14 |
0x4410ad MOV %R11D,0x7c(%RSP) |
0x4410b2 SUB %R11D,%EDX |
0x4410b5 MOVSXD %EAX,%RBX |
0x4410b8 MOV %R15,0x40(%RSP) |
0x4410bd MOV %R14,0x30(%RSP) |
0x4410c2 NOPW (%RAX,%RAX,1) |
(284) 0x4410c8 CMP %EDX,%R12D |
(284) 0x4410cb CMOVBE %R12D,%EDX |
(284) 0x4410cf LEA (%R9,%RDX,1),%ECX |
(284) 0x4410d3 MOV %ECX,0x78(%RSP) |
(284) 0x4410d7 CMP %ECX,%R9D |
(284) 0x4410da JAE 4414dd |
(284) 0x4410e0 MOV 0x30(%RSP),%R12 |
(284) 0x4410e5 MOV 0x38(%RSP),%RDI |
(284) 0x4410ea LEA -0x1(%RDX),%EAX |
(284) 0x4410ed MOV 0x28(%RSP),%RCX |
(284) 0x4410f2 MOV 0x40(%RSP),%R13 |
(284) 0x4410f7 MOV (%R12),%RSI |
(284) 0x4410fb MOV (%RDI),%R8 |
(284) 0x4410fe MOV (%RCX),%R10 |
(284) 0x441101 MOV (%R13),%R11 |
(284) 0x441105 IMUL %RBX,%R8 |
(284) 0x441109 MOV 0x10(%R13),%R15 |
(284) 0x44110d MOV 0x10(%RDI),%R14 |
(284) 0x441111 IMUL %RBX,%RSI |
(284) 0x441115 MOV 0x10(%R12),%R13 |
(284) 0x44111a MOV 0x10(%RCX),%R12 |
(284) 0x44111e IMUL %RBX,%R10 |
(284) 0x441122 IMUL %RBX,%R11 |
(284) 0x441126 MOV %R8,0x60(%RSP) |
(284) 0x44112b MOV %RSI,0x68(%RSP) |
(284) 0x441130 MOV %R10,0x70(%RSP) |
(284) 0x441135 CMP $0x6,%EAX |
(284) 0x441138 JBE 441520 |
(284) 0x44113e MOVSXD 0x7c(%RSP),%RAX |
(284) 0x441143 LEA (%R8,%RAX,1),%RCX |
(284) 0x441147 LEA (%R11,%RAX,1),%RDI |
(284) 0x44114b LEA (%R14,%RCX,8),%R8 |
(284) 0x44114f MOV 0x70(%RSP),%RCX |
(284) 0x441154 LEA (%RSI,%RAX,1),%RSI |
(284) 0x441158 LEA (%R15,%RDI,8),%R10 |
(284) 0x44115c LEA (%R13,%RSI,8),%RDI |
(284) 0x441161 ADD %RCX,%RAX |
(284) 0x441164 MOV %EDX,%ECX |
(284) 0x441166 SHR $0x3,%ECX |
(284) 0x441169 LEA (%R12,%RAX,8),%RSI |
(284) 0x44116d XOR %EAX,%EAX |
(284) 0x44116f SAL $0x6,%RCX |
(284) 0x441173 MOV %RCX,0x58(%RSP) |
(284) 0x441178 SUB $0x40,%RCX |
(284) 0x44117c SHR $0x6,%RCX |
(284) 0x441180 INC %RCX |
(284) 0x441183 AND $0x7,%ECX |
(284) 0x441186 JE 4412a4 |
(284) 0x44118c CMP $0x1,%RCX |
(284) 0x441190 JE 441279 |
(284) 0x441196 CMP $0x2,%RCX |
(284) 0x44119a JE 441259 |
(284) 0x4411a0 CMP $0x3,%RCX |
(284) 0x4411a4 JE 441239 |
(284) 0x4411aa CMP $0x4,%RCX |
(284) 0x4411ae JE 441219 |
(284) 0x4411b0 CMP $0x5,%RCX |
(284) 0x4411b4 JE 4411f9 |
(284) 0x4411b6 CMP $0x6,%RCX |
(284) 0x4411ba JE 4411d9 |
(284) 0x4411bc VMOVUPD (%R10),%ZMM3 |
(284) 0x4411c2 MOV $0x40,%EAX |
(284) 0x4411c7 VMOVUPD %ZMM3,(%R8) |
(284) 0x4411cd VMOVUPD (%RDI),%ZMM4 |
(284) 0x4411d3 VMOVUPD %ZMM4,(%RSI) |
(284) 0x4411d9 VMOVUPD (%R10,%RAX,1),%ZMM1 |
(284) 0x4411e0 VMOVUPD %ZMM1,(%R8,%RAX,1) |
(284) 0x4411e7 VMOVUPD (%RDI,%RAX,1),%ZMM2 |
(284) 0x4411ee VMOVUPD %ZMM2,(%RSI,%RAX,1) |
(284) 0x4411f5 ADD $0x40,%RAX |
(284) 0x4411f9 VMOVUPD (%R10,%RAX,1),%ZMM0 |
(284) 0x441200 VMOVUPD %ZMM0,(%R8,%RAX,1) |
(284) 0x441207 VMOVUPD (%RDI,%RAX,1),%ZMM5 |
(284) 0x44120e VMOVUPD %ZMM5,(%RSI,%RAX,1) |
(284) 0x441215 ADD $0x40,%RAX |
(284) 0x441219 VMOVUPD (%R10,%RAX,1),%ZMM6 |
(284) 0x441220 VMOVUPD %ZMM6,(%R8,%RAX,1) |
(284) 0x441227 VMOVUPD (%RDI,%RAX,1),%ZMM7 |
(284) 0x44122e VMOVUPD %ZMM7,(%RSI,%RAX,1) |
(284) 0x441235 ADD $0x40,%RAX |
(284) 0x441239 VMOVUPD (%R10,%RAX,1),%ZMM8 |
(284) 0x441240 VMOVUPD %ZMM8,(%R8,%RAX,1) |
(284) 0x441247 VMOVUPD (%RDI,%RAX,1),%ZMM9 |
(284) 0x44124e VMOVUPD %ZMM9,(%RSI,%RAX,1) |
(284) 0x441255 ADD $0x40,%RAX |
(284) 0x441259 VMOVUPD (%R10,%RAX,1),%ZMM10 |
(284) 0x441260 VMOVUPD %ZMM10,(%R8,%RAX,1) |
(284) 0x441267 VMOVUPD (%RDI,%RAX,1),%ZMM11 |
(284) 0x44126e VMOVUPD %ZMM11,(%RSI,%RAX,1) |
(284) 0x441275 ADD $0x40,%RAX |
(284) 0x441279 VMOVUPD (%R10,%RAX,1),%ZMM12 |
(284) 0x441280 VMOVUPD %ZMM12,(%R8,%RAX,1) |
(284) 0x441287 VMOVUPD (%RDI,%RAX,1),%ZMM13 |
(284) 0x44128e VMOVUPD %ZMM13,(%RSI,%RAX,1) |
(284) 0x441295 ADD $0x40,%RAX |
(284) 0x441299 CMP %RAX,0x58(%RSP) |
(284) 0x44129e JE 4413b1 |
(285) 0x4412a4 VMOVUPD (%R10,%RAX,1),%ZMM14 |
(285) 0x4412ab VMOVUPD %ZMM14,(%R8,%RAX,1) |
(285) 0x4412b2 VMOVUPD (%RDI,%RAX,1),%ZMM15 |
(285) 0x4412b9 VMOVUPD %ZMM15,(%RSI,%RAX,1) |
(285) 0x4412c0 VMOVUPD 0x40(%R10,%RAX,1),%ZMM3 |
(285) 0x4412c8 VMOVUPD %ZMM3,0x40(%R8,%RAX,1) |
(285) 0x4412d0 VMOVUPD 0x40(%RDI,%RAX,1),%ZMM4 |
(285) 0x4412d8 VMOVUPD %ZMM4,0x40(%RSI,%RAX,1) |
(285) 0x4412e0 VMOVUPD 0x80(%R10,%RAX,1),%ZMM1 |
(285) 0x4412e8 VMOVUPD %ZMM1,0x80(%R8,%RAX,1) |
(285) 0x4412f0 VMOVUPD 0x80(%RDI,%RAX,1),%ZMM2 |
(285) 0x4412f8 VMOVUPD %ZMM2,0x80(%RSI,%RAX,1) |
(285) 0x441300 VMOVUPD 0xc0(%R10,%RAX,1),%ZMM0 |
(285) 0x441308 VMOVUPD %ZMM0,0xc0(%R8,%RAX,1) |
(285) 0x441310 VMOVUPD 0xc0(%RDI,%RAX,1),%ZMM5 |
(285) 0x441318 VMOVUPD %ZMM5,0xc0(%RSI,%RAX,1) |
(285) 0x441320 VMOVUPD 0x100(%R10,%RAX,1),%ZMM6 |
(285) 0x441328 VMOVUPD %ZMM6,0x100(%R8,%RAX,1) |
(285) 0x441330 VMOVUPD 0x100(%RDI,%RAX,1),%ZMM7 |
(285) 0x441338 VMOVUPD %ZMM7,0x100(%RSI,%RAX,1) |
(285) 0x441340 VMOVUPD 0x140(%R10,%RAX,1),%ZMM8 |
(285) 0x441348 VMOVUPD %ZMM8,0x140(%R8,%RAX,1) |
(285) 0x441350 VMOVUPD 0x140(%RDI,%RAX,1),%ZMM9 |
(285) 0x441358 VMOVUPD %ZMM9,0x140(%RSI,%RAX,1) |
(285) 0x441360 VMOVUPD 0x180(%R10,%RAX,1),%ZMM10 |
(285) 0x441368 VMOVUPD %ZMM10,0x180(%R8,%RAX,1) |
(285) 0x441370 VMOVUPD 0x180(%RDI,%RAX,1),%ZMM11 |
(285) 0x441378 VMOVUPD %ZMM11,0x180(%RSI,%RAX,1) |
(285) 0x441380 VMOVUPD 0x1c0(%R10,%RAX,1),%ZMM12 |
(285) 0x441388 VMOVUPD %ZMM12,0x1c0(%R8,%RAX,1) |
(285) 0x441390 VMOVUPD 0x1c0(%RDI,%RAX,1),%ZMM13 |
(285) 0x441398 VMOVUPD %ZMM13,0x1c0(%RSI,%RAX,1) |
(285) 0x4413a0 ADD $0x200,%RAX |
(285) 0x4413a6 CMP %RAX,0x58(%RSP) |
(285) 0x4413ab JNE 4412a4 |
(284) 0x4413b1 MOV 0x7c(%RSP),%R10D |
(284) 0x4413b6 MOV %EDX,%R8D |
(284) 0x4413b9 AND $-0x8,%R8D |
(284) 0x4413bd ADD %R8D,%R9D |
(284) 0x4413c0 LEA (%R8,%R10,1),%ESI |
(284) 0x4413c4 TEST $0x7,%DL |
(284) 0x4413c7 JE 4414d8 |
(284) 0x4413cd SUB %R8D,%EDX |
(284) 0x4413d0 LEA -0x1(%RDX),%EDI |
(284) 0x4413d3 CMP $0x2,%EDI |
(284) 0x4413d6 JBE 44142f |
(284) 0x4413d8 MOVSXD 0x7c(%RSP),%RCX |
(284) 0x4413dd MOV 0x60(%RSP),%R10 |
(284) 0x4413e2 MOV 0x68(%RSP),%RDI |
(284) 0x4413e7 LEA (%R11,%RCX,1),%RAX |
(284) 0x4413eb ADD %RCX,%R10 |
(284) 0x4413ee ADD %R8,%RAX |
(284) 0x4413f1 ADD %RCX,%RDI |
(284) 0x4413f4 ADD %R8,%R10 |
(284) 0x4413f7 VMOVUPD (%R15,%RAX,8),%YMM14 |
(284) 0x4413fd MOV 0x70(%RSP),%RAX |
(284) 0x441402 ADD %R8,%RDI |
(284) 0x441405 VMOVUPD %YMM14,(%R14,%R10,8) |
(284) 0x44140b ADD %RAX,%RCX |
(284) 0x44140e VMOVUPD (%R13,%RDI,8),%YMM15 |
(284) 0x441415 ADD %R8,%RCX |
(284) 0x441418 VMOVUPD %YMM15,(%R12,%RCX,8) |
(284) 0x44141e TEST $0x3,%DL |
(284) 0x441421 JE 4414d8 |
(284) 0x441427 AND $-0x4,%EDX |
(284) 0x44142a ADD %EDX,%R9D |
(284) 0x44142d ADD %EDX,%ESI |
(284) 0x44142f MOVSXD %ESI,%R10 |
(284) 0x441432 MOV 0x60(%RSP),%RCX |
(284) 0x441437 MOV 0x68(%RSP),%RDI |
(284) 0x44143c LEA (%R11,%R10,1),%RDX |
(284) 0x441440 VMOVSD (%R15,%RDX,8),%XMM3 |
(284) 0x441446 LEA (%RCX,%R10,1),%R8 |
(284) 0x44144a LEA (%RDI,%R10,1),%RAX |
(284) 0x44144e LEA 0x1(%R9),%EDX |
(284) 0x441452 VMOVSD %XMM3,(%R14,%R8,8) |
(284) 0x441458 MOV 0x70(%RSP),%R8 |
(284) 0x44145d VMOVSD (%R13,%RAX,8),%XMM4 |
(284) 0x441464 LEA 0x1(%RSI),%EAX |
(284) 0x441467 ADD %R8,%R10 |
(284) 0x44146a VMOVSD %XMM4,(%R12,%R10,8) |
(284) 0x441470 MOV 0x78(%RSP),%R10D |
(284) 0x441475 CMP %R10D,%EDX |
(284) 0x441478 JAE 4414d8 |
(284) 0x44147a CLTQ |
(284) 0x44147c ADD $0x2,%R9D |
(284) 0x441480 ADD $0x2,%ESI |
(284) 0x441483 LEA (%R11,%RAX,1),%RDX |
(284) 0x441487 VMOVSD (%R15,%RDX,8),%XMM1 |
(284) 0x44148d LEA (%RCX,%RAX,1),%RDX |
(284) 0x441491 VMOVSD %XMM1,(%R14,%RDX,8) |
(284) 0x441497 LEA (%RDI,%RAX,1),%RDX |
(284) 0x44149b ADD %R8,%RAX |
(284) 0x44149e VMOVSD (%R13,%RDX,8),%XMM2 |
(284) 0x4414a5 VMOVSD %XMM2,(%R12,%RAX,8) |
(284) 0x4414ab CMP %R10D,%R9D |
(284) 0x4414ae JAE 4414d8 |
(284) 0x4414b0 MOVSXD %ESI,%R9 |
(284) 0x4414b3 ADD %R9,%R11 |
(284) 0x4414b6 ADD %R9,%RCX |
(284) 0x4414b9 ADD %R9,%RDI |
(284) 0x4414bc ADD %R9,%R8 |
(284) 0x4414bf VMOVSD (%R15,%R11,8),%XMM0 |
(284) 0x4414c5 VMOVSD %XMM0,(%R14,%RCX,8) |
(284) 0x4414cb VMOVSD (%R13,%RDI,8),%XMM5 |
(284) 0x4414d2 VMOVSD %XMM5,(%R12,%R8,8) |
(284) 0x4414d8 MOV 0x78(%RSP),%R9D |
(284) 0x4414dd INC %RBX |
(284) 0x4414e0 LEA (%RBX),%R15D |
(284) 0x4414e3 CMP %R15D,0x50(%RSP) |
(284) 0x4414e8 JLE 441508 |
(284) 0x4414ea MOV 0x48(%RSP),%R12D |
(284) 0x4414ef MOV 0x4c(%RSP),%R11D |
(284) 0x4414f4 MOV 0x54(%RSP),%EDX |
(284) 0x4414f8 MOV %R11D,0x7c(%RSP) |
(284) 0x4414fd SUB %R9D,%R12D |
(284) 0x441500 JMP 4410c8 |
0x441505 NOPL (%RAX) |
0x441508 VZEROUPPER |
0x44150b LEA -0x28(%RBP),%RSP |
0x44150f POP %RBX |
0x441510 POP %R12 |
0x441512 POP %R13 |
0x441514 POP %R14 |
0x441516 POP %R15 |
0x441518 POP %RBP |
0x441519 RET |
0x44151a NOPW (%RAX,%RAX,1) |
(284) 0x441520 MOV 0x7c(%RSP),%ESI |
(284) 0x441524 XOR %R8D,%R8D |
(284) 0x441527 JMP 4413cd |
0x44152c INC %R12D |
0x44152f XOR %EDX,%EDX |
0x441531 JMP 441062 |
0x441536 NOPW %CS:(%RAX,%RAX,1) |
Path / |
Source file and lines | revert.cpp:34-38 |
Module | exec |
nb instructions | 80 |
nb uops | 90 |
loop length | 279 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 10 |
micro-operation queue | 15.00 cycles |
front end | 15.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 5.70 | 8.00 | 6.00 | 6.00 | 8.50 | 5.87 | 5.70 | 8.50 | 8.50 | 8.50 | 5.73 | 6.00 |
cycles | 5.70 | 11.73 | 6.00 | 6.00 | 8.50 | 5.87 | 5.70 | 8.50 | 8.50 | 8.50 | 5.73 | 6.00 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.24-14.34 |
Stall cycles | 0.00 |
Front-end | 15.00 |
Dispatch | 11.73 |
DIV/SQRT | 12.00 |
Overall L1 | 15.00 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 20% |
all | 9% |
load | 10% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 10% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD $-0x80,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x28(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RDI),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x24(%RDI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x2,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA 0x1(%RBX),%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ESI,0x4c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 44150b <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x52b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x2(%RCX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 44150b <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x52b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R14D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %ESI,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EDI,0x54(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 404650 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 404540 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x54(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 44152c <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x54c> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %R12D,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%R12,%R9,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R10D,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R10D,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 44150b <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x52b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R9D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x4c(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%R13),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x54(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x18(%R13),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R15D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV (%R13),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%R13),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R11D,0x7c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R11D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %EAX,%RBX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R15,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 441062 <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x82> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | revert.cpp:34-38 |
Module | exec |
nb instructions | 80 |
nb uops | 90 |
loop length | 279 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 10 |
micro-operation queue | 15.00 cycles |
front end | 15.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 5.70 | 8.00 | 6.00 | 6.00 | 8.50 | 5.87 | 5.70 | 8.50 | 8.50 | 8.50 | 5.73 | 6.00 |
cycles | 5.70 | 11.73 | 6.00 | 6.00 | 8.50 | 5.87 | 5.70 | 8.50 | 8.50 | 8.50 | 5.73 | 6.00 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.24-14.34 |
Stall cycles | 0.00 |
Front-end | 15.00 |
Dispatch | 11.73 |
DIV/SQRT | 12.00 |
Overall L1 | 15.00 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 20% |
all | 9% |
load | 10% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 10% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD $-0x80,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x28(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RDI),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x24(%RDI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x2,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA 0x1(%RBX),%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ESI,0x4c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 44150b <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x52b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x2(%RCX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 44150b <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x52b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R14D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %ESI,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EDI,0x54(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 404650 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 404540 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x54(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 44152c <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x54c> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %R12D,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%R12,%R9,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R10D,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R10D,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 44150b <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x52b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R9D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x4c(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%R13),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x54(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x18(%R13),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R15D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV (%R13),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%R13),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R11D,0x7c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R11D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %EAX,%RBX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R15,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 441062 <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x82> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼revert_kernel(int, int, int, int, clover::Buffer2D | 2.26 | 1.7 |
▼Loop 284 - revert.cpp:36-38 - exec– | 0 | 0.01 |
○Loop 285 - revert.cpp:37-38 - exec | 2.26 | 1.7 |