Function: reset_field_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double> ... | Module: exec | Source: reset_field.cpp:34-38 [...] | Coverage: 2.26% |
---|
Function: reset_field_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double> ... | Module: exec | Source: reset_field.cpp:34-38 [...] | Coverage: 2.26% |
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/scratch_na/users/xoserete/qaas_runs/171-291-1828/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/reset_field.cpp: 34 - 38 |
-------------------------------------------------------------------------------- |
34: #pragma omp parallel for simd collapse(2) |
35: for (int j = (y_min + 1); j < (y_max + 2); j++) { |
36: for (int i = (x_min + 1); i < (x_max + 2); i++) { |
37: density0(i, j) = density1(i, j); |
38: energy0(i, j) = energy1(i, j); |
/scratch_na/users/xoserete/qaas_runs/171-291-1828/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69 |
-------------------------------------------------------------------------------- |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
0x440830 PUSH %RBP |
0x440831 MOV %RSP,%RBP |
0x440834 PUSH %R15 |
0x440836 PUSH %R14 |
0x440838 PUSH %R13 |
0x44083a PUSH %R12 |
0x44083c PUSH %RBX |
0x44083d AND $-0x40,%RSP |
0x440841 ADD $-0x80,%RSP |
0x440845 MOV 0x28(%RDI),%EAX |
0x440848 MOV 0x2c(%RDI),%EDX |
0x44084b MOV 0x20(%RDI),%EBX |
0x44084e MOV 0x24(%RDI),%ECX |
0x440851 ADD $0x2,%EDX |
0x440854 LEA 0x1(%RAX),%R15D |
0x440858 LEA 0x1(%RBX),%ESI |
0x44085b MOV %EDX,0x50(%RSP) |
0x44085f MOV %ESI,0x4c(%RSP) |
0x440863 CMP %EDX,%R15D |
0x440866 JGE 440d5b |
0x44086c MOV %EDX,%EBX |
0x44086e LEA 0x2(%RCX),%R14D |
0x440872 SUB %R15D,%EBX |
0x440875 CMP %R14D,%ESI |
0x440878 JGE 440d5b |
0x44087e MOV %RDI,%R13 |
0x440881 MOV %R14D,%EDI |
0x440884 SUB %ESI,%EDI |
0x440886 MOV %EDI,0x54(%RSP) |
0x44088a CALL 404650 <omp_get_num_threads@plt> |
0x44088f MOV %EAX,%R12D |
0x440892 CALL 404540 <omp_get_thread_num@plt> |
0x440897 XOR %EDX,%EDX |
0x440899 MOV %EAX,%R8D |
0x44089c MOV 0x54(%RSP),%EAX |
0x4408a0 IMUL %EBX,%EAX |
0x4408a3 DIV %R12D |
0x4408a6 MOV %EAX,%R12D |
0x4408a9 CMP %EDX,%R8D |
0x4408ac JB 440d7c |
0x4408b2 IMUL %R12D,%R8D |
0x4408b6 LEA (%R8,%RDX,1),%R9D |
0x4408ba LEA (%R12,%R9,1),%R10D |
0x4408be MOV %R10D,0x48(%RSP) |
0x4408c3 CMP %R10D,%R9D |
0x4408c6 JAE 440d5b |
0x4408cc MOV %R9D,%EAX |
0x4408cf XOR %EDX,%EDX |
0x4408d1 MOV 0x4c(%RSP),%R11D |
0x4408d6 MOV (%R13),%RSI |
0x4408da DIVL 0x54(%RSP) |
0x4408de MOV 0x10(%R13),%RBX |
0x4408e2 MOV %RSI,0x38(%RSP) |
0x4408e7 MOV %RBX,0x28(%RSP) |
0x4408ec ADD %EDX,%R11D |
0x4408ef ADD %R15D,%EAX |
0x4408f2 MOV %R14D,%EDX |
0x4408f5 MOV 0x8(%R13),%R15 |
0x4408f9 MOV 0x18(%R13),%R14 |
0x4408fd MOV %R11D,0x7c(%RSP) |
0x440902 SUB %R11D,%EDX |
0x440905 MOVSXD %EAX,%RBX |
0x440908 MOV %R15,0x40(%RSP) |
0x44090d MOV %R14,0x30(%RSP) |
0x440912 NOPW (%RAX,%RAX,1) |
(281) 0x440918 CMP %EDX,%R12D |
(281) 0x44091b CMOVBE %R12D,%EDX |
(281) 0x44091f LEA (%R9,%RDX,1),%ECX |
(281) 0x440923 MOV %ECX,0x78(%RSP) |
(281) 0x440927 CMP %ECX,%R9D |
(281) 0x44092a JAE 440d2d |
(281) 0x440930 MOV 0x30(%RSP),%R12 |
(281) 0x440935 MOV 0x38(%RSP),%RDI |
(281) 0x44093a LEA -0x1(%RDX),%EAX |
(281) 0x44093d MOV 0x28(%RSP),%RCX |
(281) 0x440942 MOV 0x40(%RSP),%R13 |
(281) 0x440947 MOV (%R12),%RSI |
(281) 0x44094b MOV (%RDI),%R8 |
(281) 0x44094e MOV (%RCX),%R10 |
(281) 0x440951 MOV (%R13),%R11 |
(281) 0x440955 IMUL %RBX,%R8 |
(281) 0x440959 MOV 0x10(%R13),%R15 |
(281) 0x44095d MOV 0x10(%RDI),%R14 |
(281) 0x440961 IMUL %RBX,%RSI |
(281) 0x440965 MOV 0x10(%R12),%R13 |
(281) 0x44096a MOV 0x10(%RCX),%R12 |
(281) 0x44096e IMUL %RBX,%R10 |
(281) 0x440972 IMUL %RBX,%R11 |
(281) 0x440976 MOV %R8,0x60(%RSP) |
(281) 0x44097b MOV %RSI,0x68(%RSP) |
(281) 0x440980 MOV %R10,0x70(%RSP) |
(281) 0x440985 CMP $0x6,%EAX |
(281) 0x440988 JBE 440d70 |
(281) 0x44098e MOVSXD 0x7c(%RSP),%RAX |
(281) 0x440993 LEA (%R8,%RAX,1),%RCX |
(281) 0x440997 LEA (%R11,%RAX,1),%RDI |
(281) 0x44099b LEA (%R14,%RCX,8),%R8 |
(281) 0x44099f MOV 0x70(%RSP),%RCX |
(281) 0x4409a4 LEA (%RSI,%RAX,1),%RSI |
(281) 0x4409a8 LEA (%R15,%RDI,8),%R10 |
(281) 0x4409ac LEA (%R13,%RSI,8),%RDI |
(281) 0x4409b1 ADD %RCX,%RAX |
(281) 0x4409b4 MOV %EDX,%ECX |
(281) 0x4409b6 SHR $0x3,%ECX |
(281) 0x4409b9 LEA (%R12,%RAX,8),%RSI |
(281) 0x4409bd XOR %EAX,%EAX |
(281) 0x4409bf SAL $0x6,%RCX |
(281) 0x4409c3 MOV %RCX,0x58(%RSP) |
(281) 0x4409c8 SUB $0x40,%RCX |
(281) 0x4409cc SHR $0x6,%RCX |
(281) 0x4409d0 INC %RCX |
(281) 0x4409d3 AND $0x7,%ECX |
(281) 0x4409d6 JE 440af4 |
(281) 0x4409dc CMP $0x1,%RCX |
(281) 0x4409e0 JE 440ac9 |
(281) 0x4409e6 CMP $0x2,%RCX |
(281) 0x4409ea JE 440aa9 |
(281) 0x4409f0 CMP $0x3,%RCX |
(281) 0x4409f4 JE 440a89 |
(281) 0x4409fa CMP $0x4,%RCX |
(281) 0x4409fe JE 440a69 |
(281) 0x440a00 CMP $0x5,%RCX |
(281) 0x440a04 JE 440a49 |
(281) 0x440a06 CMP $0x6,%RCX |
(281) 0x440a0a JE 440a29 |
(281) 0x440a0c VMOVUPD (%R10),%ZMM3 |
(281) 0x440a12 MOV $0x40,%EAX |
(281) 0x440a17 VMOVUPD %ZMM3,(%R8) |
(281) 0x440a1d VMOVUPD (%RDI),%ZMM4 |
(281) 0x440a23 VMOVUPD %ZMM4,(%RSI) |
(281) 0x440a29 VMOVUPD (%R10,%RAX,1),%ZMM1 |
(281) 0x440a30 VMOVUPD %ZMM1,(%R8,%RAX,1) |
(281) 0x440a37 VMOVUPD (%RDI,%RAX,1),%ZMM2 |
(281) 0x440a3e VMOVUPD %ZMM2,(%RSI,%RAX,1) |
(281) 0x440a45 ADD $0x40,%RAX |
(281) 0x440a49 VMOVUPD (%R10,%RAX,1),%ZMM0 |
(281) 0x440a50 VMOVUPD %ZMM0,(%R8,%RAX,1) |
(281) 0x440a57 VMOVUPD (%RDI,%RAX,1),%ZMM5 |
(281) 0x440a5e VMOVUPD %ZMM5,(%RSI,%RAX,1) |
(281) 0x440a65 ADD $0x40,%RAX |
(281) 0x440a69 VMOVUPD (%R10,%RAX,1),%ZMM6 |
(281) 0x440a70 VMOVUPD %ZMM6,(%R8,%RAX,1) |
(281) 0x440a77 VMOVUPD (%RDI,%RAX,1),%ZMM7 |
(281) 0x440a7e VMOVUPD %ZMM7,(%RSI,%RAX,1) |
(281) 0x440a85 ADD $0x40,%RAX |
(281) 0x440a89 VMOVUPD (%R10,%RAX,1),%ZMM8 |
(281) 0x440a90 VMOVUPD %ZMM8,(%R8,%RAX,1) |
(281) 0x440a97 VMOVUPD (%RDI,%RAX,1),%ZMM9 |
(281) 0x440a9e VMOVUPD %ZMM9,(%RSI,%RAX,1) |
(281) 0x440aa5 ADD $0x40,%RAX |
(281) 0x440aa9 VMOVUPD (%R10,%RAX,1),%ZMM10 |
(281) 0x440ab0 VMOVUPD %ZMM10,(%R8,%RAX,1) |
(281) 0x440ab7 VMOVUPD (%RDI,%RAX,1),%ZMM11 |
(281) 0x440abe VMOVUPD %ZMM11,(%RSI,%RAX,1) |
(281) 0x440ac5 ADD $0x40,%RAX |
(281) 0x440ac9 VMOVUPD (%R10,%RAX,1),%ZMM12 |
(281) 0x440ad0 VMOVUPD %ZMM12,(%R8,%RAX,1) |
(281) 0x440ad7 VMOVUPD (%RDI,%RAX,1),%ZMM13 |
(281) 0x440ade VMOVUPD %ZMM13,(%RSI,%RAX,1) |
(281) 0x440ae5 ADD $0x40,%RAX |
(281) 0x440ae9 CMP %RAX,0x58(%RSP) |
(281) 0x440aee JE 440c01 |
(282) 0x440af4 VMOVUPD (%R10,%RAX,1),%ZMM14 |
(282) 0x440afb VMOVUPD %ZMM14,(%R8,%RAX,1) |
(282) 0x440b02 VMOVUPD (%RDI,%RAX,1),%ZMM15 |
(282) 0x440b09 VMOVUPD %ZMM15,(%RSI,%RAX,1) |
(282) 0x440b10 VMOVUPD 0x40(%R10,%RAX,1),%ZMM3 |
(282) 0x440b18 VMOVUPD %ZMM3,0x40(%R8,%RAX,1) |
(282) 0x440b20 VMOVUPD 0x40(%RDI,%RAX,1),%ZMM4 |
(282) 0x440b28 VMOVUPD %ZMM4,0x40(%RSI,%RAX,1) |
(282) 0x440b30 VMOVUPD 0x80(%R10,%RAX,1),%ZMM1 |
(282) 0x440b38 VMOVUPD %ZMM1,0x80(%R8,%RAX,1) |
(282) 0x440b40 VMOVUPD 0x80(%RDI,%RAX,1),%ZMM2 |
(282) 0x440b48 VMOVUPD %ZMM2,0x80(%RSI,%RAX,1) |
(282) 0x440b50 VMOVUPD 0xc0(%R10,%RAX,1),%ZMM0 |
(282) 0x440b58 VMOVUPD %ZMM0,0xc0(%R8,%RAX,1) |
(282) 0x440b60 VMOVUPD 0xc0(%RDI,%RAX,1),%ZMM5 |
(282) 0x440b68 VMOVUPD %ZMM5,0xc0(%RSI,%RAX,1) |
(282) 0x440b70 VMOVUPD 0x100(%R10,%RAX,1),%ZMM6 |
(282) 0x440b78 VMOVUPD %ZMM6,0x100(%R8,%RAX,1) |
(282) 0x440b80 VMOVUPD 0x100(%RDI,%RAX,1),%ZMM7 |
(282) 0x440b88 VMOVUPD %ZMM7,0x100(%RSI,%RAX,1) |
(282) 0x440b90 VMOVUPD 0x140(%R10,%RAX,1),%ZMM8 |
(282) 0x440b98 VMOVUPD %ZMM8,0x140(%R8,%RAX,1) |
(282) 0x440ba0 VMOVUPD 0x140(%RDI,%RAX,1),%ZMM9 |
(282) 0x440ba8 VMOVUPD %ZMM9,0x140(%RSI,%RAX,1) |
(282) 0x440bb0 VMOVUPD 0x180(%R10,%RAX,1),%ZMM10 |
(282) 0x440bb8 VMOVUPD %ZMM10,0x180(%R8,%RAX,1) |
(282) 0x440bc0 VMOVUPD 0x180(%RDI,%RAX,1),%ZMM11 |
(282) 0x440bc8 VMOVUPD %ZMM11,0x180(%RSI,%RAX,1) |
(282) 0x440bd0 VMOVUPD 0x1c0(%R10,%RAX,1),%ZMM12 |
(282) 0x440bd8 VMOVUPD %ZMM12,0x1c0(%R8,%RAX,1) |
(282) 0x440be0 VMOVUPD 0x1c0(%RDI,%RAX,1),%ZMM13 |
(282) 0x440be8 VMOVUPD %ZMM13,0x1c0(%RSI,%RAX,1) |
(282) 0x440bf0 ADD $0x200,%RAX |
(282) 0x440bf6 CMP %RAX,0x58(%RSP) |
(282) 0x440bfb JNE 440af4 |
(281) 0x440c01 MOV 0x7c(%RSP),%R10D |
(281) 0x440c06 MOV %EDX,%R8D |
(281) 0x440c09 AND $-0x8,%R8D |
(281) 0x440c0d ADD %R8D,%R9D |
(281) 0x440c10 LEA (%R8,%R10,1),%ESI |
(281) 0x440c14 TEST $0x7,%DL |
(281) 0x440c17 JE 440d28 |
(281) 0x440c1d SUB %R8D,%EDX |
(281) 0x440c20 LEA -0x1(%RDX),%EDI |
(281) 0x440c23 CMP $0x2,%EDI |
(281) 0x440c26 JBE 440c7f |
(281) 0x440c28 MOVSXD 0x7c(%RSP),%RCX |
(281) 0x440c2d MOV 0x60(%RSP),%R10 |
(281) 0x440c32 MOV 0x68(%RSP),%RDI |
(281) 0x440c37 LEA (%R11,%RCX,1),%RAX |
(281) 0x440c3b ADD %RCX,%R10 |
(281) 0x440c3e ADD %R8,%RAX |
(281) 0x440c41 ADD %RCX,%RDI |
(281) 0x440c44 ADD %R8,%R10 |
(281) 0x440c47 VMOVUPD (%R15,%RAX,8),%YMM14 |
(281) 0x440c4d MOV 0x70(%RSP),%RAX |
(281) 0x440c52 ADD %R8,%RDI |
(281) 0x440c55 VMOVUPD %YMM14,(%R14,%R10,8) |
(281) 0x440c5b ADD %RAX,%RCX |
(281) 0x440c5e VMOVUPD (%R13,%RDI,8),%YMM15 |
(281) 0x440c65 ADD %R8,%RCX |
(281) 0x440c68 VMOVUPD %YMM15,(%R12,%RCX,8) |
(281) 0x440c6e TEST $0x3,%DL |
(281) 0x440c71 JE 440d28 |
(281) 0x440c77 AND $-0x4,%EDX |
(281) 0x440c7a ADD %EDX,%R9D |
(281) 0x440c7d ADD %EDX,%ESI |
(281) 0x440c7f MOVSXD %ESI,%R10 |
(281) 0x440c82 MOV 0x60(%RSP),%RCX |
(281) 0x440c87 MOV 0x68(%RSP),%RDI |
(281) 0x440c8c LEA (%R11,%R10,1),%RDX |
(281) 0x440c90 VMOVSD (%R15,%RDX,8),%XMM3 |
(281) 0x440c96 LEA (%RCX,%R10,1),%R8 |
(281) 0x440c9a LEA (%RDI,%R10,1),%RAX |
(281) 0x440c9e LEA 0x1(%R9),%EDX |
(281) 0x440ca2 VMOVSD %XMM3,(%R14,%R8,8) |
(281) 0x440ca8 MOV 0x70(%RSP),%R8 |
(281) 0x440cad VMOVSD (%R13,%RAX,8),%XMM4 |
(281) 0x440cb4 LEA 0x1(%RSI),%EAX |
(281) 0x440cb7 ADD %R8,%R10 |
(281) 0x440cba VMOVSD %XMM4,(%R12,%R10,8) |
(281) 0x440cc0 MOV 0x78(%RSP),%R10D |
(281) 0x440cc5 CMP %R10D,%EDX |
(281) 0x440cc8 JAE 440d28 |
(281) 0x440cca CLTQ |
(281) 0x440ccc ADD $0x2,%R9D |
(281) 0x440cd0 ADD $0x2,%ESI |
(281) 0x440cd3 LEA (%R11,%RAX,1),%RDX |
(281) 0x440cd7 VMOVSD (%R15,%RDX,8),%XMM1 |
(281) 0x440cdd LEA (%RCX,%RAX,1),%RDX |
(281) 0x440ce1 VMOVSD %XMM1,(%R14,%RDX,8) |
(281) 0x440ce7 LEA (%RDI,%RAX,1),%RDX |
(281) 0x440ceb ADD %R8,%RAX |
(281) 0x440cee VMOVSD (%R13,%RDX,8),%XMM2 |
(281) 0x440cf5 VMOVSD %XMM2,(%R12,%RAX,8) |
(281) 0x440cfb CMP %R10D,%R9D |
(281) 0x440cfe JAE 440d28 |
(281) 0x440d00 MOVSXD %ESI,%R9 |
(281) 0x440d03 ADD %R9,%R11 |
(281) 0x440d06 ADD %R9,%RCX |
(281) 0x440d09 ADD %R9,%RDI |
(281) 0x440d0c ADD %R9,%R8 |
(281) 0x440d0f VMOVSD (%R15,%R11,8),%XMM0 |
(281) 0x440d15 VMOVSD %XMM0,(%R14,%RCX,8) |
(281) 0x440d1b VMOVSD (%R13,%RDI,8),%XMM5 |
(281) 0x440d22 VMOVSD %XMM5,(%R12,%R8,8) |
(281) 0x440d28 MOV 0x78(%RSP),%R9D |
(281) 0x440d2d INC %RBX |
(281) 0x440d30 LEA (%RBX),%R15D |
(281) 0x440d33 CMP %R15D,0x50(%RSP) |
(281) 0x440d38 JLE 440d58 |
(281) 0x440d3a MOV 0x48(%RSP),%R12D |
(281) 0x440d3f MOV 0x4c(%RSP),%R11D |
(281) 0x440d44 MOV 0x54(%RSP),%EDX |
(281) 0x440d48 MOV %R11D,0x7c(%RSP) |
(281) 0x440d4d SUB %R9D,%R12D |
(281) 0x440d50 JMP 440918 |
0x440d55 NOPL (%RAX) |
0x440d58 VZEROUPPER |
0x440d5b LEA -0x28(%RBP),%RSP |
0x440d5f POP %RBX |
0x440d60 POP %R12 |
0x440d62 POP %R13 |
0x440d64 POP %R14 |
0x440d66 POP %R15 |
0x440d68 POP %RBP |
0x440d69 RET |
0x440d6a NOPW (%RAX,%RAX,1) |
(281) 0x440d70 MOV 0x7c(%RSP),%ESI |
(281) 0x440d74 XOR %R8D,%R8D |
(281) 0x440d77 JMP 440c1d |
0x440d7c INC %R12D |
0x440d7f XOR %EDX,%EDX |
0x440d81 JMP 4408b2 |
0x440d86 NOPW %CS:(%RAX,%RAX,1) |
Path / |
Source file and lines | reset_field.cpp:34-38 |
Module | exec |
nb instructions | 80 |
nb uops | 90 |
loop length | 279 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 10 |
micro-operation queue | 15.00 cycles |
front end | 15.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 5.70 | 8.00 | 6.00 | 6.00 | 8.50 | 5.87 | 5.70 | 8.50 | 8.50 | 8.50 | 5.73 | 6.00 |
cycles | 5.70 | 11.73 | 6.00 | 6.00 | 8.50 | 5.87 | 5.70 | 8.50 | 8.50 | 8.50 | 5.73 | 6.00 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.24-14.34 |
Stall cycles | 0.00 |
Front-end | 15.00 |
Dispatch | 11.73 |
DIV/SQRT | 12.00 |
Overall L1 | 15.00 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 20% |
all | 9% |
load | 10% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 10% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD $-0x80,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x28(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RDI),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x24(%RDI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x2,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA 0x1(%RBX),%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ESI,0x4c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 440d5b <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x52b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x2(%RCX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 440d5b <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x52b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R14D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %ESI,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EDI,0x54(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 404650 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 404540 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x54(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 440d7c <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x54c> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %R12D,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%R12,%R9,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R10D,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R10D,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 440d5b <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x52b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R9D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x4c(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R13),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x54(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x10(%R13),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R15D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x8(%R13),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%R13),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R11D,0x7c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R11D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %EAX,%RBX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R15,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 4408b2 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x82> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | reset_field.cpp:34-38 |
Module | exec |
nb instructions | 80 |
nb uops | 90 |
loop length | 279 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 10 |
micro-operation queue | 15.00 cycles |
front end | 15.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 5.70 | 8.00 | 6.00 | 6.00 | 8.50 | 5.87 | 5.70 | 8.50 | 8.50 | 8.50 | 5.73 | 6.00 |
cycles | 5.70 | 11.73 | 6.00 | 6.00 | 8.50 | 5.87 | 5.70 | 8.50 | 8.50 | 8.50 | 5.73 | 6.00 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.24-14.34 |
Stall cycles | 0.00 |
Front-end | 15.00 |
Dispatch | 11.73 |
DIV/SQRT | 12.00 |
Overall L1 | 15.00 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 20% |
all | 9% |
load | 10% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 10% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD $-0x80,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x28(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RDI),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x24(%RDI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x2,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA 0x1(%RBX),%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ESI,0x4c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 440d5b <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x52b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x2(%RCX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 440d5b <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x52b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R14D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %ESI,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EDI,0x54(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 404650 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 404540 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x54(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 440d7c <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x54c> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %R12D,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%R12,%R9,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R10D,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R10D,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 440d5b <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x52b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R9D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x4c(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R13),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x54(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x10(%R13),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R15D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x8(%R13),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%R13),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R11D,0x7c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R11D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %EAX,%RBX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R15,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 4408b2 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x82> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼reset_field_kernel(int, int, int, int, clover::Buffer2D | 2.26 | 1.7 |
▼Loop 281 - reset_field.cpp:36-38 - exec– | 0 | 0.01 |
○Loop 282 - reset_field.cpp:37-38 - exec | 2.26 | 1.7 |