Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ... | Module: exec | Source: advec_mom.cpp:95-100 [...] | Coverage: 3.01% |
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Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ... | Module: exec | Source: advec_mom.cpp:95-100 [...] | Coverage: 3.01% |
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/scratch_na/users/xoserete/qaas_runs/171-291-1828/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69 |
-------------------------------------------------------------------------------- |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
/scratch_na/users/xoserete/qaas_runs/171-291-1828/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp: 95 - 100 |
-------------------------------------------------------------------------------- |
95: #pragma omp parallel for simd collapse(2) |
96: for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) { |
97: for (int i = (x_min - 1 + 1); i < (x_max + 2 + 2); i++) { |
98: node_mass_post(i, j) = 0.25 * (density1(i + 0, j - 1) * post_vol(i + 0, j - 1) + density1(i, j) * post_vol(i, j) + |
99: density1(i - 1, j - 1) * post_vol(i - 1, j - 1) + density1(i - 1, j + 0) * post_vol(i - 1, j + 0)); |
100: node_mass_pre(i, j) = node_mass_post(i, j) - node_flux(i - 1, j + 0) + node_flux(i, j); |
0x42c5f0 PUSH %RBP |
0x42c5f1 MOV %RSP,%RBP |
0x42c5f4 PUSH %R15 |
0x42c5f6 PUSH %R14 |
0x42c5f8 PUSH %R13 |
0x42c5fa PUSH %R12 |
0x42c5fc PUSH %RBX |
0x42c5fd MOV %RDI,%RBX |
0x42c600 AND $-0x40,%RSP |
0x42c604 SUB $0x100,%RSP |
0x42c60b MOV 0x30(%RDI),%EAX |
0x42c60e MOV 0x34(%RDI),%ECX |
0x42c611 MOV 0x28(%RDI),%EDX |
0x42c614 MOV 0x2c(%RDI),%EDI |
0x42c617 ADD $0x3,%ECX |
0x42c61a LEA 0x1(%RAX),%R12D |
0x42c61e MOV %EDX,0x6c(%RSP) |
0x42c622 MOV %ECX,0x70(%RSP) |
0x42c626 CMP %ECX,%R12D |
0x42c629 JGE 42ce8b |
0x42c62f MOV %ECX,%R14D |
0x42c632 LEA 0x4(%RDI),%R15D |
0x42c636 SUB %R12D,%R14D |
0x42c639 CMP %R15D,%EDX |
0x42c63c JGE 42ce8b |
0x42c642 MOV %R15D,%ESI |
0x42c645 SUB %EDX,%ESI |
0x42c647 MOV %ESI,0x74(%RSP) |
0x42c64b CALL 404650 <omp_get_num_threads@plt> |
0x42c650 MOV %EAX,%R13D |
0x42c653 CALL 404540 <omp_get_thread_num@plt> |
0x42c658 XOR %EDX,%EDX |
0x42c65a MOV %EAX,%R8D |
0x42c65d MOV 0x74(%RSP),%EAX |
0x42c661 IMUL %R14D,%EAX |
0x42c665 DIV %R13D |
0x42c668 MOV %EAX,%ECX |
0x42c66a CMP %EDX,%R8D |
0x42c66d JB 42ceae |
0x42c673 IMUL %ECX,%R8D |
0x42c677 LEA (%R8,%RDX,1),%R9D |
0x42c67b LEA (%RCX,%R9,1),%R10D |
0x42c67f MOV %R10D,0x68(%RSP) |
0x42c684 CMP %R10D,%R9D |
0x42c687 JAE 42ce8b |
0x42c68d MOV %R9D,%EAX |
0x42c690 XOR %EDX,%EDX |
0x42c692 MOV 0x6c(%RSP),%R11D |
0x42c697 MOV (%RBX),%RDI |
0x42c69a DIVL 0x74(%RSP) |
0x42c69e MOV 0x10(%RBX),%R14 |
0x42c6a2 MOV 0x8(%RBX),%RSI |
0x42c6a6 MOV %R9D,0xfc(%RSP) |
0x42c6ae VMOVSD 0x3214a(%RIP),%XMM3 |
0x42c6b6 MOV %RDI,0x40(%RSP) |
0x42c6bb MOV %R14,0x30(%RSP) |
0x42c6c0 MOV %RSI,0x28(%RSP) |
0x42c6c5 MOV %R15D,%R8D |
0x42c6c8 MOV 0x20(%RBX),%R15 |
0x42c6cc MOV 0x18(%RBX),%RBX |
0x42c6d0 VBROADCASTSD %XMM3,%YMM4 |
0x42c6d5 VBROADCASTSD %XMM3,%ZMM2 |
0x42c6db MOV %R15,0x38(%RSP) |
0x42c6e0 MOV %RBX,0x20(%RSP) |
0x42c6e5 ADD %R12D,%EAX |
0x42c6e8 ADD %EDX,%R11D |
0x42c6eb MOVSXD %EAX,%R12 |
0x42c6ee MOV %R11D,0xf8(%RSP) |
0x42c6f6 SUB %R11D,%R8D |
0x42c6f9 MOV %EAX,0xb4(%RSP) |
0x42c700 MOV %R12,0x98(%RSP) |
0x42c708 NOPL (%RAX,%RAX,1) |
(186) 0x42c710 CMP %R8D,%ECX |
(186) 0x42c713 CMOVBE %ECX,%R8D |
(186) 0x42c717 MOV 0xfc(%RSP),%ECX |
(186) 0x42c71e LEA (%RCX,%R8,1),%R13D |
(186) 0x42c722 MOV %R8D,%R9D |
(186) 0x42c725 MOV %R13D,0xb0(%RSP) |
(186) 0x42c72d CMP %R13D,%ECX |
(186) 0x42c730 JAE 42ce40 |
(186) 0x42c736 MOV 0xb4(%RSP),%R8D |
(186) 0x42c73e MOV 0x40(%RSP),%RAX |
(186) 0x42c743 MOV 0x38(%RSP),%RDI |
(186) 0x42c748 MOV 0x98(%RSP),%R15 |
(186) 0x42c750 LEA -0x1(%R8),%R10D |
(186) 0x42c754 MOV 0x30(%RSP),%RSI |
(186) 0x42c759 MOV 0x10(%RAX),%R13 |
(186) 0x42c75d MOV (%RDI),%RCX |
(186) 0x42c760 MOVSXD %R10D,%R11 |
(186) 0x42c763 MOV (%RAX),%R10 |
(186) 0x42c766 MOV %R15,%RAX |
(186) 0x42c769 MOV %R11,%R14 |
(186) 0x42c76c MOV 0x28(%RSP),%R8 |
(186) 0x42c771 MOV 0x10(%RDI),%RDX |
(186) 0x42c775 IMUL %R10,%R14 |
(186) 0x42c779 MOV 0x10(%RSI),%RBX |
(186) 0x42c77d IMUL %RCX,%R11 |
(186) 0x42c781 MOV (%R8),%RDI |
(186) 0x42c784 IMUL %R15,%R10 |
(186) 0x42c788 MOV %RBX,0xe0(%RSP) |
(186) 0x42c790 LEA -0x1(%R9),%EBX |
(186) 0x42c794 IMUL %R15,%RCX |
(186) 0x42c798 MOV %R14,0xb8(%RSP) |
(186) 0x42c7a0 IMUL (%RSI),%R15 |
(186) 0x42c7a4 MOV %R11,0xc0(%RSP) |
(186) 0x42c7ac IMUL %RAX,%RDI |
(186) 0x42c7b0 MOV %R10,0xc8(%RSP) |
(186) 0x42c7b8 MOV %RCX,0xd0(%RSP) |
(186) 0x42c7c0 MOV %R15,0xd8(%RSP) |
(186) 0x42c7c8 MOV 0x10(%R8),%R15 |
(186) 0x42c7cc MOV 0x20(%RSP),%R8 |
(186) 0x42c7d1 MOV %RDI,0xf0(%RSP) |
(186) 0x42c7d9 MOV (%R8),%R12 |
(186) 0x42c7dc MOV 0x10(%R8),%RSI |
(186) 0x42c7e0 IMUL %RAX,%R12 |
(186) 0x42c7e4 MOV %RSI,0xe8(%RSP) |
(186) 0x42c7ec MOV %R12,0xa8(%RSP) |
(186) 0x42c7f4 CMP $0x6,%EBX |
(186) 0x42c7f7 JBE 42cea0 |
(186) 0x42c7fd MOVSXD 0xf8(%RSP),%RAX |
(186) 0x42c805 LEA (%R14,%RAX,1),%R8 |
(186) 0x42c809 LEA (%R11,%RAX,1),%RDI |
(186) 0x42c80d ADD %RAX,%RCX |
(186) 0x42c810 SAL $0x3,%R8 |
(186) 0x42c814 SAL $0x3,%RDI |
(186) 0x42c818 LEA (%R10,%RAX,1),%RBX |
(186) 0x42c81c SAL $0x3,%RBX |
(186) 0x42c820 SAL $0x3,%RCX |
(186) 0x42c824 LEA (%R13,%R8,1),%R14 |
(186) 0x42c829 LEA (%RDX,%RDI,1),%R11 |
(186) 0x42c82d LEA (%R13,%RBX,1),%R10 |
(186) 0x42c832 MOV %R14,0x80(%RSP) |
(186) 0x42c83a LEA (%RDX,%RCX,1),%R14 |
(186) 0x42c83e MOV %R11,0x88(%RSP) |
(186) 0x42c846 LEA -0x8(%R13,%RBX,1),%R11 |
(186) 0x42c84b LEA -0x8(%RDX,%RCX,1),%RBX |
(186) 0x42c850 MOV 0xd8(%RSP),%RCX |
(186) 0x42c858 LEA -0x8(%RDX,%RDI,1),%RSI |
(186) 0x42c85d MOV %R10,0x90(%RSP) |
(186) 0x42c865 MOV 0xf0(%RSP),%RDI |
(186) 0x42c86d LEA -0x8(%R13,%R8,1),%R10 |
(186) 0x42c872 MOV 0xe0(%RSP),%R8 |
(186) 0x42c87a ADD %RAX,%RCX |
(186) 0x42c87d MOV %RSI,0x78(%RSP) |
(186) 0x42c882 MOV 0xe8(%RSP),%RSI |
(186) 0x42c88a LEA (%R8,%RCX,8),%R8 |
(186) 0x42c88e LEA (%RDI,%RAX,1),%RCX |
(186) 0x42c892 ADD %R12,%RAX |
(186) 0x42c895 LEA (%RSI,%RAX,8),%RSI |
(186) 0x42c899 MOV %R9D,%EAX |
(186) 0x42c89c SAL $0x3,%RCX |
(186) 0x42c8a0 SHR $0x3,%EAX |
(186) 0x42c8a3 LEA -0x8(%R15,%RCX,1),%RDI |
(186) 0x42c8a8 ADD %R15,%RCX |
(186) 0x42c8ab MOV %RAX,%R12 |
(186) 0x42c8ae SAL $0x6,%RAX |
(186) 0x42c8b2 MOV %RAX,0xa0(%RSP) |
(186) 0x42c8ba XOR %EAX,%EAX |
(186) 0x42c8bc AND $0x1,%R12D |
(186) 0x42c8c0 JE 42c954 |
(186) 0x42c8c6 MOV 0x90(%RSP),%RAX |
(186) 0x42c8ce VMOVUPD (%R11),%ZMM5 |
(186) 0x42c8d4 MOV 0x88(%RSP),%R12 |
(186) 0x42c8dc VMOVUPD (%R10),%ZMM8 |
(186) 0x42c8e2 VMOVUPD (%RAX),%ZMM7 |
(186) 0x42c8e8 VMULPD (%RBX),%ZMM5,%ZMM1 |
(186) 0x42c8ee VMOVUPD (%R12),%ZMM6 |
(186) 0x42c8f5 MOV 0x80(%RSP),%RAX |
(186) 0x42c8fd VMULPD (%R14),%ZMM7,%ZMM0 |
(186) 0x42c903 MOV 0xa0(%RSP),%R12 |
(186) 0x42c90b VFMADD231PD (%RAX),%ZMM6,%ZMM0 |
(186) 0x42c911 MOV 0x78(%RSP),%RAX |
(186) 0x42c916 VFMADD231PD (%RAX),%ZMM8,%ZMM1 |
(186) 0x42c91c MOV $0x40,%EAX |
(186) 0x42c921 VADDPD %ZMM1,%ZMM0,%ZMM9 |
(186) 0x42c927 VMULPD %ZMM2,%ZMM9,%ZMM10 |
(186) 0x42c92d VMOVUPD %ZMM10,(%R8) |
(186) 0x42c933 VMOVUPD (%RCX),%ZMM11 |
(186) 0x42c939 VSUBPD (%RDI),%ZMM11,%ZMM12 |
(186) 0x42c93f VADDPD %ZMM10,%ZMM12,%ZMM13 |
(186) 0x42c945 VMOVUPD %ZMM13,(%RSI) |
(186) 0x42c94b CMP %R12,%RAX |
(186) 0x42c94e JE 42ca87 |
(186) 0x42c954 MOV %R15,0x58(%RSP) |
(186) 0x42c959 MOV 0x88(%RSP),%R12 |
(186) 0x42c961 MOV %R9D,0x64(%RSP) |
(186) 0x42c966 MOV 0x80(%RSP),%R9 |
(186) 0x42c96e MOV %RDX,0x50(%RSP) |
(186) 0x42c973 MOV 0x90(%RSP),%RDX |
(186) 0x42c97b MOV %R13,0x48(%RSP) |
(186) 0x42c980 MOV 0x78(%RSP),%R13 |
(187) 0x42c985 VMOVUPD (%RDX,%RAX,1),%ZMM14 |
(187) 0x42c98c VMOVUPD (%R11,%RAX,1),%ZMM0 |
(187) 0x42c993 VMOVUPD (%R12,%RAX,1),%ZMM7 |
(187) 0x42c99a VMOVUPD (%R10,%RAX,1),%ZMM5 |
(187) 0x42c9a1 VMULPD (%R14,%RAX,1),%ZMM14,%ZMM15 |
(187) 0x42c9a8 MOV 0xa0(%RSP),%R15 |
(187) 0x42c9b0 VMULPD (%RBX,%RAX,1),%ZMM0,%ZMM6 |
(187) 0x42c9b7 VFMADD231PD (%R9,%RAX,1),%ZMM7,%ZMM15 |
(187) 0x42c9be VFMADD231PD (%R13,%RAX,1),%ZMM5,%ZMM6 |
(187) 0x42c9c6 VADDPD %ZMM6,%ZMM15,%ZMM1 |
(187) 0x42c9cc VMULPD %ZMM2,%ZMM1,%ZMM8 |
(187) 0x42c9d2 VMOVUPD %ZMM8,(%R8,%RAX,1) |
(187) 0x42c9d9 VMOVUPD (%RCX,%RAX,1),%ZMM9 |
(187) 0x42c9e0 VSUBPD (%RDI,%RAX,1),%ZMM9,%ZMM10 |
(187) 0x42c9e7 VADDPD %ZMM8,%ZMM10,%ZMM11 |
(187) 0x42c9ed VMOVUPD %ZMM11,(%RSI,%RAX,1) |
(187) 0x42c9f4 VMOVUPD 0x40(%RDX,%RAX,1),%ZMM12 |
(187) 0x42c9fc VMOVUPD 0x40(%R11,%RAX,1),%ZMM15 |
(187) 0x42ca04 VMOVUPD 0x40(%R12,%RAX,1),%ZMM14 |
(187) 0x42ca0c VMOVUPD 0x40(%R10,%RAX,1),%ZMM7 |
(187) 0x42ca14 VMULPD 0x40(%R14,%RAX,1),%ZMM12,%ZMM13 |
(187) 0x42ca1c VMULPD 0x40(%RBX,%RAX,1),%ZMM15,%ZMM0 |
(187) 0x42ca24 VFMADD231PD 0x40(%R9,%RAX,1),%ZMM14,%ZMM13 |
(187) 0x42ca2c VFMADD231PD 0x40(%R13,%RAX,1),%ZMM7,%ZMM0 |
(187) 0x42ca34 VADDPD %ZMM0,%ZMM13,%ZMM6 |
(187) 0x42ca3a VMULPD %ZMM2,%ZMM6,%ZMM8 |
(187) 0x42ca40 VMOVUPD %ZMM8,0x40(%R8,%RAX,1) |
(187) 0x42ca48 VMOVUPD 0x40(%RCX,%RAX,1),%ZMM5 |
(187) 0x42ca50 VSUBPD 0x40(%RDI,%RAX,1),%ZMM5,%ZMM1 |
(187) 0x42ca58 VADDPD %ZMM8,%ZMM1,%ZMM9 |
(187) 0x42ca5e VMOVUPD %ZMM9,0x40(%RSI,%RAX,1) |
(187) 0x42ca66 SUB $-0x80,%RAX |
(187) 0x42ca6a CMP %R15,%RAX |
(187) 0x42ca6d JNE 42c985 |
(186) 0x42ca73 MOV 0x64(%RSP),%R9D |
(186) 0x42ca78 MOV 0x58(%RSP),%R15 |
(186) 0x42ca7d MOV 0x50(%RSP),%RDX |
(186) 0x42ca82 MOV 0x48(%RSP),%R13 |
(186) 0x42ca87 MOV 0xf8(%RSP),%EAX |
(186) 0x42ca8e MOV %R9D,%ESI |
(186) 0x42ca91 AND $-0x8,%ESI |
(186) 0x42ca94 ADD %ESI,0xfc(%RSP) |
(186) 0x42ca9b ADD %ESI,%EAX |
(186) 0x42ca9d TEST $0x7,%R9B |
(186) 0x42caa1 JE 42ce30 |
(186) 0x42caa7 MOV %R9D,%EDI |
(186) 0x42caaa SUB %ESI,%EDI |
(186) 0x42caac LEA -0x1(%RDI),%R14D |
(186) 0x42cab0 CMP $0x2,%R14D |
(186) 0x42cab4 JBE 42cba9 |
(186) 0x42caba MOVSXD 0xf8(%RSP),%RCX |
(186) 0x42cac2 MOV 0xc0(%RSP),%R11 |
(186) 0x42caca MOV 0xc8(%RSP),%RBX |
(186) 0x42cad2 MOV 0xb8(%RSP),%R10 |
(186) 0x42cada LEA (%R11,%RCX,1),%R9 |
(186) 0x42cade MOV 0xd8(%RSP),%R8 |
(186) 0x42cae6 MOV 0xf0(%RSP),%R14 |
(186) 0x42caee LEA (%RBX,%RCX,1),%R11 |
(186) 0x42caf2 MOV 0xd0(%RSP),%RBX |
(186) 0x42cafa LEA (%R10,%RCX,1),%R10 |
(186) 0x42cafe ADD %RSI,%R9 |
(186) 0x42cb01 ADD %RSI,%R11 |
(186) 0x42cb04 ADD %RSI,%R10 |
(186) 0x42cb07 LEA (%R8,%RCX,1),%R12 |
(186) 0x42cb0b ADD %RCX,%RBX |
(186) 0x42cb0e VMOVUPD (%R13,%R11,8),%YMM10 |
(186) 0x42cb15 VMOVUPD (%R13,%R10,8),%YMM12 |
(186) 0x42cb1c LEA (%R14,%RCX,1),%R8 |
(186) 0x42cb20 ADD %RSI,%RBX |
(186) 0x42cb23 VMOVUPD -0x8(%R13,%R10,8),%YMM15 |
(186) 0x42cb2a MOV 0xa8(%RSP),%R14 |
(186) 0x42cb32 ADD %RSI,%R8 |
(186) 0x42cb35 VMOVUPD -0x8(%RDX,%RBX,8),%YMM13 |
(186) 0x42cb3b VMULPD (%RDX,%RBX,8),%YMM10,%YMM11 |
(186) 0x42cb40 ADD %RSI,%R12 |
(186) 0x42cb43 ADD %R14,%RCX |
(186) 0x42cb46 MOV 0xe8(%RSP),%R10 |
(186) 0x42cb4e VMULPD -0x8(%R13,%R11,8),%YMM13,%YMM14 |
(186) 0x42cb55 ADD %RSI,%RCX |
(186) 0x42cb58 MOV 0xe0(%RSP),%RSI |
(186) 0x42cb60 VFMADD231PD (%RDX,%R9,8),%YMM12,%YMM11 |
(186) 0x42cb66 VFMADD231PD -0x8(%RDX,%R9,8),%YMM15,%YMM14 |
(186) 0x42cb6d VADDPD %YMM14,%YMM11,%YMM0 |
(186) 0x42cb72 VMULPD %YMM4,%YMM0,%YMM6 |
(186) 0x42cb76 VMOVUPD %YMM6,(%RSI,%R12,8) |
(186) 0x42cb7c VMOVUPD (%R15,%R8,8),%YMM7 |
(186) 0x42cb82 VSUBPD -0x8(%R15,%R8,8),%YMM7,%YMM8 |
(186) 0x42cb89 VADDPD %YMM6,%YMM8,%YMM5 |
(186) 0x42cb8d VMOVUPD %YMM5,(%R10,%RCX,8) |
(186) 0x42cb93 TEST $0x3,%DIL |
(186) 0x42cb97 JE 42ce30 |
(186) 0x42cb9d AND $-0x4,%EDI |
(186) 0x42cba0 ADD %EDI,0xfc(%RSP) |
(186) 0x42cba7 ADD %EDI,%EAX |
(186) 0x42cba9 MOV 0xc8(%RSP),%R12 |
(186) 0x42cbb1 MOVSXD %EAX,%RCX |
(186) 0x42cbb4 MOV 0xb8(%RSP),%RDI |
(186) 0x42cbbc MOV 0xc0(%RSP),%RBX |
(186) 0x42cbc4 LEA (%R12,%RCX,1),%R14 |
(186) 0x42cbc8 LEA (%RDI,%RCX,1),%R9 |
(186) 0x42cbcc LEA (%R13,%R14,8),%R10 |
(186) 0x42cbd1 MOV 0xd0(%RSP),%R14 |
(186) 0x42cbd9 LEA (%RBX,%RCX,1),%R11 |
(186) 0x42cbdd LEA (%R13,%R9,8),%R8 |
(186) 0x42cbe2 LEA (%RDX,%R11,8),%R9 |
(186) 0x42cbe6 LEA (%R14,%RCX,1),%RSI |
(186) 0x42cbea VMOVSD (%R9),%XMM10 |
(186) 0x42cbef LEA (%RDX,%RSI,8),%R11 |
(186) 0x42cbf3 LEA -0x1(%RAX),%ESI |
(186) 0x42cbf6 MOVSXD %ESI,%RSI |
(186) 0x42cbf9 VMOVSD (%R11),%XMM1 |
(186) 0x42cbfe ADD %RSI,%R14 |
(186) 0x42cc01 ADD %RSI,%R12 |
(186) 0x42cc04 ADD %RSI,%RBX |
(186) 0x42cc07 ADD %RSI,%RDI |
(186) 0x42cc0a VMOVSD (%RDX,%R14,8),%XMM11 |
(186) 0x42cc10 VMULSD (%R10),%XMM1,%XMM9 |
(186) 0x42cc15 VMOVSD (%RDX,%RBX,8),%XMM13 |
(186) 0x42cc1a MOV 0xe0(%RSP),%RBX |
(186) 0x42cc22 VMULSD (%R13,%R12,8),%XMM11,%XMM12 |
(186) 0x42cc29 MOV 0xf0(%RSP),%R12 |
(186) 0x42cc31 LEA (%R12,%RCX,1),%R14 |
(186) 0x42cc35 ADD %R12,%RSI |
(186) 0x42cc38 MOV 0xb0(%RSP),%R12D |
(186) 0x42cc40 VFMADD231SD (%R8),%XMM10,%XMM9 |
(186) 0x42cc45 VFMADD231SD (%R13,%RDI,8),%XMM13,%XMM12 |
(186) 0x42cc4c MOV 0xd8(%RSP),%RDI |
(186) 0x42cc54 ADD %RCX,%RDI |
(186) 0x42cc57 VADDSD %XMM12,%XMM9,%XMM14 |
(186) 0x42cc5c VMULSD %XMM3,%XMM14,%XMM15 |
(186) 0x42cc60 VMOVSD %XMM15,(%RBX,%RDI,8) |
(186) 0x42cc65 LEA (%R15,%R14,8),%RDI |
(186) 0x42cc69 MOV 0xa8(%RSP),%RBX |
(186) 0x42cc71 MOV 0xfc(%RSP),%R14D |
(186) 0x42cc79 VMOVSD (%RDI),%XMM0 |
(186) 0x42cc7d ADD %RBX,%RCX |
(186) 0x42cc80 INC %R14D |
(186) 0x42cc83 VSUBSD (%R15,%RSI,8),%XMM0,%XMM6 |
(186) 0x42cc89 MOV 0xe8(%RSP),%RSI |
(186) 0x42cc91 VADDSD %XMM15,%XMM6,%XMM7 |
(186) 0x42cc96 VMOVSD %XMM7,(%RSI,%RCX,8) |
(186) 0x42cc9b LEA 0x1(%RAX),%ECX |
(186) 0x42cc9e CMP %R12D,%R14D |
(186) 0x42cca1 JAE 42ce30 |
(186) 0x42cca7 MOV 0xb8(%RSP),%RBX |
(186) 0x42ccaf MOV 0xc0(%RSP),%R14 |
(186) 0x42ccb7 MOVSXD %ECX,%RCX |
(186) 0x42ccba ADD $0x2,%EAX |
(186) 0x42ccbd MOV 0xc8(%RSP),%R12 |
(186) 0x42ccc5 VMOVSD (%R11),%XMM9 |
(186) 0x42ccca LEA (%RBX,%RCX,1),%RSI |
(186) 0x42ccce ADD %RCX,%R14 |
(186) 0x42ccd1 VMOVSD (%R9),%XMM11 |
(186) 0x42ccd6 MOV 0xf0(%RSP),%R11 |
(186) 0x42ccde LEA (%R13,%RSI,8),%RBX |
(186) 0x42cce3 LEA (%RDX,%R14,8),%RSI |
(186) 0x42cce7 VMULSD (%R10),%XMM9,%XMM10 |
(186) 0x42ccec ADD %RCX,%R12 |
(186) 0x42ccef LEA (%R13,%R12,8),%R14 |
(186) 0x42ccf4 MOV 0xd0(%RSP),%R12 |
(186) 0x42ccfc VMOVSD (%RSI),%XMM1 |
(186) 0x42cd00 MOV 0xe0(%RSP),%R10 |
(186) 0x42cd08 ADD %RCX,%R12 |
(186) 0x42cd0b LEA (%RDX,%R12,8),%R12 |
(186) 0x42cd0f VMOVSD (%R12),%XMM8 |
(186) 0x42cd15 VFMADD231SD (%R8),%XMM11,%XMM10 |
(186) 0x42cd1a MOV 0xd8(%RSP),%R8 |
(186) 0x42cd22 VMULSD (%R14),%XMM8,%XMM5 |
(186) 0x42cd27 LEA (%R8,%RCX,1),%R9 |
(186) 0x42cd2b LEA (%R11,%RCX,1),%R8 |
(186) 0x42cd2f LEA (%R15,%R8,8),%R8 |
(186) 0x42cd33 VFMADD132SD (%RBX),%XMM5,%XMM1 |
(186) 0x42cd38 VADDSD %XMM1,%XMM10,%XMM12 |
(186) 0x42cd3c VMULSD %XMM3,%XMM12,%XMM13 |
(186) 0x42cd40 VMOVSD %XMM13,(%R10,%R9,8) |
(186) 0x42cd46 MOV 0xa8(%RSP),%R9 |
(186) 0x42cd4e MOV 0xb0(%RSP),%R10D |
(186) 0x42cd56 VMOVSD (%R8),%XMM14 |
(186) 0x42cd5b ADD %R9,%RCX |
(186) 0x42cd5e VSUBSD (%RDI),%XMM14,%XMM15 |
(186) 0x42cd62 MOV 0xe8(%RSP),%RDI |
(186) 0x42cd6a VADDSD %XMM13,%XMM15,%XMM0 |
(186) 0x42cd6f VMOVSD %XMM0,(%RDI,%RCX,8) |
(186) 0x42cd74 MOV 0xfc(%RSP),%ECX |
(186) 0x42cd7b ADD $0x2,%ECX |
(186) 0x42cd7e CMP %R10D,%ECX |
(186) 0x42cd81 JAE 42ce30 |
(186) 0x42cd87 MOV 0xc8(%RSP),%R9 |
(186) 0x42cd8f CLTQ |
(186) 0x42cd91 MOV 0xd0(%RSP),%R10 |
(186) 0x42cd99 VMOVSD (%R14),%XMM5 |
(186) 0x42cd9e MOV 0xb8(%RSP),%RCX |
(186) 0x42cda6 ADD %RAX,%R11 |
(186) 0x42cda9 ADD %RAX,%R9 |
(186) 0x42cdac ADD %RAX,%R10 |
(186) 0x42cdaf MOV 0xc0(%RSP),%RDI |
(186) 0x42cdb7 VMOVSD (%RBX),%XMM9 |
(186) 0x42cdbb VMOVSD (%R13,%R9,8),%XMM6 |
(186) 0x42cdc2 VMULSD (%R12),%XMM5,%XMM1 |
(186) 0x42cdc8 ADD %RAX,%RCX |
(186) 0x42cdcb VMOVSD (%R13,%RCX,8),%XMM7 |
(186) 0x42cdd2 ADD %RAX,%RDI |
(186) 0x42cdd5 MOV 0xe0(%RSP),%R13 |
(186) 0x42cddd VMULSD (%RDX,%R10,8),%XMM6,%XMM8 |
(186) 0x42cde3 MOV 0xa8(%RSP),%RBX |
(186) 0x42cdeb ADD %RAX,%RBX |
(186) 0x42cdee VFMADD231SD (%RSI),%XMM9,%XMM1 |
(186) 0x42cdf3 VFMADD231SD (%RDX,%RDI,8),%XMM7,%XMM8 |
(186) 0x42cdf9 MOV 0xd8(%RSP),%RDX |
(186) 0x42ce01 ADD %RAX,%RDX |
(186) 0x42ce04 MOV 0xe8(%RSP),%RAX |
(186) 0x42ce0c VADDSD %XMM1,%XMM8,%XMM10 |
(186) 0x42ce10 VMULSD %XMM3,%XMM10,%XMM11 |
(186) 0x42ce14 VMOVSD %XMM11,(%R13,%RDX,8) |
(186) 0x42ce1b VMOVSD (%R15,%R11,8),%XMM12 |
(186) 0x42ce21 VSUBSD (%R8),%XMM12,%XMM13 |
(186) 0x42ce26 VADDSD %XMM11,%XMM13,%XMM14 |
(186) 0x42ce2b VMOVSD %XMM14,(%RAX,%RBX,8) |
(186) 0x42ce30 MOV 0xb0(%RSP),%R15D |
(186) 0x42ce38 MOV %R15D,0xfc(%RSP) |
(186) 0x42ce40 INCL 0xb4(%RSP) |
(186) 0x42ce47 INCQ 0x98(%RSP) |
(186) 0x42ce4f MOV 0xb4(%RSP),%ESI |
(186) 0x42ce56 CMP %ESI,0x70(%RSP) |
(186) 0x42ce5a JLE 42ce88 |
(186) 0x42ce5c MOV 0x68(%RSP),%ECX |
(186) 0x42ce60 MOV 0xfc(%RSP),%R14D |
(186) 0x42ce68 MOV 0x6c(%RSP),%R12D |
(186) 0x42ce6d MOV 0x74(%RSP),%R8D |
(186) 0x42ce72 SUB %R14D,%ECX |
(186) 0x42ce75 MOV %R12D,0xf8(%RSP) |
(186) 0x42ce7d JMP 42c710 |
0x42ce82 NOPW (%RAX,%RAX,1) |
0x42ce88 VZEROUPPER |
0x42ce8b LEA -0x28(%RBP),%RSP |
0x42ce8f POP %RBX |
0x42ce90 POP %R12 |
0x42ce92 POP %R13 |
0x42ce94 POP %R14 |
0x42ce96 POP %R15 |
0x42ce98 POP %RBP |
0x42ce99 RET |
0x42ce9a NOPW (%RAX,%RAX,1) |
(186) 0x42cea0 MOV 0xf8(%RSP),%EAX |
(186) 0x42cea7 XOR %ESI,%ESI |
(186) 0x42cea9 JMP 42caa7 |
0x42ceae INC %ECX |
0x42ceb0 XOR %EDX,%EDX |
0x42ceb2 JMP 42c673 |
0x42ceb7 NOPW (%RAX,%RAX,1) |
Path / |
Source file and lines | advec_mom.cpp:95-100 |
Module | exec |
nb instructions | 87 |
nb uops | 97 |
loop length | 336 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 1 |
used ymm registers | 1 |
used zmm registers | 1 |
nb stack references | 14 |
micro-operation queue | 16.17 cycles |
front end | 16.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.30 | 8.00 | 6.67 | 6.67 | 10.50 | 6.20 | 6.30 | 10.50 | 10.50 | 10.50 | 6.20 | 6.67 |
cycles | 6.30 | 11.73 | 6.67 | 6.67 | 10.50 | 6.20 | 6.30 | 10.50 | 10.50 | 10.50 | 6.20 | 6.67 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 15.42-15.52 |
Stall cycles | 0.00 |
Front-end | 16.17 |
Dispatch | 11.73 |
DIV/SQRT | 12.00 |
Overall L1 | 16.17 |
all | 3% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 9% |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 2% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 9% |
all | 8% |
load | 10% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 8% |
all | 12% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
all | 9% |
load | 10% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 9% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0x100,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x30(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x34(%RDI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%RDI),%EDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x3,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%RAX),%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x6c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ECX,0x70(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %ECX,%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 42ce8b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x89b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %ECX,%R14D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x4(%RDI),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R12D,%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R15D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 42ce8b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x89b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R15D,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %EDX,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ESI,0x74(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 404650 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 404540 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x74(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %R14D,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R13D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 42ceae <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x8be> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %ECX,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RCX,%R9,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R10D,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R10D,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 42ce8b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x89b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R9D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x6c(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RBX),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x74(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x10(%RBX),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RBX),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R9D,0xfc(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD 0x3214a(%RIP),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDI,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RSI,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15D,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x20(%RBX),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RBX),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VBROADCASTSD %XMM3,%YMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VBROADCASTSD %XMM3,%ZMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %R15,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %R12D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %EDX,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %EAX,%R12 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R11D,0xf8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R11D,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EAX,0xb4(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,0x98(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 42c673 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x83> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | advec_mom.cpp:95-100 |
Module | exec |
nb instructions | 87 |
nb uops | 97 |
loop length | 336 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 1 |
used ymm registers | 1 |
used zmm registers | 1 |
nb stack references | 14 |
micro-operation queue | 16.17 cycles |
front end | 16.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.30 | 8.00 | 6.67 | 6.67 | 10.50 | 6.20 | 6.30 | 10.50 | 10.50 | 10.50 | 6.20 | 6.67 |
cycles | 6.30 | 11.73 | 6.67 | 6.67 | 10.50 | 6.20 | 6.30 | 10.50 | 10.50 | 10.50 | 6.20 | 6.67 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 15.42-15.52 |
Stall cycles | 0.00 |
Front-end | 16.17 |
Dispatch | 11.73 |
DIV/SQRT | 12.00 |
Overall L1 | 16.17 |
all | 3% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 9% |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 2% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 9% |
all | 8% |
load | 10% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 8% |
all | 12% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
all | 9% |
load | 10% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 9% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0x100,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x30(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x34(%RDI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%RDI),%EDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x3,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%RAX),%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x6c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ECX,0x70(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %ECX,%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 42ce8b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x89b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %ECX,%R14D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x4(%RDI),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R12D,%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R15D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 42ce8b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x89b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R15D,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %EDX,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ESI,0x74(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 404650 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 404540 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x74(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %R14D,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R13D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 42ceae <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x8be> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %ECX,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RCX,%R9,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R10D,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R10D,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 42ce8b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x89b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R9D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x6c(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RBX),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x74(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x10(%RBX),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RBX),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R9D,0xfc(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD 0x3214a(%RIP),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDI,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RSI,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15D,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x20(%RBX),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RBX),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VBROADCASTSD %XMM3,%YMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VBROADCASTSD %XMM3,%ZMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %R15,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %R12D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %EDX,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %EAX,%R12 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R11D,0xf8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R11D,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EAX,0xb4(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,0x98(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 42c673 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x83> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D | 3.01 | 2.26 |
▼Loop 186 - advec_mom.cpp:97-100 - exec– | 0.01 | 0 |
○Loop 187 - advec_mom.cpp:98-100 - exec | 3 | 2.26 |