Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ... | Module: exec | Source: advec_cell.cpp:54-58 [...] | Coverage: 1.26% |
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Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ... | Module: exec | Source: advec_cell.cpp:54-58 [...] | Coverage: 1.26% |
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/scratch_na/users/xoserete/qaas_runs/171-291-1828/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69 |
-------------------------------------------------------------------------------- |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
/scratch_na/users/xoserete/qaas_runs/171-291-1828/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp: 54 - 58 |
-------------------------------------------------------------------------------- |
54: #pragma omp parallel for simd collapse(2) |
55: for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) { |
56: for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) { |
57: pre_vol(i, j) = volume(i, j) + vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j); |
58: post_vol(i, j) = volume(i, j); |
0x4270f0 PUSH %RBP |
0x4270f1 MOV %RSP,%RBP |
0x4270f4 PUSH %R15 |
0x4270f6 PUSH %R14 |
0x4270f8 PUSH %R13 |
0x4270fa PUSH %R12 |
0x4270fc PUSH %RBX |
0x4270fd AND $-0x40,%RSP |
0x427101 ADD $-0x80,%RSP |
0x427105 MOV 0x28(%RDI),%EAX |
0x427108 MOV 0x2c(%RDI),%ECX |
0x42710b MOV 0x20(%RDI),%ESI |
0x42710e MOV 0x24(%RDI),%EDX |
0x427111 ADD $0x4,%ECX |
0x427114 LEA -0x1(%RAX),%R15D |
0x427118 DEC %ESI |
0x42711a MOV %ECX,0x48(%RSP) |
0x42711e MOV %ESI,0x44(%RSP) |
0x427122 CMP %ECX,%R15D |
0x427125 JGE 4275d3 |
0x42712b MOV %ECX,%EBX |
0x42712d LEA 0x4(%RDX),%R14D |
0x427131 SUB %R15D,%EBX |
0x427134 CMP %R14D,%ESI |
0x427137 JGE 4275d3 |
0x42713d MOV %RDI,%R13 |
0x427140 MOV %R14D,%EDI |
0x427143 SUB %ESI,%EDI |
0x427145 MOV %EDI,0x4c(%RSP) |
0x427149 CALL 404650 <omp_get_num_threads@plt> |
0x42714e MOV %EAX,%R12D |
0x427151 CALL 404540 <omp_get_thread_num@plt> |
0x427156 XOR %EDX,%EDX |
0x427158 MOV %EAX,%R8D |
0x42715b MOV 0x4c(%RSP),%EAX |
0x42715f IMUL %EBX,%EAX |
0x427162 DIV %R12D |
0x427165 MOV %EAX,%ECX |
0x427167 CMP %EDX,%R8D |
0x42716a JB 4275f3 |
0x427170 IMUL %ECX,%R8D |
0x427174 LEA (%R8,%RDX,1),%R11D |
0x427178 LEA (%RCX,%R11,1),%R9D |
0x42717c MOV %R9D,0x40(%RSP) |
0x427181 CMP %R9D,%R11D |
0x427184 JAE 4275d3 |
0x42718a MOV %R11D,%EAX |
0x42718d XOR %EDX,%EDX |
0x42718f MOV 0x44(%RSP),%R10D |
0x427194 MOV 0x8(%R13),%RSI |
0x427198 DIVL 0x4c(%RSP) |
0x42719c MOV 0x18(%R13),%RBX |
0x4271a0 MOV %RSI,0x30(%RSP) |
0x4271a5 MOV %RBX,0x20(%RSP) |
0x4271aa ADD %EDX,%R10D |
0x4271ad ADD %R15D,%EAX |
0x4271b0 MOV %R14D,%EDX |
0x4271b3 MOV (%R13),%R15 |
0x4271b7 MOV 0x10(%R13),%R14 |
0x4271bb MOV %R10D,0x74(%RSP) |
0x4271c0 SUB %R10D,%EDX |
0x4271c3 MOVSXD %EAX,%R12 |
0x4271c6 MOV %R15,0x38(%RSP) |
0x4271cb MOV %R14,0x28(%RSP) |
(161) 0x4271d0 CMP %EDX,%ECX |
(161) 0x4271d2 CMOVBE %ECX,%EDX |
(161) 0x4271d5 LEA (%R11,%RDX,1),%ECX |
(161) 0x4271d9 MOV %ECX,0x70(%RSP) |
(161) 0x4271dd CMP %ECX,%R11D |
(161) 0x4271e0 JAE 4275a2 |
(161) 0x4271e6 MOV 0x38(%RSP),%R13 |
(161) 0x4271eb MOV 0x28(%RSP),%R9 |
(161) 0x4271f0 MOV 0x20(%RSP),%RAX |
(161) 0x4271f5 MOV 0x30(%RSP),%RDI |
(161) 0x4271fa MOV (%R13),%RBX |
(161) 0x4271fe MOV 0x10(%R9),%R8 |
(161) 0x427202 MOV (%R9),%R10 |
(161) 0x427205 MOV (%RAX),%R9 |
(161) 0x427208 IMUL %R12,%RBX |
(161) 0x42720c MOV (%RDI),%R14 |
(161) 0x42720f MOV 0x10(%RAX),%RCX |
(161) 0x427213 MOV %R8,0x60(%RSP) |
(161) 0x427218 IMUL %R12,%R10 |
(161) 0x42721c MOV 0x10(%R13),%R15 |
(161) 0x427220 LEA -0x1(%RDX),%R13D |
(161) 0x427224 MOV 0x10(%RDI),%RSI |
(161) 0x427228 IMUL %R12,%R9 |
(161) 0x42722c MOV %RCX,0x78(%RSP) |
(161) 0x427231 MOV %RBX,0x50(%RSP) |
(161) 0x427236 IMUL %R12,%R14 |
(161) 0x42723a MOV %R10,0x58(%RSP) |
(161) 0x42723f MOV %R9,0x68(%RSP) |
(161) 0x427244 CMP $0x6,%R13D |
(161) 0x427248 JBE 4275e8 |
(161) 0x42724e MOVSXD 0x74(%RSP),%RAX |
(161) 0x427253 LEA (%R10,%RAX,1),%R10 |
(161) 0x427257 LEA (%RBX,%RAX,1),%RBX |
(161) 0x42725b LEA (%R8,%R10,8),%R10 |
(161) 0x42725f MOV 0x78(%RSP),%R8 |
(161) 0x427264 LEA 0x1(%R14,%RAX,1),%RDI |
(161) 0x427269 ADD %R9,%RAX |
(161) 0x42726c SAL $0x3,%RDI |
(161) 0x427270 LEA (%R15,%RBX,8),%RCX |
(161) 0x427274 LEA (%R8,%RAX,8),%R9 |
(161) 0x427278 MOV %EDX,%R8D |
(161) 0x42727b LEA (%RSI,%RDI,1),%R13 |
(161) 0x42727f XOR %EAX,%EAX |
(161) 0x427281 SHR $0x3,%R8D |
(161) 0x427285 LEA -0x8(%RSI,%RDI,1),%RBX |
(161) 0x42728a SAL $0x6,%R8 |
(161) 0x42728e LEA -0x40(%R8),%RDI |
(161) 0x427292 SHR $0x6,%RDI |
(161) 0x427296 INC %RDI |
(161) 0x427299 AND $0x3,%EDI |
(161) 0x42729c JE 42733f |
(161) 0x4272a2 CMP $0x1,%RDI |
(161) 0x4272a6 JE 427307 |
(161) 0x4272a8 CMP $0x2,%RDI |
(161) 0x4272ac JE 4272d8 |
(161) 0x4272ae VMOVUPD (%RCX),%ZMM6 |
(161) 0x4272b4 MOV $0x40,%EAX |
(161) 0x4272b9 VADDPD (%R13),%ZMM6,%ZMM0 |
(161) 0x4272c0 VSUBPD (%RBX),%ZMM0,%ZMM1 |
(161) 0x4272c6 VMOVUPD %ZMM1,(%R10) |
(161) 0x4272cc VMOVUPD (%RCX),%ZMM7 |
(161) 0x4272d2 VMOVUPD %ZMM7,(%R9) |
(161) 0x4272d8 VMOVUPD (%RCX,%RAX,1),%ZMM2 |
(161) 0x4272df VADDPD (%R13,%RAX,1),%ZMM2,%ZMM3 |
(161) 0x4272e7 VSUBPD (%RBX,%RAX,1),%ZMM3,%ZMM4 |
(161) 0x4272ee VMOVUPD %ZMM4,(%R10,%RAX,1) |
(161) 0x4272f5 VMOVUPD (%RCX,%RAX,1),%ZMM5 |
(161) 0x4272fc VMOVUPD %ZMM5,(%R9,%RAX,1) |
(161) 0x427303 ADD $0x40,%RAX |
(161) 0x427307 VMOVUPD (%RCX,%RAX,1),%ZMM8 |
(161) 0x42730e VADDPD (%R13,%RAX,1),%ZMM8,%ZMM9 |
(161) 0x427316 VSUBPD (%RBX,%RAX,1),%ZMM9,%ZMM10 |
(161) 0x42731d VMOVUPD %ZMM10,(%R10,%RAX,1) |
(161) 0x427324 VMOVUPD (%RCX,%RAX,1),%ZMM11 |
(161) 0x42732b VMOVUPD %ZMM11,(%R9,%RAX,1) |
(161) 0x427332 ADD $0x40,%RAX |
(161) 0x427336 CMP %RAX,%R8 |
(161) 0x427339 JE 427409 |
(162) 0x42733f VMOVUPD (%RCX,%RAX,1),%ZMM12 |
(162) 0x427346 VADDPD (%R13,%RAX,1),%ZMM12,%ZMM13 |
(162) 0x42734e VSUBPD (%RBX,%RAX,1),%ZMM13,%ZMM14 |
(162) 0x427355 VMOVUPD %ZMM14,(%R10,%RAX,1) |
(162) 0x42735c VMOVUPD (%RCX,%RAX,1),%ZMM15 |
(162) 0x427363 VMOVUPD %ZMM15,(%R9,%RAX,1) |
(162) 0x42736a VMOVUPD 0x40(%RCX,%RAX,1),%ZMM6 |
(162) 0x427372 VADDPD 0x40(%R13,%RAX,1),%ZMM6,%ZMM0 |
(162) 0x42737a VSUBPD 0x40(%RBX,%RAX,1),%ZMM0,%ZMM1 |
(162) 0x427382 VMOVUPD %ZMM1,0x40(%R10,%RAX,1) |
(162) 0x42738a VMOVUPD 0x40(%RCX,%RAX,1),%ZMM7 |
(162) 0x427392 VMOVUPD %ZMM7,0x40(%R9,%RAX,1) |
(162) 0x42739a VMOVUPD 0x80(%RCX,%RAX,1),%ZMM2 |
(162) 0x4273a2 VADDPD 0x80(%R13,%RAX,1),%ZMM2,%ZMM3 |
(162) 0x4273aa VSUBPD 0x80(%RBX,%RAX,1),%ZMM3,%ZMM4 |
(162) 0x4273b2 VMOVUPD %ZMM4,0x80(%R10,%RAX,1) |
(162) 0x4273ba VMOVUPD 0x80(%RCX,%RAX,1),%ZMM5 |
(162) 0x4273c2 VMOVUPD %ZMM5,0x80(%R9,%RAX,1) |
(162) 0x4273ca VMOVUPD 0xc0(%RCX,%RAX,1),%ZMM8 |
(162) 0x4273d2 VADDPD 0xc0(%R13,%RAX,1),%ZMM8,%ZMM9 |
(162) 0x4273da VSUBPD 0xc0(%RBX,%RAX,1),%ZMM9,%ZMM10 |
(162) 0x4273e2 VMOVUPD %ZMM10,0xc0(%R10,%RAX,1) |
(162) 0x4273ea VMOVUPD 0xc0(%RCX,%RAX,1),%ZMM11 |
(162) 0x4273f2 VMOVUPD %ZMM11,0xc0(%R9,%RAX,1) |
(162) 0x4273fa ADD $0x100,%RAX |
(162) 0x427400 CMP %RAX,%R8 |
(162) 0x427403 JNE 42733f |
(161) 0x427409 MOV 0x74(%RSP),%EAX |
(161) 0x42740d MOV %EDX,%EDI |
(161) 0x42740f AND $-0x8,%EDI |
(161) 0x427412 ADD %EDI,%R11D |
(161) 0x427415 ADD %EDI,%EAX |
(161) 0x427417 TEST $0x7,%DL |
(161) 0x42741a JE 42759d |
(161) 0x427420 SUB %EDI,%EDX |
(161) 0x427422 LEA -0x1(%RDX),%ECX |
(161) 0x427425 CMP $0x2,%ECX |
(161) 0x427428 JBE 42749b |
(161) 0x42742a MOVSXD 0x74(%RSP),%R13 |
(161) 0x42742f MOV 0x50(%RSP),%RBX |
(161) 0x427434 LEA (%R14,%R13,1),%R8 |
(161) 0x427438 LEA (%RBX,%R13,1),%R10 |
(161) 0x42743c MOV 0x58(%RSP),%RBX |
(161) 0x427441 LEA 0x1(%RDI,%R8,1),%RCX |
(161) 0x427446 ADD %RDI,%R10 |
(161) 0x427449 MOV 0x60(%RSP),%R8 |
(161) 0x42744e VMOVUPD (%RSI,%RCX,8),%YMM12 |
(161) 0x427453 LEA (%R15,%R10,8),%R9 |
(161) 0x427457 LEA (%RBX,%R13,1),%R10 |
(161) 0x42745b ADD %RDI,%R10 |
(161) 0x42745e VSUBPD -0x8(%RSI,%RCX,8),%YMM12,%YMM13 |
(161) 0x427464 VADDPD (%R9),%YMM13,%YMM14 |
(161) 0x427469 VMOVUPD %YMM14,(%R8,%R10,8) |
(161) 0x42746f VMOVUPD (%R9),%YMM15 |
(161) 0x427474 MOV 0x68(%RSP),%R9 |
(161) 0x427479 ADD %R9,%R13 |
(161) 0x42747c ADD %RDI,%R13 |
(161) 0x42747f MOV 0x78(%RSP),%RDI |
(161) 0x427484 VMOVUPD %YMM15,(%RDI,%R13,8) |
(161) 0x42748a TEST $0x3,%DL |
(161) 0x42748d JE 42759d |
(161) 0x427493 AND $-0x4,%EDX |
(161) 0x427496 ADD %EDX,%R11D |
(161) 0x427499 ADD %EDX,%EAX |
(161) 0x42749b MOV 0x50(%RSP),%RBX |
(161) 0x4274a0 MOVSXD %EAX,%RCX |
(161) 0x4274a3 LEA 0x1(%RAX),%R13D |
(161) 0x4274a7 LEA (%RBX,%RCX,1),%RDX |
(161) 0x4274ab LEA (%R15,%RDX,8),%RDI |
(161) 0x4274af MOVSXD %R13D,%RDX |
(161) 0x4274b2 MOV 0x58(%RSP),%R13 |
(161) 0x4274b7 LEA (%R14,%RDX,1),%R10 |
(161) 0x4274bb LEA (%RSI,%R10,8),%R8 |
(161) 0x4274bf LEA (%R14,%RCX,1),%R10 |
(161) 0x4274c3 VMOVSD (%R8),%XMM6 |
(161) 0x4274c8 LEA (%R13,%RCX,1),%R9 |
(161) 0x4274cd VSUBSD (%RSI,%R10,8),%XMM6,%XMM0 |
(161) 0x4274d3 MOV 0x60(%RSP),%R10 |
(161) 0x4274d8 VADDSD (%RDI),%XMM0,%XMM1 |
(161) 0x4274dc VMOVSD %XMM1,(%R10,%R9,8) |
(161) 0x4274e2 MOV 0x78(%RSP),%R9 |
(161) 0x4274e7 MOV 0x70(%RSP),%R10D |
(161) 0x4274ec VMOVSD (%RDI),%XMM7 |
(161) 0x4274f0 MOV 0x68(%RSP),%RDI |
(161) 0x4274f5 ADD %RDI,%RCX |
(161) 0x4274f8 VMOVSD %XMM7,(%R9,%RCX,8) |
(161) 0x4274fe LEA 0x1(%R11),%ECX |
(161) 0x427502 CMP %R10D,%ECX |
(161) 0x427505 JAE 42759d |
(161) 0x42750b LEA 0x2(%RAX),%R9D |
(161) 0x42750f LEA (%RDX,%RBX,1),%RDI |
(161) 0x427513 ADD $0x2,%R11D |
(161) 0x427517 MOVSXD %R9D,%RCX |
(161) 0x42751a LEA (%R15,%RDI,8),%RDI |
(161) 0x42751e LEA (%R14,%RCX,1),%R10 |
(161) 0x427522 LEA (%RSI,%R10,8),%R9 |
(161) 0x427526 LEA (%R13,%RDX,1),%R10 |
(161) 0x42752b VMOVSD (%R9),%XMM2 |
(161) 0x427530 VADDSD (%RDI),%XMM2,%XMM3 |
(161) 0x427534 VSUBSD (%R8),%XMM3,%XMM4 |
(161) 0x427539 MOV 0x60(%RSP),%R8 |
(161) 0x42753e VMOVSD %XMM4,(%R8,%R10,8) |
(161) 0x427544 MOV 0x68(%RSP),%R10 |
(161) 0x427549 VMOVSD (%RDI),%XMM5 |
(161) 0x42754d MOV 0x78(%RSP),%RDI |
(161) 0x427552 ADD %R10,%RDX |
(161) 0x427555 VMOVSD %XMM5,(%RDI,%RDX,8) |
(161) 0x42755a MOV 0x70(%RSP),%EDX |
(161) 0x42755e CMP %EDX,%R11D |
(161) 0x427561 JAE 42759d |
(161) 0x427563 ADD $0x3,%EAX |
(161) 0x427566 ADD %RCX,%RBX |
(161) 0x427569 ADD %RCX,%R13 |
(161) 0x42756c ADD %RCX,%R10 |
(161) 0x42756f CLTQ |
(161) 0x427571 LEA (%R15,%RBX,8),%R11 |
(161) 0x427575 MOV 0x78(%RSP),%R15 |
(161) 0x42757a ADD %R14,%RAX |
(161) 0x42757d VMOVSD (%RSI,%RAX,8),%XMM8 |
(161) 0x427582 VADDSD (%R11),%XMM8,%XMM9 |
(161) 0x427587 VSUBSD (%R9),%XMM9,%XMM10 |
(161) 0x42758c VMOVSD %XMM10,(%R8,%R13,8) |
(161) 0x427592 VMOVSD (%R11),%XMM11 |
(161) 0x427597 VMOVSD %XMM11,(%R15,%R10,8) |
(161) 0x42759d MOV 0x70(%RSP),%R11D |
(161) 0x4275a2 INC %R12 |
(161) 0x4275a5 LEA (%R12),%ESI |
(161) 0x4275a9 CMP %ESI,0x48(%RSP) |
(161) 0x4275ad JLE 4275d0 |
(161) 0x4275af MOV 0x40(%RSP),%ECX |
(161) 0x4275b3 MOV 0x44(%RSP),%R14D |
(161) 0x4275b8 MOV 0x4c(%RSP),%EDX |
(161) 0x4275bc MOV %R14D,0x74(%RSP) |
(161) 0x4275c1 SUB %R11D,%ECX |
(161) 0x4275c4 JMP 4271d0 |
0x4275c9 NOPL (%RAX) |
0x4275d0 VZEROUPPER |
0x4275d3 LEA -0x28(%RBP),%RSP |
0x4275d7 POP %RBX |
0x4275d8 POP %R12 |
0x4275da POP %R13 |
0x4275dc POP %R14 |
0x4275de POP %R15 |
0x4275e0 POP %RBP |
0x4275e1 RET |
0x4275e2 NOPW (%RAX,%RAX,1) |
(161) 0x4275e8 MOV 0x74(%RSP),%EAX |
(161) 0x4275ec XOR %EDI,%EDI |
(161) 0x4275ee JMP 427420 |
0x4275f3 INC %ECX |
0x4275f5 XOR %EDX,%EDX |
0x4275f7 JMP 427170 |
0x4275fc NOPL (%RAX) |
Path / |
Source file and lines | advec_cell.cpp:54-58 |
Module | exec |
nb instructions | 79 |
nb uops | 89 |
loop length | 268 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 10 |
micro-operation queue | 14.83 cycles |
front end | 14.83 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 5.70 | 8.00 | 6.00 | 6.00 | 8.50 | 5.87 | 5.70 | 8.50 | 8.50 | 8.50 | 5.73 | 6.00 |
cycles | 5.70 | 11.73 | 6.00 | 6.00 | 8.50 | 5.87 | 5.70 | 8.50 | 8.50 | 8.50 | 5.73 | 6.00 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.07-14.16 |
Stall cycles | 0.00 |
Front-end | 14.83 |
Dispatch | 11.73 |
DIV/SQRT | 12.00 |
Overall L1 | 14.83 |
all | 3% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 12% |
all | 8% |
load | 9% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 9% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD $-0x80,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x28(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%RDI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x24(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x4,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA -0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
DEC %ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ECX,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ESI,0x44(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %ECX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 4275d3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.1+0x4e3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %ECX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x4(%RDX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 4275d3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.1+0x4e3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R14D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %ESI,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EDI,0x4c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 404650 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 404540 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x4c(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 4275f3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.1+0x503> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %ECX,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RCX,%R11,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R9D,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R9D,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 4275d3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.1+0x4e3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R11D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x44(%RSP),%R10D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%R13),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x4c(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x18(%R13),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R15D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV (%R13),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%R13),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10D,0x74(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R10D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %EAX,%R12 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R15,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 427170 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.1+0x80> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | advec_cell.cpp:54-58 |
Module | exec |
nb instructions | 79 |
nb uops | 89 |
loop length | 268 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 10 |
micro-operation queue | 14.83 cycles |
front end | 14.83 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 5.70 | 8.00 | 6.00 | 6.00 | 8.50 | 5.87 | 5.70 | 8.50 | 8.50 | 8.50 | 5.73 | 6.00 |
cycles | 5.70 | 11.73 | 6.00 | 6.00 | 8.50 | 5.87 | 5.70 | 8.50 | 8.50 | 8.50 | 5.73 | 6.00 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.07-14.16 |
Stall cycles | 0.00 |
Front-end | 14.83 |
Dispatch | 11.73 |
DIV/SQRT | 12.00 |
Overall L1 | 14.83 |
all | 3% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 12% |
all | 8% |
load | 9% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 9% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD $-0x80,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x28(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%RDI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x24(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x4,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA -0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
DEC %ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ECX,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ESI,0x44(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %ECX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 4275d3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.1+0x4e3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %ECX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x4(%RDX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 4275d3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.1+0x4e3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R14D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %ESI,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EDI,0x4c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 404650 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 404540 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x4c(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 4275f3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.1+0x503> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %ECX,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RCX,%R11,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R9D,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R9D,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 4275d3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.1+0x4e3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R11D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x44(%RSP),%R10D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%R13),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x4c(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x18(%R13),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R15D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV (%R13),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%R13),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10D,0x74(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R10D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %EAX,%R12 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R15,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 427170 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.1+0x80> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D | 1.26 | 0.95 |
▼Loop 161 - advec_cell.cpp:56-58 - exec– | 0 | 0 |
○Loop 162 - advec_cell.cpp:57-58 - exec | 1.26 | 0.95 |