Function: initialise_chunk(int, global_variables&) [clone ._omp_fn.4] | Module: exec | Source: initialise_chunk.cpp:77-82 [...] | Coverage: 0.03% |
---|
Function: initialise_chunk(int, global_variables&) [clone ._omp_fn.4] | Module: exec | Source: initialise_chunk.cpp:77-82 [...] | Coverage: 0.03% |
---|
/scratch_na/users/xoserete/qaas_runs/171-291-1828/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/initialise_chunk.cpp: 77 - 82 |
-------------------------------------------------------------------------------- |
77: #pragma omp parallel for simd collapse(2) |
78: for (int j = (0); j < (yrange1); j++) { |
79: for (int i = (0); i < (xrange1); i++) { |
80: field.volume(i, j) = dx * dy; |
81: field.xarea(i, j) = field.celldy[j]; |
82: field.yarea(i, j) = field.celldx[i]; |
/scratch_na/users/xoserete/qaas_runs/171-291-1828/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 46 - 69 |
-------------------------------------------------------------------------------- |
46: T &operator[](size_t i) const { return data[i]; } |
[...] |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
0x4397e0 PUSH %RBP |
0x4397e1 MOV %RSP,%RBP |
0x4397e4 PUSH %R15 |
0x4397e6 PUSH %R14 |
0x4397e8 PUSH %R13 |
0x4397ea PUSH %R12 |
0x4397ec PUSH %RBX |
0x4397ed AND $-0x40,%RSP |
0x4397f1 SUB $0x40,%RSP |
0x4397f5 MOV 0x1c(%RDI),%R14D |
0x4397f9 MOV 0x18(%RDI),%R15D |
0x4397fd MOV %R14D,0x10(%RSP) |
0x439802 MOV %R15D,0x4(%RSP) |
0x439807 TEST %R14D,%R14D |
0x43980a JLE 439d63 |
0x439810 TEST %R15D,%R15D |
0x439813 JLE 439d63 |
0x439819 MOV %RDI,%R12 |
0x43981c CALL 404650 <omp_get_num_threads@plt> |
0x439821 MOV %EAX,%EBX |
0x439823 CALL 404540 <omp_get_thread_num@plt> |
0x439828 XOR %EDX,%EDX |
0x43982a MOV %EAX,%ESI |
0x43982c MOV %R14D,%EAX |
0x43982f IMUL %R15D,%EAX |
0x439833 DIV %EBX |
0x439835 MOV %EAX,%ECX |
0x439837 CMP %EDX,%ESI |
0x439839 JB 439d84 |
0x43983f IMUL %ECX,%ESI |
0x439842 LEA (%RSI,%RDX,1),%R10D |
0x439846 LEA (%RCX,%R10,1),%EDI |
0x43984a MOV %EDI,(%RSP) |
0x43984d CMP %EDI,%R10D |
0x439850 JAE 439d63 |
0x439856 MOV 0x4(%RSP),%R8D |
0x43985b MOV %R10D,%EAX |
0x43985e XOR %EDX,%EDX |
0x439860 VMOVSD 0x8(%R12),%XMM2 |
0x439867 MOV 0x10(%R12),%R13 |
0x43986c DIV %R8D |
0x43986f VMULSD (%R12),%XMM2,%XMM8 |
0x439875 VBROADCASTSD %XMM8,%YMM3 |
0x43987a VBROADCASTSD %XMM8,%ZMM0 |
0x439880 SUB %EDX,%R8D |
0x439883 MOV %EDX,0x30(%RSP) |
0x439887 MOVSXD %EAX,%RBX |
0x43988a MOV %R8D,%EDX |
0x43988d NOPL (%RAX) |
(248) 0x439890 CMP %EDX,%ECX |
(248) 0x439892 CMOVBE %ECX,%EDX |
(248) 0x439895 LEA (%R10,%RDX,1),%ECX |
(248) 0x439899 MOV %ECX,0x14(%RSP) |
(248) 0x43989d CMP %ECX,%R10D |
(248) 0x4398a0 JAE 439d38 |
(248) 0x4398a6 MOV 0x290(%R13),%R11 |
(248) 0x4398ad MOV 0x2a8(%R13),%RDI |
(248) 0x4398b4 LEA -0x1(%RDX),%R8D |
(248) 0x4398b8 MOV 0x2c0(%R13),%RAX |
(248) 0x4398bf MOV 0x248(%R13),%R9 |
(248) 0x4398c6 IMUL %RBX,%R11 |
(248) 0x4398ca MOV 0x2d0(%R13),%RSI |
(248) 0x4398d1 MOV 0x2a0(%R13),%R15 |
(248) 0x4398d8 IMUL %RBX,%RDI |
(248) 0x4398dc MOV 0x2b8(%R13),%R14 |
(248) 0x4398e3 MOV 0x228(%R13),%R12 |
(248) 0x4398ea LEA (%R9,%RBX,8),%RCX |
(248) 0x4398ee IMUL %RBX,%RAX |
(248) 0x4398f2 MOV %RSI,0x38(%RSP) |
(248) 0x4398f7 MOV %R11,0x18(%RSP) |
(248) 0x4398fc MOV %RDI,0x20(%RSP) |
(248) 0x439901 MOV %RAX,0x28(%RSP) |
(248) 0x439906 CMP $0x6,%R8D |
(248) 0x43990a JBE 439d78 |
(248) 0x439910 MOVSXD 0x30(%RSP),%RAX |
(248) 0x439915 LEA (%RDI,%RAX,1),%RSI |
(248) 0x439919 MOV 0x28(%RSP),%RDI |
(248) 0x43991e LEA (%R11,%RAX,1),%R11 |
(248) 0x439922 LEA (%R14,%RSI,8),%R9 |
(248) 0x439926 MOV 0x38(%RSP),%RSI |
(248) 0x43992b LEA (%R12,%RAX,8),%R8 |
(248) 0x43992f ADD %RDI,%RAX |
(248) 0x439932 LEA (%R15,%R11,8),%R11 |
(248) 0x439936 LEA (%RSI,%RAX,8),%RDI |
(248) 0x43993a MOV %EDX,%ESI |
(248) 0x43993c XOR %EAX,%EAX |
(248) 0x43993e SHR $0x3,%ESI |
(248) 0x439941 SAL $0x6,%RSI |
(248) 0x439945 MOV %RSI,0x8(%RSP) |
(248) 0x43994a SUB $0x40,%RSI |
(248) 0x43994e SHR $0x6,%RSI |
(248) 0x439952 INC %RSI |
(248) 0x439955 AND $0x7,%ESI |
(248) 0x439958 JE 439aa0 |
(248) 0x43995e CMP $0x1,%RSI |
(248) 0x439962 JE 439a6f |
(248) 0x439968 CMP $0x2,%RSI |
(248) 0x43996c JE 439a49 |
(248) 0x439972 CMP $0x3,%RSI |
(248) 0x439976 JE 439a23 |
(248) 0x43997c CMP $0x4,%RSI |
(248) 0x439980 JE 4399fd |
(248) 0x439982 CMP $0x5,%RSI |
(248) 0x439986 JE 4399d7 |
(248) 0x439988 CMP $0x6,%RSI |
(248) 0x43998c JE 4399b1 |
(248) 0x43998e VMOVUPD %ZMM0,(%R11) |
(248) 0x439994 MOV $0x40,%EAX |
(248) 0x439999 VBROADCASTSD (%RCX),%ZMM1 |
(248) 0x43999f VMOVUPD %ZMM1,(%R9) |
(248) 0x4399a5 VMOVUPD (%R8),%ZMM5 |
(248) 0x4399ab VMOVUPD %ZMM5,(%RDI) |
(248) 0x4399b1 VMOVUPD %ZMM0,(%R11,%RAX,1) |
(248) 0x4399b8 VBROADCASTSD (%RCX),%ZMM4 |
(248) 0x4399be VMOVUPD %ZMM4,(%R9,%RAX,1) |
(248) 0x4399c5 VMOVUPD (%R8,%RAX,1),%ZMM7 |
(248) 0x4399cc VMOVUPD %ZMM7,(%RDI,%RAX,1) |
(248) 0x4399d3 ADD $0x40,%RAX |
(248) 0x4399d7 VMOVUPD %ZMM0,(%R11,%RAX,1) |
(248) 0x4399de VBROADCASTSD (%RCX),%ZMM6 |
(248) 0x4399e4 VMOVUPD %ZMM6,(%R9,%RAX,1) |
(248) 0x4399eb VMOVUPD (%R8,%RAX,1),%ZMM9 |
(248) 0x4399f2 VMOVUPD %ZMM9,(%RDI,%RAX,1) |
(248) 0x4399f9 ADD $0x40,%RAX |
(248) 0x4399fd VMOVUPD %ZMM0,(%R11,%RAX,1) |
(248) 0x439a04 VBROADCASTSD (%RCX),%ZMM10 |
(248) 0x439a0a VMOVUPD %ZMM10,(%R9,%RAX,1) |
(248) 0x439a11 VMOVUPD (%R8,%RAX,1),%ZMM11 |
(248) 0x439a18 VMOVUPD %ZMM11,(%RDI,%RAX,1) |
(248) 0x439a1f ADD $0x40,%RAX |
(248) 0x439a23 VMOVUPD %ZMM0,(%R11,%RAX,1) |
(248) 0x439a2a VBROADCASTSD (%RCX),%ZMM12 |
(248) 0x439a30 VMOVUPD %ZMM12,(%R9,%RAX,1) |
(248) 0x439a37 VMOVUPD (%R8,%RAX,1),%ZMM13 |
(248) 0x439a3e VMOVUPD %ZMM13,(%RDI,%RAX,1) |
(248) 0x439a45 ADD $0x40,%RAX |
(248) 0x439a49 VMOVUPD %ZMM0,(%R11,%RAX,1) |
(248) 0x439a50 VBROADCASTSD (%RCX),%ZMM14 |
(248) 0x439a56 VMOVUPD %ZMM14,(%R9,%RAX,1) |
(248) 0x439a5d VMOVUPD (%R8,%RAX,1),%ZMM15 |
(248) 0x439a64 VMOVUPD %ZMM15,(%RDI,%RAX,1) |
(248) 0x439a6b ADD $0x40,%RAX |
(248) 0x439a6f VMOVUPD %ZMM0,(%R11,%RAX,1) |
(248) 0x439a76 VBROADCASTSD (%RCX),%ZMM2 |
(248) 0x439a7c VMOVUPD %ZMM2,(%R9,%RAX,1) |
(248) 0x439a83 VMOVUPD (%R8,%RAX,1),%ZMM1 |
(248) 0x439a8a VMOVUPD %ZMM1,(%RDI,%RAX,1) |
(248) 0x439a91 ADD $0x40,%RAX |
(248) 0x439a95 CMP %RAX,0x8(%RSP) |
(248) 0x439a9a JE 439bdd |
(249) 0x439aa0 VMOVUPD %ZMM0,(%R11,%RAX,1) |
(249) 0x439aa7 VBROADCASTSD (%RCX),%ZMM5 |
(249) 0x439aad VMOVUPD %ZMM5,(%R9,%RAX,1) |
(249) 0x439ab4 VMOVUPD (%R8,%RAX,1),%ZMM4 |
(249) 0x439abb VMOVUPD %ZMM4,(%RDI,%RAX,1) |
(249) 0x439ac2 VMOVUPD %ZMM0,0x40(%R11,%RAX,1) |
(249) 0x439aca VBROADCASTSD (%RCX),%ZMM7 |
(249) 0x439ad0 VMOVUPD %ZMM7,0x40(%R9,%RAX,1) |
(249) 0x439ad8 VMOVUPD 0x40(%R8,%RAX,1),%ZMM6 |
(249) 0x439ae0 VMOVUPD %ZMM6,0x40(%RDI,%RAX,1) |
(249) 0x439ae8 VMOVUPD %ZMM0,0x80(%R11,%RAX,1) |
(249) 0x439af0 VBROADCASTSD (%RCX),%ZMM9 |
(249) 0x439af6 VMOVUPD %ZMM9,0x80(%R9,%RAX,1) |
(249) 0x439afe VMOVUPD 0x80(%R8,%RAX,1),%ZMM10 |
(249) 0x439b06 VMOVUPD %ZMM10,0x80(%RDI,%RAX,1) |
(249) 0x439b0e VMOVUPD %ZMM0,0xc0(%R11,%RAX,1) |
(249) 0x439b16 VBROADCASTSD (%RCX),%ZMM11 |
(249) 0x439b1c VMOVUPD %ZMM11,0xc0(%R9,%RAX,1) |
(249) 0x439b24 VMOVUPD 0xc0(%R8,%RAX,1),%ZMM12 |
(249) 0x439b2c VMOVUPD %ZMM12,0xc0(%RDI,%RAX,1) |
(249) 0x439b34 VMOVUPD %ZMM0,0x100(%R11,%RAX,1) |
(249) 0x439b3c VBROADCASTSD (%RCX),%ZMM13 |
(249) 0x439b42 VMOVUPD %ZMM13,0x100(%R9,%RAX,1) |
(249) 0x439b4a VMOVUPD 0x100(%R8,%RAX,1),%ZMM14 |
(249) 0x439b52 VMOVUPD %ZMM14,0x100(%RDI,%RAX,1) |
(249) 0x439b5a VMOVUPD %ZMM0,0x140(%R11,%RAX,1) |
(249) 0x439b62 VBROADCASTSD (%RCX),%ZMM15 |
(249) 0x439b68 VMOVUPD %ZMM15,0x140(%R9,%RAX,1) |
(249) 0x439b70 VMOVUPD 0x140(%R8,%RAX,1),%ZMM2 |
(249) 0x439b78 VMOVUPD %ZMM2,0x140(%RDI,%RAX,1) |
(249) 0x439b80 VMOVUPD %ZMM0,0x180(%R11,%RAX,1) |
(249) 0x439b88 VBROADCASTSD (%RCX),%ZMM1 |
(249) 0x439b8e VMOVUPD %ZMM1,0x180(%R9,%RAX,1) |
(249) 0x439b96 VMOVUPD 0x180(%R8,%RAX,1),%ZMM5 |
(249) 0x439b9e VMOVUPD %ZMM5,0x180(%RDI,%RAX,1) |
(249) 0x439ba6 VMOVUPD %ZMM0,0x1c0(%R11,%RAX,1) |
(249) 0x439bae VBROADCASTSD (%RCX),%ZMM4 |
(249) 0x439bb4 VMOVUPD %ZMM4,0x1c0(%R9,%RAX,1) |
(249) 0x439bbc VMOVUPD 0x1c0(%R8,%RAX,1),%ZMM7 |
(249) 0x439bc4 VMOVUPD %ZMM7,0x1c0(%RDI,%RAX,1) |
(249) 0x439bcc ADD $0x200,%RAX |
(249) 0x439bd2 CMP %RAX,0x8(%RSP) |
(249) 0x439bd7 JNE 439aa0 |
(248) 0x439bdd MOV 0x30(%RSP),%R11D |
(248) 0x439be2 MOV %EDX,%R9D |
(248) 0x439be5 AND $-0x8,%R9D |
(248) 0x439be9 ADD %R9D,%R10D |
(248) 0x439bec LEA (%R9,%R11,1),%EDI |
(248) 0x439bf0 TEST $0x7,%DL |
(248) 0x439bf3 JE 439d33 |
(248) 0x439bf9 SUB %R9D,%EDX |
(248) 0x439bfc LEA -0x1(%RDX),%R8D |
(248) 0x439c00 CMP $0x2,%R8D |
(248) 0x439c04 JBE 439c69 |
(248) 0x439c06 MOVSXD 0x30(%RSP),%RAX |
(248) 0x439c0b MOV 0x18(%RSP),%RSI |
(248) 0x439c10 MOV 0x20(%RSP),%R8 |
(248) 0x439c15 VMOVSD (%RCX),%XMM6 |
(248) 0x439c19 LEA (%RSI,%RAX,1),%R11 |
(248) 0x439c1d LEA (%R8,%RAX,1),%RSI |
(248) 0x439c21 MOV 0x28(%RSP),%R8 |
(248) 0x439c26 ADD %R9,%R11 |
(248) 0x439c29 VBROADCASTSD %XMM6,%YMM9 |
(248) 0x439c2e ADD %R9,%RSI |
(248) 0x439c31 VMOVUPD %YMM3,(%R15,%R11,8) |
(248) 0x439c37 LEA (%RAX,%R9,1),%R11 |
(248) 0x439c3b VMOVUPD %YMM9,(%R14,%RSI,8) |
(248) 0x439c41 ADD %R8,%RAX |
(248) 0x439c44 ADD %R9,%RAX |
(248) 0x439c47 VMOVUPD (%R12,%R11,8),%YMM10 |
(248) 0x439c4d MOV 0x38(%RSP),%R9 |
(248) 0x439c52 VMOVUPD %YMM10,(%R9,%RAX,8) |
(248) 0x439c58 TEST $0x3,%DL |
(248) 0x439c5b JE 439d33 |
(248) 0x439c61 AND $-0x4,%EDX |
(248) 0x439c64 ADD %EDX,%R10D |
(248) 0x439c67 ADD %EDX,%EDI |
(248) 0x439c69 MOV 0x18(%RSP),%R9 |
(248) 0x439c6e MOVSXD %EDI,%RAX |
(248) 0x439c71 MOV 0x20(%RSP),%R11 |
(248) 0x439c76 LEA (,%RAX,8),%R8 |
(248) 0x439c7e LEA (%R9,%RAX,1),%RDX |
(248) 0x439c82 LEA (%R11,%RAX,1),%RSI |
(248) 0x439c86 MOV %R8,0x30(%RSP) |
(248) 0x439c8b MOV 0x28(%RSP),%R8 |
(248) 0x439c90 VMOVSD %XMM8,(%R15,%RDX,8) |
(248) 0x439c96 MOV 0x38(%RSP),%RDX |
(248) 0x439c9b VMOVSD (%RCX),%XMM11 |
(248) 0x439c9f VMOVSD %XMM11,(%R14,%RSI,8) |
(248) 0x439ca5 LEA 0x1(%R10),%ESI |
(248) 0x439ca9 VMOVSD (%R12,%RAX,8),%XMM12 |
(248) 0x439caf ADD %R8,%RAX |
(248) 0x439cb2 VMOVSD %XMM12,(%RDX,%RAX,8) |
(248) 0x439cb7 MOV 0x14(%RSP),%EDX |
(248) 0x439cbb LEA 0x1(%RDI),%EAX |
(248) 0x439cbe CMP %EDX,%ESI |
(248) 0x439cc0 JAE 439d33 |
(248) 0x439cc2 CLTQ |
(248) 0x439cc4 ADD $0x2,%R10D |
(248) 0x439cc8 ADD $0x2,%EDI |
(248) 0x439ccb LEA (%R9,%RAX,1),%RSI |
(248) 0x439ccf VMOVSD %XMM8,(%R15,%RSI,8) |
(248) 0x439cd5 LEA (%R11,%RAX,1),%RSI |
(248) 0x439cd9 ADD %R8,%RAX |
(248) 0x439cdc VMOVSD (%RCX),%XMM13 |
(248) 0x439ce0 VMOVSD %XMM13,(%R14,%RSI,8) |
(248) 0x439ce6 MOV 0x30(%RSP),%RSI |
(248) 0x439ceb VMOVSD 0x8(%R12,%RSI,1),%XMM14 |
(248) 0x439cf2 MOV %R8,%RSI |
(248) 0x439cf5 MOV 0x38(%RSP),%R8 |
(248) 0x439cfa VMOVSD %XMM14,(%R8,%RAX,8) |
(248) 0x439d00 CMP %EDX,%R10D |
(248) 0x439d03 JAE 439d33 |
(248) 0x439d05 MOVSXD %EDI,%R10 |
(248) 0x439d08 ADD %R10,%R9 |
(248) 0x439d0b ADD %R10,%R11 |
(248) 0x439d0e ADD %R10,%RSI |
(248) 0x439d11 VMOVSD %XMM8,(%R15,%R9,8) |
(248) 0x439d17 MOV 0x30(%RSP),%R15 |
(248) 0x439d1c VMOVSD (%RCX),%XMM15 |
(248) 0x439d20 VMOVSD %XMM15,(%R14,%R11,8) |
(248) 0x439d26 VMOVSD 0x10(%R12,%R15,1),%XMM2 |
(248) 0x439d2d VMOVSD %XMM2,(%R8,%RSI,8) |
(248) 0x439d33 MOV 0x14(%RSP),%R10D |
(248) 0x439d38 INC %RBX |
(248) 0x439d3b CMP %EBX,0x10(%RSP) |
(248) 0x439d3f JLE 439d60 |
(248) 0x439d41 MOV (%RSP),%ECX |
(248) 0x439d44 MOV 0x4(%RSP),%EDX |
(248) 0x439d48 MOVL $0,0x30(%RSP) |
(248) 0x439d50 SUB %R10D,%ECX |
(248) 0x439d53 JMP 439890 |
0x439d58 NOPL (%RAX,%RAX,1) |
0x439d60 VZEROUPPER |
0x439d63 LEA -0x28(%RBP),%RSP |
0x439d67 POP %RBX |
0x439d68 POP %R12 |
0x439d6a POP %R13 |
0x439d6c POP %R14 |
0x439d6e POP %R15 |
0x439d70 POP %RBP |
0x439d71 RET |
0x439d72 NOPW (%RAX,%RAX,1) |
(248) 0x439d78 MOV 0x30(%RSP),%EDI |
(248) 0x439d7c XOR %R9D,%R9D |
(248) 0x439d7f JMP 439bf9 |
0x439d84 INC %ECX |
0x439d86 XOR %EDX,%EDX |
0x439d88 JMP 43983f |
0x439d8d NOPL (%RAX) |
Path / |
Source file and lines | initialise_chunk.cpp:77-82 |
Module | exec |
nb instructions | 64 |
nb uops | 73 |
loop length | 220 |
used x86 registers | 14 |
used mmx registers | 0 |
used xmm registers | 2 |
used ymm registers | 1 |
used zmm registers | 1 |
nb stack references | 5 |
micro-operation queue | 12.17 cycles |
front end | 12.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 4.60 | 8.00 | 4.33 | 4.33 | 6.00 | 4.40 | 4.60 | 6.00 | 6.00 | 6.00 | 4.40 | 4.33 |
cycles | 4.60 | 10.13 | 4.33 | 4.33 | 6.00 | 4.40 | 4.60 | 6.00 | 6.00 | 6.00 | 4.40 | 4.33 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 12.18-12.22 |
Stall cycles | 0.01-0.05 |
ROB full (events) | 0.02-0.08 |
Front-end | 12.17 |
Dispatch | 10.13 |
DIV/SQRT | 12.00 |
Overall L1 | 12.17 |
all | 5% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 11% |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 0% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 4% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 11% |
all | 7% |
load | 7% |
store | 6% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 9% |
all | 12% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 12% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
all | 8% |
load | 9% |
store | 6% |
mul | 12% |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 10% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0x40,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x1c(%RDI),%R14D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RDI),%R15D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R14D,0x10(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15D,0x4(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %R14D,%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 439d63 <_Z16initialise_chunkiR16global_variables._omp_fn.4+0x583> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
TEST %R15D,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 439d63 <_Z16initialise_chunkiR16global_variables._omp_fn.4+0x583> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 404650 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 404540 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R14D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %R15D,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %EBX | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 439d84 <_Z16initialise_chunkiR16global_variables._omp_fn.4+0x5a4> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %ECX,%ESI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%RSI,%RDX,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RCX,%R10,1),%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDI,(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDI,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 439d63 <_Z16initialise_chunkiR16global_variables._omp_fn.4+0x583> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x4(%RSP),%R8D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVSD 0x8(%R12),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%R12),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIV %R8D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
VMULSD (%R12),%XMM2,%XMM8 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VBROADCASTSD %XMM8,%YMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VBROADCASTSD %XMM8,%ZMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
SUB %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EDX,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVSXD %EAX,%RBX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R8D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 43983f <_Z16initialise_chunkiR16global_variables._omp_fn.4+0x5f> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | initialise_chunk.cpp:77-82 |
Module | exec |
nb instructions | 64 |
nb uops | 73 |
loop length | 220 |
used x86 registers | 14 |
used mmx registers | 0 |
used xmm registers | 2 |
used ymm registers | 1 |
used zmm registers | 1 |
nb stack references | 5 |
micro-operation queue | 12.17 cycles |
front end | 12.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 4.60 | 8.00 | 4.33 | 4.33 | 6.00 | 4.40 | 4.60 | 6.00 | 6.00 | 6.00 | 4.40 | 4.33 |
cycles | 4.60 | 10.13 | 4.33 | 4.33 | 6.00 | 4.40 | 4.60 | 6.00 | 6.00 | 6.00 | 4.40 | 4.33 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 12.18-12.22 |
Stall cycles | 0.01-0.05 |
ROB full (events) | 0.02-0.08 |
Front-end | 12.17 |
Dispatch | 10.13 |
DIV/SQRT | 12.00 |
Overall L1 | 12.17 |
all | 5% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 11% |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 0% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 4% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 11% |
all | 7% |
load | 7% |
store | 6% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 9% |
all | 12% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 12% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
all | 8% |
load | 9% |
store | 6% |
mul | 12% |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 10% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0x40,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x1c(%RDI),%R14D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RDI),%R15D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R14D,0x10(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15D,0x4(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %R14D,%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 439d63 <_Z16initialise_chunkiR16global_variables._omp_fn.4+0x583> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
TEST %R15D,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 439d63 <_Z16initialise_chunkiR16global_variables._omp_fn.4+0x583> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 404650 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 404540 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R14D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %R15D,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %EBX | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 439d84 <_Z16initialise_chunkiR16global_variables._omp_fn.4+0x5a4> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %ECX,%ESI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%RSI,%RDX,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RCX,%R10,1),%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDI,(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDI,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 439d63 <_Z16initialise_chunkiR16global_variables._omp_fn.4+0x583> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x4(%RSP),%R8D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVSD 0x8(%R12),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%R12),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIV %R8D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
VMULSD (%R12),%XMM2,%XMM8 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VBROADCASTSD %XMM8,%YMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VBROADCASTSD %XMM8,%ZMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
SUB %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EDX,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVSXD %EAX,%RBX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R8D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 43983f <_Z16initialise_chunkiR16global_variables._omp_fn.4+0x5f> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼initialise_chunk(int, global_variables&) [clone ._omp_fn.4]– | 0.03 | 0.02 |
▼Loop 248 - initialise_chunk.cpp:77-82 - exec– | 0 | 0 |
○Loop 249 - initialise_chunk.cpp:80-82 - exec | 0.03 | 0.02 |