Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ... | Module: exec | Source: advec_cell.cpp:136-140 [...] | Coverage: 1.47% |
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Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ... | Module: exec | Source: advec_cell.cpp:136-140 [...] | Coverage: 1.47% |
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/scratch_na/users/xoserete/qaas_runs/171-291-1828/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69 |
-------------------------------------------------------------------------------- |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
/scratch_na/users/xoserete/qaas_runs/171-291-1828/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp: 136 - 140 |
-------------------------------------------------------------------------------- |
136: #pragma omp parallel for simd collapse(2) |
137: for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) { |
138: for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) { |
139: pre_vol(i, j) = volume(i, j) + (vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j) + vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j)); |
140: post_vol(i, j) = pre_vol(i, j) - (vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j)); |
0x427d70 PUSH %RBP |
0x427d71 MOV %RSP,%RBP |
0x427d74 PUSH %R15 |
0x427d76 PUSH %R14 |
0x427d78 PUSH %R13 |
0x427d7a PUSH %R12 |
0x427d7c MOV %RDI,%R12 |
0x427d7f PUSH %RBX |
0x427d80 AND $-0x40,%RSP |
0x427d84 SUB $0xc0,%RSP |
0x427d8b MOV 0x30(%RDI),%EAX |
0x427d8e MOV 0x34(%RDI),%ECX |
0x427d91 MOV 0x28(%RDI),%EDI |
0x427d94 MOV 0x2c(%R12),%EDX |
0x427d99 ADD $0x4,%ECX |
0x427d9c LEA -0x1(%RAX),%R15D |
0x427da0 DEC %EDI |
0x427da2 MOV %ECX,0x5c(%RSP) |
0x427da6 MOV %EDI,0x58(%RSP) |
0x427daa CMP %ECX,%R15D |
0x427dad JGE 42851b |
0x427db3 MOV %ECX,%EBX |
0x427db5 LEA 0x4(%RDX),%R14D |
0x427db9 SUB %R15D,%EBX |
0x427dbc CMP %R14D,%EDI |
0x427dbf JGE 42851b |
0x427dc5 MOV %R14D,%ESI |
0x427dc8 SUB %EDI,%ESI |
0x427dca MOV %ESI,0x78(%RSP) |
0x427dce CALL 404650 <omp_get_num_threads@plt> |
0x427dd3 MOV %EAX,%R13D |
0x427dd6 CALL 404540 <omp_get_thread_num@plt> |
0x427ddb XOR %EDX,%EDX |
0x427ddd MOV %EAX,%R8D |
0x427de0 MOV 0x78(%RSP),%EAX |
0x427de4 IMUL %EBX,%EAX |
0x427de7 DIV %R13D |
0x427dea MOV %EAX,%R13D |
0x427ded CMP %EDX,%R8D |
0x427df0 JB 42854f |
0x427df6 IMUL %R13D,%R8D |
0x427dfa LEA (%R8,%RDX,1),%R9D |
0x427dfe LEA (%R13,%R9,1),%R10D |
0x427e03 MOV %R10D,0x54(%RSP) |
0x427e08 CMP %R10D,%R9D |
0x427e0b JAE 42851b |
0x427e11 MOV %R9D,%EAX |
0x427e14 XOR %EDX,%EDX |
0x427e16 MOV 0x58(%RSP),%R11D |
0x427e1b MOV (%R12),%RCX |
0x427e1f DIVL 0x78(%RSP) |
0x427e23 MOV 0x10(%R12),%RDI |
0x427e28 MOV 0x18(%R12),%RBX |
0x427e2d MOV %RCX,0x48(%RSP) |
0x427e32 MOV %RDI,0x40(%RSP) |
0x427e37 MOV %RBX,0x30(%RSP) |
0x427e3c MOV %R14D,%R10D |
0x427e3f MOV 0x8(%R12),%R14 |
0x427e44 MOV 0x20(%R12),%R12 |
0x427e49 MOV %R14,0x38(%RSP) |
0x427e4e MOV %R12,0x28(%RSP) |
0x427e53 ADD %EDX,%R11D |
0x427e56 LEA (%RAX,%R15,1),%R15D |
0x427e5a MOV %R11D,0xa0(%RSP) |
0x427e62 SUB %R11D,%R10D |
0x427e65 MOVSXD %R15D,%RCX |
0x427e68 NOPL (%RAX,%RAX,1) |
(165) 0x427e70 CMP %R10D,%R13D |
(165) 0x427e73 CMOVBE %R13D,%R10D |
(165) 0x427e77 LEA (%R9,%R10,1),%ESI |
(165) 0x427e7b MOV %R10D,%EDX |
(165) 0x427e7e MOV %ESI,0x7c(%RSP) |
(165) 0x427e82 CMP %ESI,%R9D |
(165) 0x427e85 JAE 428530 |
(165) 0x427e8b MOV 0x40(%RSP),%R10 |
(165) 0x427e90 MOV 0x48(%RSP),%R8 |
(165) 0x427e95 LEA 0x1(%RCX),%RSI |
(165) 0x427e99 MOV 0x38(%RSP),%R11 |
(165) 0x427e9e MOV 0x30(%RSP),%R12 |
(165) 0x427ea3 MOV %RSI,0x60(%RSP) |
(165) 0x427ea8 MOV (%R10),%RAX |
(165) 0x427eab MOV 0x10(%R8),%R15 |
(165) 0x427eaf MOV (%R8),%R14 |
(165) 0x427eb2 MOV 0x10(%R12),%R13 |
(165) 0x427eb7 IMUL %RAX,%RSI |
(165) 0x427ebb MOV 0x10(%R10),%RDI |
(165) 0x427ebf MOV 0x10(%R11),%R8 |
(165) 0x427ec3 MOV %R15,0x90(%RSP) |
(165) 0x427ecb MOV 0x28(%RSP),%R10 |
(165) 0x427ed0 MOV (%R11),%R11 |
(165) 0x427ed3 IMUL %RCX,%R14 |
(165) 0x427ed7 MOV %R13,0xa8(%RSP) |
(165) 0x427edf MOV (%R12),%R12 |
(165) 0x427ee3 IMUL %RCX,%R11 |
(165) 0x427ee7 MOV %RSI,%RBX |
(165) 0x427eea MOV %RSI,0x68(%RSP) |
(165) 0x427eef IMUL %RCX,%R12 |
(165) 0x427ef3 SUB %RAX,%RBX |
(165) 0x427ef6 MOV 0x10(%R10),%RAX |
(165) 0x427efa MOV %R14,0x88(%RSP) |
(165) 0x427f02 IMUL (%R10),%RCX |
(165) 0x427f06 MOV %RBX,0x98(%RSP) |
(165) 0x427f0e MOV %R11,0x70(%RSP) |
(165) 0x427f13 MOV %R12,0x80(%RSP) |
(165) 0x427f1b MOV %RCX,0xb8(%RSP) |
(165) 0x427f23 LEA -0x1(%RDX),%ECX |
(165) 0x427f26 MOV %RAX,0xb0(%RSP) |
(165) 0x427f2e CMP $0x6,%ECX |
(165) 0x427f31 JBE 428540 |
(165) 0x427f37 MOVSXD 0xa0(%RSP),%RAX |
(165) 0x427f3f LEA (%RAX,%RBX,1),%RBX |
(165) 0x427f43 LEA 0x1(%RAX,%R11,1),%R11 |
(165) 0x427f48 LEA (%RAX,%RSI,1),%R10 |
(165) 0x427f4c LEA (%RAX,%R14,1),%R14 |
(165) 0x427f50 SAL $0x3,%R11 |
(165) 0x427f54 LEA (%RDI,%RBX,8),%RSI |
(165) 0x427f58 MOV 0xb8(%RSP),%RBX |
(165) 0x427f60 LEA (%R15,%R14,8),%R15 |
(165) 0x427f64 LEA (%R8,%R11,1),%R13 |
(165) 0x427f68 LEA -0x8(%R8,%R11,1),%R14 |
(165) 0x427f6d MOV 0xb0(%RSP),%R11 |
(165) 0x427f75 LEA (%RAX,%R12,1),%R12 |
(165) 0x427f79 ADD %RBX,%RAX |
(165) 0x427f7c LEA (%RDI,%R10,8),%RCX |
(165) 0x427f80 MOV 0xa8(%RSP),%R10 |
(165) 0x427f88 LEA (%R11,%RAX,8),%RBX |
(165) 0x427f8c MOV %EDX,%R11D |
(165) 0x427f8f XOR %EAX,%EAX |
(165) 0x427f91 SHR $0x3,%R11D |
(165) 0x427f95 LEA (%R10,%R12,8),%R12 |
(165) 0x427f99 SAL $0x6,%R11 |
(165) 0x427f9d LEA -0x40(%R11),%R10 |
(165) 0x427fa1 SHR $0x6,%R10 |
(165) 0x427fa5 INC %R10 |
(165) 0x427fa8 AND $0x3,%R10D |
(165) 0x427fac JE 4280b4 |
(165) 0x427fb2 CMP $0x1,%R10 |
(165) 0x427fb6 JE 42805b |
(165) 0x427fbc CMP $0x2,%R10 |
(165) 0x427fc0 JE 42800b |
(165) 0x427fc2 VMOVUPD (%R15),%ZMM3 |
(165) 0x427fc8 VMOVUPD (%RSI),%ZMM6 |
(165) 0x427fce MOV $0x40,%EAX |
(165) 0x427fd3 VADDPD (%RCX),%ZMM3,%ZMM0 |
(165) 0x427fd9 VADDPD (%R14),%ZMM6,%ZMM1 |
(165) 0x427fdf VSUBPD %ZMM1,%ZMM0,%ZMM2 |
(165) 0x427fe5 VADDPD (%R13),%ZMM2,%ZMM4 |
(165) 0x427fec VMOVUPD %ZMM4,(%R12) |
(165) 0x427ff3 VMOVUPD (%RSI),%ZMM7 |
(165) 0x427ff9 VSUBPD (%RCX),%ZMM7,%ZMM5 |
(165) 0x427fff VADDPD %ZMM4,%ZMM5,%ZMM8 |
(165) 0x428005 VMOVUPD %ZMM8,(%RBX) |
(165) 0x42800b VMOVUPD (%R15,%RAX,1),%ZMM9 |
(165) 0x428012 VMOVUPD (%RSI,%RAX,1),%ZMM11 |
(165) 0x428019 VADDPD (%RCX,%RAX,1),%ZMM9,%ZMM10 |
(165) 0x428020 VADDPD (%R14,%RAX,1),%ZMM11,%ZMM12 |
(165) 0x428027 VSUBPD %ZMM12,%ZMM10,%ZMM13 |
(165) 0x42802d VADDPD (%R13,%RAX,1),%ZMM13,%ZMM14 |
(165) 0x428035 VMOVUPD %ZMM14,(%R12,%RAX,1) |
(165) 0x42803c VMOVUPD (%RSI,%RAX,1),%ZMM15 |
(165) 0x428043 VSUBPD (%RCX,%RAX,1),%ZMM15,%ZMM3 |
(165) 0x42804a VADDPD %ZMM14,%ZMM3,%ZMM0 |
(165) 0x428050 VMOVUPD %ZMM0,(%RBX,%RAX,1) |
(165) 0x428057 ADD $0x40,%RAX |
(165) 0x42805b VMOVUPD (%R15,%RAX,1),%ZMM6 |
(165) 0x428062 VMOVUPD (%RSI,%RAX,1),%ZMM1 |
(165) 0x428069 VADDPD (%RCX,%RAX,1),%ZMM6,%ZMM2 |
(165) 0x428070 VADDPD (%R14,%RAX,1),%ZMM1,%ZMM4 |
(165) 0x428077 VSUBPD %ZMM4,%ZMM2,%ZMM7 |
(165) 0x42807d VADDPD (%R13,%RAX,1),%ZMM7,%ZMM5 |
(165) 0x428085 VMOVUPD %ZMM5,(%R12,%RAX,1) |
(165) 0x42808c VMOVUPD (%RSI,%RAX,1),%ZMM8 |
(165) 0x428093 VSUBPD (%RCX,%RAX,1),%ZMM8,%ZMM9 |
(165) 0x42809a VADDPD %ZMM5,%ZMM9,%ZMM10 |
(165) 0x4280a0 VMOVUPD %ZMM10,(%RBX,%RAX,1) |
(165) 0x4280a7 ADD $0x40,%RAX |
(165) 0x4280ab CMP %RAX,%R11 |
(165) 0x4280ae JE 42820b |
(166) 0x4280b4 VMOVUPD (%R15,%RAX,1),%ZMM11 |
(166) 0x4280bb VMOVUPD (%RSI,%RAX,1),%ZMM13 |
(166) 0x4280c2 VADDPD (%RCX,%RAX,1),%ZMM11,%ZMM12 |
(166) 0x4280c9 VADDPD (%R14,%RAX,1),%ZMM13,%ZMM14 |
(166) 0x4280d0 VSUBPD %ZMM14,%ZMM12,%ZMM15 |
(166) 0x4280d6 VADDPD (%R13,%RAX,1),%ZMM15,%ZMM3 |
(166) 0x4280de VMOVUPD %ZMM3,(%R12,%RAX,1) |
(166) 0x4280e5 VMOVUPD (%RSI,%RAX,1),%ZMM0 |
(166) 0x4280ec VSUBPD (%RCX,%RAX,1),%ZMM0,%ZMM6 |
(166) 0x4280f3 VADDPD %ZMM3,%ZMM6,%ZMM2 |
(166) 0x4280f9 VMOVUPD %ZMM2,(%RBX,%RAX,1) |
(166) 0x428100 VMOVUPD 0x40(%R15,%RAX,1),%ZMM1 |
(166) 0x428108 VMOVUPD 0x40(%RSI,%RAX,1),%ZMM4 |
(166) 0x428110 VADDPD 0x40(%RCX,%RAX,1),%ZMM1,%ZMM7 |
(166) 0x428118 VADDPD 0x40(%R14,%RAX,1),%ZMM4,%ZMM5 |
(166) 0x428120 VSUBPD %ZMM5,%ZMM7,%ZMM8 |
(166) 0x428126 VADDPD 0x40(%R13,%RAX,1),%ZMM8,%ZMM9 |
(166) 0x42812e VMOVUPD %ZMM9,0x40(%R12,%RAX,1) |
(166) 0x428136 VMOVUPD 0x40(%RSI,%RAX,1),%ZMM10 |
(166) 0x42813e VSUBPD 0x40(%RCX,%RAX,1),%ZMM10,%ZMM11 |
(166) 0x428146 VADDPD %ZMM9,%ZMM11,%ZMM12 |
(166) 0x42814c VMOVUPD %ZMM12,0x40(%RBX,%RAX,1) |
(166) 0x428154 VMOVUPD 0x80(%R15,%RAX,1),%ZMM13 |
(166) 0x42815c VMOVUPD 0x80(%RSI,%RAX,1),%ZMM15 |
(166) 0x428164 VADDPD 0x80(%RCX,%RAX,1),%ZMM13,%ZMM14 |
(166) 0x42816c VADDPD 0x80(%R14,%RAX,1),%ZMM15,%ZMM3 |
(166) 0x428174 VSUBPD %ZMM3,%ZMM14,%ZMM0 |
(166) 0x42817a VADDPD 0x80(%R13,%RAX,1),%ZMM0,%ZMM6 |
(166) 0x428182 VMOVUPD %ZMM6,0x80(%R12,%RAX,1) |
(166) 0x42818a VMOVUPD 0x80(%RSI,%RAX,1),%ZMM2 |
(166) 0x428192 VSUBPD 0x80(%RCX,%RAX,1),%ZMM2,%ZMM1 |
(166) 0x42819a VADDPD %ZMM6,%ZMM1,%ZMM7 |
(166) 0x4281a0 VMOVUPD %ZMM7,0x80(%RBX,%RAX,1) |
(166) 0x4281a8 VMOVUPD 0xc0(%R15,%RAX,1),%ZMM4 |
(166) 0x4281b0 VMOVUPD 0xc0(%RSI,%RAX,1),%ZMM8 |
(166) 0x4281b8 VADDPD 0xc0(%RCX,%RAX,1),%ZMM4,%ZMM5 |
(166) 0x4281c0 VADDPD 0xc0(%R14,%RAX,1),%ZMM8,%ZMM9 |
(166) 0x4281c8 VSUBPD %ZMM9,%ZMM5,%ZMM10 |
(166) 0x4281ce VADDPD 0xc0(%R13,%RAX,1),%ZMM10,%ZMM11 |
(166) 0x4281d6 VMOVUPD %ZMM11,0xc0(%R12,%RAX,1) |
(166) 0x4281de VMOVUPD 0xc0(%RSI,%RAX,1),%ZMM12 |
(166) 0x4281e6 VSUBPD 0xc0(%RCX,%RAX,1),%ZMM12,%ZMM13 |
(166) 0x4281ee VADDPD %ZMM11,%ZMM13,%ZMM14 |
(166) 0x4281f4 VMOVUPD %ZMM14,0xc0(%RBX,%RAX,1) |
(166) 0x4281fc ADD $0x100,%RAX |
(166) 0x428202 CMP %RAX,%R11 |
(166) 0x428205 JNE 4280b4 |
(165) 0x42820b MOV 0xa0(%RSP),%R15D |
(165) 0x428213 MOV %EDX,%R13D |
(165) 0x428216 AND $-0x8,%R13D |
(165) 0x42821a ADD %R13D,%R9D |
(165) 0x42821d LEA (%R13,%R15,1),%ESI |
(165) 0x428222 TEST $0x7,%DL |
(165) 0x428225 JE 4284e6 |
(165) 0x42822b SUB %R13D,%EDX |
(165) 0x42822e LEA -0x1(%RDX),%ECX |
(165) 0x428231 CMP $0x2,%ECX |
(165) 0x428234 JBE 428302 |
(165) 0x42823a MOVSXD 0xa0(%RSP),%RAX |
(165) 0x428242 MOV 0x98(%RSP),%RBX |
(165) 0x42824a MOV 0x68(%RSP),%R14 |
(165) 0x42824f MOV 0x70(%RSP),%R15 |
(165) 0x428254 LEA (%RBX,%RAX,1),%R10 |
(165) 0x428258 MOV 0x88(%RSP),%RBX |
(165) 0x428260 LEA (%R14,%RAX,1),%R12 |
(165) 0x428264 ADD %R13,%R10 |
(165) 0x428267 LEA (%R15,%RAX,1),%R14 |
(165) 0x42826b MOV 0x90(%RSP),%R15 |
(165) 0x428273 ADD %R13,%R12 |
(165) 0x428276 LEA (%RDI,%R10,8),%RCX |
(165) 0x42827a LEA (%RBX,%RAX,1),%R10 |
(165) 0x42827e MOV 0xa8(%RSP),%RBX |
(165) 0x428286 LEA (%RDI,%R12,8),%R11 |
(165) 0x42828a ADD %R13,%R10 |
(165) 0x42828d LEA 0x1(%R13,%R14,1),%R12 |
(165) 0x428292 MOV 0x80(%RSP),%R14 |
(165) 0x42829a VMOVUPD (%R8,%R12,8),%YMM3 |
(165) 0x4282a0 VMOVUPD (%R15,%R10,8),%YMM15 |
(165) 0x4282a6 VSUBPD (%RCX),%YMM3,%YMM6 |
(165) 0x4282aa VADDPD (%R11),%YMM15,%YMM0 |
(165) 0x4282af VADDPD %YMM6,%YMM0,%YMM2 |
(165) 0x4282b3 VSUBPD -0x8(%R8,%R12,8),%YMM2,%YMM7 |
(165) 0x4282ba LEA (%R14,%RAX,1),%R12 |
(165) 0x4282be ADD %R13,%R12 |
(165) 0x4282c1 VMOVUPD %YMM7,(%RBX,%R12,8) |
(165) 0x4282c7 VMOVUPD (%RCX),%YMM1 |
(165) 0x4282cb VSUBPD (%R11),%YMM1,%YMM4 |
(165) 0x4282d0 MOV 0xb8(%RSP),%R11 |
(165) 0x4282d8 ADD %R11,%RAX |
(165) 0x4282db VADDPD %YMM7,%YMM4,%YMM5 |
(165) 0x4282df ADD %R13,%RAX |
(165) 0x4282e2 MOV 0xb0(%RSP),%R13 |
(165) 0x4282ea VMOVUPD %YMM5,(%R13,%RAX,8) |
(165) 0x4282f1 TEST $0x3,%DL |
(165) 0x4282f4 JE 4284e6 |
(165) 0x4282fa AND $-0x4,%EDX |
(165) 0x4282fd ADD %EDX,%R9D |
(165) 0x428300 ADD %EDX,%ESI |
(165) 0x428302 MOV 0x68(%RSP),%R15 |
(165) 0x428307 MOVSXD %ESI,%RDX |
(165) 0x42830a MOV 0x70(%RSP),%R14 |
(165) 0x42830f MOV 0x98(%RSP),%R13 |
(165) 0x428317 LEA (%R15,%RDX,1),%RAX |
(165) 0x42831b LEA (%RDI,%RAX,8),%R10 |
(165) 0x42831f LEA 0x1(%RSI),%EAX |
(165) 0x428322 CLTQ |
(165) 0x428324 LEA (%R13,%RDX,1),%RCX |
(165) 0x428329 LEA (%R14,%RAX,1),%R12 |
(165) 0x42832d LEA (%RDI,%RCX,8),%R11 |
(165) 0x428331 MOV 0x90(%RSP),%RCX |
(165) 0x428339 LEA (%R8,%R12,8),%RBX |
(165) 0x42833d MOV 0x88(%RSP),%R12 |
(165) 0x428345 MOV %RBX,0xa0(%RSP) |
(165) 0x42834d LEA (%R12,%RDX,1),%RBX |
(165) 0x428351 VMOVSD (%RCX,%RBX,8),%XMM8 |
(165) 0x428356 LEA (%R14,%RDX,1),%RCX |
(165) 0x42835a MOV 0xa0(%RSP),%RBX |
(165) 0x428362 VADDSD (%R10),%XMM8,%XMM9 |
(165) 0x428367 VMOVSD (%RBX),%XMM10 |
(165) 0x42836b MOV 0x80(%RSP),%RBX |
(165) 0x428373 VSUBSD (%R11),%XMM10,%XMM11 |
(165) 0x428378 ADD %RDX,%RBX |
(165) 0x42837b VADDSD %XMM11,%XMM9,%XMM12 |
(165) 0x428380 VSUBSD (%R8,%RCX,8),%XMM12,%XMM13 |
(165) 0x428386 MOV 0xa8(%RSP),%RCX |
(165) 0x42838e VMOVSD %XMM13,(%RCX,%RBX,8) |
(165) 0x428393 MOV 0xb8(%RSP),%RBX |
(165) 0x42839b VMOVSD (%R11),%XMM14 |
(165) 0x4283a0 MOV 0x7c(%RSP),%R11D |
(165) 0x4283a5 ADD %RBX,%RDX |
(165) 0x4283a8 VSUBSD (%R10),%XMM14,%XMM15 |
(165) 0x4283ad MOV 0xb0(%RSP),%R10 |
(165) 0x4283b5 VADDSD %XMM13,%XMM15,%XMM0 |
(165) 0x4283ba VMOVSD %XMM0,(%R10,%RDX,8) |
(165) 0x4283c0 LEA 0x1(%R9),%EDX |
(165) 0x4283c4 CMP %R11D,%EDX |
(165) 0x4283c7 JAE 4284e6 |
(165) 0x4283cd LEA (%RAX,%R13,1),%R13 |
(165) 0x4283d1 ADD %RAX,%R12 |
(165) 0x4283d4 LEA (%RAX,%R15,1),%RCX |
(165) 0x4283d8 ADD $0x2,%R9D |
(165) 0x4283dc LEA (%RDI,%R13,8),%R11 |
(165) 0x4283e0 MOV 0x90(%RSP),%R13 |
(165) 0x4283e8 LEA (%RDI,%RCX,8),%R10 |
(165) 0x4283ec LEA 0x2(%RSI),%EBX |
(165) 0x4283ef VMOVSD (%R13,%R12,8),%XMM3 |
(165) 0x4283f6 MOV 0xa0(%RSP),%R12 |
(165) 0x4283fe MOVSXD %EBX,%RDX |
(165) 0x428401 LEA (%R14,%RDX,1),%RCX |
(165) 0x428405 MOV 0xa8(%RSP),%R13 |
(165) 0x42840d VMOVSD (%R12),%XMM2 |
(165) 0x428413 VADDSD (%R10),%XMM3,%XMM6 |
(165) 0x428418 LEA (%R8,%RCX,8),%RBX |
(165) 0x42841c MOV 0x80(%RSP),%R12 |
(165) 0x428424 VADDSD (%R11),%XMM2,%XMM7 |
(165) 0x428429 MOV %R12,%RCX |
(165) 0x42842c ADD %RAX,%RCX |
(165) 0x42842f VSUBSD %XMM7,%XMM6,%XMM1 |
(165) 0x428433 VADDSD (%RBX),%XMM1,%XMM4 |
(165) 0x428437 VMOVSD %XMM4,(%R13,%RCX,8) |
(165) 0x42843e MOV 0xb8(%RSP),%RCX |
(165) 0x428446 VMOVSD (%R11),%XMM5 |
(165) 0x42844b MOV 0xb0(%RSP),%R11 |
(165) 0x428453 ADD %RCX,%RAX |
(165) 0x428456 VSUBSD (%R10),%XMM5,%XMM8 |
(165) 0x42845b VADDSD %XMM4,%XMM8,%XMM9 |
(165) 0x42845f VMOVSD %XMM9,(%R11,%RAX,8) |
(165) 0x428465 MOV 0x7c(%RSP),%EAX |
(165) 0x428469 CMP %EAX,%R9D |
(165) 0x42846c JAE 4284e6 |
(165) 0x42846e MOV 0x98(%RSP),%R9 |
(165) 0x428476 ADD %RDX,%R15 |
(165) 0x428479 MOV 0x90(%RSP),%RAX |
(165) 0x428481 ADD $0x3,%ESI |
(165) 0x428484 LEA (%RDI,%R15,8),%R10 |
(165) 0x428488 MOVSXD %ESI,%RSI |
(165) 0x42848b ADD %RDX,%R12 |
(165) 0x42848e ADD %RDX,%R9 |
(165) 0x428491 ADD %R14,%RSI |
(165) 0x428494 LEA (%RDI,%R9,8),%RCX |
(165) 0x428498 MOV 0x88(%RSP),%RDI |
(165) 0x4284a0 VMOVSD (%RCX),%XMM12 |
(165) 0x4284a4 ADD %RDX,%RDI |
(165) 0x4284a7 VMOVSD (%RAX,%RDI,8),%XMM10 |
(165) 0x4284ac VADDSD (%RBX),%XMM12,%XMM13 |
(165) 0x4284b0 VADDSD (%R10),%XMM10,%XMM11 |
(165) 0x4284b5 VSUBSD %XMM13,%XMM11,%XMM14 |
(165) 0x4284ba VADDSD (%R8,%RSI,8),%XMM14,%XMM15 |
(165) 0x4284c0 MOV 0xb8(%RSP),%R8 |
(165) 0x4284c8 ADD %RDX,%R8 |
(165) 0x4284cb VMOVSD %XMM15,(%R13,%R12,8) |
(165) 0x4284d2 VMOVSD (%RCX),%XMM0 |
(165) 0x4284d6 VSUBSD (%R10),%XMM0,%XMM3 |
(165) 0x4284db VADDSD %XMM15,%XMM3,%XMM6 |
(165) 0x4284e0 VMOVSD %XMM6,(%R11,%R8,8) |
(165) 0x4284e6 MOV 0x7c(%RSP),%R9D |
(165) 0x4284eb MOV 0x60(%RSP),%RCX |
(165) 0x4284f0 LEA (%RCX),%EDX |
(165) 0x4284f2 CMP %EDX,0x5c(%RSP) |
(165) 0x4284f6 JLE 428518 |
(165) 0x4284f8 MOV 0x54(%RSP),%R13D |
(165) 0x4284fd MOV 0x58(%RSP),%EBX |
(165) 0x428501 MOV 0x78(%RSP),%R10D |
(165) 0x428506 MOV %EBX,0xa0(%RSP) |
(165) 0x42850d SUB %R9D,%R13D |
(165) 0x428510 JMP 427e70 |
0x428515 NOPL (%RAX) |
0x428518 VZEROUPPER |
0x42851b LEA -0x28(%RBP),%RSP |
0x42851f POP %RBX |
0x428520 POP %R12 |
0x428522 POP %R13 |
0x428524 POP %R14 |
0x428526 POP %R15 |
0x428528 POP %RBP |
0x428529 RET |
0x42852a NOPW (%RAX,%RAX,1) |
(165) 0x428530 LEA 0x1(%RCX),%R13 |
(165) 0x428534 MOV %R13,0x60(%RSP) |
(165) 0x428539 JMP 4284eb |
0x42853b NOPL (%RAX,%RAX,1) |
(165) 0x428540 MOV 0xa0(%RSP),%ESI |
(165) 0x428547 XOR %R13D,%R13D |
(165) 0x42854a JMP 42822b |
0x42854f INC %R13D |
0x428552 XOR %EDX,%EDX |
0x428554 JMP 427df6 |
0x428559 NOPL (%RAX) |
Path / |
Source file and lines | advec_cell.cpp:136-140 |
Module | exec |
nb instructions | 83 |
nb uops | 93 |
loop length | 305 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 11 |
micro-operation queue | 15.50 cycles |
front end | 15.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.10 | 8.00 | 6.33 | 6.33 | 9.00 | 6.07 | 5.90 | 9.00 | 9.00 | 9.00 | 5.93 | 6.33 |
cycles | 6.10 | 11.93 | 6.33 | 6.33 | 9.00 | 6.07 | 5.90 | 9.00 | 9.00 | 9.00 | 5.93 | 6.33 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.75-14.83 |
Stall cycles | 0.00 |
Front-end | 15.50 |
Dispatch | 11.93 |
DIV/SQRT | 12.00 |
Overall L1 | 15.50 |
all | 3% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 11% |
all | 8% |
load | 9% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 9% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0xc0,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x30(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x34(%RDI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RDI),%EDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%R12),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x4,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA -0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
DEC %EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ECX,0x5c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EDI,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %ECX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 42851b <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4+0x7ab> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %ECX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x4(%RDX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 42851b <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4+0x7ab> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R14D,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %EDI,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ESI,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 404650 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 404540 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x78(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R13D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 42854f <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4+0x7df> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %R13D,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%R13,%R9,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R10D,0x54(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R10D,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 42851b <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4+0x7ab> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R9D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x58(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R12),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x78(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x10(%R12),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%R12),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDI,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14D,%R10D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x8(%R12),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%R12),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R14,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%RAX,%R15,1),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R11D,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R11D,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %R15D,%RCX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %R13D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 427df6 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4+0x86> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | advec_cell.cpp:136-140 |
Module | exec |
nb instructions | 83 |
nb uops | 93 |
loop length | 305 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 11 |
micro-operation queue | 15.50 cycles |
front end | 15.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.10 | 8.00 | 6.33 | 6.33 | 9.00 | 6.07 | 5.90 | 9.00 | 9.00 | 9.00 | 5.93 | 6.33 |
cycles | 6.10 | 11.93 | 6.33 | 6.33 | 9.00 | 6.07 | 5.90 | 9.00 | 9.00 | 9.00 | 5.93 | 6.33 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.75-14.83 |
Stall cycles | 0.00 |
Front-end | 15.50 |
Dispatch | 11.93 |
DIV/SQRT | 12.00 |
Overall L1 | 15.50 |
all | 3% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 11% |
all | 8% |
load | 9% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 9% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0xc0,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x30(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x34(%RDI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RDI),%EDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%R12),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x4,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA -0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
DEC %EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ECX,0x5c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EDI,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %ECX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 42851b <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4+0x7ab> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %ECX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x4(%RDX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 42851b <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4+0x7ab> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R14D,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %EDI,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ESI,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 404650 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 404540 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x78(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R13D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 42854f <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4+0x7df> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %R13D,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%R13,%R9,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R10D,0x54(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R10D,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 42851b <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4+0x7ab> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R9D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x58(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R12),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x78(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x10(%R12),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%R12),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDI,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14D,%R10D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x8(%R12),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%R12),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R14,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%RAX,%R15,1),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R11D,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R11D,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %R15D,%RCX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %R13D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 427df6 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4+0x86> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D | 1.47 | 1.11 |
▼Loop 165 - advec_cell.cpp:136-140 - exec– | 0 | 0 |
○Loop 166 - advec_cell.cpp:139-140 - exec | 1.46 | 1.1 |