Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ... | Module: exec | Source: advec_cell.cpp:44-48 [...] | Coverage: 1.5% |
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Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ... | Module: exec | Source: advec_cell.cpp:44-48 [...] | Coverage: 1.5% |
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/scratch_na/users/xoserete/qaas_runs/171-291-1828/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69 |
-------------------------------------------------------------------------------- |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
/scratch_na/users/xoserete/qaas_runs/171-291-1828/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp: 44 - 48 |
-------------------------------------------------------------------------------- |
44: #pragma omp parallel for simd collapse(2) |
45: for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) { |
46: for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) { |
47: pre_vol(i, j) = volume(i, j) + (vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j) + vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j)); |
48: post_vol(i, j) = pre_vol(i, j) - (vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j)); |
0x426920 PUSH %RBP |
0x426921 MOV %RSP,%RBP |
0x426924 PUSH %R15 |
0x426926 PUSH %R14 |
0x426928 PUSH %R13 |
0x42692a PUSH %R12 |
0x42692c MOV %RDI,%R12 |
0x42692f PUSH %RBX |
0x426930 AND $-0x40,%RSP |
0x426934 SUB $0xc0,%RSP |
0x42693b MOV 0x30(%RDI),%EAX |
0x42693e MOV 0x34(%RDI),%ECX |
0x426941 MOV 0x28(%RDI),%EDI |
0x426944 MOV 0x2c(%R12),%EDX |
0x426949 ADD $0x4,%ECX |
0x42694c LEA -0x1(%RAX),%R15D |
0x426950 DEC %EDI |
0x426952 MOV %ECX,0x5c(%RSP) |
0x426956 MOV %EDI,0x58(%RSP) |
0x42695a CMP %ECX,%R15D |
0x42695d JGE 4270b3 |
0x426963 MOV %ECX,%EBX |
0x426965 LEA 0x4(%RDX),%R14D |
0x426969 SUB %R15D,%EBX |
0x42696c CMP %R14D,%EDI |
0x42696f JGE 4270b3 |
0x426975 MOV %R14D,%ESI |
0x426978 SUB %EDI,%ESI |
0x42697a MOV %ESI,0x88(%RSP) |
0x426981 CALL 404650 <omp_get_num_threads@plt> |
0x426986 MOV %EAX,%R13D |
0x426989 CALL 404540 <omp_get_thread_num@plt> |
0x42698e XOR %EDX,%EDX |
0x426990 MOV %EAX,%R8D |
0x426993 MOV 0x88(%RSP),%EAX |
0x42699a IMUL %EBX,%EAX |
0x42699d DIV %R13D |
0x4269a0 MOV %EAX,%ESI |
0x4269a2 CMP %EDX,%R8D |
0x4269a5 JB 4270e7 |
0x4269ab IMUL %ESI,%R8D |
0x4269af LEA (%R8,%RDX,1),%R9D |
0x4269b3 LEA (%RSI,%R9,1),%R10D |
0x4269b7 MOV %R10D,0x54(%RSP) |
0x4269bc CMP %R10D,%R9D |
0x4269bf JAE 4270b3 |
0x4269c5 MOV %R9D,%EAX |
0x4269c8 XOR %EDX,%EDX |
0x4269ca MOV 0x58(%RSP),%R11D |
0x4269cf MOV (%R12),%RCX |
0x4269d3 DIVL 0x88(%RSP) |
0x4269da MOV 0x8(%R12),%RDI |
0x4269df MOV 0x18(%R12),%RBX |
0x4269e4 MOV %RCX,0x48(%RSP) |
0x4269e9 MOV %RDI,0x40(%RSP) |
0x4269ee MOV %RBX,0x30(%RSP) |
0x4269f3 MOV %R14D,%R10D |
0x4269f6 MOV 0x10(%R12),%R14 |
0x4269fb MOV 0x20(%R12),%R12 |
0x426a00 MOV %R14,0x38(%RSP) |
0x426a05 MOV %R12,0x28(%RSP) |
0x426a0a ADD %EDX,%R11D |
0x426a0d LEA (%RAX,%R15,1),%R15D |
0x426a11 MOV %R11D,0xa0(%RSP) |
0x426a19 SUB %R11D,%R10D |
0x426a1c MOVSXD %R15D,%RCX |
0x426a1f NOP |
(159) 0x426a20 CMP %R10D,%ESI |
(159) 0x426a23 CMOVBE %ESI,%R10D |
(159) 0x426a27 LEA (%R9,%R10,1),%ESI |
(159) 0x426a2b MOV %R10D,%EDX |
(159) 0x426a2e MOV %ESI,0x8c(%RSP) |
(159) 0x426a35 CMP %ESI,%R9D |
(159) 0x426a38 JAE 4270c8 |
(159) 0x426a3e MOV 0x38(%RSP),%RAX |
(159) 0x426a43 LEA 0x1(%RCX),%R14 |
(159) 0x426a47 MOV 0x48(%RSP),%R8 |
(159) 0x426a4c MOV 0x40(%RSP),%R10 |
(159) 0x426a51 MOV 0x30(%RSP),%R13 |
(159) 0x426a56 MOV %R14,0x60(%RSP) |
(159) 0x426a5b MOV (%RAX),%R12 |
(159) 0x426a5e MOV (%R8),%RSI |
(159) 0x426a61 MOV (%R10),%R11 |
(159) 0x426a64 MOV 0x10(%RAX),%RDI |
(159) 0x426a68 IMUL %R12,%R14 |
(159) 0x426a6c MOV 0x28(%RSP),%RAX |
(159) 0x426a71 MOV 0x10(%R8),%R15 |
(159) 0x426a75 IMUL %RCX,%RSI |
(159) 0x426a79 MOV 0x10(%R10),%R8 |
(159) 0x426a7d MOV 0x10(%R13),%R10 |
(159) 0x426a81 IMUL %RCX,%R11 |
(159) 0x426a85 MOV %R15,0x98(%RSP) |
(159) 0x426a8d MOV %R14,%RBX |
(159) 0x426a90 MOV %R14,0x78(%RSP) |
(159) 0x426a95 SUB %R12,%RBX |
(159) 0x426a98 MOV (%R13),%R12 |
(159) 0x426a9c MOV 0x10(%RAX),%R13 |
(159) 0x426aa0 MOV %RSI,0x68(%RSP) |
(159) 0x426aa5 MOV %R11,0x70(%RSP) |
(159) 0x426aaa IMUL %RCX,%R12 |
(159) 0x426aae MOV %RBX,0x80(%RSP) |
(159) 0x426ab6 IMUL (%RAX),%RCX |
(159) 0x426aba MOV %R10,0xa8(%RSP) |
(159) 0x426ac2 MOV %R13,0xb8(%RSP) |
(159) 0x426aca MOV %R12,0x90(%RSP) |
(159) 0x426ad2 MOV %RCX,0xb0(%RSP) |
(159) 0x426ada LEA -0x1(%RDX),%ECX |
(159) 0x426add CMP $0x6,%ECX |
(159) 0x426ae0 JBE 4270d8 |
(159) 0x426ae6 MOVSXD 0xa0(%RSP),%RAX |
(159) 0x426aee LEA 0x1(%RAX,%R11,1),%R11 |
(159) 0x426af3 LEA (%RAX,%RSI,1),%R10 |
(159) 0x426af7 SAL $0x3,%R11 |
(159) 0x426afb LEA (%RAX,%R14,1),%R14 |
(159) 0x426aff LEA (%RAX,%RBX,1),%RBX |
(159) 0x426b03 LEA (%R8,%R11,1),%RCX |
(159) 0x426b07 LEA -0x8(%R8,%R11,1),%RSI |
(159) 0x426b0c MOV 0xb0(%RSP),%R11 |
(159) 0x426b14 LEA (%RAX,%R12,1),%R12 |
(159) 0x426b18 LEA (%R15,%R10,8),%R15 |
(159) 0x426b1c MOV 0xa8(%RSP),%R10 |
(159) 0x426b24 ADD %R11,%RAX |
(159) 0x426b27 MOV %EDX,%R11D |
(159) 0x426b2a LEA (%RDI,%R14,8),%R13 |
(159) 0x426b2e SHR $0x3,%R11D |
(159) 0x426b32 LEA (%R10,%R12,8),%R12 |
(159) 0x426b36 LEA (%RDI,%RBX,8),%R14 |
(159) 0x426b3a MOV 0xb8(%RSP),%RBX |
(159) 0x426b42 SAL $0x6,%R11 |
(159) 0x426b46 LEA -0x40(%R11),%R10 |
(159) 0x426b4a LEA (%RBX,%RAX,8),%RBX |
(159) 0x426b4e XOR %EAX,%EAX |
(159) 0x426b50 SHR $0x6,%R10 |
(159) 0x426b54 INC %R10 |
(159) 0x426b57 AND $0x3,%R10D |
(159) 0x426b5b JE 426c63 |
(159) 0x426b61 CMP $0x1,%R10 |
(159) 0x426b65 JE 426c0a |
(159) 0x426b6b CMP $0x2,%R10 |
(159) 0x426b6f JE 426bba |
(159) 0x426b71 VMOVUPD (%R15),%ZMM4 |
(159) 0x426b77 VMOVUPD (%RSI),%ZMM5 |
(159) 0x426b7d MOV $0x40,%EAX |
(159) 0x426b82 VADDPD (%RCX),%ZMM4,%ZMM0 |
(159) 0x426b88 VADDPD (%R14),%ZMM5,%ZMM1 |
(159) 0x426b8e VSUBPD %ZMM1,%ZMM0,%ZMM2 |
(159) 0x426b94 VADDPD (%R13),%ZMM2,%ZMM3 |
(159) 0x426b9b VMOVUPD %ZMM3,(%R12) |
(159) 0x426ba2 VMOVUPD (%RSI),%ZMM6 |
(159) 0x426ba8 VSUBPD (%RCX),%ZMM6,%ZMM7 |
(159) 0x426bae VADDPD %ZMM3,%ZMM7,%ZMM8 |
(159) 0x426bb4 VMOVUPD %ZMM8,(%RBX) |
(159) 0x426bba VMOVUPD (%R15,%RAX,1),%ZMM9 |
(159) 0x426bc1 VMOVUPD (%RSI,%RAX,1),%ZMM11 |
(159) 0x426bc8 VADDPD (%RCX,%RAX,1),%ZMM9,%ZMM10 |
(159) 0x426bcf VADDPD (%R14,%RAX,1),%ZMM11,%ZMM12 |
(159) 0x426bd6 VSUBPD %ZMM12,%ZMM10,%ZMM13 |
(159) 0x426bdc VADDPD (%R13,%RAX,1),%ZMM13,%ZMM14 |
(159) 0x426be4 VMOVUPD %ZMM14,(%R12,%RAX,1) |
(159) 0x426beb VMOVUPD (%RSI,%RAX,1),%ZMM15 |
(159) 0x426bf2 VSUBPD (%RCX,%RAX,1),%ZMM15,%ZMM4 |
(159) 0x426bf9 VADDPD %ZMM14,%ZMM4,%ZMM0 |
(159) 0x426bff VMOVUPD %ZMM0,(%RBX,%RAX,1) |
(159) 0x426c06 ADD $0x40,%RAX |
(159) 0x426c0a VMOVUPD (%R15,%RAX,1),%ZMM5 |
(159) 0x426c11 VMOVUPD (%RSI,%RAX,1),%ZMM1 |
(159) 0x426c18 VADDPD (%RCX,%RAX,1),%ZMM5,%ZMM2 |
(159) 0x426c1f VADDPD (%R14,%RAX,1),%ZMM1,%ZMM3 |
(159) 0x426c26 VSUBPD %ZMM3,%ZMM2,%ZMM6 |
(159) 0x426c2c VADDPD (%R13,%RAX,1),%ZMM6,%ZMM7 |
(159) 0x426c34 VMOVUPD %ZMM7,(%R12,%RAX,1) |
(159) 0x426c3b VMOVUPD (%RSI,%RAX,1),%ZMM8 |
(159) 0x426c42 VSUBPD (%RCX,%RAX,1),%ZMM8,%ZMM9 |
(159) 0x426c49 VADDPD %ZMM7,%ZMM9,%ZMM10 |
(159) 0x426c4f VMOVUPD %ZMM10,(%RBX,%RAX,1) |
(159) 0x426c56 ADD $0x40,%RAX |
(159) 0x426c5a CMP %RAX,%R11 |
(159) 0x426c5d JE 426dba |
(160) 0x426c63 VMOVUPD (%R15,%RAX,1),%ZMM11 |
(160) 0x426c6a VMOVUPD (%RSI,%RAX,1),%ZMM13 |
(160) 0x426c71 VADDPD (%RCX,%RAX,1),%ZMM11,%ZMM12 |
(160) 0x426c78 VADDPD (%R14,%RAX,1),%ZMM13,%ZMM14 |
(160) 0x426c7f VSUBPD %ZMM14,%ZMM12,%ZMM15 |
(160) 0x426c85 VADDPD (%R13,%RAX,1),%ZMM15,%ZMM4 |
(160) 0x426c8d VMOVUPD %ZMM4,(%R12,%RAX,1) |
(160) 0x426c94 VMOVUPD (%RSI,%RAX,1),%ZMM0 |
(160) 0x426c9b VSUBPD (%RCX,%RAX,1),%ZMM0,%ZMM5 |
(160) 0x426ca2 VADDPD %ZMM4,%ZMM5,%ZMM2 |
(160) 0x426ca8 VMOVUPD %ZMM2,(%RBX,%RAX,1) |
(160) 0x426caf VMOVUPD 0x40(%R15,%RAX,1),%ZMM1 |
(160) 0x426cb7 VMOVUPD 0x40(%RSI,%RAX,1),%ZMM6 |
(160) 0x426cbf VADDPD 0x40(%RCX,%RAX,1),%ZMM1,%ZMM3 |
(160) 0x426cc7 VADDPD 0x40(%R14,%RAX,1),%ZMM6,%ZMM7 |
(160) 0x426ccf VSUBPD %ZMM7,%ZMM3,%ZMM8 |
(160) 0x426cd5 VADDPD 0x40(%R13,%RAX,1),%ZMM8,%ZMM9 |
(160) 0x426cdd VMOVUPD %ZMM9,0x40(%R12,%RAX,1) |
(160) 0x426ce5 VMOVUPD 0x40(%RSI,%RAX,1),%ZMM10 |
(160) 0x426ced VSUBPD 0x40(%RCX,%RAX,1),%ZMM10,%ZMM11 |
(160) 0x426cf5 VADDPD %ZMM9,%ZMM11,%ZMM12 |
(160) 0x426cfb VMOVUPD %ZMM12,0x40(%RBX,%RAX,1) |
(160) 0x426d03 VMOVUPD 0x80(%R15,%RAX,1),%ZMM13 |
(160) 0x426d0b VMOVUPD 0x80(%RSI,%RAX,1),%ZMM15 |
(160) 0x426d13 VADDPD 0x80(%RCX,%RAX,1),%ZMM13,%ZMM14 |
(160) 0x426d1b VADDPD 0x80(%R14,%RAX,1),%ZMM15,%ZMM4 |
(160) 0x426d23 VSUBPD %ZMM4,%ZMM14,%ZMM0 |
(160) 0x426d29 VADDPD 0x80(%R13,%RAX,1),%ZMM0,%ZMM5 |
(160) 0x426d31 VMOVUPD %ZMM5,0x80(%R12,%RAX,1) |
(160) 0x426d39 VMOVUPD 0x80(%RSI,%RAX,1),%ZMM2 |
(160) 0x426d41 VSUBPD 0x80(%RCX,%RAX,1),%ZMM2,%ZMM1 |
(160) 0x426d49 VADDPD %ZMM5,%ZMM1,%ZMM3 |
(160) 0x426d4f VMOVUPD %ZMM3,0x80(%RBX,%RAX,1) |
(160) 0x426d57 VMOVUPD 0xc0(%R15,%RAX,1),%ZMM6 |
(160) 0x426d5f VMOVUPD 0xc0(%RSI,%RAX,1),%ZMM8 |
(160) 0x426d67 VADDPD 0xc0(%RCX,%RAX,1),%ZMM6,%ZMM7 |
(160) 0x426d6f VADDPD 0xc0(%R14,%RAX,1),%ZMM8,%ZMM9 |
(160) 0x426d77 VSUBPD %ZMM9,%ZMM7,%ZMM10 |
(160) 0x426d7d VADDPD 0xc0(%R13,%RAX,1),%ZMM10,%ZMM11 |
(160) 0x426d85 VMOVUPD %ZMM11,0xc0(%R12,%RAX,1) |
(160) 0x426d8d VMOVUPD 0xc0(%RSI,%RAX,1),%ZMM12 |
(160) 0x426d95 VSUBPD 0xc0(%RCX,%RAX,1),%ZMM12,%ZMM13 |
(160) 0x426d9d VADDPD %ZMM11,%ZMM13,%ZMM14 |
(160) 0x426da3 VMOVUPD %ZMM14,0xc0(%RBX,%RAX,1) |
(160) 0x426dab ADD $0x100,%RAX |
(160) 0x426db1 CMP %RAX,%R11 |
(160) 0x426db4 JNE 426c63 |
(159) 0x426dba MOV 0xa0(%RSP),%R15D |
(159) 0x426dc2 MOV %EDX,%R13D |
(159) 0x426dc5 AND $-0x8,%R13D |
(159) 0x426dc9 ADD %R13D,%R9D |
(159) 0x426dcc LEA (%R13,%R15,1),%ESI |
(159) 0x426dd1 TEST $0x7,%DL |
(159) 0x426dd4 JE 42707b |
(159) 0x426dda SUB %R13D,%EDX |
(159) 0x426ddd LEA -0x1(%RDX),%ECX |
(159) 0x426de0 CMP $0x2,%ECX |
(159) 0x426de3 JBE 426eb0 |
(159) 0x426de9 MOVSXD 0xa0(%RSP),%RAX |
(159) 0x426df1 MOV 0x70(%RSP),%R14 |
(159) 0x426df6 MOV 0x78(%RSP),%R15 |
(159) 0x426dfb MOV 0x68(%RSP),%R10 |
(159) 0x426e00 LEA (%R14,%RAX,1),%R12 |
(159) 0x426e04 LEA 0x1(%R13,%R12,1),%R11 |
(159) 0x426e09 LEA (%R15,%RAX,1),%R12 |
(159) 0x426e0d MOV 0x90(%RSP),%R15 |
(159) 0x426e15 SAL $0x3,%R11 |
(159) 0x426e19 ADD %R13,%R12 |
(159) 0x426e1c LEA (%R10,%RAX,1),%R14 |
(159) 0x426e20 MOV 0x80(%RSP),%R10 |
(159) 0x426e28 LEA (%R8,%R11,1),%RBX |
(159) 0x426e2c VMOVUPD (%RDI,%R12,8),%YMM15 |
(159) 0x426e32 LEA -0x8(%R8,%R11,1),%RCX |
(159) 0x426e37 MOV 0x98(%RSP),%R11 |
(159) 0x426e3f VMOVUPD (%RBX),%YMM0 |
(159) 0x426e43 ADD %R13,%R14 |
(159) 0x426e46 LEA (%R15,%RAX,1),%R12 |
(159) 0x426e4a VADDPD (%R11,%R14,8),%YMM15,%YMM4 |
(159) 0x426e50 LEA (%R10,%RAX,1),%R14 |
(159) 0x426e54 MOV 0xa8(%RSP),%R11 |
(159) 0x426e5c ADD %R13,%R12 |
(159) 0x426e5f VSUBPD (%RCX),%YMM0,%YMM5 |
(159) 0x426e63 ADD %R13,%R14 |
(159) 0x426e66 VADDPD %YMM5,%YMM4,%YMM2 |
(159) 0x426e6a VSUBPD (%RDI,%R14,8),%YMM2,%YMM3 |
(159) 0x426e70 VMOVUPD %YMM3,(%R11,%R12,8) |
(159) 0x426e76 VMOVUPD (%RCX),%YMM1 |
(159) 0x426e7a VSUBPD (%RBX),%YMM1,%YMM6 |
(159) 0x426e7e MOV 0xb0(%RSP),%RBX |
(159) 0x426e86 ADD %RBX,%RAX |
(159) 0x426e89 VADDPD %YMM3,%YMM6,%YMM7 |
(159) 0x426e8d ADD %R13,%RAX |
(159) 0x426e90 MOV 0xb8(%RSP),%R13 |
(159) 0x426e98 VMOVUPD %YMM7,(%R13,%RAX,8) |
(159) 0x426e9f TEST $0x3,%DL |
(159) 0x426ea2 JE 42707b |
(159) 0x426ea8 AND $-0x4,%EDX |
(159) 0x426eab ADD %EDX,%R9D |
(159) 0x426eae ADD %EDX,%ESI |
(159) 0x426eb0 MOV 0x70(%RSP),%R15 |
(159) 0x426eb5 LEA 0x1(%RSI),%EDX |
(159) 0x426eb8 MOV 0x68(%RSP),%R14 |
(159) 0x426ebd MOVSXD %ESI,%RAX |
(159) 0x426ec0 MOVSXD %EDX,%RDX |
(159) 0x426ec3 MOV 0x98(%RSP),%R12 |
(159) 0x426ecb MOV 0x78(%RSP),%R13 |
(159) 0x426ed0 LEA (%R15,%RDX,1),%RCX |
(159) 0x426ed4 LEA (%R14,%RAX,1),%RBX |
(159) 0x426ed8 LEA (%R8,%RCX,8),%RCX |
(159) 0x426edc VMOVSD (%R12,%RBX,8),%XMM8 |
(159) 0x426ee2 LEA (%R15,%RAX,1),%R10 |
(159) 0x426ee6 MOV 0x80(%RSP),%R12 |
(159) 0x426eee VMOVSD (%RCX),%XMM10 |
(159) 0x426ef2 LEA (%R8,%R10,8),%R10 |
(159) 0x426ef6 LEA (%R13,%RAX,1),%R11 |
(159) 0x426efb VADDSD (%RDI,%R11,8),%XMM8,%XMM9 |
(159) 0x426f01 LEA (%R12,%RAX,1),%RBX |
(159) 0x426f05 MOV 0x90(%RSP),%R11 |
(159) 0x426f0d VSUBSD (%R10),%XMM10,%XMM11 |
(159) 0x426f12 LEA (%R11,%RAX,1),%R11 |
(159) 0x426f16 VADDSD %XMM11,%XMM9,%XMM12 |
(159) 0x426f1b VSUBSD (%RDI,%RBX,8),%XMM12,%XMM13 |
(159) 0x426f20 MOV 0xa8(%RSP),%RBX |
(159) 0x426f28 VMOVSD %XMM13,(%RBX,%R11,8) |
(159) 0x426f2e MOV 0xb0(%RSP),%R11 |
(159) 0x426f36 MOV 0x8c(%RSP),%EBX |
(159) 0x426f3d VMOVSD (%R10),%XMM14 |
(159) 0x426f42 MOV 0xb8(%RSP),%R10 |
(159) 0x426f4a ADD %R11,%RAX |
(159) 0x426f4d VSUBSD (%RCX),%XMM14,%XMM15 |
(159) 0x426f51 VADDSD %XMM13,%XMM15,%XMM4 |
(159) 0x426f56 VMOVSD %XMM4,(%R10,%RAX,8) |
(159) 0x426f5c LEA 0x1(%R9),%EAX |
(159) 0x426f60 CMP %EBX,%EAX |
(159) 0x426f62 JAE 42707b |
(159) 0x426f68 LEA 0x2(%RSI),%EAX |
(159) 0x426f6b MOV %R15,%RBX |
(159) 0x426f6e LEA (%RDX,%R14,1),%R11 |
(159) 0x426f72 ADD $0x2,%R9D |
(159) 0x426f76 CLTQ |
(159) 0x426f78 LEA (%R15,%RAX,1),%R15 |
(159) 0x426f7c LEA (%R8,%R15,8),%R10 |
(159) 0x426f80 MOV 0x98(%RSP),%R15 |
(159) 0x426f88 MOV %R10,0xa0(%RSP) |
(159) 0x426f90 VMOVSD (%R15,%R11,8),%XMM0 |
(159) 0x426f96 MOV %R12,%R15 |
(159) 0x426f99 LEA (%R12,%RDX,1),%R12 |
(159) 0x426f9d VMOVSD (%RDI,%R12,8),%XMM2 |
(159) 0x426fa3 MOV 0x90(%RSP),%R12 |
(159) 0x426fab VADDSD (%R10),%XMM0,%XMM5 |
(159) 0x426fb0 LEA (%R13,%RDX,1),%R10 |
(159) 0x426fb5 VADDSD (%RCX),%XMM2,%XMM3 |
(159) 0x426fb9 LEA (%R12,%RDX,1),%R11 |
(159) 0x426fbd VSUBSD %XMM3,%XMM5,%XMM1 |
(159) 0x426fc1 VADDSD (%RDI,%R10,8),%XMM1,%XMM6 |
(159) 0x426fc7 MOV 0xa8(%RSP),%R10 |
(159) 0x426fcf VMOVSD %XMM6,(%R10,%R11,8) |
(159) 0x426fd5 MOV 0xb0(%RSP),%R11 |
(159) 0x426fdd VMOVSD (%RCX),%XMM7 |
(159) 0x426fe1 MOV 0xa0(%RSP),%RCX |
(159) 0x426fe9 ADD %R11,%RDX |
(159) 0x426fec VSUBSD (%RCX),%XMM7,%XMM8 |
(159) 0x426ff0 MOV 0xb8(%RSP),%RCX |
(159) 0x426ff8 VADDSD %XMM6,%XMM8,%XMM9 |
(159) 0x426ffc VMOVSD %XMM9,(%RCX,%RDX,8) |
(159) 0x427001 MOV 0x8c(%RSP),%EDX |
(159) 0x427008 CMP %EDX,%R9D |
(159) 0x42700b JAE 42707b |
(159) 0x42700d ADD $0x3,%ESI |
(159) 0x427010 ADD %RAX,%R14 |
(159) 0x427013 ADD %RAX,%R15 |
(159) 0x427016 ADD %RAX,%R13 |
(159) 0x427019 MOVSXD %ESI,%R9 |
(159) 0x42701c MOV 0x98(%RSP),%RSI |
(159) 0x427024 VMOVSD (%RDI,%R15,8),%XMM12 |
(159) 0x42702a ADD %RAX,%R12 |
(159) 0x42702d ADD %RBX,%R9 |
(159) 0x427030 MOV 0xa0(%RSP),%RBX |
(159) 0x427038 ADD %RAX,%R11 |
(159) 0x42703b VMOVSD (%RSI,%R14,8),%XMM10 |
(159) 0x427041 LEA (%R8,%R9,8),%R8 |
(159) 0x427045 VADDSD (%RBX),%XMM12,%XMM13 |
(159) 0x427049 VADDSD (%R8),%XMM10,%XMM11 |
(159) 0x42704e VSUBSD %XMM13,%XMM11,%XMM14 |
(159) 0x427053 VADDSD (%RDI,%R13,8),%XMM14,%XMM15 |
(159) 0x427059 MOV 0xb8(%RSP),%RDI |
(159) 0x427061 VMOVSD %XMM15,(%R10,%R12,8) |
(159) 0x427067 VMOVSD (%RBX),%XMM4 |
(159) 0x42706b VSUBSD (%R8),%XMM4,%XMM0 |
(159) 0x427070 VADDSD %XMM15,%XMM0,%XMM5 |
(159) 0x427075 VMOVSD %XMM5,(%RDI,%R11,8) |
(159) 0x42707b MOV 0x8c(%RSP),%R9D |
(159) 0x427083 MOV 0x60(%RSP),%RCX |
(159) 0x427088 LEA (%RCX),%EAX |
(159) 0x42708a CMP %EAX,0x5c(%RSP) |
(159) 0x42708e JLE 4270b0 |
(159) 0x427090 MOV 0x54(%RSP),%ESI |
(159) 0x427094 MOV 0x58(%RSP),%EDX |
(159) 0x427098 MOV 0x88(%RSP),%R10D |
(159) 0x4270a0 MOV %EDX,0xa0(%RSP) |
(159) 0x4270a7 SUB %R9D,%ESI |
(159) 0x4270aa JMP 426a20 |
0x4270af NOP |
0x4270b0 VZEROUPPER |
0x4270b3 LEA -0x28(%RBP),%RSP |
0x4270b7 POP %RBX |
0x4270b8 POP %R12 |
0x4270ba POP %R13 |
0x4270bc POP %R14 |
0x4270be POP %R15 |
0x4270c0 POP %RBP |
0x4270c1 RET |
0x4270c2 NOPW (%RAX,%RAX,1) |
(159) 0x4270c8 LEA 0x1(%RCX),%R13 |
(159) 0x4270cc MOV %R13,0x60(%RSP) |
(159) 0x4270d1 JMP 427083 |
0x4270d3 NOPL (%RAX,%RAX,1) |
(159) 0x4270d8 MOV 0xa0(%RSP),%ESI |
(159) 0x4270df XOR %R13D,%R13D |
(159) 0x4270e2 JMP 426dda |
0x4270e7 INC %ESI |
0x4270e9 XOR %EDX,%EDX |
0x4270eb JMP 4269ab |
Path / |
Source file and lines | advec_cell.cpp:44-48 |
Module | exec |
nb instructions | 82 |
nb uops | 92 |
loop length | 295 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 11 |
micro-operation queue | 15.33 cycles |
front end | 15.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.10 | 8.00 | 6.33 | 6.33 | 9.00 | 6.07 | 5.90 | 9.00 | 9.00 | 9.00 | 5.93 | 6.33 |
cycles | 6.10 | 11.93 | 6.33 | 6.33 | 9.00 | 6.07 | 5.90 | 9.00 | 9.00 | 9.00 | 5.93 | 6.33 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.56-14.66 |
Stall cycles | 0.00 |
Front-end | 15.33 |
Dispatch | 11.93 |
DIV/SQRT | 12.00 |
Overall L1 | 15.33 |
all | 3% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 11% |
all | 8% |
load | 9% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 9% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0xc0,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x30(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x34(%RDI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RDI),%EDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%R12),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x4,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA -0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
DEC %EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ECX,0x5c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EDI,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %ECX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 4270b3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x793> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %ECX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x4(%RDX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 4270b3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x793> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R14D,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %EDI,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ESI,0x88(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 404650 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 404540 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x88(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R13D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 4270e7 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x7c7> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %ESI,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RSI,%R9,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R10D,0x54(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R10D,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 4270b3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x793> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R9D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x58(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R12),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x88(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x8(%R12),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%R12),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDI,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14D,%R10D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x10(%R12),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%R12),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R14,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%RAX,%R15,1),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R11D,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R11D,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %R15D,%RCX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 4269ab <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x8b> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
Source file and lines | advec_cell.cpp:44-48 |
Module | exec |
nb instructions | 82 |
nb uops | 92 |
loop length | 295 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 11 |
micro-operation queue | 15.33 cycles |
front end | 15.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.10 | 8.00 | 6.33 | 6.33 | 9.00 | 6.07 | 5.90 | 9.00 | 9.00 | 9.00 | 5.93 | 6.33 |
cycles | 6.10 | 11.93 | 6.33 | 6.33 | 9.00 | 6.07 | 5.90 | 9.00 | 9.00 | 9.00 | 5.93 | 6.33 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.56-14.66 |
Stall cycles | 0.00 |
Front-end | 15.33 |
Dispatch | 11.93 |
DIV/SQRT | 12.00 |
Overall L1 | 15.33 |
all | 3% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 11% |
all | 8% |
load | 9% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 9% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0xc0,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x30(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x34(%RDI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RDI),%EDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%R12),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x4,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA -0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
DEC %EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ECX,0x5c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EDI,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %ECX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 4270b3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x793> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %ECX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x4(%RDX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 4270b3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x793> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R14D,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %EDI,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ESI,0x88(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 404650 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 404540 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x88(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R13D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 4270e7 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x7c7> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %ESI,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R8,%RDX,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RSI,%R9,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R10D,0x54(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R10D,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 4270b3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x793> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R9D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x58(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R12),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x88(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x8(%R12),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%R12),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDI,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14D,%R10D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x10(%R12),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%R12),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R14,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%RAX,%R15,1),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R11D,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R11D,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %R15D,%RCX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 4269ab <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x8b> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D | 1.5 | 1.13 |
▼Loop 159 - advec_cell.cpp:44-48 - exec– | 0 | 0 |
○Loop 160 - advec_cell.cpp:47-48 - exec | 1.5 | 1.13 |