Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ... | Module: exec | Source: advec_mom.cpp:44-48 [...] | Coverage: 3.03% |
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Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ... | Module: exec | Source: advec_mom.cpp:44-48 [...] | Coverage: 3.03% |
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/scratch_na/users/xoserete/qaas_runs/171-291-1828/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69 |
-------------------------------------------------------------------------------- |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
/scratch_na/users/xoserete/qaas_runs/171-291-1828/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp: 44 - 48 |
-------------------------------------------------------------------------------- |
44: #pragma omp parallel for simd collapse(2) |
45: for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) { |
46: for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) { |
47: post_vol(i, j) = volume(i, j) + vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j); |
48: pre_vol(i, j) = post_vol(i, j) + vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j); |
0x42abe0 PUSH %RBP |
0x42abe1 MOV %RSP,%RBP |
0x42abe4 PUSH %R15 |
0x42abe6 PUSH %R14 |
0x42abe8 PUSH %R13 |
0x42abea PUSH %R12 |
0x42abec MOV %RDI,%R12 |
0x42abef PUSH %RBX |
0x42abf0 AND $-0x40,%RSP |
0x42abf4 SUB $0xc0,%RSP |
0x42abfb MOV 0x30(%RDI),%EAX |
0x42abfe MOV 0x34(%RDI),%EDX |
0x42ac01 MOV 0x28(%RDI),%ESI |
0x42ac04 MOV 0x2c(%R12),%ECX |
0x42ac09 ADD $0x4,%EDX |
0x42ac0c LEA -0x1(%RAX),%R15D |
0x42ac10 LEA -0x1(%RSI),%EDI |
0x42ac13 MOV %EDX,0x60(%RSP) |
0x42ac17 MOV %EDI,0x5c(%RSP) |
0x42ac1b CMP %EDX,%R15D |
0x42ac1e JGE 42b27b |
0x42ac24 MOV %EDX,%EBX |
0x42ac26 LEA 0x4(%RCX),%R14D |
0x42ac2a SUB %R15D,%EBX |
0x42ac2d CMP %R14D,%EDI |
0x42ac30 JGE 42b27b |
0x42ac36 MOV %R14D,%R8D |
0x42ac39 SUB %EDI,%R8D |
0x42ac3c MOV %R8D,0x64(%RSP) |
0x42ac41 CALL 404650 <omp_get_num_threads@plt> |
0x42ac46 MOV %EAX,%R13D |
0x42ac49 CALL 404540 <omp_get_thread_num@plt> |
0x42ac4e XOR %EDX,%EDX |
0x42ac50 MOV %EAX,%R9D |
0x42ac53 MOV 0x64(%RSP),%EAX |
0x42ac57 IMUL %EBX,%EAX |
0x42ac5a DIV %R13D |
0x42ac5d MOV %EAX,%R13D |
0x42ac60 CMP %EDX,%R9D |
0x42ac63 JB 42b2b0 |
0x42ac69 IMUL %R13D,%R9D |
0x42ac6d LEA (%R9,%RDX,1),%EDI |
0x42ac71 LEA (%R13,%RDI,1),%R10D |
0x42ac76 MOV %R10D,0x58(%RSP) |
0x42ac7b CMP %R10D,%EDI |
0x42ac7e JAE 42b27b |
0x42ac84 MOV %EDI,%EAX |
0x42ac86 XOR %EDX,%EDX |
0x42ac88 MOV 0x5c(%RSP),%R11D |
0x42ac8d MOV (%R12),%R8 |
0x42ac91 DIVL 0x64(%RSP) |
0x42ac95 MOV 0x10(%R12),%RSI |
0x42ac9a MOV 0x20(%R12),%RBX |
0x42ac9f MOV %R8,0x38(%RSP) |
0x42aca4 MOV %RSI,0x50(%RSP) |
0x42aca9 MOV %RBX,0x40(%RSP) |
0x42acae ADD %EDX,%R11D |
0x42acb1 MOV %R14D,%EDX |
0x42acb4 MOV 0x8(%R12),%R14 |
0x42acb9 MOV 0x18(%R12),%R12 |
0x42acbe MOV %R11D,0xb4(%RSP) |
0x42acc6 LEA (%RAX,%R15,1),%R15D |
0x42acca SUB %R11D,%EDX |
0x42accd MOV %R14,0x48(%RSP) |
0x42acd2 MOVSXD %R15D,%R8 |
0x42acd5 MOV %R12,0x30(%RSP) |
0x42acda NOPW (%RAX,%RAX,1) |
(178) 0x42ace0 CMP %EDX,%R13D |
(178) 0x42ace3 CMOVBE %R13D,%EDX |
(178) 0x42ace7 LEA (%RDI,%RDX,1),%ECX |
(178) 0x42acea MOV %ECX,0xb0(%RSP) |
(178) 0x42acf1 CMP %ECX,%EDI |
(178) 0x42acf3 JAE 42b290 |
(178) 0x42acf9 MOV 0x48(%RSP),%R10 |
(178) 0x42acfe LEA 0x1(%R8),%R15 |
(178) 0x42ad02 MOV 0x50(%RSP),%R9 |
(178) 0x42ad07 MOV %R15,0x68(%RSP) |
(178) 0x42ad0c MOV 0x40(%RSP),%R11 |
(178) 0x42ad11 MOV (%R10),%RAX |
(178) 0x42ad14 MOV 0x10(%R9),%R13 |
(178) 0x42ad18 MOV (%R9),%R14 |
(178) 0x42ad1b MOV 0x10(%R10),%RCX |
(178) 0x42ad1f IMUL %RAX,%R15 |
(178) 0x42ad23 MOV 0x38(%RSP),%R9 |
(178) 0x42ad28 MOV 0x10(%R11),%R12 |
(178) 0x42ad2c MOV %R13,0xa0(%RSP) |
(178) 0x42ad34 MOV (%R11),%R11 |
(178) 0x42ad37 IMUL %R8,%R14 |
(178) 0x42ad3b MOV 0x10(%R9),%RSI |
(178) 0x42ad3f MOV (%R9),%R9 |
(178) 0x42ad42 MOV %R12,0xa8(%RSP) |
(178) 0x42ad4a MOV %R15,%RBX |
(178) 0x42ad4d IMUL %R8,%R11 |
(178) 0x42ad51 MOV %R15,0x78(%RSP) |
(178) 0x42ad56 SUB %RAX,%RBX |
(178) 0x42ad59 MOV 0x30(%RSP),%RAX |
(178) 0x42ad5e IMUL %R8,%R9 |
(178) 0x42ad62 MOV %R14,0x70(%RSP) |
(178) 0x42ad67 MOV %RBX,0x80(%RSP) |
(178) 0x42ad6f MOV 0x10(%RAX),%R10 |
(178) 0x42ad73 MOV %R11,0x88(%RSP) |
(178) 0x42ad7b MOV %R9,0x90(%RSP) |
(178) 0x42ad83 MOV %R10,0xb8(%RSP) |
(178) 0x42ad8b MOV (%RAX),%R10 |
(178) 0x42ad8e IMUL %R8,%R10 |
(178) 0x42ad92 LEA -0x1(%RDX),%R8D |
(178) 0x42ad96 MOV %R10,0x98(%RSP) |
(178) 0x42ad9e CMP $0x6,%R8D |
(178) 0x42ada2 JBE 42b2a0 |
(178) 0x42ada8 MOVSXD 0xb4(%RSP),%RAX |
(178) 0x42adb0 LEA 0x1(%R9,%RAX,1),%R8 |
(178) 0x42adb5 MOV %EDX,%R9D |
(178) 0x42adb8 LEA (%RBX,%RAX,1),%RBX |
(178) 0x42adbc SHR $0x3,%R9D |
(178) 0x42adc0 LEA (%R11,%RAX,1),%R11 |
(178) 0x42adc4 SAL $0x3,%R8 |
(178) 0x42adc8 LEA (%R14,%RAX,1),%R14 |
(178) 0x42adcc SAL $0x6,%R9 |
(178) 0x42add0 LEA (%R13,%R14,8),%R14 |
(178) 0x42add5 LEA (%R12,%R11,8),%R12 |
(178) 0x42add9 LEA (%RCX,%RBX,8),%R13 |
(178) 0x42addd LEA -0x8(%RSI,%R8,1),%R11 |
(178) 0x42ade2 LEA (%RSI,%R8,1),%RBX |
(178) 0x42ade6 LEA -0x40(%R9),%R8 |
(178) 0x42adea LEA (%R15,%RAX,1),%R15 |
(178) 0x42adee SHR $0x6,%R8 |
(178) 0x42adf2 ADD %R10,%RAX |
(178) 0x42adf5 MOV 0xb8(%RSP),%R10 |
(178) 0x42adfd INC %R8 |
(178) 0x42ae00 LEA (%RCX,%R15,8),%R15 |
(178) 0x42ae04 LEA (%R10,%RAX,8),%R10 |
(178) 0x42ae08 XOR %EAX,%EAX |
(178) 0x42ae0a AND $0x3,%R8D |
(178) 0x42ae0e JE 42aed8 |
(178) 0x42ae14 CMP $0x1,%R8 |
(178) 0x42ae18 JE 42ae93 |
(178) 0x42ae1a CMP $0x2,%R8 |
(178) 0x42ae1e JE 42ae57 |
(178) 0x42ae20 VMOVUPD (%R14),%ZMM7 |
(178) 0x42ae26 MOV $0x40,%EAX |
(178) 0x42ae2b VADDPD (%R15),%ZMM7,%ZMM0 |
(178) 0x42ae31 VSUBPD (%R13),%ZMM0,%ZMM2 |
(178) 0x42ae38 VMOVUPD %ZMM2,(%R12) |
(178) 0x42ae3f VMOVUPD (%RBX),%ZMM1 |
(178) 0x42ae45 VSUBPD (%R11),%ZMM1,%ZMM3 |
(178) 0x42ae4b VADDPD %ZMM2,%ZMM3,%ZMM4 |
(178) 0x42ae51 VMOVUPD %ZMM4,(%R10) |
(178) 0x42ae57 VMOVUPD (%R14,%RAX,1),%ZMM5 |
(178) 0x42ae5e VADDPD (%R15,%RAX,1),%ZMM5,%ZMM6 |
(178) 0x42ae65 VSUBPD (%R13,%RAX,1),%ZMM6,%ZMM8 |
(178) 0x42ae6d VMOVUPD %ZMM8,(%R12,%RAX,1) |
(178) 0x42ae74 VMOVUPD (%RBX,%RAX,1),%ZMM9 |
(178) 0x42ae7b VSUBPD (%R11,%RAX,1),%ZMM9,%ZMM10 |
(178) 0x42ae82 VADDPD %ZMM8,%ZMM10,%ZMM11 |
(178) 0x42ae88 VMOVUPD %ZMM11,(%R10,%RAX,1) |
(178) 0x42ae8f ADD $0x40,%RAX |
(178) 0x42ae93 VMOVUPD (%R14,%RAX,1),%ZMM12 |
(178) 0x42ae9a VADDPD (%R15,%RAX,1),%ZMM12,%ZMM13 |
(178) 0x42aea1 VSUBPD (%R13,%RAX,1),%ZMM13,%ZMM14 |
(178) 0x42aea9 VMOVUPD %ZMM14,(%R12,%RAX,1) |
(178) 0x42aeb0 VMOVUPD (%RBX,%RAX,1),%ZMM15 |
(178) 0x42aeb7 VSUBPD (%R11,%RAX,1),%ZMM15,%ZMM7 |
(178) 0x42aebe VADDPD %ZMM14,%ZMM7,%ZMM0 |
(178) 0x42aec4 VMOVUPD %ZMM0,(%R10,%RAX,1) |
(178) 0x42aecb ADD $0x40,%RAX |
(178) 0x42aecf CMP %RAX,%R9 |
(178) 0x42aed2 JE 42afd9 |
(179) 0x42aed8 VMOVUPD (%R14,%RAX,1),%ZMM2 |
(179) 0x42aedf VADDPD (%R15,%RAX,1),%ZMM2,%ZMM1 |
(179) 0x42aee6 VSUBPD (%R13,%RAX,1),%ZMM1,%ZMM3 |
(179) 0x42aeee VMOVUPD %ZMM3,(%R12,%RAX,1) |
(179) 0x42aef5 VMOVUPD (%RBX,%RAX,1),%ZMM4 |
(179) 0x42aefc VSUBPD (%R11,%RAX,1),%ZMM4,%ZMM5 |
(179) 0x42af03 VADDPD %ZMM3,%ZMM5,%ZMM6 |
(179) 0x42af09 VMOVUPD %ZMM6,(%R10,%RAX,1) |
(179) 0x42af10 VMOVUPD 0x40(%R14,%RAX,1),%ZMM8 |
(179) 0x42af18 VADDPD 0x40(%R15,%RAX,1),%ZMM8,%ZMM9 |
(179) 0x42af20 VSUBPD 0x40(%R13,%RAX,1),%ZMM9,%ZMM10 |
(179) 0x42af28 VMOVUPD %ZMM10,0x40(%R12,%RAX,1) |
(179) 0x42af30 VMOVUPD 0x40(%RBX,%RAX,1),%ZMM11 |
(179) 0x42af38 VSUBPD 0x40(%R11,%RAX,1),%ZMM11,%ZMM12 |
(179) 0x42af40 VADDPD %ZMM10,%ZMM12,%ZMM13 |
(179) 0x42af46 VMOVUPD %ZMM13,0x40(%R10,%RAX,1) |
(179) 0x42af4e VMOVUPD 0x80(%R14,%RAX,1),%ZMM14 |
(179) 0x42af56 VADDPD 0x80(%R15,%RAX,1),%ZMM14,%ZMM15 |
(179) 0x42af5e VSUBPD 0x80(%R13,%RAX,1),%ZMM15,%ZMM7 |
(179) 0x42af66 VMOVUPD %ZMM7,0x80(%R12,%RAX,1) |
(179) 0x42af6e VMOVUPD 0x80(%RBX,%RAX,1),%ZMM0 |
(179) 0x42af76 VSUBPD 0x80(%R11,%RAX,1),%ZMM0,%ZMM2 |
(179) 0x42af7e VADDPD %ZMM7,%ZMM2,%ZMM1 |
(179) 0x42af84 VMOVUPD %ZMM1,0x80(%R10,%RAX,1) |
(179) 0x42af8c VMOVUPD 0xc0(%R14,%RAX,1),%ZMM3 |
(179) 0x42af94 VADDPD 0xc0(%R15,%RAX,1),%ZMM3,%ZMM4 |
(179) 0x42af9c VSUBPD 0xc0(%R13,%RAX,1),%ZMM4,%ZMM6 |
(179) 0x42afa4 VMOVUPD %ZMM6,0xc0(%R12,%RAX,1) |
(179) 0x42afac VMOVUPD 0xc0(%RBX,%RAX,1),%ZMM5 |
(179) 0x42afb4 VSUBPD 0xc0(%R11,%RAX,1),%ZMM5,%ZMM8 |
(179) 0x42afbc VADDPD %ZMM6,%ZMM8,%ZMM9 |
(179) 0x42afc2 VMOVUPD %ZMM9,0xc0(%R10,%RAX,1) |
(179) 0x42afca ADD $0x100,%RAX |
(179) 0x42afd0 CMP %RAX,%R9 |
(179) 0x42afd3 JNE 42aed8 |
(178) 0x42afd9 MOV 0xb4(%RSP),%R14D |
(178) 0x42afe1 MOV %EDX,%R13D |
(178) 0x42afe4 AND $-0x8,%R13D |
(178) 0x42afe8 ADD %R13D,%EDI |
(178) 0x42afeb LEA (%R13,%R14,1),%R9D |
(178) 0x42aff0 TEST $0x7,%DL |
(178) 0x42aff3 JE 42b240 |
(178) 0x42aff9 SUB %R13D,%EDX |
(178) 0x42affc LEA -0x1(%RDX),%R15D |
(178) 0x42b000 CMP $0x2,%R15D |
(178) 0x42b004 JBE 42b0c0 |
(178) 0x42b00a MOVSXD 0xb4(%RSP),%R12 |
(178) 0x42b012 MOV 0x78(%RSP),%R14 |
(178) 0x42b017 MOV 0x90(%RSP),%RBX |
(178) 0x42b01f MOV 0x70(%RSP),%R10 |
(178) 0x42b024 LEA (%R14,%R12,1),%R15 |
(178) 0x42b028 ADD %R13,%R15 |
(178) 0x42b02b LEA (%RBX,%R12,1),%R11 |
(178) 0x42b02f LEA (%R10,%R12,1),%RAX |
(178) 0x42b033 MOV 0xa0(%RSP),%RBX |
(178) 0x42b03b VMOVUPD (%RCX,%R15,8),%YMM10 |
(178) 0x42b041 LEA 0x1(%R13,%R11,1),%R8 |
(178) 0x42b046 ADD %R13,%RAX |
(178) 0x42b049 MOV 0x80(%RSP),%R11 |
(178) 0x42b051 MOV 0xa8(%RSP),%R15 |
(178) 0x42b059 VADDPD (%RBX,%RAX,8),%YMM10,%YMM11 |
(178) 0x42b05e LEA (%R11,%R12,1),%R10 |
(178) 0x42b062 MOV 0x88(%RSP),%RAX |
(178) 0x42b06a ADD %R13,%R10 |
(178) 0x42b06d LEA (%RAX,%R12,1),%R14 |
(178) 0x42b071 VSUBPD (%RCX,%R10,8),%YMM11,%YMM12 |
(178) 0x42b077 ADD %R13,%R14 |
(178) 0x42b07a VMOVUPD %YMM12,(%R15,%R14,8) |
(178) 0x42b080 VMOVUPD (%RSI,%R8,8),%YMM13 |
(178) 0x42b086 VSUBPD -0x8(%RSI,%R8,8),%YMM13,%YMM14 |
(178) 0x42b08d MOV 0x98(%RSP),%R8 |
(178) 0x42b095 ADD %R8,%R12 |
(178) 0x42b098 VADDPD %YMM12,%YMM14,%YMM15 |
(178) 0x42b09d ADD %R13,%R12 |
(178) 0x42b0a0 MOV 0xb8(%RSP),%R13 |
(178) 0x42b0a8 VMOVUPD %YMM15,(%R13,%R12,8) |
(178) 0x42b0af TEST $0x3,%DL |
(178) 0x42b0b2 JE 42b240 |
(178) 0x42b0b8 AND $-0x4,%EDX |
(178) 0x42b0bb ADD %EDX,%EDI |
(178) 0x42b0bd ADD %EDX,%R9D |
(178) 0x42b0c0 MOV 0x78(%RSP),%R14 |
(178) 0x42b0c5 MOVSXD %R9D,%RDX |
(178) 0x42b0c8 MOV 0x70(%RSP),%R15 |
(178) 0x42b0cd MOV 0xa0(%RSP),%RBX |
(178) 0x42b0d5 MOV 0x88(%RSP),%R13 |
(178) 0x42b0dd LEA (%R14,%RDX,1),%R12 |
(178) 0x42b0e1 LEA (%R15,%RDX,1),%R11 |
(178) 0x42b0e5 MOV 0xa8(%RSP),%R8 |
(178) 0x42b0ed VMOVSD (%RCX,%R12,8),%XMM7 |
(178) 0x42b0f3 LEA (%R13,%RDX,1),%RAX |
(178) 0x42b0f8 VADDSD (%RBX,%R11,8),%XMM7,%XMM0 |
(178) 0x42b0fe MOV 0x80(%RSP),%R11 |
(178) 0x42b106 MOV 0x90(%RSP),%RBX |
(178) 0x42b10e LEA (%R11,%RDX,1),%R10 |
(178) 0x42b112 VSUBSD (%RCX,%R10,8),%XMM0,%XMM2 |
(178) 0x42b118 VMOVSD %XMM2,(%R8,%RAX,8) |
(178) 0x42b11e LEA 0x1(%R9),%EAX |
(178) 0x42b122 CLTQ |
(178) 0x42b124 LEA (%RBX,%RAX,1),%R12 |
(178) 0x42b128 LEA (%RSI,%R12,8),%R8 |
(178) 0x42b12c MOV 0x98(%RSP),%R12 |
(178) 0x42b134 VMOVSD (%R8),%XMM1 |
(178) 0x42b139 LEA (%R12,%RDX,1),%R10 |
(178) 0x42b13d ADD %RBX,%RDX |
(178) 0x42b140 VSUBSD (%RSI,%RDX,8),%XMM1,%XMM3 |
(178) 0x42b145 MOV 0xb8(%RSP),%RDX |
(178) 0x42b14d VADDSD %XMM2,%XMM3,%XMM4 |
(178) 0x42b151 VMOVSD %XMM4,(%RDX,%R10,8) |
(178) 0x42b157 MOV 0xb0(%RSP),%R10D |
(178) 0x42b15f LEA 0x1(%RDI),%EDX |
(178) 0x42b162 CMP %R10D,%EDX |
(178) 0x42b165 JAE 42b240 |
(178) 0x42b16b LEA (%RAX,%R14,1),%R10 |
(178) 0x42b16f LEA (%RAX,%R15,1),%RDX |
(178) 0x42b173 ADD $0x2,%EDI |
(178) 0x42b176 VMOVSD (%RCX,%R10,8),%XMM6 |
(178) 0x42b17c MOV 0xa0(%RSP),%R10 |
(178) 0x42b184 VADDSD (%R10,%RDX,8),%XMM6,%XMM5 |
(178) 0x42b18a LEA (%RAX,%R11,1),%RDX |
(178) 0x42b18e MOV 0xa8(%RSP),%R10 |
(178) 0x42b196 VSUBSD (%RCX,%RDX,8),%XMM5,%XMM8 |
(178) 0x42b19b LEA (%RAX,%R13,1),%RDX |
(178) 0x42b19f ADD %R12,%RAX |
(178) 0x42b1a2 VMOVSD %XMM8,(%R10,%RDX,8) |
(178) 0x42b1a8 LEA 0x2(%R9),%EDX |
(178) 0x42b1ac MOVSXD %EDX,%RDX |
(178) 0x42b1af LEA (%RBX,%RDX,1),%R10 |
(178) 0x42b1b3 LEA (%RSI,%R10,8),%R10 |
(178) 0x42b1b7 VMOVSD (%R10),%XMM9 |
(178) 0x42b1bc VSUBSD (%R8),%XMM9,%XMM10 |
(178) 0x42b1c1 MOV 0xb8(%RSP),%R8 |
(178) 0x42b1c9 VADDSD %XMM8,%XMM10,%XMM11 |
(178) 0x42b1ce VMOVSD %XMM11,(%R8,%RAX,8) |
(178) 0x42b1d4 MOV 0xb0(%RSP),%EAX |
(178) 0x42b1db CMP %EAX,%EDI |
(178) 0x42b1dd JAE 42b240 |
(178) 0x42b1df MOV %R14,%RDI |
(178) 0x42b1e2 MOV 0xa0(%RSP),%R14 |
(178) 0x42b1ea ADD %RDX,%R15 |
(178) 0x42b1ed ADD %RDX,%R11 |
(178) 0x42b1f0 ADD %RDX,%RDI |
(178) 0x42b1f3 ADD $0x3,%R9D |
(178) 0x42b1f7 ADD %RDX,%R13 |
(178) 0x42b1fa ADD %RDX,%R12 |
(178) 0x42b1fd VMOVSD (%R14,%R15,8),%XMM12 |
(178) 0x42b203 MOVSXD %R9D,%R9 |
(178) 0x42b206 ADD %RBX,%R9 |
(178) 0x42b209 VADDSD (%RCX,%RDI,8),%XMM12,%XMM13 |
(178) 0x42b20e VSUBSD (%RCX,%R11,8),%XMM13,%XMM14 |
(178) 0x42b214 MOV 0xa8(%RSP),%RCX |
(178) 0x42b21c VMOVSD %XMM14,(%RCX,%R13,8) |
(178) 0x42b222 VMOVSD (%RSI,%R9,8),%XMM15 |
(178) 0x42b228 MOV 0xb8(%RSP),%RSI |
(178) 0x42b230 VSUBSD (%R10),%XMM15,%XMM7 |
(178) 0x42b235 VADDSD %XMM14,%XMM7,%XMM0 |
(178) 0x42b23a VMOVSD %XMM0,(%RSI,%R12,8) |
(178) 0x42b240 MOV 0xb0(%RSP),%EDI |
(178) 0x42b247 MOV 0x68(%RSP),%R8 |
(178) 0x42b24c LEA (%R8),%EBX |
(178) 0x42b24f CMP %EBX,0x60(%RSP) |
(178) 0x42b253 JLE 42b278 |
(178) 0x42b255 MOV 0x58(%RSP),%R13D |
(178) 0x42b25a MOV 0x5c(%RSP),%R10D |
(178) 0x42b25f MOV 0x64(%RSP),%EDX |
(178) 0x42b263 MOV %R10D,0xb4(%RSP) |
(178) 0x42b26b SUB %EDI,%R13D |
(178) 0x42b26e JMP 42ace0 |
0x42b273 NOPL (%RAX,%RAX,1) |
0x42b278 VZEROUPPER |
0x42b27b LEA -0x28(%RBP),%RSP |
0x42b27f POP %RBX |
0x42b280 POP %R12 |
0x42b282 POP %R13 |
0x42b284 POP %R14 |
0x42b286 POP %R15 |
0x42b288 POP %RBP |
0x42b289 RET |
0x42b28a NOPW (%RAX,%RAX,1) |
(178) 0x42b290 LEA 0x1(%R8),%R13 |
(178) 0x42b294 MOV %R13,0x68(%RSP) |
(178) 0x42b299 JMP 42b247 |
0x42b29b NOPL (%RAX,%RAX,1) |
(178) 0x42b2a0 MOV 0xb4(%RSP),%R9D |
(178) 0x42b2a8 XOR %R13D,%R13D |
(178) 0x42b2ab JMP 42aff9 |
0x42b2b0 INC %R13D |
0x42b2b3 XOR %EDX,%EDX |
0x42b2b5 JMP 42ac69 |
0x42b2ba NOPW (%RAX,%RAX,1) |
Path / |
Source file and lines | advec_mom.cpp:44-48 |
Module | exec |
nb instructions | 83 |
nb uops | 93 |
loop length | 306 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 11 |
micro-operation queue | 15.50 cycles |
front end | 15.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.10 | 8.00 | 6.33 | 6.33 | 9.00 | 6.07 | 5.90 | 9.00 | 9.00 | 9.00 | 5.93 | 6.33 |
cycles | 6.10 | 11.93 | 6.33 | 6.33 | 9.00 | 6.07 | 5.90 | 9.00 | 9.00 | 9.00 | 5.93 | 6.33 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.75-14.83 |
Stall cycles | 0.00 |
Front-end | 15.50 |
Dispatch | 11.93 |
DIV/SQRT | 12.00 |
Overall L1 | 15.50 |
all | 3% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 12% |
all | 9% |
load | 10% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 9% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0xc0,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x30(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x34(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%R12),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x4,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA -0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA -0x1(%RSI),%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x60(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EDI,0x5c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 42b27b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x69b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x4(%RCX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 42b27b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x69b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R14D,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %EDI,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R8D,0x64(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 404650 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 404540 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R9D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x64(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R13D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 42b2b0 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x6d0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %R13D,%R9D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R9,%RDX,1),%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%R13,%RDI,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R10D,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R10D,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 42b27b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x69b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EDI,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x5c(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R12),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x64(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x10(%R12),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%R12),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R8,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RSI,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x8(%R12),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%R12),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R11D,0xb4(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%RAX,%R15,1),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R11D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVSXD %R15D,%R8 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R12,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %R13D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 42ac69 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x89> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | advec_mom.cpp:44-48 |
Module | exec |
nb instructions | 83 |
nb uops | 93 |
loop length | 306 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 11 |
micro-operation queue | 15.50 cycles |
front end | 15.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.10 | 8.00 | 6.33 | 6.33 | 9.00 | 6.07 | 5.90 | 9.00 | 9.00 | 9.00 | 5.93 | 6.33 |
cycles | 6.10 | 11.93 | 6.33 | 6.33 | 9.00 | 6.07 | 5.90 | 9.00 | 9.00 | 9.00 | 5.93 | 6.33 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 14.75-14.83 |
Stall cycles | 0.00 |
Front-end | 15.50 |
Dispatch | 11.93 |
DIV/SQRT | 12.00 |
Overall L1 | 15.50 |
all | 3% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 12% |
all | 9% |
load | 10% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 9% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0xc0,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x30(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x34(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x2c(%R12),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x4,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA -0x1(%RAX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA -0x1(%RSI),%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x60(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EDI,0x5c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 42b27b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x69b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x4(%RCX),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R14D,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 42b27b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x69b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R14D,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %EDI,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R8D,0x64(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 404650 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 404540 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%R9D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x64(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EBX,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIV %R13D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
MOV %EAX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 42b2b0 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x6d0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %R13D,%R9D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%R9,%RDX,1),%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%R13,%RDI,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R10D,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R10D,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 42b27b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x69b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EDI,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x5c(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R12),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DIVL 0x64(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV 0x10(%R12),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%R12),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R8,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RSI,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %EDX,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x8(%R12),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%R12),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R11D,0xb4(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%RAX,%R15,1),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R11D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVSXD %R15D,%R8 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R12,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %R13D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 42ac69 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x89> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D | 3.03 | 2.28 |
▼Loop 178 - advec_mom.cpp:44-48 - exec– | 0.01 | 0.01 |
○Loop 179 - advec_mom.cpp:47-48 - exec | 3.02 | 2.27 |