Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ... | Module: exec | Source: advec_cell.cpp:65-110 [...] | Coverage: 3.42% |
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Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ... | Module: exec | Source: advec_cell.cpp:65-110 [...] | Coverage: 3.42% |
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/software/compilers/gcc/gcc-13.1.0-full+isl+binutils/include/c++/13.1.0/bits/stl_algobase.h: 238 - 238 |
-------------------------------------------------------------------------------- |
238: if (__b < __a) |
/scratch_na/users/xoserete/qaas_runs/171-291-1828/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 46 - 69 |
-------------------------------------------------------------------------------- |
46: T &operator[](size_t i) const { return data[i]; } |
[...] |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
/scratch_na/users/xoserete/qaas_runs/171-291-1828/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp: 65 - 110 |
-------------------------------------------------------------------------------- |
65: #pragma omp parallel for simd collapse(2) |
66: for (int j = (y_min + 1); j < (y_max + 2); j++) { |
67: for (int i = (x_min + 1); i < (x_max + 2 + 2); i++) |
68: ({ |
69: int upwind, donor, downwind, dif; |
70: double sigmat, sigma3, sigma4, sigmav, sigmam, diffuw, diffdw, limiter, wind; |
71: if (vol_flux_x(i, j) > 0.0) { |
72: upwind = i - 2; |
73: donor = i - 1; |
74: downwind = i; |
75: dif = donor; |
76: } else { |
77: upwind = std::min(i + 1, x_max + 2); |
78: donor = i; |
79: downwind = i - 1; |
80: dif = upwind; |
81: } |
82: sigmat = std::fabs(vol_flux_x(i, j)) / pre_vol(donor, j); |
83: sigma3 = (1.0 + sigmat) * (vertexdx[i] / vertexdx[dif]); |
84: sigma4 = 2.0 - sigmat; |
85: sigmav = sigmat; |
86: diffuw = density1(donor, j) - density1(upwind, j); |
87: diffdw = density1(downwind, j) - density1(donor, j); |
88: wind = 1.0; |
89: if (diffdw <= 0.0) wind = -1.0; |
90: if (diffuw * diffdw > 0.0) { |
91: limiter = (1.0 - sigmav) * wind * |
92: std::fmin(std::fmin(std::fabs(diffuw), std::fabs(diffdw)), |
93: one_by_six * (sigma3 * std::fabs(diffuw) + sigma4 * std::fabs(diffdw))); |
94: } else { |
95: limiter = 0.0; |
96: } |
97: mass_flux_x(i, j) = vol_flux_x(i, j) * (density1(donor, j) + limiter); |
98: sigmam = std::fabs(mass_flux_x(i, j)) / (density1(donor, j) * pre_vol(donor, j)); |
99: diffuw = energy1(donor, j) - energy1(upwind, j); |
100: diffdw = energy1(downwind, j) - energy1(donor, j); |
101: wind = 1.0; |
102: if (diffdw <= 0.0) wind = -1.0; |
103: if (diffuw * diffdw > 0.0) { |
104: limiter = (1.0 - sigmam) * wind * |
105: std::fmin(std::fmin(std::fabs(diffuw), std::fabs(diffdw)), |
106: one_by_six * (sigma3 * std::fabs(diffuw) + sigma4 * std::fabs(diffdw))); |
107: } else { |
108: limiter = 0.0; |
109: } |
110: ener_flux(i, j) = mass_flux_x(i, j) * (energy1(donor, j) + limiter); |
0x429280 PUSH %RBP |
0x429281 MOV %RSP,%RBP |
0x429284 PUSH %R15 |
0x429286 PUSH %R14 |
0x429288 PUSH %R13 |
0x42928a PUSH %R12 |
0x42928c MOV %RDI,%R12 |
0x42928f PUSH %RBX |
0x429290 AND $-0x40,%RSP |
0x429294 SUB $0x1c0,%RSP |
0x42929b MOV 0x40(%RDI),%EAX |
0x42929e MOV 0x44(%RDI),%EDX |
0x4292a1 MOV 0x3c(%RDI),%EBX |
0x4292a4 MOV 0x38(%RDI),%EDI |
0x4292a7 ADD $0x2,%EDX |
0x4292aa LEA 0x1(%RAX),%R13D |
0x4292ae INC %EDI |
0x4292b0 MOV %EDX,0x54(%RSP) |
0x4292b4 MOV %EDI,0x50(%RSP) |
0x4292b8 CMP %EDX,%R13D |
0x4292bb JGE 429c03 |
0x4292c1 MOV %EDX,%R14D |
0x4292c4 LEA 0x4(%RBX),%R15D |
0x4292c8 SUB %R13D,%R14D |
0x4292cb CMP %R15D,%EDI |
0x4292ce JGE 429c03 |
0x4292d4 MOV %R15D,%ECX |
0x4292d7 SUB %EDI,%ECX |
0x4292d9 MOV %ECX,0x1b8(%RSP) |
0x4292e0 CALL 404650 <omp_get_num_threads@plt> |
0x4292e5 MOV %EAX,0x1bc(%RSP) |
0x4292ec CALL 404540 <omp_get_thread_num@plt> |
0x4292f1 XOR %EDX,%EDX |
0x4292f3 MOV %EAX,%ESI |
0x4292f5 MOV 0x1b8(%RSP),%EAX |
0x4292fc IMUL %R14D,%EAX |
0x429300 DIVL 0x1bc(%RSP) |
0x429307 MOV %EAX,%ECX |
0x429309 CMP %EDX,%ESI |
0x42930b JB 429c72 |
0x429311 IMUL %ECX,%ESI |
0x429314 LEA (%RSI,%RDX,1),%EAX |
0x429317 LEA (%RCX,%RAX,1),%R8D |
0x42931b MOV %EAX,0x1a4(%RSP) |
0x429322 MOV %R8D,0x4c(%RSP) |
0x429327 CMP %R8D,%EAX |
0x42932a JAE 429c03 |
0x429330 XOR %EDX,%EDX |
0x429332 MOV 0x50(%RSP),%R9D |
0x429337 MOV 0x20(%R12),%R11 |
0x42933c LEA 0x2(%RBX),%EBX |
0x42933f DIVL 0x1b8(%RSP) |
0x429346 MOV (%R12),%RDI |
0x42934a MOV 0x18(%R12),%R14 |
0x42934f MOV %EBX,0x194(%RSP) |
0x429356 MOV 0x10(%R12),%RSI |
0x42935b VMOVSD 0x35233(%RIP),%XMM25 |
0x429365 MOV %R11,0x38(%RSP) |
0x42936a MOV %RDI,0x28(%RSP) |
0x42936f MOV %R14,0x18(%RSP) |
0x429374 MOV %RSI,0x10(%RSP) |
0x429379 VMOVD %EBX,%XMM3 |
0x42937d VPBROADCASTD %XMM3,%ZMM0 |
0x429383 VMOVDQA32 %ZMM0,0x80(%RSP) |
0x42938b ADD %EDX,%R9D |
0x42938e LEA (%RAX,%R13,1),%R10D |
0x429392 MOV %R15D,%EDX |
0x429395 MOV 0x28(%R12),%R13 |
0x42939a MOV 0x8(%R12),%R15 |
0x42939f MOV 0x30(%R12),%R12 |
0x4293a4 MOVSXD %R10D,%R8 |
0x4293a7 MOV %R9D,0x1a0(%RSP) |
0x4293af MOV %R10D,0x48(%RSP) |
0x4293b4 SUB %R9D,%EDX |
0x4293b7 MOV %R13,0x30(%RSP) |
0x4293bc MOV %R15,0x20(%RSP) |
0x4293c1 MOV %R12,0x8(%RSP) |
0x4293c6 MOV %R8,0x40(%RSP) |
0x4293cb MOV %R8,0x198(%RSP) |
0x4293d3 NOPL (%RAX,%RAX,1) |
(172) 0x4293d8 CMP %EDX,%ECX |
(172) 0x4293da CMOVBE %ECX,%EDX |
(172) 0x4293dd MOV 0x1a4(%RSP),%ECX |
(172) 0x4293e4 MOV %EDX,0x190(%RSP) |
(172) 0x4293eb ADD %ECX,%EDX |
(172) 0x4293ed MOV %EDX,0x1bc(%RSP) |
(172) 0x4293f4 CMP %EDX,%ECX |
(172) 0x4293f6 JAE 429c26 |
(172) 0x4293fc MOV 0x38(%RSP),%RAX |
(172) 0x429401 MOV 0x30(%RSP),%RDX |
(172) 0x429406 MOV 0x18(%RSP),%R12 |
(172) 0x42940b MOV 0x28(%RSP),%R13 |
(172) 0x429410 MOV 0x10(%RDX),%R9 |
(172) 0x429414 MOV 0x10(%RAX),%R11 |
(172) 0x429418 MOV (%RAX),%RSI |
(172) 0x42941b MOV 0x20(%RSP),%R14 |
(172) 0x429420 MOV 0x10(%RSP),%RAX |
(172) 0x429425 MOV 0x198(%RSP),%R10 |
(172) 0x42942d MOV %R9,0x1b0(%RSP) |
(172) 0x429435 MOV (%RDX),%RBX |
(172) 0x429438 MOV (%R12),%RCX |
(172) 0x42943c MOV %R11,0x78(%RSP) |
(172) 0x429441 MOV 0x8(%R13),%RDI |
(172) 0x429445 MOV 0x10(%R14),%R15 |
(172) 0x429449 IMUL %R10,%RSI |
(172) 0x42944d MOV 0x8(%RSP),%R13 |
(172) 0x429452 MOV (%R14),%R14 |
(172) 0x429455 IMUL %R10,%RBX |
(172) 0x429459 MOV (%RAX),%R9 |
(172) 0x42945c IMUL %R10,%RCX |
(172) 0x429460 MOV 0x10(%R12),%R8 |
(172) 0x429465 MOV 0x10(%R13),%RDX |
(172) 0x429469 IMUL %R10,%R14 |
(172) 0x42946d MOV %RSI,0x70(%RSP) |
(172) 0x429472 IMUL %R10,%R9 |
(172) 0x429476 MOV %R8,0x188(%RSP) |
(172) 0x42947e MOV 0x10(%RAX),%R8 |
(172) 0x429482 IMUL (%R13),%R10 |
(172) 0x429487 MOV 0x190(%RSP),%R13D |
(172) 0x42948f MOV %RBX,0x1a8(%RSP) |
(172) 0x429497 MOV %RCX,0x68(%RSP) |
(172) 0x42949c LEA -0x1(%R13),%R12D |
(172) 0x4294a0 MOV %RDX,0x180(%RSP) |
(172) 0x4294a8 MOV %R10,0x60(%RSP) |
(172) 0x4294ad CMP $0xe,%R12D |
(172) 0x4294b1 JBE 4299c1 |
(172) 0x4294b7 MOVSXD 0x1a0(%RSP),%RAX |
(172) 0x4294bf SHR $0x4,%R13D |
(172) 0x4294c3 VPBROADCASTD 0x1a0(%RSP),%ZMM1 |
(172) 0x4294cb LEA (%R15,%R14,8),%RDX |
(172) 0x4294cf KXNORB %K1,%K1,%K1 |
(172) 0x4294d3 SAL $0x7,%R13 |
(172) 0x4294d7 VBROADCASTSD 0x348cf(%RIP),%ZMM3 |
(172) 0x4294e1 VBROADCASTSD 0x350ad(%RIP),%ZMM9 |
(172) 0x4294eb VXORPD %XMM8,%XMM8,%XMM8 |
(172) 0x4294f0 LEA (%RSI,%RAX,1),%RSI |
(172) 0x4294f4 MOV %R13,0x58(%RSP) |
(172) 0x4294f9 MOV $0x10,%R13D |
(172) 0x4294ff ADD %RAX,%RCX |
(172) 0x429502 LEA (%R11,%RSI,8),%R12 |
(172) 0x429506 MOV 0x1b0(%RSP),%R11 |
(172) 0x42950e VPBROADCASTD %R13D,%ZMM5 |
(172) 0x429514 MOV $-0x2,%R13D |
(172) 0x42951a VPBROADCASTD %R13D,%ZMM2 |
(172) 0x429520 MOV $0x1,%R13D |
(172) 0x429526 VPADDD 0x351d0(%RIP),%ZMM1,%ZMM27 |
(172) 0x429530 VBROADCASTSD 0x3519e(%RIP),%ZMM26 |
(172) 0x42953a LEA (%R11,%RBX,8),%RSI |
(172) 0x42953e MOV 0x188(%RSP),%R11 |
(172) 0x429546 LEA (%RDI,%RAX,8),%RBX |
(172) 0x42954a ADD %R10,%RAX |
(172) 0x42954d MOV 0x180(%RSP),%R10 |
(172) 0x429555 VPBROADCASTD %R13D,%ZMM4 |
(172) 0x42955b VBROADCASTSD 0x351db(%RIP),%ZMM24 |
(172) 0x429565 VMOVDQA32 %ZMM5,0x140(%RSP) |
(172) 0x42956d VBROADCASTSD 0x35209(%RIP),%ZMM23 |
(172) 0x429577 MOV 0x58(%RSP),%R13 |
(172) 0x42957c LEA (%R11,%RCX,8),%R11 |
(172) 0x429580 VMOVDQA32 %ZMM2,0x100(%RSP) |
(172) 0x429588 LEA (%R10,%RAX,8),%R10 |
(172) 0x42958c LEA (%R8,%R9,8),%RCX |
(172) 0x429590 XOR %EAX,%EAX |
(172) 0x429592 VMOVDQA32 %ZMM4,0xc0(%RSP) |
(172) 0x42959a NOPW (%RAX,%RAX,1) |
(174) 0x4295a0 VMOVDQA32 %ZMM27,%ZMM10 |
(174) 0x4295a6 VMOVUPD 0x40(%R12,%RAX,1),%ZMM4 |
(174) 0x4295ae VMOVUPD (%R12,%RAX,1),%ZMM11 |
(174) 0x4295b5 KMOVB %K1,%K4 |
(174) 0x4295b9 KMOVB %K1,%K5 |
(174) 0x4295bd KMOVB %K1,%K6 |
(174) 0x4295c1 VPADDD 0xc0(%RSP),%ZMM10,%ZMM14 |
(174) 0x4295c9 VPADDD 0x351ed(%RIP),%ZMM10,%ZMM7 |
(174) 0x4295d3 VEXTRACTI32X8 $0x1,%ZMM10,%YMM6 |
(174) 0x4295da KMOVB %K1,%K7 |
(174) 0x4295de VCMPPD $0xe,%ZMM8,%ZMM11,%K3 |
(174) 0x4295e5 VCMPPD $0xe,%ZMM8,%ZMM4,%K2 |
(174) 0x4295ec VPMOVSXDQ %YMM10,%ZMM12 |
(174) 0x4295f2 VPMINSD 0x80(%RSP),%ZMM14,%ZMM0 |
(174) 0x4295fa VPMOVSXDQ %YMM6,%ZMM13 |
(174) 0x429600 VPADDD 0x100(%RSP),%ZMM10,%ZMM15 |
(174) 0x429608 VEXTRACTI32X8 $0x1,%ZMM7,%YMM1 |
(174) 0x42960f VMOVDQA64 %ZMM12,%ZMM18 |
(174) 0x429615 VMOVDQA64 %ZMM13,%ZMM17 |
(174) 0x42961b VPMOVSXDQ %YMM0,%ZMM14 |
(174) 0x429621 VEXTRACTI32X8 $0x1,%ZMM0,%YMM2 |
(174) 0x429628 VPMOVSXDQ %YMM7,%ZMM18{%K3} |
(174) 0x42962e VMOVDQA64 %ZMM14,%ZMM11 |
(174) 0x429634 VPMOVSXDQ %YMM1,%ZMM17{%K2} |
(174) 0x42963a VPMOVSXDQ %YMM2,%ZMM0 |
(174) 0x429640 VMOVUPD (%RBX,%RAX,1),%ZMM2 |
(174) 0x429647 VPMOVSXDQ %YMM7,%ZMM11{%K3} |
(174) 0x42964d VPMOVSXDQ %YMM7,%ZMM22 |
(174) 0x429653 VPMOVSXDQ %YMM1,%ZMM21 |
(174) 0x429659 VANDPD (%R12,%RAX,1),%ZMM3,%ZMM7 |
(174) 0x429660 VMOVDQA64 %ZMM12,%ZMM22{%K3} |
(174) 0x429666 VMOVDQA64 %ZMM13,%ZMM21{%K2} |
(174) 0x42966c VPMOVSXDQ %YMM15,%ZMM14{%K3} |
(174) 0x429672 VGATHERQPD (%RSI,%ZMM18,8),%ZMM13{%K4} |
(174) 0x429679 VEXTRACTI32X8 $0x1,%ZMM15,%YMM12 |
(174) 0x429680 KMOVB %K1,%K3 |
(174) 0x429684 KMOVB %K1,%K4 |
(174) 0x429688 VGATHERQPD (%RSI,%ZMM17,8),%ZMM15{%K5} |
(174) 0x42968f VANDPD %ZMM3,%ZMM4,%ZMM5 |
(174) 0x429695 VMOVDQA64 %ZMM0,%ZMM6 |
(174) 0x42969b VDIVPD %ZMM13,%ZMM7,%ZMM10 |
(174) 0x4296a1 KMOVB %K1,%K5 |
(174) 0x4296a5 VDIVPD %ZMM15,%ZMM5,%ZMM7 |
(174) 0x4296ab VPMOVSXDQ %YMM1,%ZMM6{%K2} |
(174) 0x4296b1 VADDPD %ZMM9,%ZMM7,%ZMM13 |
(174) 0x4296b7 VGATHERQPD (%RDI,%ZMM11,8),%ZMM4{%K6} |
(174) 0x4296be KMOVB %K1,%K6 |
(174) 0x4296c2 VGATHERQPD (%RDI,%ZMM6,8),%ZMM1{%K7} |
(174) 0x4296c9 VADDPD %ZMM9,%ZMM10,%ZMM11 |
(174) 0x4296cf VMOVUPD 0x40(%RBX,%RAX,1),%ZMM6 |
(174) 0x4296d7 VPMOVSXDQ %YMM12,%ZMM0{%K2} |
(174) 0x4296dd VDIVPD %ZMM4,%ZMM2,%ZMM16 |
(174) 0x4296e3 KMOVB %K1,%K2 |
(174) 0x4296e7 VGATHERQPD (%RDX,%ZMM14,8),%ZMM15{%K4} |
(174) 0x4296ee VGATHERQPD (%RDX,%ZMM17,8),%ZMM5{%K2} |
(174) 0x4296f5 VGATHERQPD (%RDX,%ZMM0,8),%ZMM4{%K5} |
(174) 0x4296fc KMOVB %K1,%K7 |
(174) 0x429700 VDIVPD %ZMM1,%ZMM6,%ZMM12 |
(174) 0x429706 VGATHERQPD (%RDX,%ZMM18,8),%ZMM6{%K3} |
(174) 0x42970d VSUBPD %ZMM7,%ZMM26,%ZMM20 |
(174) 0x429713 VSUBPD %ZMM10,%ZMM26,%ZMM2 |
(174) 0x429719 VMULPD %ZMM13,%ZMM12,%ZMM1 |
(174) 0x42971f VGATHERQPD (%RDX,%ZMM21,8),%ZMM13{%K7} |
(174) 0x429726 VGATHERQPD (%RDX,%ZMM22,8),%ZMM12{%K6} |
(174) 0x42972d KMOVB %K1,%K7 |
(174) 0x429731 KMOVB %K1,%K6 |
(174) 0x429735 VMULPD %ZMM11,%ZMM16,%ZMM16 |
(174) 0x42973b VSUBPD %ZMM5,%ZMM13,%ZMM13 |
(174) 0x429741 VSUBPD %ZMM15,%ZMM6,%ZMM11 |
(174) 0x429747 VSUBPD %ZMM4,%ZMM5,%ZMM15 |
(174) 0x42974d VSUBPD %ZMM6,%ZMM12,%ZMM12 |
(174) 0x429753 VSUBPD %ZMM7,%ZMM9,%ZMM7 |
(174) 0x429759 VSUBPD %ZMM10,%ZMM9,%ZMM10 |
(174) 0x42975f VCMPPD $0x2,%ZMM8,%ZMM13,%K2 |
(174) 0x429766 VPADDD 0x140(%RSP),%ZMM27,%ZMM27 |
(174) 0x42976e VMULPD %ZMM13,%ZMM15,%ZMM28 |
(174) 0x429774 VANDPD %ZMM3,%ZMM13,%ZMM13 |
(174) 0x42977a VANDPD %ZMM3,%ZMM15,%ZMM4 |
(174) 0x429780 VMULPD %ZMM13,%ZMM20,%ZMM19 |
(174) 0x429786 VCMPPD $0x2,%ZMM8,%ZMM12,%K3 |
(174) 0x42978d VMULPD %ZMM12,%ZMM11,%ZMM30 |
(174) 0x429793 VANDPD %ZMM3,%ZMM12,%ZMM12 |
(174) 0x429799 VANDPD %ZMM3,%ZMM11,%ZMM11 |
(174) 0x42979f VMULPD %ZMM12,%ZMM2,%ZMM15 |
(174) 0x4297a5 VBLENDMPD %ZMM24,%ZMM9,%ZMM31{%K2} |
(174) 0x4297ab KMOVB %K1,%K2 |
(174) 0x4297af VBLENDMPD %ZMM24,%ZMM9,%ZMM29{%K3} |
(174) 0x4297b5 KMOVB %K1,%K3 |
(174) 0x4297b9 VCMPPD $0xe,%ZMM8,%ZMM28,%K5 |
(174) 0x4297c0 VFMADD231PD %ZMM4,%ZMM1,%ZMM19 |
(174) 0x4297c6 VMINPD %ZMM13,%ZMM4,%ZMM4 |
(174) 0x4297cc VCMPPD $0xe,%ZMM8,%ZMM30,%K4 |
(174) 0x4297d3 VFMADD231PD %ZMM11,%ZMM16,%ZMM15 |
(174) 0x4297d9 VMINPD %ZMM12,%ZMM11,%ZMM11 |
(174) 0x4297df VMULPD %ZMM23,%ZMM19,%ZMM19 |
(174) 0x4297e5 VMULPD %ZMM23,%ZMM15,%ZMM15 |
(174) 0x4297eb VMINPD %ZMM4,%ZMM19,%ZMM13 |
(174) 0x4297f1 VMULPD %ZMM31,%ZMM7,%ZMM4 |
(174) 0x4297f7 VMULPD %ZMM29,%ZMM10,%ZMM7 |
(174) 0x4297fd VMINPD %ZMM11,%ZMM15,%ZMM12 |
(174) 0x429803 VFMADD231PD %ZMM13,%ZMM4,%ZMM5{%K5} |
(174) 0x429809 KMOVB %K1,%K5 |
(174) 0x42980d VFMADD231PD %ZMM12,%ZMM7,%ZMM6{%K4} |
(174) 0x429813 KMOVB %K1,%K4 |
(174) 0x429817 VMULPD 0x40(%R12,%RAX,1),%ZMM5,%ZMM5 |
(174) 0x42981f VMULPD (%R12,%RAX,1),%ZMM6,%ZMM6 |
(174) 0x429826 VMOVUPD %ZMM5,0x40(%R11,%RAX,1) |
(174) 0x42982e VMOVUPD %ZMM6,(%R11,%RAX,1) |
(174) 0x429835 VGATHERQPD (%RCX,%ZMM18,8),%ZMM10{%K4} |
(174) 0x42983c VGATHERQPD (%RSI,%ZMM18,8),%ZMM15{%K3} |
(174) 0x429843 VGATHERQPD (%RSI,%ZMM17,8),%ZMM13{%K2} |
(174) 0x42984a KMOVB %K1,%K3 |
(174) 0x42984e KMOVB %K1,%K2 |
(174) 0x429852 VGATHERQPD (%RCX,%ZMM17,8),%ZMM7{%K5} |
(174) 0x429859 VGATHERQPD (%RDX,%ZMM18,8),%ZMM12{%K6} |
(174) 0x429860 VGATHERQPD (%RDX,%ZMM17,8),%ZMM11{%K7} |
(174) 0x429867 KMOVB %K1,%K6 |
(174) 0x42986b KMOVB %K1,%K7 |
(174) 0x42986f VMULPD %ZMM15,%ZMM12,%ZMM12 |
(174) 0x429875 VGATHERQPD (%RCX,%ZMM14,8),%ZMM4{%K6} |
(174) 0x42987c VGATHERQPD (%RCX,%ZMM0,8),%ZMM18{%K7} |
(174) 0x429883 VGATHERQPD (%RCX,%ZMM22,8),%ZMM29{%K3} |
(174) 0x42988a VGATHERQPD (%RCX,%ZMM21,8),%ZMM14{%K2} |
(174) 0x429891 VSUBPD %ZMM4,%ZMM10,%ZMM0 |
(174) 0x429897 VSUBPD %ZMM7,%ZMM14,%ZMM4 |
(174) 0x42989d VSUBPD %ZMM10,%ZMM29,%ZMM31 |
(174) 0x4298a3 VMULPD %ZMM13,%ZMM11,%ZMM11 |
(174) 0x4298a9 VSUBPD %ZMM18,%ZMM7,%ZMM17 |
(174) 0x4298af VANDPD %ZMM3,%ZMM4,%ZMM28 |
(174) 0x4298b5 VCMPPD $0x2,%ZMM8,%ZMM4,%K5 |
(174) 0x4298bc VANDPD %ZMM3,%ZMM31,%ZMM19 |
(174) 0x4298c2 VMULPD %ZMM28,%ZMM20,%ZMM20 |
(174) 0x4298c8 VCMPPD $0x2,%ZMM8,%ZMM31,%K4 |
(174) 0x4298cf VANDPD %ZMM3,%ZMM17,%ZMM18 |
(174) 0x4298d5 VMULPD %ZMM19,%ZMM2,%ZMM2 |
(174) 0x4298db VMULPD %ZMM31,%ZMM0,%ZMM21 |
(174) 0x4298e1 VANDPD %ZMM3,%ZMM0,%ZMM0 |
(174) 0x4298e7 VBLENDMPD %ZMM24,%ZMM9,%ZMM22{%K5} |
(174) 0x4298ed VMULPD %ZMM4,%ZMM17,%ZMM14 |
(174) 0x4298f3 VBLENDMPD %ZMM24,%ZMM9,%ZMM30{%K4} |
(174) 0x4298f9 VFMADD132PD %ZMM18,%ZMM20,%ZMM1 |
(174) 0x4298ff VFMADD231PD %ZMM0,%ZMM16,%ZMM2 |
(174) 0x429905 VMINPD %ZMM28,%ZMM18,%ZMM16 |
(174) 0x42990b VMINPD %ZMM19,%ZMM0,%ZMM0 |
(174) 0x429911 VCMPPD $0xe,%ZMM8,%ZMM21,%K6 |
(174) 0x429918 VCMPPD $0xe,%ZMM8,%ZMM14,%K7 |
(174) 0x42991f VANDPD %ZMM3,%ZMM5,%ZMM14 |
(174) 0x429925 VDIVPD %ZMM11,%ZMM14,%ZMM13 |
(174) 0x42992b VMULPD %ZMM23,%ZMM1,%ZMM4 |
(174) 0x429931 VMULPD %ZMM23,%ZMM2,%ZMM2 |
(174) 0x429937 VMINPD %ZMM16,%ZMM4,%ZMM1 |
(174) 0x42993d VMULPD %ZMM22,%ZMM1,%ZMM4 |
(174) 0x429943 VMINPD %ZMM0,%ZMM2,%ZMM1 |
(174) 0x429949 VANDPD %ZMM3,%ZMM6,%ZMM0 |
(174) 0x42994f VDIVPD %ZMM12,%ZMM0,%ZMM15 |
(174) 0x429955 VSUBPD %ZMM15,%ZMM9,%ZMM0 |
(174) 0x42995b VMULPD %ZMM30,%ZMM1,%ZMM2 |
(174) 0x429961 VSUBPD %ZMM13,%ZMM9,%ZMM1 |
(174) 0x429967 VFMADD231PD %ZMM1,%ZMM4,%ZMM7{%K7} |
(174) 0x42996d VFMADD231PD %ZMM0,%ZMM2,%ZMM10{%K6} |
(174) 0x429973 VMULPD %ZMM5,%ZMM7,%ZMM5 |
(174) 0x429979 VMULPD %ZMM6,%ZMM10,%ZMM6 |
(174) 0x42997f VMOVUPD %ZMM5,0x40(%R10,%RAX,1) |
(174) 0x429987 VMOVUPD %ZMM6,(%R10,%RAX,1) |
(174) 0x42998e SUB $-0x80,%RAX |
(174) 0x429992 CMP %RAX,%R13 |
(174) 0x429995 JNE 4295a0 |
(172) 0x42999b MOV 0x190(%RSP),%R12D |
(172) 0x4299a3 MOV %R12D,%ESI |
(172) 0x4299a6 AND $-0x10,%ESI |
(172) 0x4299a9 ADD %ESI,0x1a4(%RSP) |
(172) 0x4299b0 ADD %ESI,0x1a0(%RSP) |
(172) 0x4299b7 AND $0xf,%R12D |
(172) 0x4299bb JE 429c18 |
(172) 0x4299c1 MOV 0x68(%RSP),%R13 |
(172) 0x4299c6 MOV 0x188(%RSP),%R10 |
(172) 0x4299ce VXORPD %XMM15,%XMM15,%XMM15 |
(172) 0x4299d3 MOV 0x78(%RSP),%R11 |
(172) 0x4299d8 MOV 0x70(%RSP),%RDX |
(172) 0x4299dd LEA (%R10,%R13,8),%R12 |
(172) 0x4299e1 MOVSXD 0x1a0(%RSP),%RAX |
(172) 0x4299e9 MOV 0x180(%RSP),%RSI |
(172) 0x4299f1 LEA (%R11,%RDX,8),%RCX |
(172) 0x4299f5 MOV 0x60(%RSP),%R11 |
(172) 0x4299fa VMOVSD 0x34d3e(%RIP),%XMM8 |
(172) 0x429a02 MOV %R12,0x100(%RSP) |
(172) 0x429a0a MOV 0x1a4(%RSP),%R12D |
(172) 0x429a12 MOV %RCX,0x140(%RSP) |
(172) 0x429a1a LEA (%RSI,%R11,8),%R13 |
(172) 0x429a1e SUB %EAX,%R12D |
(172) 0x429a21 JMP 429bc4 |
0x429a26 NOPW %CS:(%RAX,%RAX,1) |
(173) 0x429a30 LEA -0x1(%RAX),%RDX |
(173) 0x429a34 LEA -0x2(%RAX),%R10D |
(173) 0x429a38 MOV %RAX,%RSI |
(173) 0x429a3b MOVSXD %R10D,%RCX |
(173) 0x429a3e MOV %RDX,%R11 |
(173) 0x429a41 VMOVSD (%RDI,%RAX,8),%XMM9 |
(173) 0x429a46 MOV 0x1a8(%RSP),%RBX |
(173) 0x429a4e VMOVSD %XMM25,%XMM25,%XMM5 |
(173) 0x429a54 VANDPD 0x34354(%RIP),%XMM12,%XMM3 |
(173) 0x429a5c VMOVSD 0x34c74(%RIP),%XMM10 |
(173) 0x429a64 VDIVSD (%RDI,%R11,8),%XMM9,%XMM4 |
(173) 0x429a6a LEA (%R14,%RDX,1),%R11 |
(173) 0x429a6e LEA (%RBX,%RDX,1),%R10 |
(173) 0x429a72 MOV 0x1b0(%RSP),%RBX |
(173) 0x429a7a LEA (%R15,%R11,8),%R11 |
(173) 0x429a7e VMOVSD (%R11),%XMM11 |
(173) 0x429a83 LEA (%RBX,%R10,8),%R10 |
(173) 0x429a87 LEA (%R14,%RCX,1),%RBX |
(173) 0x429a8b VDIVSD (%R10),%XMM3,%XMM2 |
(173) 0x429a90 VADDSD %XMM25,%XMM2,%XMM0 |
(173) 0x429a96 VSUBSD %XMM2,%XMM10,%XMM13 |
(173) 0x429a9a VSUBSD (%R15,%RBX,8),%XMM11,%XMM7 |
(173) 0x429aa0 LEA (%R14,%RSI,1),%RBX |
(173) 0x429aa4 VMOVSD (%R15,%RBX,8),%XMM1 |
(173) 0x429aaa VMULSD %XMM0,%XMM4,%XMM14 |
(173) 0x429aae VSUBSD %XMM11,%XMM1,%XMM6 |
(173) 0x429ab3 VMULSD %XMM6,%XMM7,%XMM4 |
(173) 0x429ab7 VCMPSD $0x6,%XMM15,%XMM6,%XMM3 |
(173) 0x429abd VBLENDVPD %XMM3,%XMM5,%XMM8,%XMM9 |
(173) 0x429ac3 VCOMISD %XMM15,%XMM4 |
(173) 0x429ac8 JBE 429b04 |
(173) 0x429aca VANDPD 0x342de(%RIP),%XMM6,%XMM10 |
(173) 0x429ad2 VANDPD 0x342d6(%RIP),%XMM7,%XMM0 |
(173) 0x429ada VSUBSD %XMM2,%XMM25,%XMM2 |
(173) 0x429ae0 VMULSD %XMM13,%XMM10,%XMM7 |
(173) 0x429ae5 VMINSD %XMM10,%XMM0,%XMM1 |
(173) 0x429aea VFMADD231SD %XMM14,%XMM0,%XMM7 |
(173) 0x429aef VMULSD 0x34c89(%RIP),%XMM7,%XMM6 |
(173) 0x429af7 VMINSD %XMM1,%XMM6,%XMM3 |
(173) 0x429afb VMULSD %XMM2,%XMM3,%XMM5 |
(173) 0x429aff VFMADD231SD %XMM5,%XMM9,%XMM11 |
(173) 0x429b04 VMULSD %XMM11,%XMM12,%XMM12 |
(173) 0x429b09 MOV 0x100(%RSP),%RBX |
(173) 0x429b11 ADD %R9,%RDX |
(173) 0x429b14 ADD %R9,%RSI |
(173) 0x429b17 ADD %R9,%RCX |
(173) 0x429b1a VMOVSD %XMM25,%XMM25,%XMM1 |
(173) 0x429b20 VMOVSD %XMM12,(%RBX,%RAX,8) |
(173) 0x429b25 VMOVSD (%R8,%RDX,8),%XMM0 |
(173) 0x429b2b VMOVSD (%R8,%RSI,8),%XMM10 |
(173) 0x429b31 VMOVSD (%R11),%XMM9 |
(173) 0x429b36 VMOVSD (%R10),%XMM11 |
(173) 0x429b3b VSUBSD %XMM0,%XMM10,%XMM7 |
(173) 0x429b3f VSUBSD (%R8,%RCX,8),%XMM0,%XMM4 |
(173) 0x429b45 VMULSD %XMM7,%XMM4,%XMM3 |
(173) 0x429b49 VCMPSD $0x6,%XMM15,%XMM7,%XMM6 |
(173) 0x429b4f VBLENDVPD %XMM6,%XMM1,%XMM8,%XMM2 |
(173) 0x429b55 VCOMISD %XMM15,%XMM3 |
(173) 0x429b5a JBE 429ba6 |
(173) 0x429b5c VMULSD %XMM11,%XMM9,%XMM5 |
(173) 0x429b61 VANDPD 0x34247(%RIP),%XMM7,%XMM7 |
(173) 0x429b69 VANDPD 0x3423f(%RIP),%XMM4,%XMM4 |
(173) 0x429b71 VMULSD %XMM13,%XMM7,%XMM13 |
(173) 0x429b76 VMINSD %XMM7,%XMM4,%XMM6 |
(173) 0x429b7a VFMADD231SD %XMM14,%XMM4,%XMM13 |
(173) 0x429b7f VANDPD 0x34229(%RIP),%XMM12,%XMM14 |
(173) 0x429b87 VDIVSD %XMM5,%XMM14,%XMM9 |
(173) 0x429b8b VMULSD 0x34bed(%RIP),%XMM13,%XMM10 |
(173) 0x429b93 VMINSD %XMM6,%XMM10,%XMM1 |
(173) 0x429b97 VSUBSD %XMM9,%XMM25,%XMM11 |
(173) 0x429b9d VMULSD %XMM1,%XMM11,%XMM3 |
(173) 0x429ba1 VFMADD231SD %XMM3,%XMM2,%XMM0 |
(173) 0x429ba6 VMULSD %XMM12,%XMM0,%XMM12 |
(173) 0x429bab MOV 0x1bc(%RSP),%ECX |
(173) 0x429bb2 VMOVSD %XMM12,(%R13,%RAX,8) |
(173) 0x429bb9 INC %RAX |
(173) 0x429bbc LEA (%R12,%RAX,1),%ESI |
(173) 0x429bc0 CMP %ECX,%ESI |
(173) 0x429bc2 JAE 429c18 |
(173) 0x429bc4 MOV 0x140(%RSP),%RBX |
(173) 0x429bcc VMOVSD (%RBX,%RAX,8),%XMM12 |
(173) 0x429bd1 VCOMISD %XMM15,%XMM12 |
(173) 0x429bd6 JA 429a30 |
(173) 0x429bdc MOV 0x194(%RSP),%ECX |
(173) 0x429be3 LEA 0x1(%RAX),%EDX |
(173) 0x429be6 LEA -0x1(%RAX),%RSI |
(173) 0x429bea CMP %ECX,%EDX |
(173) 0x429bec CMOVG %ECX,%EDX |
(173) 0x429bef MOVSXD %EDX,%R11 |
(173) 0x429bf2 MOV %RAX,%RDX |
(173) 0x429bf5 MOV %R11,%RCX |
(173) 0x429bf8 JMP 429a41 |
0x429bfd NOPL (%RAX) |
0x429c00 VZEROUPPER |
0x429c03 LEA -0x28(%RBP),%RSP |
0x429c07 POP %RBX |
0x429c08 POP %R12 |
0x429c0a POP %R13 |
0x429c0c POP %R14 |
0x429c0e POP %R15 |
0x429c10 POP %RBP |
0x429c11 RET |
0x429c12 NOPW (%RAX,%RAX,1) |
(172) 0x429c18 MOV 0x1bc(%RSP),%EDX |
(172) 0x429c1f MOV %EDX,0x1a4(%RSP) |
(172) 0x429c26 INCQ 0x198(%RSP) |
(172) 0x429c2e MOV 0x48(%RSP),%EAX |
(172) 0x429c32 MOV 0x40(%RSP),%R8D |
(172) 0x429c37 SUB %R8D,%EAX |
(172) 0x429c3a MOV 0x198(%RSP),%RDI |
(172) 0x429c42 ADD %EDI,%EAX |
(172) 0x429c44 CMP %EAX,0x54(%RSP) |
(172) 0x429c48 JLE 429c00 |
(172) 0x429c4a MOV 0x4c(%RSP),%ECX |
(172) 0x429c4e MOV 0x1a4(%RSP),%R9D |
(172) 0x429c56 MOV 0x50(%RSP),%R12D |
(172) 0x429c5b MOV 0x1b8(%RSP),%EDX |
(172) 0x429c62 SUB %R9D,%ECX |
(172) 0x429c65 MOV %R12D,0x1a0(%RSP) |
(172) 0x429c6d JMP 4293d8 |
0x429c72 INC %ECX |
0x429c74 XOR %EDX,%EDX |
0x429c76 JMP 429311 |
0x429c7b NOPL (%RAX,%RAX,1) |
Path / |
Source file and lines | advec_cell.cpp:65-110 |
Module | exec |
nb instructions | 96 |
nb uops | 107 |
loop length | 395 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 2 |
used ymm registers | 0 |
used zmm registers | 1 |
nb stack references | 20 |
micro-operation queue | 17.83 cycles |
front end | 17.83 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.70 | 8.00 | 7.67 | 7.67 | 13.50 | 6.80 | 6.70 | 13.50 | 13.50 | 13.50 | 6.80 | 7.67 |
cycles | 6.70 | 12.13 | 7.67 | 7.67 | 13.50 | 6.80 | 6.70 | 13.50 | 13.50 | 13.50 | 6.80 | 7.67 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 16.88-17.02 |
Stall cycles | 0.00 |
Front-end | 17.83 |
Dispatch | 13.50 |
DIV/SQRT | 12.00 |
Overall L1 | 17.83 |
all | 5% |
load | 0% |
store | 5% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 9% |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 5% |
load | 0% |
store | 5% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 11% |
all | 11% |
load | 9% |
store | 14% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 8% |
all | 12% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 11% |
load | 9% |
store | 14% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 9% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0x1c0,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x40(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x44(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x3c(%RDI),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x38(%RDI),%EDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x2,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%RAX),%R13D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
INC %EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EDX,0x54(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EDI,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%R13D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 429c03 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x983> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EDX,%R14D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x4(%RBX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R13D,%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R15D,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 429c03 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x983> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R15D,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %EDI,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ECX,0x1b8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 404650 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,0x1bc(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 404540 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x1b8(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %R14D,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIVL 0x1bc(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV %EAX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 429c72 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x9f2> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %ECX,%ESI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%RSI,%RDX,1),%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RCX,%RAX,1),%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EAX,0x1a4(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8D,0x4c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R8D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 429c03 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x983> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x50(%RSP),%R9D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%R12),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA 0x2(%RBX),%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
DIVL 0x1b8(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV (%R12),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%R12),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EBX,0x194(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x10(%R12),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0x35233(%RIP),%XMM25 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R11,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDI,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RSI,0x10(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVD %EBX,%XMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VPBROADCASTD %XMM3,%ZMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVDQA32 %ZMM0,0x80(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
ADD %EDX,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%RAX,%R13,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R15D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x28(%R12),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%R12),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x30(%R12),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVSXD %R10D,%R8 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R9D,0x1a0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10D,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R9D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R13,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,0x8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,0x198(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 429311 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x91> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | advec_cell.cpp:65-110 |
Module | exec |
nb instructions | 96 |
nb uops | 107 |
loop length | 395 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 2 |
used ymm registers | 0 |
used zmm registers | 1 |
nb stack references | 20 |
micro-operation queue | 17.83 cycles |
front end | 17.83 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.70 | 8.00 | 7.67 | 7.67 | 13.50 | 6.80 | 6.70 | 13.50 | 13.50 | 13.50 | 6.80 | 7.67 |
cycles | 6.70 | 12.13 | 7.67 | 7.67 | 13.50 | 6.80 | 6.70 | 13.50 | 13.50 | 13.50 | 6.80 | 7.67 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 16.88-17.02 |
Stall cycles | 0.00 |
Front-end | 17.83 |
Dispatch | 13.50 |
DIV/SQRT | 12.00 |
Overall L1 | 17.83 |
all | 5% |
load | 0% |
store | 5% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 9% |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 5% |
load | 0% |
store | 5% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 11% |
all | 11% |
load | 9% |
store | 14% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 8% |
all | 12% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 11% |
load | 9% |
store | 14% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 9% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0x1c0,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x40(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x44(%RDI),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x3c(%RDI),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x38(%RDI),%EDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x2,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%RAX),%R13D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
INC %EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EDX,0x54(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EDI,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EDX,%R13D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 429c03 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x983> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EDX,%R14D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x4(%RBX),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R13D,%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R15D,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 429c03 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x983> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R15D,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %EDI,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ECX,0x1b8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 404650 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,0x1bc(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 404540 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EAX,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x1b8(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %R14D,%EAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DIVL 0x1bc(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV %EAX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 429c72 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x9f2> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %ECX,%ESI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%RSI,%RDX,1),%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%RCX,%RAX,1),%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EAX,0x1a4(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8D,0x4c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R8D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 429c03 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x983> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x50(%RSP),%R9D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%R12),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA 0x2(%RBX),%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
DIVL 0x1b8(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
MOV (%R12),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%R12),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EBX,0x194(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x10(%R12),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0x35233(%RIP),%XMM25 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R11,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDI,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RSI,0x10(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVD %EBX,%XMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VPBROADCASTD %XMM3,%ZMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVDQA32 %ZMM0,0x80(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
ADD %EDX,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%RAX,%R13,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R15D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x28(%R12),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%R12),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x30(%R12),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVSXD %R10D,%R8 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R9D,0x1a0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10D,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R9D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R13,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,0x8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,0x198(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 429311 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x91> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D | 3.42 | 2.58 |
▼Loop 172 - advec_cell.cpp:67-110 - exec– | 0 | 0 |
○Loop 174 - advec_cell.cpp:71-110 - exec | 3.41 | 2.57 |
○Loop 173 - advec_cell.cpp:71-110 - exec | 0 | 0 |