	*************************************************
	*                                               *
	*          ONE-View report generation           *
	*                                               *
	*************************************************

[MAQAO] Info: Experiment configuration summary is available adding -dbg=1 in command line

* [MAQAO] Warning: Experiment directory /home/eoseret/qaas/qaas_runs/178-540-1875/intel/CloverLeaf2.0-CXX/run/oneview_runs/defaults/armclang/oneview_results_1785402399 already exists and is reused.
           It can be replaced using --replace in the command line.
[MAQAO] Info: 
[MAQAO] Info: START THE APPLICATION PROFILING
[MAQAO] Info: -> RUNNING THE PROFILER...
[MAQAO] Info:   LPROF has already been run
[MAQAO] Info: STOP THE APPLICATION PROFILING
[MAQAO] Info: 
[MAQAO] Info: START FUNCTIONS AND LOOPS ANALYSIS ...
[MAQAO] Info: STOP FUNCTIONS AND LOOPS ANALYSIS ...
[MAQAO] Info: 
[MAQAO] Info: START THE REPORT GENERATION
[MAQAO] Info: -> ONE-VIEW EXPERIMENT DIRECTORY: /home/eoseret/qaas/qaas_runs/178-540-1875/intel/CloverLeaf2.0-CXX/run/oneview_runs/defaults/armclang/oneview_results_1785402399


+===================================================================================================================+
+                                                   1  -  GLOBAL                                                    +
+===================================================================================================================+


+-------------------------------------------------------------------------------------------------------------------+
+                                            1.1  -  Experiment Summary                                             +
+-------------------------------------------------------------------------------------------------------------------+

  Application:			/home/eoseret/qaas/qaas_runs/178-540-1875/intel/CloverLeaf2.0-CXX/run/oneview_runs/defaults/orig/exec
  Timestamp:			2026-07-30 09:06:38
  Universal Timestamp:		1785402398
  Experiment Type:		MPI; OpenMP; Throughput; 
  Machine:			ip-172-31-9-132.ec2.internal
  Architecture:			aarch64
  Micro Architecture:		ARM_NEOVERSE_V2
  OS Version:			Linux 6.1.170-213.321.amzn2023.aarch64 #1 SMP Thu May 14 12:18:13 UTC 2026
  Compilation Options:		
		exec: Arm Toolchain for Linux 22.1.0 clang version 22.1.0 (https://github.com/arm/arm-toolchain.git c95792353373404441df364b5a762338e5642230) /opt/arm/arm-toolchain-for-linux/bin/clang-22 -frtlib-add-rpath -fveclib=ArmPL -mllvm -gvn-add-phi-translation=1 -mllvm -store-to-load-forwarding-conflict-detection=0 --driver-mode=g++ -D USE_OMP -I /home/eoseret/qaas/qaas_runs/178-540-1875/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/omp -I /home/eoseret/qaas/qaas_runs/178-540-1875/intel/CloverLeaf2.0-CXX/build/build/generated -I /home/eoseret/qaas/qaas_runs/178-540-1875/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/driver -I /home/eoseret/qaas/qaas_runs/178-540-1875/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp -O3 -mcpu=native -g -fno-omit-frame-pointer -fcf-protection=none -no-pie -grecord-command-line -D NDEBUG -std=c++17 -Wall -Wno-unused-parameter -Wno-unused-function -Wno-unused-variable -O3 -fopenmp=libomp -MD -MT CMakeFiles/cloverleaf.dir/src/omp/advec_mom.cpp.o -MF CMakeFiles/cloverleaf.dir/src/omp/advec_mom.cpp.o.d -o CMakeFiles/cloverleaf.dir/src/omp/advec_mom.cpp.o -c /home/eoseret/qaas/qaas_runs/178-540-1875/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp -I /home/eoseret/tools/mpi/openmpi-armclang-22.1/include 
  Number of processes observed:	1
  Number of threads observed:	96
  MAQAO version:		2026.0.1
  MAQAO build:			Build information not available




+-------------------------------------------------------------------------------------------------------------------+
+                                              1.2  -  Global Metrics                                               +
+-------------------------------------------------------------------------------------------------------------------+

  Total Time:				87.85 s
  Max (Thread Active Time):		87.56 s
  Average Active Time:			84.52 s
  Activity Ratio:			96.3 %
  Average number of active threads:	92.360
  Affinity Stability:			96.5 %
  Time spent in analyzed loops:		92.2 %
  Time spent in analyzed innermost loops: 92.2 %
  Time spent in user code:		92.3 %
  Compilation Options Score:		100
  Array Access Efficiency:		36.5 %

   Potential Speedups
  ----------------------------------------------------
  Perfect Flow Complexity:		1.00
  Perfect OpenMP/MPI/Pthread/TBB:	1.06
  Perfect OpenMP/MPI/Pthread/TBB + Load Distribution:	1.10
  If No Scalar Integer:
      Potential Speedup:		1.00
      Nb Loops to get 80%:		1
  If FP Vectorized:
      Potential Speedup:		1.00
      Nb Loops to get 80%:		1
  If Fully Vectorized:
      Potential Speedup:		1.01
      Nb Loops to get 80%:		1
  If Only FP Arithmetic:
      Potential Speedup:		1.39
      Nb Loops to get 80%:		13




+-------------------------------------------------------------------------------------------------------------------+
+                                            1.3  -  Potential Speedups                                             +
+-------------------------------------------------------------------------------------------------------------------+

  If No Scalar Integer:
      Number of loops   | 1      | 9      | 18     | 26     | 35     | 
      Cumulated Speedup | 1.0005 | 1.0005 | 1.0005 | 1.0005 | 1.0005 | 
  Top 5 loops:
    exec - 147:	1.0005
    exec - 306:	1.0005
    exec - 313:	1.0005
    exec - 311:	1.0005
    exec - 150:	1.0005

  If FP Vectorized:
      Number of loops   | 1      | 9      | 18     | 26     | 35     | 
      Cumulated Speedup | 1.0000 | 1.0000 | 1.0000 | 1.0000 | 1.0000 | 
  Top 5 loops:
    exec - 306:	1
    exec - 313:	1
    exec - 311:	1
    exec - 150:	1
    exec - 316:	1

  If Fully Vectorized:
      Number of loops   | 1      | 9      | 18     | 26     | 35     | 
      Cumulated Speedup | 1.0058 | 1.0058 | 1.0058 | 1.0058 | 1.0058 | 
  Top 5 loops:
    exec - 147:	1.0058
    exec - 306:	1.0058
    exec - 313:	1.0058
    exec - 311:	1.0058
    exec - 150:	1.0058

  If Only FP Arithmetic:
      Number of loops   | 1      | 9      | 18     | 26     | 35     | 
      Cumulated Speedup | 1.0324 | 1.2453 | 1.3842 | 1.3901 | 1.3901 | 
  Top 5 loops:
    exec - 233:	1.0324
    exec - 306:	1.0634
    exec - 167:	1.0901
    exec - 169:	1.1173
    exec - 304:	1.1452



+===================================================================================================================+
+                                                   2  -  SUMMARY                                                   +
+===================================================================================================================+


+-------------------------------------------------------------------------------------------------------------------+
+                                            2.1  -  EXPERIMENT QUALITY                                             +
+-------------------------------------------------------------------------------------------------------------------+

  [4 / 4] Application profile is long enough (87.56 s)
To have good quality measurements, it is advised that the application profiling time is greater than 10 seconds.

  [3 / 3] Most of time spent in analyzed modules comes from functions with source/debug info
-g option gives access to debugging informations, such are source locations.

  [3 / 3] Most of time spent in analyzed modules comes from functions with compilation options informations and
-fno-omit-frame-pointer is present
-fno-omit-frame-pointer improves the accuracy of callchains found during the application profiling.

  [3 / 3] Host configuration allows retrieval of all necessary metrics.


  [2.999190082057 / 3] Most of time spent in analyzed modules (99.97%) comes from functions compiled with architecture specialization option
-mcpu


  [3 / 3] Optimization level option is correctly used


  [2 / 2] Application is correctly profiled ("Others" category represents 0.00 % of the execution time)
To have a representative profiling, it is advised that the category "Others" represents less than 20% of the
execution time in order to analyze as much as possible of the user code

  [1 / 1] Lstopo present. The Topology lstopo report will be generated.


  [0 / 0] Fastmath not used
Consider to add ffast-math to compilation flags (or replace -O3 with -Ofast) to unlock potential extra speedup by
relaxing floating-point computation consistency. Warning: floating-point accuracy may be reduced and the compliance
to IEEE/ISO rules/specifications for math functions will be relaxed, typically 'errno' will no longer be set after
calling some math functions.


+-------------------------------------------------------------------------------------------------------------------+
+                                               2.2  -  CODE QUALITY                                                +
+-------------------------------------------------------------------------------------------------------------------+

  [4 / 4] Enough time of the experiment time spent in analyzed loops (92.21%)
If the time spent in analyzed loops is less than 30%, standard loop optimizations will have a limited impact on
application performances.

  [4 / 4] Threads activity is good
On average, more than 96.21% of observed threads are actually active 

  [4 / 4] CPU activity is good
CPU cores are active 96.25% of time

  [4 / 4] Loop profile is not flat
At least one loop coverage is greater than 4% (6.77%), representing an hotspot for the application

  [4 / 4] Enough time of the experiment time spent in analyzed innermost loops (92.21%)
If the time spent in analyzed innermost loops is less than 15%, standard innermost loop optimizations such as
vectorisation will have a limited impact on application performances.

  [4 / 4] Affinity is good (96.51%)
Threads are not migrating to CPU cores: probably successfully pinned

  [3 / 3] Less than 10% (0.00%) is spend in BLAS1 operations
It could be more efficient to inline by hand BLAS1 operations

  [3 / 3] Functions mostly use all threads
Functions running on a reduced number of threads (typically sequential code) cover less than 10% of application
walltime (5.79%)

  [3 / 3] Cumulative Outermost/In between loops coverage (0.00%) lower than cumulative innermost loop coverage (92.21%)
Having cumulative Outermost/In between loops coverage greater than cumulative innermost loop coverage will make loop
optimization more complex

  [2 / 2] Less than 10% (0.00%) is spend in BLAS2 operations
BLAS2 calls usually could make a poor cache usage and could benefit from inlining.

  [2 / 2] Less than 10% (0.00%) is spend in Libm/SVML (special functions)



+-------------------------------------------------------------------------------------------------------------------+
+                                              2.3  -  LOOPS OVERVIEW                                               +
+-------------------------------------------------------------------------------------------------------------------+

  Top 5 loops:
   + exec - 306 :
     analysis: Execution Time: 6 % - Vectorization Ratio: 65.41 % - Vector Length Use: 83.37 %
     Loop Computation Issues: 20
        [16] [SA] Presence of expensive FP instructions - Perform hoisting, change algorithm, use SVML or proper
            numerical library or perform value profiling (count the number of distinct input values). There are 4
            issues (= instructions) costing 4 points each.
        [4] [SA] Less than 10% of the FP ADD/SUB/MUL arithmetic operations are performed using FMA - Reorganize
            arithmetic expressions to exhibit potential for FMA. This issue costs 4 points.
     Data Access Issues: 144
        [92] [SA] Presence of constant non unit stride data access - Use array restructuring, perform loop interchange
            or use gather instructions to lower a bit the cost. There are 46 issues ( = data accesses) costing 2
            point each.
        [52] [SA] Presence of indirect accesses - Use array restructuring or gather instructions to lower the cost.
            There are 13 issues ( = indirect data accesses) costing 4 point each.
     Vectorization Roadblocks: 144
        [92] [SA] Presence of constant non unit stride data access - Use array restructuring, perform loop interchange
            or use gather instructions to lower a bit the cost. There are 46 issues ( = data accesses) costing 2
            point each.
        [52] [SA] Presence of indirect accesses - Use array restructuring or gather instructions to lower the cost.
            There are 13 issues ( = indirect data accesses) costing 4 point each.

   + exec - 147 :
     analysis: Execution Time: 5 % - Vectorization Ratio: 69.33 % - Vector Length Use: 86.00 %
     Loop Computation Issues: 4
        [4] [SA] Presence of expensive FP instructions - Perform hoisting, change algorithm, use SVML or proper
            numerical library or perform value profiling (count the number of distinct input values). There are 1
            issues (= instructions) costing 4 points each.
     Data Access Issues: 120
        [80] [SA] Presence of constant non unit stride data access - Use array restructuring, perform loop interchange
            or use gather instructions to lower a bit the cost. There are 40 issues ( = data accesses) costing 2
            point each.
        [40] [SA] Presence of indirect accesses - Use array restructuring or gather instructions to lower the cost.
            There are 10 issues ( = indirect data accesses) costing 4 point each.
     Vectorization Roadblocks: 120
        [80] [SA] Presence of constant non unit stride data access - Use array restructuring, perform loop interchange
            or use gather instructions to lower a bit the cost. There are 40 issues ( = data accesses) costing 2
            point each.
        [40] [SA] Presence of indirect accesses - Use array restructuring or gather instructions to lower the cost.
            There are 10 issues ( = indirect data accesses) costing 4 point each.

   + exec - 304 :
     analysis: Execution Time: 5 % - Vectorization Ratio: 71.21 % - Vector Length Use: 86.03 %
     Loop Computation Issues: 20
        [16] [SA] Presence of expensive FP instructions - Perform hoisting, change algorithm, use SVML or proper
            numerical library or perform value profiling (count the number of distinct input values). There are 4
            issues (= instructions) costing 4 points each.
        [4] [SA] Less than 10% of the FP ADD/SUB/MUL arithmetic operations are performed using FMA - Reorganize
            arithmetic expressions to exhibit potential for FMA. This issue costs 4 points.
     Data Access Issues: 112
        [68] [SA] Presence of constant non unit stride data access - Use array restructuring, perform loop interchange
            or use gather instructions to lower a bit the cost. There are 34 issues ( = data accesses) costing 2
            point each.
        [44] [SA] Presence of indirect accesses - Use array restructuring or gather instructions to lower the cost.
            There are 11 issues ( = indirect data accesses) costing 4 point each.
     Vectorization Roadblocks: 112
        [68] [SA] Presence of constant non unit stride data access - Use array restructuring, perform loop interchange
            or use gather instructions to lower a bit the cost. There are 34 issues ( = data accesses) costing 2
            point each.
        [44] [SA] Presence of indirect accesses - Use array restructuring or gather instructions to lower the cost.
            There are 11 issues ( = indirect data accesses) costing 4 point each.

   + exec - 188 :
     analysis: Execution Time: 4 % - Vectorization Ratio: 78.08 % - Vector Length Use: 92.47 %
     Loop Computation Issues: 16
        [16] [SA] Presence of expensive FP instructions - Perform hoisting, change algorithm, use SVML or proper
            numerical library or perform value profiling (count the number of distinct input values). There are 4
            issues (= instructions) costing 4 points each.
     Data Access Issues: 40
        [20] [SA] Presence of constant non unit stride data access - Use array restructuring, perform loop interchange
            or use gather instructions to lower a bit the cost. There are 10 issues ( = data accesses) costing 2
            point each.
        [20] [SA] Presence of indirect accesses - Use array restructuring or gather instructions to lower the cost.
            There are 5 issues ( = indirect data accesses) costing 4 point each.
     Vectorization Roadblocks: 40
        [20] [SA] Presence of constant non unit stride data access - Use array restructuring, perform loop interchange
            or use gather instructions to lower a bit the cost. There are 10 issues ( = data accesses) costing 2
            point each.
        [20] [SA] Presence of indirect accesses - Use array restructuring or gather instructions to lower the cost.
            There are 5 issues ( = indirect data accesses) costing 4 point each.

   + exec - 190 :
     analysis: Execution Time: 4 % - Vectorization Ratio: 64.71 % - Vector Length Use: 85.29 %
     Loop Computation Issues: 4
        [4] [SA] Presence of expensive FP instructions - Perform hoisting, change algorithm, use SVML or proper
            numerical library or perform value profiling (count the number of distinct input values). There are 1
            issues (= instructions) costing 4 points each.
     Data Access Issues: 34
        [18] [SA] Presence of constant non unit stride data access - Use array restructuring, perform loop interchange
            or use gather instructions to lower a bit the cost. There are 9 issues ( = data accesses) costing 2
            point each.
        [16] [SA] Presence of indirect accesses - Use array restructuring or gather instructions to lower the cost.
            There are 4 issues ( = indirect data accesses) costing 4 point each.
     Vectorization Roadblocks: 34
        [18] [SA] Presence of constant non unit stride data access - Use array restructuring, perform loop interchange
            or use gather instructions to lower a bit the cost. There are 9 issues ( = data accesses) costing 2
            point each.
        [16] [SA] Presence of indirect accesses - Use array restructuring or gather instructions to lower the cost.
            There are 4 issues ( = indirect data accesses) costing 4 point each.



+===================================================================================================================+
+                                                 3  -  APPLICATION                                                 +
+===================================================================================================================+


+-------------------------------------------------------------------------------------------------------------------+
+                                              3.1  -  Categorization                                               +
+-------------------------------------------------------------------------------------------------------------------+

   Category | IO     | Exe    | System  | Others | Memory | String | MPI   | TBB   | OMP   | Pthread | Math  |
  ----------+--------+--------+---------+--------+--------+--------+-------+-------+-------+---------+-------+
   Time (%) | 0.00   | 92.26  | 1.91    | 0.00   | 0.00   | 0.00   | 0.00  | 0.00  | 5.83  | 0.00    | 0.00  |




+-------------------------------------------------------------------------------------------------------------------+
+                                         3.2  -  Function Based Profiling                                          +
+-------------------------------------------------------------------------------------------------------------------+

   Buckets                   | Nb Functions              | Coverage                  | Cumulated Coverage        |
  ---------------------------+---------------------------+---------------------------+---------------------------+
   > 8%                      | 0                         | 0.00                      | 0.00                      |
   4% to 8%                  | 9                         | 44.21                     | 44.21                     |
   2% to 4%                  | 13                        | 39.52                     | 83.72                     |
   1% to 2%                  | 8                         | 11.49                     | 95.21                     |
   0.5% to 1%                | 4                         | 2.99                      | 98.20                     |
   0.25% to 0.5%             | 2                         | 0.61                      | 98.80                     |
   0.125% to 0.25%           | 3                         | 0.58                      | 99.38                     |
   < 0.125%                  | 95                        | 0.51                      | 99.89                     |




+-------------------------------------------------------------------------------------------------------------------+
+                                           3.3  -  Loop Based Profiling                                            +
+-------------------------------------------------------------------------------------------------------------------+

   Buckets                   | Nb Loops                  | Coverage                  | Cumulated Coverage        |
  ---------------------------+---------------------------+---------------------------+---------------------------+
   > 8%                      | 0                         | 0.00                      | 0.00                      |
   4% to 8%                  | 8                         | 39.83                     | 39.83                     |
   2% to 4%                  | 13                        | 39.51                     | 79.34                     |
   1% to 2%                  | 8                         | 11.49                     | 90.83                     |
   0.5% to 1%                | 1                         | 0.95                      | 91.78                     |
   0.25% to 0.5%             | 1                         | 0.30                      | 92.07                     |
   0.125% to 0.25%           | 0                         | 0.00                      | 92.07                     |
   < 0.125%                  | 22                        | 0.14                      | 92.21                     |


+===================================================================================================================+
+                                                  4  -  FUNCTIONS                                                  +
+===================================================================================================================+


+-------------------------------------------------------------------------------------------------------------------+
+                                             4.1  -  Top 10 Functions                                              +
+-------------------------------------------------------------------------------------------------------------------+

   Function                                               | Module               | Coverage (%)  | Time (s)      |
  --------------------------------------------------------+----------------------+---------------+---------------+
   PdV_kernel(bool, int, int, int, int, double, clover... | exec                 | 6.77          | 5.72          |
   accelerate_kernel(int, int, int, int, double, clove... | exec                 | 5.72          | 4.83          |
   PdV_kernel(bool, int, int, int, int, double, clover... | exec                 | 5.23          | 4.42          |
   advec_mom_kernel(int, int, int, int, clover::Buffer... | exec                 | 4.74          | 4.01          |
   kmp_flag_64<false, true>::wait(kmp_info*, int, void*)  | libomp.so            | 4.38          | 3.70          |
   advec_mom_kernel(int, int, int, int, clover::Buffer... | exec                 | 4.36          | 3.69          |
   ideal_gas_kernel(int, int, int, int, clover::Buffer... | exec                 | 4.35          | 3.68          |
   advec_mom_kernel(int, int, int, int, clover::Buffer... | exec                 | 4.34          | 3.67          |
   advec_mom_kernel(int, int, int, int, clover::Buffer... | exec                 | 4.31          | 3.64          |
   flux_calc_kernel(int, int, int, int, double, clover... | exec                 | 3.98          | 3.37          |


+===================================================================================================================+
+                                                    5  -  LOOPS                                                    +
+===================================================================================================================+


+-------------------------------------------------------------------------------------------------------------------+
+                                               5.1  -  Top 10 Loops                                                +
+-------------------------------------------------------------------------------------------------------------------+

   Loop Id        | Module               | Source Location                                       | Coverage (%)  |
  ----------------+----------------------+-------------------------------------------------------+---------------+
   306            | exec                 | context.h:69-69,PdV.cpp:70-83                         | 6.77          |
   147            | exec                 | accelerate.cpp:41-53,context.h:69-69                  | 5.72          |
   304            | exec                 | context.h:69-69,PdV.cpp:49-63                         | 5.23          |
   188            | exec                 | context.h:69-69,advec_mom.cpp:181-211                 | 4.74          |
   190            | exec                 | context.h:69-69,advec_mom.cpp:219-221                 | 4.36          |
   246            | exec                 | ideal_gas.cpp:38-45,context.h:69-69                   | 4.35          |
   180            | exec                 | context.h:69-69,advec_mom.cpp:109-139                 | 4.34          |
   182            | exec                 | context.h:69-69,advec_mom.cpp:147-149                 | 4.31          |
   233            | exec                 | flux_calc.cpp:37-40,context.h:69-69                   | 3.98          |
   165            | exec                 | advec_cell.cpp:209-216,context.h:69-69                | 3.76          |





+===================================================================================================================+
+                                                     6  -  CQA                                                     +
+===================================================================================================================+


+-------------------------------------------------------------------------------------------------------------------+
+                                                   6.1  -  Loops                                                   +
+-------------------------------------------------------------------------------------------------------------------+





      6.1.1  -  Loop 306 from exec
  =========================================================================================================

The loop is defined in:
 - /home/eoseret/qaas/qaas_runs/178-540-1875/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
 - /home/eoseret/qaas/qaas_runs/178-540-1875/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:70-83


The related source loop is unrolled by 2 (including vectorization).

      6.1.1.1  -  Path 1
  ---------------------------------------------------------------------------------------------------------

Warnings:
 - The number of fused uops of the instruction [MUL	Z7.D, Z1.D, Z15.D] is unknown
 - The number of fused uops of the instruction [MUL	Z17.D, Z2.D, Z15.D] is unknown
 - The number of fused uops of the instruction [MUL	Z6.D, Z0.D, Z15.D] is unknown
 - The number of fused uops of the instruction [MUL	Z16.D, Z1.D, Z0.D] is unknown
 - The number of fused uops of the instruction [MUL	Z19.D, Z2.D, Z0.D] is unknown
 - The number of fused uops of the instruction [MUL	Z16.D, Z3.D, Z15.D] is unknown
 - The number of fused uops of the instruction [MUL	Z19.D, Z4.D, Z15.D] is unknown
 - The number of fused uops of the instruction [MUL	Z19.D, Z5.D, Z15.D] is unknown
 - The number of fused uops of the instruction [MUL	Z19.D, Z3.D, Z0.D] is unknown
 - The number of fused uops of the instruction [MUL	Z25.D, Z4.D, Z0.D] is unknown
 - The number of fused uops of the instruction [MUL	Z0.D, Z5.D, Z0.D] is unknown
 - The number of fused uops of the instruction [MUL	Z20.D, Z20.D, Z15.D] is unknown
 - The number of fused uops of the instruction [MUL	Z19.D, Z19.D, Z15.D] is unknown
 - The number of fused uops of the instruction [MUL	Z21.D, Z21.D, Z15.D] is unknown
 - The number of fused uops of the instruction [MUL	Z22.D, Z22.D, Z15.D] is unknown
 - The number of fused uops of the instruction [MUL	Z7.D, Z7.D, Z15.D] is unknown

4% of peak computational performance is used (1.54 out of 32.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.1.1.1  -  Vectorization
  ---------------------------------------------------------------------------------------------------------

Your loop is partially vectorized.
83% of vector register length is used (average across all VPU instructions).


Details
65% of VPU instructions are used in vector version (process two or more data elements in vector registers):
 - 45% of VPU loads are used in vector version.
 - 34% of VPU addition or subtraction instructions are used in vector version.
 - 20% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.





      6.1.1.1.2  -  Expensive FP math instructions/calls
  ---------------------------------------------------------------------------------------------------------

Detected performance impact from expensive FP math instructions/calls.
By removing/reexpressing them, you can lower the cost of an iteration from 47.97 to 30.75 cycles (1.56x speedup).


      6.1.1.1.3  -  FMA
  ---------------------------------------------------------------------------------------------------------

Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.1.1.4  -  Slow data structures access
  ---------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Constant unknown stride: 46 occurrence(s)
 - Irregular (variable stride) or indirect: 13 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)
 - Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.



      6.1.1.1.5  -  Matching between your loop (in the source code) and the binary loop
  ---------------------------------------------------------------------------------------------------------

The binary loop is composed of 74 FP arithmetical operations:
 - 36: addition or subtraction
 - 30: multiply
 - 8: divide
The binary loop is loading 613 bytes.
The binary loop is storing 32 bytes.


      6.1.1.1.6  -  Arithmetic intensity
  ---------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.11 FP operations per loaded or stored byte.







      6.1.2  -  Loop 147 from exec
  =========================================================================================================

The loop is defined in:
 - /home/eoseret/qaas/qaas_runs/178-540-1875/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp:41-53
 - /home/eoseret/qaas/qaas_runs/178-540-1875/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69


The related source loop is unrolled by 2 (including vectorization).

      6.1.2.1  -  Path 1
  ---------------------------------------------------------------------------------------------------------

Warnings:
 - The number of fused uops of the instruction [MUL	Z2.D, Z0.D, Z12.D] is unknown
 - The number of fused uops of the instruction [MUL	Z5.D, Z0.D, Z15.D] is unknown
 - The number of fused uops of the instruction [MUL	Z19.D, Z1.D, Z15.D] is unknown
 - The number of fused uops of the instruction [MUL	Z26.D, Z1.D, Z12.D] is unknown
 - The number of fused uops of the instruction [MUL	Z20.D, Z3.D, Z15.D] is unknown
 - The number of fused uops of the instruction [MUL	Z22.D, Z4.D, Z12.D] is unknown
 - The number of fused uops of the instruction [MUL	Z16.D, Z16.D, Z15.D] is unknown
 - The number of fused uops of the instruction [MUL	Z2.D, Z3.D, Z12.D] is unknown
 - The number of fused uops of the instruction [MUL	Z20.D, Z4.D, Z15.D] is unknown
 - The number of fused uops of the instruction [MUL	Z7.D, Z7.D, Z15.D] is unknown
 - The number of fused uops of the instruction [MUL	Z28.D, Z28.D, Z15.D] is unknown
 - The number of fused uops of the instruction [MUL	Z19.D, Z19.D, Z15.D] is unknown
 - The number of fused uops of the instruction [MUL	Z16.D, Z17.D, Z12.D] is unknown
 - The number of fused uops of the instruction [MUL	Z21.D, Z21.D, Z15.D] is unknown
 - The number of fused uops of the instruction [MUL	Z22.D, Z17.D, Z15.D] is unknown

7% of peak computational performance is used (2.47 out of 32.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.2.1.1  -  Vectorization
  ---------------------------------------------------------------------------------------------------------

Your loop is partially vectorized.
86% of vector register length is used (average across all VPU instructions).
By fully vectorizing your loop, you can lower the cost of an iteration from 30.00 to 26.99 cycles (1.11x speedup).

Details
69% of VPU instructions are used in vector version (process two or more data elements in vector registers):
 - 55% of VPU loads are used in vector version.
 - 25% of VPU addition or subtraction instructions are used in vector version.
 - 37% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.
Since your execution units are vector units, only a fully vectorized loop can use their full power.


Workaround
 - Try another compiler or update/tune your current one:
  * recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
 - Remove inter-iterations dependences from your loop and make it unit-stride:
  * If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly:
C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)<<image_row_maj>>
  * If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA):
for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)





      6.1.2.1.2  -  FMA
  ---------------------------------------------------------------------------------------------------------

Detected 22 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.2.1.3  -  Slow data structures access
  ---------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Constant unknown stride: 40 occurrence(s)
 - Irregular (variable stride) or indirect: 10 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)
 - Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.



      6.1.2.1.4  -  Matching between your loop (in the source code) and the binary loop
  ---------------------------------------------------------------------------------------------------------

The binary loop is composed of 74 FP arithmetical operations:
 - 38: addition or subtraction (22 inside FMA instructions)
 - 34: multiply (22 inside FMA instructions)
 - 2: divide
The binary loop is loading 788 bytes.
The binary loop is storing 64 bytes.


      6.1.2.1.5  -  Arithmetic intensity
  ---------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.09 FP operations per loaded or stored byte.







      6.1.3  -  Loop 304 from exec
  =========================================================================================================

The loop is defined in:
 - /home/eoseret/qaas/qaas_runs/178-540-1875/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
 - /home/eoseret/qaas/qaas_runs/178-540-1875/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:49-63


The related source loop is unrolled by 2 (including vectorization).

      6.1.3.1  -  Path 1
  ---------------------------------------------------------------------------------------------------------

Warnings:
 - The number of fused uops of the instruction [MUL	Z7.D, Z1.D, Z31.D] is unknown
 - The number of fused uops of the instruction [MUL	Z17.D, Z1.D, Z19.D] is unknown
 - The number of fused uops of the instruction [MUL	Z21.D, Z2.D, Z31.D] is unknown
 - The number of fused uops of the instruction [MUL	Z5.D, Z5.D, Z31.D] is unknown
 - The number of fused uops of the instruction [MUL	Z18.D, Z3.D, Z31.D] is unknown
 - The number of fused uops of the instruction [MUL	Z20.D, Z2.D, Z19.D] is unknown
 - The number of fused uops of the instruction [MUL	Z19.D, Z3.D, Z19.D] is unknown
 - The number of fused uops of the instruction [MUL	Z20.D, Z20.D, Z31.D] is unknown
 - The number of fused uops of the instruction [MUL	Z17.D, Z17.D, Z31.D] is unknown
 - The number of fused uops of the instruction [MUL	Z6.D, Z6.D, Z31.D] is unknown
 - The number of fused uops of the instruction [MUL	Z18.D, Z18.D, Z31.D] is unknown
 - The number of fused uops of the instruction [MUL	Z16.D, Z16.D, Z31.D] is unknown

5% of peak computational performance is used (1.71 out of 32.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.3.1.1  -  Vectorization
  ---------------------------------------------------------------------------------------------------------

Your loop is partially vectorized.
86% of vector register length is used (average across all VPU instructions).


Details
71% of VPU instructions are used in vector version (process two or more data elements in vector registers):
 - 45% of VPU loads are used in vector version.
 - 41% of VPU addition or subtraction instructions are used in vector version.
 - 40% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.





      6.1.3.1.2  -  Expensive FP math instructions/calls
  ---------------------------------------------------------------------------------------------------------

Detected performance impact from expensive FP math instructions/calls.
By removing/reexpressing them, you can lower the cost of an iteration from 47.97 to 26.50 cycles (1.81x speedup).


      6.1.3.1.3  -  FMA
  ---------------------------------------------------------------------------------------------------------

Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.3.1.4  -  Slow data structures access
  ---------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Constant unknown stride: 34 occurrence(s)
 - Irregular (variable stride) or indirect: 11 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)
 - Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.



      6.1.3.1.5  -  Matching between your loop (in the source code) and the binary loop
  ---------------------------------------------------------------------------------------------------------

The binary loop is composed of 82 FP arithmetical operations:
 - 36: addition or subtraction
 - 38: multiply
 - 8: divide
The binary loop is loading 452 bytes.
The binary loop is storing 32 bytes.


      6.1.3.1.6  -  Arithmetic intensity
  ---------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.17 FP operations per loaded or stored byte.







      6.1.4  -  Loop 188 from exec
  =========================================================================================================

The loop is defined in:
 - /home/eoseret/qaas/qaas_runs/178-540-1875/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
 - /home/eoseret/qaas/qaas_runs/178-540-1875/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:181-211


The related source loop is unrolled by 2 (including vectorization).

      6.1.4.1  -  Path 1
  ---------------------------------------------------------------------------------------------------------

Warnings:
 - The number of fused uops of the instruction [MUL	Z27.D, Z0.D, Z26.D] is unknown
 - The number of fused uops of the instruction [MUL	Z26.D, Z3.D, Z26.D] is unknown
 - The number of fused uops of the instruction [MUL	Z10.D, Z1.D, Z9.D] is unknown
 - The number of fused uops of the instruction [MUL	Z9.D, Z2.D, Z9.D] is unknown
 - The number of fused uops of the instruction [MUL	Z8.D, Z2.D, Z8.D] is unknown
 - The number of fused uops of the instruction [MUL	Z30.D, Z2.D, Z30.D] is unknown

2% of peak computational performance is used (0.71 out of 32.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.4.1.1  -  Vectorization
  ---------------------------------------------------------------------------------------------------------

Your loop is partially vectorized.
92% of vector register length is used (average across all VPU instructions).


Details
78% of VPU instructions are used in vector version (process two or more data elements in vector registers):
 - 41% of VPU loads are used in vector version.
 - 52% of VPU addition or subtraction instructions are used in vector version.
 - 79% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.





      6.1.4.1.2  -  Expensive FP math instructions/calls
  ---------------------------------------------------------------------------------------------------------

Detected performance impact from expensive FP math instructions/calls.
By removing/reexpressing them, you can lower the cost of an iteration from 47.97 to 16.00 cycles (3.00x speedup).


      6.1.4.1.3  -  FMA
  ---------------------------------------------------------------------------------------------------------

Detected 2 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.4.1.4  -  Slow data structures access
  ---------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Constant unknown stride: 10 occurrence(s)
 - Irregular (variable stride) or indirect: 5 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)
 - Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.



      6.1.4.1.5  -  Matching between your loop (in the source code) and the binary loop
  ---------------------------------------------------------------------------------------------------------

The binary loop is composed of 34 FP arithmetical operations:
 - 14: addition or subtraction (2 inside FMA instructions)
 - 12: multiply (2 inside FMA instructions)
 - 8: divide
The binary loop is loading 113 bytes.
The binary loop is storing 16 bytes.


      6.1.4.1.6  -  Arithmetic intensity
  ---------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.26 FP operations per loaded or stored byte.







      6.1.5  -  Loop 190 from exec
  =========================================================================================================

The loop is defined in:
 - /home/eoseret/qaas/qaas_runs/178-540-1875/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
 - /home/eoseret/qaas/qaas_runs/178-540-1875/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:219-221


The related source loop is unrolled by 2 (including vectorization).

      6.1.5.1  -  Path 1
  ---------------------------------------------------------------------------------------------------------

Warnings:
 - The number of fused uops of the instruction [MUL	Z27.D, Z1.D, Z23.D] is unknown
 - The number of fused uops of the instruction [MUL	Z25.D, Z0.D, Z23.D] is unknown
 - The number of fused uops of the instruction [MUL	Z22.D, Z2.D, Z22.D] is unknown
 - The number of fused uops of the instruction [MUL	Z29.D, Z2.D, Z23.D] is unknown
 - The number of fused uops of the instruction [MUL	Z23.D, Z3.D, Z23.D] is unknown

0% of peak computational performance is used (0.30 out of 32.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.5.1.1  -  Vectorization
  ---------------------------------------------------------------------------------------------------------

Your loop is partially vectorized.
85% of vector register length is used (average across all VPU instructions).


Details
64% of VPU instructions are used in vector version (process two or more data elements in vector registers):
 - 35% of VPU loads are used in vector version.
 - 37% of VPU addition or subtraction instructions are used in vector version.
 - 50% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.





      6.1.5.1.2  -  Expensive FP math instructions/calls
  ---------------------------------------------------------------------------------------------------------

Detected performance impact from expensive FP math instructions/calls.
By removing/reexpressing them, you can lower the cost of an iteration from 26.99 to 7.00 cycles (3.86x speedup).


      6.1.5.1.3  -  FMA
  ---------------------------------------------------------------------------------------------------------

Detected 2 FMA (fused multiply-add) operations.




      6.1.5.1.4  -  Slow data structures access
  ---------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Constant unknown stride: 9 occurrence(s)
 - Irregular (variable stride) or indirect: 4 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)
 - Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.



      6.1.5.1.5  -  Matching between your loop (in the source code) and the binary loop
  ---------------------------------------------------------------------------------------------------------

The binary loop is composed of 8 FP arithmetical operations:
 - 4: addition or subtraction (2 inside FMA instructions)
 - 2: multiply (all inside FMA instructions)
 - 2: divide
The binary loop is loading 81 bytes.
The binary loop is storing 16 bytes.


      6.1.5.1.6  -  Arithmetic intensity
  ---------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.







      6.1.6  -  Loop 246 from exec
  =========================================================================================================

The loop is defined in:
 - /home/eoseret/qaas/qaas_runs/178-540-1875/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/ideal_gas.cpp:38-45
 - /home/eoseret/qaas/qaas_runs/178-540-1875/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69


The related source loop is unrolled by 2 (including vectorization).

      6.1.6.1  -  Path 1
  ---------------------------------------------------------------------------------------------------------

Warnings:
 - The number of fused uops of the instruction [MUL	Z25.D, Z0.D, Z24.D] is unknown
 - The number of fused uops of the instruction [MUL	Z27.D, Z1.D, Z24.D] is unknown
 - The number of fused uops of the instruction [MUL	Z28.D, Z2.D, Z24.D] is unknown
 - The number of fused uops of the instruction [MUL	Z24.D, Z3.D, Z24.D] is unknown

1% of peak computational performance is used (0.49 out of 32.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.6.1.1  -  Vectorization
  ---------------------------------------------------------------------------------------------------------

Your loop is partially vectorized.
86% of vector register length is used (average across all VPU instructions).


Details
70% of VPU instructions are used in vector version (process two or more data elements in vector registers):
 - 27% of VPU loads are used in vector version.
 - 25% of VPU addition or subtraction instructions are used in vector version.
 - 50% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.





      6.1.6.1.2  -  Expensive FP math instructions/calls
  ---------------------------------------------------------------------------------------------------------

Detected performance impact from expensive FP math instructions/calls.
By removing/reexpressing them, you can lower the cost of an iteration from 41.08 to 7.25 cycles (5.67x speedup).


      6.1.6.1.3  -  FMA
  ---------------------------------------------------------------------------------------------------------

Detected 2 FMA (fused multiply-add) operations.




      6.1.6.1.4  -  Slow data structures access
  ---------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Constant unknown stride: 8 occurrence(s)
 - Irregular (variable stride) or indirect: 4 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)
 - Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.



      6.1.6.1.5  -  Matching between your loop (in the source code) and the binary loop
  ---------------------------------------------------------------------------------------------------------

The binary loop is composed of 20 FP arithmetical operations:
 - 2: addition or subtraction (all inside FMA instructions)
 - 14: multiply (2 inside FMA instructions)
 - 2: divide
 - 2: square root
The binary loop is loading 49 bytes.
The binary loop is storing 32 bytes.


      6.1.6.1.6  -  Arithmetic intensity
  ---------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.25 FP operations per loaded or stored byte.







      6.1.7  -  Loop 180 from exec
  =========================================================================================================

The loop is defined in:
 - /home/eoseret/qaas/qaas_runs/178-540-1875/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
 - /home/eoseret/qaas/qaas_runs/178-540-1875/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:109-139


The related source loop is unrolled by 2 (including vectorization).

      6.1.7.1  -  Path 1
  ---------------------------------------------------------------------------------------------------------

Warnings:
 - The number of fused uops of the instruction [MUL	Z27.D, Z0.D, Z26.D] is unknown
 - The number of fused uops of the instruction [MUL	Z30.D, Z1.D, Z26.D] is unknown
 - The number of fused uops of the instruction [MUL	Z10.D, Z2.D, Z26.D] is unknown
 - The number of fused uops of the instruction [MUL	Z26.D, Z3.D, Z26.D] is unknown

2% of peak computational performance is used (0.71 out of 32.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.7.1.1  -  Vectorization
  ---------------------------------------------------------------------------------------------------------

Your loop is partially vectorized.
91% of vector register length is used (average across all VPU instructions).


Details
75% of VPU instructions are used in vector version (process two or more data elements in vector registers):
 - 36% of VPU loads are used in vector version.
 - 48% of VPU addition or subtraction instructions are used in vector version.
 - 79% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.





      6.1.7.1.2  -  Expensive FP math instructions/calls
  ---------------------------------------------------------------------------------------------------------

Detected performance impact from expensive FP math instructions/calls.
By removing/reexpressing them, you can lower the cost of an iteration from 47.97 to 16.50 cycles (2.91x speedup).


      6.1.7.1.3  -  FMA
  ---------------------------------------------------------------------------------------------------------

Detected 2 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.7.1.4  -  Slow data structures access
  ---------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Constant unknown stride: 12 occurrence(s)
 - Irregular (variable stride) or indirect: 5 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)
 - Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.



      6.1.7.1.5  -  Matching between your loop (in the source code) and the binary loop
  ---------------------------------------------------------------------------------------------------------

The binary loop is composed of 34 FP arithmetical operations:
 - 14: addition or subtraction (2 inside FMA instructions)
 - 12: multiply (2 inside FMA instructions)
 - 8: divide
The binary loop is loading 113 bytes.
The binary loop is storing 16 bytes.


      6.1.7.1.6  -  Arithmetic intensity
  ---------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.26 FP operations per loaded or stored byte.







      6.1.8  -  Loop 182 from exec
  =========================================================================================================

The loop is defined in:
 - /home/eoseret/qaas/qaas_runs/178-540-1875/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
 - /home/eoseret/qaas/qaas_runs/178-540-1875/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:147-149


The related source loop is unrolled by 2 (including vectorization).

      6.1.8.1  -  Path 1
  ---------------------------------------------------------------------------------------------------------

Warnings:
 - The number of fused uops of the instruction [MUL	Z27.D, Z1.D, Z23.D] is unknown
 - The number of fused uops of the instruction [MUL	Z25.D, Z0.D, Z23.D] is unknown
 - The number of fused uops of the instruction [MUL	Z28.D, Z2.D, Z23.D] is unknown
 - The number of fused uops of the instruction [MUL	Z23.D, Z3.D, Z23.D] is unknown

0% of peak computational performance is used (0.30 out of 32.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.8.1.1  -  Vectorization
  ---------------------------------------------------------------------------------------------------------

Your loop is partially vectorized.
82% of vector register length is used (average across all VPU instructions).


Details
62% of VPU instructions are used in vector version (process two or more data elements in vector registers):
 - 33% of VPU loads are used in vector version.
 - 31% of VPU addition or subtraction instructions are used in vector version.
 - 50% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.





      6.1.8.1.2  -  Expensive FP math instructions/calls
  ---------------------------------------------------------------------------------------------------------

Detected performance impact from expensive FP math instructions/calls.
By removing/reexpressing them, you can lower the cost of an iteration from 26.99 to 6.75 cycles (4.00x speedup).


      6.1.8.1.3  -  FMA
  ---------------------------------------------------------------------------------------------------------

Detected 2 FMA (fused multiply-add) operations.




      6.1.8.1.4  -  Slow data structures access
  ---------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Constant unknown stride: 10 occurrence(s)
 - Irregular (variable stride) or indirect: 4 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)
 - Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.



      6.1.8.1.5  -  Matching between your loop (in the source code) and the binary loop
  ---------------------------------------------------------------------------------------------------------

The binary loop is composed of 8 FP arithmetical operations:
 - 4: addition or subtraction (2 inside FMA instructions)
 - 2: multiply (all inside FMA instructions)
 - 2: divide
The binary loop is loading 81 bytes.
The binary loop is storing 16 bytes.


      6.1.8.1.6  -  Arithmetic intensity
  ---------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.







      6.1.9  -  Loop 233 from exec
  =========================================================================================================

The loop is defined in:
 - /home/eoseret/qaas/qaas_runs/178-540-1875/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/flux_calc.cpp:37-40
 - /home/eoseret/qaas/qaas_runs/178-540-1875/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69


The related source loop is unrolled by 2 (including vectorization).

      6.1.9.1  -  Path 1
  ---------------------------------------------------------------------------------------------------------

Warnings:
 - The number of fused uops of the instruction [MUL	Z12.D, Z0.D, Z8.D] is unknown
 - The number of fused uops of the instruction [MUL	Z14.D, Z1.D, Z8.D] is unknown
 - The number of fused uops of the instruction [MUL	Z0.D, Z1.D, Z11.D] is unknown
 - The number of fused uops of the instruction [MUL	Z3.D, Z2.D, Z8.D] is unknown
 - The number of fused uops of the instruction [MUL	Z11.D, Z2.D, Z11.D] is unknown
 - The number of fused uops of the instruction [MUL	Z15.D, Z5.D, Z8.D] is unknown
 - The number of fused uops of the instruction [MUL	Z13.D, Z4.D, Z8.D] is unknown
 - The number of fused uops of the instruction [MUL	Z12.D, Z6.D, Z8.D] is unknown
 - The number of fused uops of the instruction [MUL	Z3.D, Z3.D, Z8.D] is unknown
 - The number of fused uops of the instruction [MUL	Z3.D, Z7.D, Z8.D] is unknown

3% of peak computational performance is used (1.10 out of 32.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.9.1.1  -  Vectorization
  ---------------------------------------------------------------------------------------------------------

Your loop is partially vectorized.
81% of vector register length is used (average across all VPU instructions).


Details
60% of VPU instructions are used in vector version (process two or more data elements in vector registers):
 - 33% of VPU loads are used in vector version.
 - 34% of VPU addition or subtraction instructions are used in vector version.
 - 87% of VPU multiply instructions are used in vector version.
 - 66% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.





      6.1.9.1.2  -  Expensive FP math instructions/calls
  ---------------------------------------------------------------------------------------------------------

Detected performance impact from expensive FP math instructions/calls.
By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 14.75 cycles (1.36x speedup).


      6.1.9.1.3  -  FMA
  ---------------------------------------------------------------------------------------------------------

Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.9.1.4  -  Slow data structures access
  ---------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Constant unknown stride: 23 occurrence(s)
 - Irregular (variable stride) or indirect: 8 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)
 - Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.



      6.1.9.1.5  -  Matching between your loop (in the source code) and the binary loop
  ---------------------------------------------------------------------------------------------------------

The binary loop is composed of 22 FP arithmetical operations:
 - 12: addition or subtraction
 - 10: multiply
The binary loop is loading 194 bytes.
The binary loop is storing 32 bytes.


      6.1.9.1.6  -  Arithmetic intensity
  ---------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.10 FP operations per loaded or stored byte.







      6.1.10  -  Loop 165 from exec
  =========================================================================================================

The loop is defined in:
 - /home/eoseret/qaas/qaas_runs/178-540-1875/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:209-216
 - /home/eoseret/qaas/qaas_runs/178-540-1875/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69


The related source loop is unrolled by 2 (including vectorization).

      6.1.10.1  -  Path 1
  ---------------------------------------------------------------------------------------------------------

Warnings:
 - The number of fused uops of the instruction [MUL	Z31.D, Z1.D, Z27.D] is unknown
 - The number of fused uops of the instruction [MUL	Z10.D, Z2.D, Z26.D] is unknown
 - The number of fused uops of the instruction [MUL	Z29.D, Z0.D, Z27.D] is unknown
 - The number of fused uops of the instruction [MUL	Z12.D, Z4.D, Z27.D] is unknown
 - The number of fused uops of the instruction [MUL	Z14.D, Z4.D, Z26.D] is unknown
 - The number of fused uops of the instruction [MUL	Z26.D, Z5.D, Z26.D] is unknown
 - The number of fused uops of the instruction [MUL	Z8.D, Z2.D, Z27.D] is unknown
 - The number of fused uops of the instruction [MUL	Z10.D, Z3.D, Z27.D] is unknown
 - The number of fused uops of the instruction [MUL	Z27.D, Z5.D, Z27.D] is unknown

1% of peak computational performance is used (0.59 out of 32.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.10.1.1  -  Vectorization
  ---------------------------------------------------------------------------------------------------------

Your loop is partially vectorized.
85% of vector register length is used (average across all VPU instructions).


Details
67% of VPU instructions are used in vector version (process two or more data elements in vector registers):
 - 37% of VPU loads are used in vector version.
 - 38% of VPU addition or subtraction instructions are used in vector version.
 - 50% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.





      6.1.10.1.2  -  Expensive FP math instructions/calls
  ---------------------------------------------------------------------------------------------------------

Detected performance impact from expensive FP math instructions/calls.
By removing/reexpressing them, you can lower the cost of an iteration from 33.99 to 11.25 cycles (3.02x speedup).


      6.1.10.1.3  -  FMA
  ---------------------------------------------------------------------------------------------------------

Detected 2 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.10.1.4  -  Slow data structures access
  ---------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Constant unknown stride: 15 occurrence(s)
 - Irregular (variable stride) or indirect: 6 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)
 - Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.



      6.1.10.1.5  -  Matching between your loop (in the source code) and the binary loop
  ---------------------------------------------------------------------------------------------------------

The binary loop is composed of 20 FP arithmetical operations:
 - 12: addition or subtraction (2 inside FMA instructions)
 - 4: multiply (2 inside FMA instructions)
 - 4: divide
The binary loop is loading 145 bytes.
The binary loop is storing 32 bytes.


      6.1.10.1.6  -  Arithmetic intensity
  ---------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.11 FP operations per loaded or stored byte.





[MAQAO] Info: STOP THE REPORT GENERATION
[MAQAO] Info: 
[MAQAO] Info: If your application produces files, they can be found in directory "/home/eoseret/qaas/qaas_runs/178-540-1875/intel/CloverLeaf2.0-CXX/run/oneview_runs/defaults/orig/oneview_run_1785402399"
[MAQAO] Info: 
