OV - exec - Loop 419

	Loop Id: 419	Module: exec	Source: reset_field.cpp:37-38	Coverage: 2.18%

0x42e1e8 LDR	Q21, [X4, X0]    [1]

0x42e1ec ADD	X14, X0, #16

0x42e1f0 ADD	X28, X0, #32

0x42e1f4 ADD	X27, X0, #48

0x42e1f8 ADD	X26, X0, #64

0x42e1fc ADD	X25, X0, #80

0x42e200 ADD	X23, X0, #96

0x42e204 ADD	X19, X0, #112

0x42e208 STR	Q21, [X3, X0]    [4]

0x42e20c LDR	Q22, [X2, X0]    [3]

0x42e210 STR	Q22, [X1, X0]    [2]

0x42e214 ADD	X0, X0, #128

0x42e218 LDR	Q23, [X4, X14]    [1]

0x42e21c STR	Q23, [X3, X14]    [4]

0x42e220 LDR	Q24, [X2, X14]    [3]

0x42e224 STR	Q24, [X1, X14]    [2]

0x42e228 LDR	Q25, [X4, X28]    [1]

0x42e22c STR	Q25, [X3, X28]    [4]

0x42e230 LDR	Q26, [X2, X28]    [3]

0x42e234 STR	Q26, [X1, X28]    [2]

0x42e238 LDR	Q27, [X4, X27]    [1]

0x42e23c STR	Q27, [X3, X27]    [4]

0x42e240 LDR	Q28, [X2, X27]    [3]

0x42e244 STR	Q28, [X1, X27]    [2]

0x42e248 LDR	Q29, [X4, X26]    [1]

0x42e24c STR	Q29, [X3, X26]    [4]

0x42e250 LDR	Q30, [X2, X26]    [3]

0x42e254 STR	Q30, [X1, X26]    [2]

0x42e258 LDR	Q31, [X4, X25]    [1]

0x42e25c STR	Q31, [X3, X25]    [4]

0x42e260 LDR	Q0, [X2, X25]    [3]

0x42e264 STR	Q0, [X1, X25]    [2]

0x42e268 LDR	Q1, [X4, X23]    [1]

0x42e26c STR	Q1, [X3, X23]    [4]

0x42e270 LDR	Q2, [X2, X23]    [3]

0x42e274 STR	Q2, [X1, X23]    [2]

0x42e278 LDR	Q3, [X4, X19]    [1]

0x42e27c STR	Q3, [X3, X19]    [4]

0x42e280 LDR	Q4, [X2, X19]    [3]

0x42e284 STR	Q4, [X1, X19]    [2]

0x42e288 CMP	X8, X0

0x42e28c B.NE	42e1e8

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/reset_field.cpp: 37 - 38

--------------------------------------------------------------------------------

37:       density0(i, j) = density1(i, j);

38:       energy0(i, j) = energy1(i, j);

Coverage (%)	Name	Source Location	Module
►98.96+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.04+	GOMP_parallel	libgomp.h:980	libgomp.so.1.0.0
○	reset_field(global_variables&)	reset_field.cpp:34	exec
○	hydro(global_variables&, paral[...]	basic_string.h:1076	exec
○	main	clover_leaf.cpp:209	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.cpp:51	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.33
Bottlenecks	P12, P13, P14,
Function	reset_field_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.0]
Source	reset_field.cpp:37-38
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	10.67
CQA cycles if no scalar integer	10.67
CQA cycles if FP arith vectorized	10.67
CQA cycles if fully vectorized	10.67
Front-end cycles	5.25
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	1.58
P3 cycles	1.58
P4 cycles	1.50
P5 cycles	1.50
P6 cycles	1.42
P7 cycles	1.42
P8 cycles	8.00
P9 cycles	8.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	10.67
P13 cycles	10.67
P14 cycles	10.67
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	42.00
Nb uops	42.00
Nb loads	NA
Nb stores	16.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	48.00
Bytes prefetched	0.00
Bytes loaded	256.00
Bytes stored	256.00
Stride 0	0.00
Stride 1	0.00
Stride n	4.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.33
Bottlenecks	P12, P13, P14,
Function	reset_field_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.0]
Source	reset_field.cpp:37-38
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	10.67
CQA cycles if no scalar integer	10.67
CQA cycles if FP arith vectorized	10.67
CQA cycles if fully vectorized	10.67
Front-end cycles	5.25
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	1.58
P3 cycles	1.58
P4 cycles	1.50
P5 cycles	1.50
P6 cycles	1.42
P7 cycles	1.42
P8 cycles	8.00
P9 cycles	8.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	10.67
P13 cycles	10.67
P14 cycles	10.67
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	42.00
Nb uops	42.00
Nb loads	NA
Nb stores	16.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	48.00
Bytes prefetched	0.00
Bytes loaded	256.00
Bytes stored	256.00
Stride 0	0.00
Stride 1	0.00
Stride n	4.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	reset_field_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.0]
Source file and lines	reset_field.cpp:37-38
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/reset_field.cpp:37-38.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All VPU instructions are used in vector version (process two or more data elements in vector registers).

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 256 bytes. The binary loop is storing 256 bytes.

General properties

nb instructions	42
loop length	168
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	1.58	1.58	1.50	1.50	1.42	1.42	8.00	8.00	0.00	0.00	10.67	10.67	10.67	0.00	0.00
cycles	0.50	0.50	1.58	1.58	1.50	1.50	1.42	1.42	8.00	8.00	0.00	0.00	10.67	10.67	10.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	5.25
Data deps.	1.00
Overall L1	10.67

Vectorization ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 10.67 cycles. At this rate:

24% of peak load performance is reached (24.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
49% of peak store performance is reached (24.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 42e1e8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDR Q21, [X4, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ADD X14, X0, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X28, X0, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X27, X0, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X26, X0, #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X25, X0, #80	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X23, X0, #96	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X19, X0, #112	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR Q21, [X3, X0]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
LDR Q22, [X2, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
STR Q22, [X1, X0]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
ADD X0, X0, #128	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR Q23, [X4, X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
STR Q23, [X3, X14]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
LDR Q24, [X2, X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
STR Q24, [X1, X14]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
LDR Q25, [X4, X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
STR Q25, [X3, X28]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
LDR Q26, [X2, X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
STR Q26, [X1, X28]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
LDR Q27, [X4, X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
STR Q27, [X3, X27]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
LDR Q28, [X2, X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
STR Q28, [X1, X27]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
LDR Q29, [X4, X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
STR Q29, [X3, X26]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
LDR Q30, [X2, X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
STR Q30, [X1, X26]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
LDR Q31, [X4, X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
STR Q31, [X3, X25]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
LDR Q0, [X2, X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
STR Q0, [X1, X25]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
LDR Q1, [X4, X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
STR Q1, [X3, X23]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
LDR Q2, [X2, X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
STR Q2, [X1, X23]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
LDR Q3, [X4, X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
STR Q3, [X3, X19]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
LDR Q4, [X2, X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
STR Q4, [X1, X19]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
CMP X8, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.NE 42e1e8 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x218>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	reset_field_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.0]
Source file and lines	reset_field.cpp:37-38
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All VPU instructions are used in vector version (process two or more data elements in vector registers).

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 256 bytes. The binary loop is storing 256 bytes.

General properties

nb instructions	42
loop length	168
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	1.58	1.58	1.50	1.50	1.42	1.42	8.00	8.00	0.00	0.00	10.67	10.67	10.67	0.00	0.00
cycles	0.50	0.50	1.58	1.58	1.50	1.50	1.42	1.42	8.00	8.00	0.00	0.00	10.67	10.67	10.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	5.25
Data deps.	1.00
Overall L1	10.67

Vectorization ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 10.67 cycles. At this rate:

24% of peak load performance is reached (24.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
49% of peak store performance is reached (24.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 42e1e8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDR Q21, [X4, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ADD X14, X0, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X28, X0, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X27, X0, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X26, X0, #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X25, X0, #80	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X23, X0, #96	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X19, X0, #112	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR Q21, [X3, X0]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
LDR Q22, [X2, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
STR Q22, [X1, X0]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
ADD X0, X0, #128	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR Q23, [X4, X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
STR Q23, [X3, X14]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
LDR Q24, [X2, X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
STR Q24, [X1, X14]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
LDR Q25, [X4, X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
STR Q25, [X3, X28]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
LDR Q26, [X2, X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
STR Q26, [X1, X28]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
LDR Q27, [X4, X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
STR Q27, [X3, X27]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
LDR Q28, [X2, X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
STR Q28, [X1, X27]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
LDR Q29, [X4, X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
STR Q29, [X3, X26]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
LDR Q30, [X2, X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
STR Q30, [X1, X26]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
LDR Q31, [X4, X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
STR Q31, [X3, X25]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
LDR Q0, [X2, X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
STR Q0, [X1, X25]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
LDR Q1, [X4, X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
STR Q1, [X3, X23]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
LDR Q2, [X2, X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
STR Q2, [X1, X23]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
LDR Q3, [X4, X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
STR Q3, [X3, X19]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
LDR Q4, [X2, X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
STR Q4, [X1, X19]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (100.0%)
CMP X8, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.NE 42e1e8 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x218>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code