OV - exec - Loop 312

	Loop Id: 312	Module: exec	Source: context.h:69-69 [...]	Coverage: 0.33%

0x4266e8 SDIV	W25, W5, W20

0x4266ec ADD	W24, W25, W11

0x4266f0 MSUB	W23, W25, W20, W5

0x4266f4 ADD	X1, X10, W23,SXTW

0x4266f8 ADD	X2, X1, #1

0x4266fc ADD	W3, W24, #1

0x426700 SBFM	X22, X24, #0, #31

0x426704 SBFM	X25, X3, #0, #31

0x426708 ADD	W5, W5, #1

0x42670c MADD	X24, X22, X7, X2

0x426710 ADD	W4, W23, W21

0x426714 MADD	X23, X25, X7, X2

0x426718 SBFM	X1, X4, #0, #31

0x42671c MADD	X3, X25, X9, X2

0x426720 UBFM	X24, X24, #61, #60

0x426724 MADD	X2, X22, X9, X2

0x426728 UBFM	X4, X23, #61, #60

0x42672c MADD	X25, X22, X13, X1

0x426730 LDR	Q30, [X6, X24]    [1]

0x426734 UBFM	X3, X3, #61, #60

0x426738 MADD	X24, X22, X18, X1

0x42673c UBFM	X2, X2, #61, #60

0x426740 MADD	X23, X17, X22, X1

0x426744 LDR	Q31, [X6, X4]    [1]

0x426748 MADD	X22, X22, X16, X1

0x42674c LDR	Q26, [X8, X3]    [2]

0x426750 LDR	Q25, [X8, X2]    [2]

0x426754 FMUL	V0.2D, V30.2D, V30.2D

0x426758 FMUL	V1.2D, V31.2D, V31.2D

0x42675c LDR	D28, [X12, X25,LSL #3]    [4]

0x426760 LDR	D29, [X30, X24,LSL #3]    [3]

0x426764 FMLA	V0.2D, V25.2D, V25.2D

0x426768 LDR	D2, [X15, X23,LSL #3]    [6]

0x42676c LDR	D20, [X14, X22,LSL #3]    [5]

0x426770 FADD	D24, D24, D28

0x426774 FMLA	V1.2D, V26.2D, V26.2D

0x426778 FMUL	D3, D28, D29

0x42677c FMADD	D15, D28, D20, D15

0x426780 FMUL	V4.2D, V0.2D, V21.2D

0x426784 FMADD	D27, D3, D2, D27

0x426788 FADD	D23, D23, D3

0x42678c FMUL	V5.2D, V1.2D, V21.2D

0x426790 FADDP	D6, V4.2D

0x426794 FADDP	D7, V5.2D

0x426798 FADD	D16, D7, D6

0x42679c FMUL	D17, D16, D19

0x4267a0 FMADD	D22, D3, D17, D22

0x4267a4 CMP	W0, W5

0x4267a8 B.NE	4266e8

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp: 77 - 91

--------------------------------------------------------------------------------

77:       const int j = xmin + 1 + idx % (xmax - xmin + 1);

78:       const int k = ymin + 1 + idx / (xmax - xmin + 1);

79:       double vsqrd = 0.0;

80:       for (int kv = k; kv <= k + 1; ++kv) {

81:         for (int jv = j; jv <= j + 1; ++jv) {

82:           vsqrd += 0.25 * (field.xvel0(jv, kv) * field.xvel0(jv, kv) + field.yvel0(jv, kv) * field.yvel0(jv, kv));

83:         }

84:       }

85:       double cell_vol = field.volume(j, k);

86:       double cell_mass = cell_vol * field.density0(j, k);

87:       vol += cell_vol;

88:       mass += cell_mass;

89:       ie += cell_mass * field.energy0(j, k);

90:       ke += cell_mass * 0.5 * vsqrd;

91:       press += cell_vol * field.pressure(j, k);

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

Coverage (%)	Name	Source Location	Module
►98.96+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	3.75 - 4.69
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.63 - 1.25
Bottlenecks	P8, P10,
Function	field_summary(global_variables&, parallel_&) [clone ._omp_fn.0]
Source	field_summary.cpp:77-91,context.h:69-69
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	10.00 - 12.50
CQA cycles if no scalar integer	2.67
CQA cycles if FP arith vectorized	10.00 - 12.50
CQA cycles if fully vectorized	10.00 - 12.50
Front-end cycles	6.13
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	2.83
P3 cycles	2.83
P4 cycles	2.83
P5 cycles	2.83
P6 cycles	10.00
P7 cycles	2.67
P8 cycles	4.00
P9 cycles	4.00
P10 cycles	4.00
P11 cycles	4.00
P12 cycles	2.67
P13 cycles	2.67
P14 cycles	2.67
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	5.00 - 12.50
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	49.00
Nb uops	49.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	2.90 - 2.32
Nb FLOP add-sub	5.00
Nb FLOP mul	10.00
Nb FLOP fma	7.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	7.68 - 9.60
Bytes prefetched	0.00
Bytes loaded	96.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	6.00
Vectorization ratio all	38.46
Vectorization ratio load	50.00
Vectorization ratio store	NA
Vectorization ratio mul	66.67
Vectorization ratio add_sub	0.00
Vectorization ratio fma	40.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	75.00
Vector-efficiency ratio load	75.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	83.33
Vector-efficiency ratio add_sub	66.67
Vector-efficiency ratio fma	70.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	3.75 - 4.69
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.63 - 1.25
Bottlenecks	P8, P10,
Function	field_summary(global_variables&, parallel_&) [clone ._omp_fn.0]
Source	field_summary.cpp:77-91,context.h:69-69
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	10.00 - 12.50
CQA cycles if no scalar integer	2.67
CQA cycles if FP arith vectorized	10.00 - 12.50
CQA cycles if fully vectorized	10.00 - 12.50
Front-end cycles	6.13
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	2.83
P3 cycles	2.83
P4 cycles	2.83
P5 cycles	2.83
P6 cycles	10.00
P7 cycles	2.67
P8 cycles	4.00
P9 cycles	4.00
P10 cycles	4.00
P11 cycles	4.00
P12 cycles	2.67
P13 cycles	2.67
P14 cycles	2.67
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	5.00 - 12.50
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	49.00
Nb uops	49.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	2.90 - 2.32
Nb FLOP add-sub	5.00
Nb FLOP mul	10.00
Nb FLOP fma	7.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	7.68 - 9.60
Bytes prefetched	0.00
Bytes loaded	96.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	6.00
Vectorization ratio all	38.46
Vectorization ratio load	50.00
Vectorization ratio store	NA
Vectorization ratio mul	66.67
Vectorization ratio add_sub	0.00
Vectorization ratio fma	40.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	75.00
Vector-efficiency ratio load	75.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	83.33
Vector-efficiency ratio add_sub	66.67
Vector-efficiency ratio fma	70.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	field_summary(global_variables&, parallel_&) [clone ._omp_fn.0]
Source file and lines	context.h:69-69
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:77-91
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.50 to 2.67 cycles (4.69x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 75% of vector register length is used (average across all VPU instructions).

Details

38% of VPU instructions are used in vector version (process two or more data elements in vector registers):

50% of VPU loads are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
66% of VPU multiply instructions are used in vector version.
40% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

FMA

Detected 7 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 29 FP arithmetical operations:

12: addition or subtraction (7 inside FMA instructions)
17: multiply (7 inside FMA instructions)

The binary loop is loading 96 bytes.

Arithmetic intensity

Arithmetic intensity is 0.30 FP operations per loaded or stored byte.

General properties

nb instructions	49
loop length	196
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	2.83	2.83	2.83	2.83	10.00	2.67	4.00	4.00	4.00	4.00	2.67	2.67	2.67	0.00	0.00
cycles	0.50	0.50	2.83	2.83	2.83	2.83	10.00	2.67	4.00	4.00	4.00	4.00	2.67	2.67	2.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	5.00-12.50
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	6.13
Data deps.	2.00
Overall L1	10.00-12.50

Vectorization ratios

INT

all	40%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	37%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	66%
add-sub	0%
fma	40%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	38%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	66%
add-sub	0%
fma	40%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.50 cycles. At this rate:

8% of peak load performance is reached (7.68 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4266e8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SDIV W25, W5, W20	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
ADD W24, W25, W11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
MSUB W23, W25, W20, W5	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X1, X10, W23,SXTW	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
ADD X2, X1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD W3, W24, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X22, X24, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X25, X3, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD W5, W5, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
MADD X24, X22, X7, X2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD W4, W23, W21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
MADD X23, X25, X7, X2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
SBFM X1, X4, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
MADD X3, X25, X9, X2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
UBFM X24, X24, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
MADD X2, X22, X9, X2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
UBFM X4, X23, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
MADD X25, X22, X13, X1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
LDR Q30, [X6, X24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
UBFM X3, X3, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
MADD X24, X22, X18, X1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
UBFM X2, X2, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
MADD X23, X17, X22, X1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
LDR Q31, [X6, X4]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
MADD X22, X22, X16, X1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
LDR Q26, [X8, X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR Q25, [X8, X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMUL V0.2D, V30.2D, V30.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMUL V1.2D, V31.2D, V31.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
LDR D28, [X12, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D29, [X30, X24,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMLA V0.2D, V25.2D, V25.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDR D2, [X15, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D20, [X14, X22,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FADD D24, D24, D28	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
FMLA V1.2D, V26.2D, V26.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMUL D3, D28, D29	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FMADD D15, D28, D20, D15	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FMUL V4.2D, V0.2D, V21.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMADD D27, D3, D2, D27	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FADD D23, D23, D3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
FMUL V5.2D, V1.2D, V21.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FADDP D6, V4.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FADDP D7, V5.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FADD D16, D7, D6	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
FMUL D17, D16, D19	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FMADD D22, D3, D17, D22	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
CMP W0, W5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.NE 4266e8 <_Z13field_summaryR16global_variablesR9parallel_._omp_fn.0+0xc8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	field_summary(global_variables&, parallel_&) [clone ._omp_fn.0]
Source file and lines	context.h:69-69
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:77-91
/home/hbollore/qaas/qaas-runs/174-169-1878/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.50 to 2.67 cycles (4.69x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 75% of vector register length is used (average across all VPU instructions).

Details

38% of VPU instructions are used in vector version (process two or more data elements in vector registers):

50% of VPU loads are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
66% of VPU multiply instructions are used in vector version.
40% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

FMA

Detected 7 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 29 FP arithmetical operations:

12: addition or subtraction (7 inside FMA instructions)
17: multiply (7 inside FMA instructions)

The binary loop is loading 96 bytes.

Arithmetic intensity

Arithmetic intensity is 0.30 FP operations per loaded or stored byte.

General properties

nb instructions	49
loop length	196
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	2.83	2.83	2.83	2.83	10.00	2.67	4.00	4.00	4.00	4.00	2.67	2.67	2.67	0.00	0.00
cycles	0.50	0.50	2.83	2.83	2.83	2.83	10.00	2.67	4.00	4.00	4.00	4.00	2.67	2.67	2.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	5.00-12.50
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	6.13
Data deps.	2.00
Overall L1	10.00-12.50

Vectorization ratios

INT

all	40%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	37%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	66%
add-sub	0%
fma	40%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	38%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	66%
add-sub	0%
fma	40%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.50 cycles. At this rate:

8% of peak load performance is reached (7.68 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4266e8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SDIV W25, W5, W20	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
ADD W24, W25, W11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
MSUB W23, W25, W20, W5	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X1, X10, W23,SXTW	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
ADD X2, X1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD W3, W24, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X22, X24, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X25, X3, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD W5, W5, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
MADD X24, X22, X7, X2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD W4, W23, W21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
MADD X23, X25, X7, X2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
SBFM X1, X4, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
MADD X3, X25, X9, X2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
UBFM X24, X24, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
MADD X2, X22, X9, X2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
UBFM X4, X23, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
MADD X25, X22, X13, X1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
LDR Q30, [X6, X24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
UBFM X3, X3, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
MADD X24, X22, X18, X1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
UBFM X2, X2, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
MADD X23, X17, X22, X1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
LDR Q31, [X6, X4]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
MADD X22, X22, X16, X1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
LDR Q26, [X8, X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR Q25, [X8, X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMUL V0.2D, V30.2D, V30.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMUL V1.2D, V31.2D, V31.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
LDR D28, [X12, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D29, [X30, X24,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMLA V0.2D, V25.2D, V25.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDR D2, [X15, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D20, [X14, X22,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FADD D24, D24, D28	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
FMLA V1.2D, V26.2D, V26.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMUL D3, D28, D29	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FMADD D15, D28, D20, D15	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FMUL V4.2D, V0.2D, V21.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMADD D27, D3, D2, D27	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FADD D23, D23, D3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
FMUL V5.2D, V1.2D, V21.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FADDP D6, V4.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FADDP D7, V5.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
FADD D16, D7, D6	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
FMUL D17, D16, D19	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FMADD D22, D3, D17, D22	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
CMP W0, W5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.NE 4266e8 <_Z13field_summaryR16global_variablesR9parallel_._omp_fn.0+0xc8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code